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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c@144:ef7eb2e8f9f7
Child:
157:ff67d9f36b67
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_irda.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief IRDA HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the IrDA SIR ENDEC block (IrDA):
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization methods
<> 144:ef7eb2e8f9f7 11 * + IO operation methods
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control methods
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 The IRDA HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (#) Declare a IRDA_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 22 (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
<> 144:ef7eb2e8f9f7 23 (##) Enable the USARTx interface clock.
<> 144:ef7eb2e8f9f7 24 (##) IRDA pins configuration:
<> 144:ef7eb2e8f9f7 25 (+++) Enable the clock for the IRDA GPIOs.
<> 144:ef7eb2e8f9f7 26 (+++) Configure these IRDA pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 27 (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 28 and HAL_IRDA_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 29 (+++) Configure the USARTx interrupt priority.
<> 144:ef7eb2e8f9f7 30 (+++) Enable the NVIC USART IRQ handle.
<> 144:ef7eb2e8f9f7 31 (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 32 and HAL_IRDA_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 33 (+++) Declare a DMA handle structure for the Tx/Rx stream.
<> 144:ef7eb2e8f9f7 34 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 37 (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 38 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
<> 144:ef7eb2e8f9f7 41 and Mode(Receiver/Transmitter) in the hirda Init structure.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
<> 144:ef7eb2e8f9f7 44 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 45 by calling the customized HAL_IRDA_MspInit() API.
<> 144:ef7eb2e8f9f7 46 -@@- The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 47 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 48 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 53 =================================
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 56 (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 59 ===================================
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61 (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 62 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 63 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 64 (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 65 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 68 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 71 =============================
<> 144:ef7eb2e8f9f7 72 [..]
<> 144:ef7eb2e8f9f7 73 (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 74 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 75 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 76 (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 77 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 78 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 79 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 *** IRDA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 83 ===================================
<> 144:ef7eb2e8f9f7 84 [..]
<> 144:ef7eb2e8f9f7 85 Below the list of most used macros in IRDA HAL driver.
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
<> 144:ef7eb2e8f9f7 88 (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
<> 144:ef7eb2e8f9f7 89 (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
<> 144:ef7eb2e8f9f7 90 (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
<> 144:ef7eb2e8f9f7 91 (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 92 (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 (@) You can refer to the IRDA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 @endverbatim
<> 144:ef7eb2e8f9f7 97 ******************************************************************************
<> 144:ef7eb2e8f9f7 98 * @attention
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 103 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 104 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 105 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 106 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 107 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 108 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 109 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 110 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 111 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 114 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 115 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 116 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 117 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 118 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 119 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 120 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 121 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 122 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 ******************************************************************************
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup IRDA IRDA
<> 144:ef7eb2e8f9f7 135 * @brief HAL IRDA module driver
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 #ifdef HAL_IRDA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /** @addtogroup IRDA_Private_Constants
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 #define TEACK_REACK_TIMEOUT 1000U
<> 144:ef7eb2e8f9f7 146 #define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U
<> 144:ef7eb2e8f9f7 147 #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
<> 144:ef7eb2e8f9f7 148 | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @}
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 153 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 154 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 155 /** @addtogroup IRDA_Private_Functions
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 159 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 160 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 161 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 163 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 164 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 165 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 166 static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 167 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 168 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 169 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 170 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 171 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 176 /** @defgroup IRDA_Exported_Functions IrDA Exported Functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 181 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 182 *
<> 144:ef7eb2e8f9f7 183 @verbatim
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 ===============================================================================
<> 144:ef7eb2e8f9f7 186 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 187 ===============================================================================
<> 144:ef7eb2e8f9f7 188 [..]
<> 144:ef7eb2e8f9f7 189 This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<> 144:ef7eb2e8f9f7 190 in IrDA mode.
<> 144:ef7eb2e8f9f7 191 (+) For the asynchronous mode only these parameters can be configured:
<> 144:ef7eb2e8f9f7 192 (++) BaudRate
<> 144:ef7eb2e8f9f7 193 (++) WordLength
<> 144:ef7eb2e8f9f7 194 (++) Parity: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 195 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 196 Depending on the frame length defined by the M bit (8-bits or 9-bits),
<> 144:ef7eb2e8f9f7 197 please refer to Reference manual for possible IRDA frame formats.
<> 144:ef7eb2e8f9f7 198 (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
<> 144:ef7eb2e8f9f7 199 not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
<> 144:ef7eb2e8f9f7 200 specification specifies a minimum of 10 ms delay between transmission and
<> 144:ef7eb2e8f9f7 201 reception (IrDA is a half duplex protocol).
<> 144:ef7eb2e8f9f7 202 (++) Mode: Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 203 (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
<> 144:ef7eb2e8f9f7 204 [..]
<> 144:ef7eb2e8f9f7 205 The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
<> 144:ef7eb2e8f9f7 206 are available in reference manual).
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 @endverbatim
<> 144:ef7eb2e8f9f7 209 * @{
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @brief Initializes the IRDA mode according to the specified
<> 144:ef7eb2e8f9f7 214 * parameters in the IRDA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 215 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 216 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 217 * @retval HAL status
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 222 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Check the USART/UART associated to the IRDA handle */
<> 144:ef7eb2e8f9f7 228 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 if(hirda->gState == HAL_IRDA_STATE_RESET)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 233 hirda->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 234 /* Init the low level hardware : GPIO, CLOCK, CORTEX */
<> 144:ef7eb2e8f9f7 235 HAL_IRDA_MspInit(hirda);
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Disable the Peripheral to update the configuration registers */
<> 144:ef7eb2e8f9f7 241 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Set the IRDA Communication parameters */
<> 144:ef7eb2e8f9f7 244 IRDA_SetConfig(hirda);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* In IRDA mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 247 - LINEN, STOP and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 248 - SCEN and HDSEL bits in the USART_CR3 register.*/
<> 144:ef7eb2e8f9f7 249 CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 250 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* set the UART/USART in IRDA mode */
<> 144:ef7eb2e8f9f7 253 SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 256 __HAL_IRDA_ENABLE(hirda);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* TEACK and/or REACK to check before moving hirda->State to Ready */
<> 144:ef7eb2e8f9f7 259 return (IRDA_CheckIdleState(hirda));
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief DeInitializes the IRDA peripheral
<> 144:ef7eb2e8f9f7 264 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 265 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 266 * @retval HAL status
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 271 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Check the parameters */
<> 144:ef7eb2e8f9f7 277 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 282 HAL_IRDA_MspDeInit(hirda);
<> 144:ef7eb2e8f9f7 283 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 284 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 287 hirda->gState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 288 hirda->RxState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Release Lock */
<> 144:ef7eb2e8f9f7 291 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 return HAL_OK;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @brief IRDA MSP Init.
<> 144:ef7eb2e8f9f7 298 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 299 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 300 * @retval None
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 305 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 308 the HAL_IRDA_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /**
<> 144:ef7eb2e8f9f7 313 * @brief IRDA MSP DeInit.
<> 144:ef7eb2e8f9f7 314 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 315 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 316 * @retval None
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 321 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 324 the HAL_IRDA_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @}
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 333 * @brief IRDA Transmit/Receive functions
<> 144:ef7eb2e8f9f7 334 *
<> 144:ef7eb2e8f9f7 335 @verbatim
<> 144:ef7eb2e8f9f7 336 ===============================================================================
<> 144:ef7eb2e8f9f7 337 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 338 ===============================================================================
<> 144:ef7eb2e8f9f7 339 This subsection provides a set of functions allowing to manage the IRDA data transfers.
<> 144:ef7eb2e8f9f7 340 [..]
<> 144:ef7eb2e8f9f7 341 IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
<> 144:ef7eb2e8f9f7 342 on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
<> 144:ef7eb2e8f9f7 343 is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
<> 144:ef7eb2e8f9f7 344 While receiving data, transmission should be avoided as the data to be transmitted
<> 144:ef7eb2e8f9f7 345 could be corrupted.
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 348 (++) Blocking mode: the communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 349 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 350 after finishing transfer.
<> 144:ef7eb2e8f9f7 351 (++) No-Blocking mode: the communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 352 or DMA, these API's return the HAL status.
<> 144:ef7eb2e8f9f7 353 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 354 dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 355 using DMA mode.
<> 144:ef7eb2e8f9f7 356 The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 357 will be executed respectively at the end of the Transmit or Receive process
<> 144:ef7eb2e8f9f7 358 The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 (#) Blocking mode API's are :
<> 144:ef7eb2e8f9f7 361 (++) HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 362 (++) HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 (#) Non-Blocking mode API's with Interrupt are :
<> 144:ef7eb2e8f9f7 365 (++) HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 366 (++) HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 367 (++) HAL_IRDA_IRQHandler()
<> 144:ef7eb2e8f9f7 368 (++) IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 369 (++) IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 (#) Non-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 372 (++) HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 373 (++) HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
<> 144:ef7eb2e8f9f7 376 (++) HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 377 (++) HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 378 (++) HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 @endverbatim
<> 144:ef7eb2e8f9f7 381 * @{
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief Sends an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 386 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 387 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 388 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 389 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 390 * @param Timeout: Specify timeout value
<> 144:ef7eb2e8f9f7 391 * @retval HAL status
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 396 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 399 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Process Locked */
<> 144:ef7eb2e8f9f7 407 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 408 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 409 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Init tickstart for timeout managment*/
<> 144:ef7eb2e8f9f7 412 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 415 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 416 while(hirda->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 417 {
<> 144:ef7eb2e8f9f7 418 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 tmp = (uint16_t*) pData;
<> 144:ef7eb2e8f9f7 427 hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 428 pData +=2;
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430 else
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 442 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 445 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 return HAL_OK;
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449 else
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 457 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 458 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 459 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 460 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 461 * @param Timeout: Specify timeout value
<> 144:ef7eb2e8f9f7 462 * @retval HAL status
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 467 uint16_t uhMask;
<> 144:ef7eb2e8f9f7 468 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 471 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 476 }
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /* Process Locked */
<> 144:ef7eb2e8f9f7 479 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 480 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 481 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Init tickstart for timeout managment*/
<> 144:ef7eb2e8f9f7 484 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 487 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Computation of the mask to apply to the RDR register
<> 144:ef7eb2e8f9f7 490 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 491 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 492 uhMask = hirda->Mask;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Check data remaining to be received */
<> 144:ef7eb2e8f9f7 495 while(hirda->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 hirda->RxXferCount--;
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 506 *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
<> 144:ef7eb2e8f9f7 507 pData +=2;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509 else
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 516 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 519 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 return HAL_OK;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 else
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /**
<> 144:ef7eb2e8f9f7 530 * @brief Send an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 531 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 532 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 533 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 534 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 535 * @retval HAL status
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 540 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Process Locked */
<> 144:ef7eb2e8f9f7 548 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 551 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 552 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 555 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 558 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 561 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 return HAL_OK;
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565 else
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 573 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 574 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 575 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 576 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 577 * @retval HAL status
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 582 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Process Locked */
<> 144:ef7eb2e8f9f7 590 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 593 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 594 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Computation of the mask to apply to the RDR register
<> 144:ef7eb2e8f9f7 597 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 598 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 601 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 604 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Enable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 607 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 610 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Enable the IRDA Data Register not empty Interrupt */
<> 144:ef7eb2e8f9f7 613 SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 return HAL_OK;
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617 else
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /**
<> 144:ef7eb2e8f9f7 624 * @brief Sends an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 625 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 626 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 627 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 628 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 629 * @retval HAL status
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 636 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 639 {
<> 144:ef7eb2e8f9f7 640 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Process Locked */
<> 144:ef7eb2e8f9f7 644 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 647 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 648 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 651 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 654 hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 657 hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 660 hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Set the DMA abort callback */
<> 144:ef7eb2e8f9f7 663 hirda->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Enable the IRDA transmit DMA channel */
<> 144:ef7eb2e8f9f7 666 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 667 HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Clear the TC flag in the SR register by writing 0 to it */
<> 144:ef7eb2e8f9f7 670 __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC);
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 673 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 676 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 677 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 return HAL_OK;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681 else
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 689 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 690 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 691 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 692 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 693 * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
<> 144:ef7eb2e8f9f7 694 * @retval HAL status
<> 144:ef7eb2e8f9f7 695 */
<> 144:ef7eb2e8f9f7 696 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 701 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Process Locked */
<> 144:ef7eb2e8f9f7 709 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 712 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 715 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 718 hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 721 hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 724 hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Set the DMA abort callback */
<> 144:ef7eb2e8f9f7 727 hirda->hdmarx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 730 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 731 HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 734 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Enable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 737 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 740 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 743 in the USART CR3 register */
<> 144:ef7eb2e8f9f7 744 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 return HAL_OK;
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748 else
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /**
<> 144:ef7eb2e8f9f7 755 * @brief Pauses the DMA Transfer.
<> 144:ef7eb2e8f9f7 756 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 757 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 758 * @retval HAL status
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 /* Process Locked */
<> 144:ef7eb2e8f9f7 763 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)&&
<> 144:ef7eb2e8f9f7 766 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 /* Disable the UART DMA Tx request */
<> 144:ef7eb2e8f9f7 769 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771 if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)&&
<> 144:ef7eb2e8f9f7 772 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 775 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 776 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Disable the UART DMA Rx request */
<> 144:ef7eb2e8f9f7 779 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 783 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 return HAL_OK;
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /**
<> 144:ef7eb2e8f9f7 789 * @brief Resumes the DMA Transfer.
<> 144:ef7eb2e8f9f7 790 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 791 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 792 * @retval HAL status
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 /* Process Locked */
<> 144:ef7eb2e8f9f7 797 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 /* Enable the UART DMA Tx request */
<> 144:ef7eb2e8f9f7 802 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 /* Clear the Overrun flag before resuming the Rx transfer*/
<> 144:ef7eb2e8f9f7 807 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 810 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 811 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Enable the UART DMA Rx request */
<> 144:ef7eb2e8f9f7 814 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 818 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 return HAL_OK;
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /**
<> 144:ef7eb2e8f9f7 824 * @brief Stops the DMA Transfer.
<> 144:ef7eb2e8f9f7 825 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 826 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 827 * @retval HAL status
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 832 to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
<> 144:ef7eb2e8f9f7 833 HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
<> 144:ef7eb2e8f9f7 834 indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
<> 144:ef7eb2e8f9f7 835 interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
<> 144:ef7eb2e8f9f7 836 the stream and the corresponding call back is executed. */
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Stop IRDA DMA Tx request if ongoing */
<> 144:ef7eb2e8f9f7 839 if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
<> 144:ef7eb2e8f9f7 840 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Abort the IRDA DMA Tx channel */
<> 144:ef7eb2e8f9f7 845 if(hirda->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 HAL_DMA_Abort(hirda->hdmatx);
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 IRDA_EndTxTransfer(hirda);
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Stop IRDA DMA Rx request if ongoing */
<> 144:ef7eb2e8f9f7 853 if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
<> 144:ef7eb2e8f9f7 854 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<> 144:ef7eb2e8f9f7 855 {
<> 144:ef7eb2e8f9f7 856 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Abort the IRDA DMA Rx channel */
<> 144:ef7eb2e8f9f7 859 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 HAL_DMA_Abort(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865 return HAL_OK;
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /**
<> 144:ef7eb2e8f9f7 869 * @brief DMA IRDA communication abort callback, when call by HAL services on Error
<> 144:ef7eb2e8f9f7 870 * (To be called at end of DMA Abort procedure following error occurrence).
<> 144:ef7eb2e8f9f7 871 * @param hdma: DMA handle.
<> 144:ef7eb2e8f9f7 872 * @retval None
<> 144:ef7eb2e8f9f7 873 */
<> 144:ef7eb2e8f9f7 874 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 877 hirda->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 878 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /**
<> 144:ef7eb2e8f9f7 884 * @brief This function handles IRDA interrupt request.
<> 144:ef7eb2e8f9f7 885 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 886 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 887 * @retval None
<> 144:ef7eb2e8f9f7 888 */
<> 144:ef7eb2e8f9f7 889 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 890 {
<> 144:ef7eb2e8f9f7 891 uint32_t isrflags, cr1its, cr3its, errorflags;
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 isrflags = READ_REG(hirda->Instance->ISR);
<> 144:ef7eb2e8f9f7 894 cr1its = READ_REG(hirda->Instance->CR1);
<> 144:ef7eb2e8f9f7 895 cr3its = READ_REG(hirda->Instance->CR3);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* If no error occurs */
<> 144:ef7eb2e8f9f7 898 errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
<> 144:ef7eb2e8f9f7 899 if (errorflags == RESET)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 /* IRDA in mode Receiver ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 902 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 905 /* Clear RXNE interrupt flag */
<> 144:ef7eb2e8f9f7 906 __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908 }
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* If some errors occur */
<> 144:ef7eb2e8f9f7 911 if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 /* IRDA parity error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 914 if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
<> 144:ef7eb2e8f9f7 917 hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* IRDA frame error interrupt occurred --------------------------------------*/
<> 144:ef7eb2e8f9f7 921 if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 922 {
<> 144:ef7eb2e8f9f7 923 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
<> 144:ef7eb2e8f9f7 924 hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* IRDA noise error interrupt occurred --------------------------------------*/
<> 144:ef7eb2e8f9f7 928 if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
<> 144:ef7eb2e8f9f7 931 hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /* IRDA Over-Run interrupt occurred -----------------------------------------*/
<> 144:ef7eb2e8f9f7 935 if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 936 {
<> 144:ef7eb2e8f9f7 937 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 938 hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /* Call IRDA Error Call back function if need be --------------------------*/
<> 144:ef7eb2e8f9f7 942 if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 /* IRDA in mode Receiver ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 945 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* If Overrun error occurs, or if any error occurs in DMA mode reception,
<> 144:ef7eb2e8f9f7 951 consider error as blocking */
<> 144:ef7eb2e8f9f7 952 if (((hirda->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
<> 144:ef7eb2e8f9f7 953 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 /* Blocking error : transfer is aborted
<> 144:ef7eb2e8f9f7 956 Set the IRDA state ready to be able to start again the process,
<> 144:ef7eb2e8f9f7 957 Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<> 144:ef7eb2e8f9f7 958 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /* Disable the IRDA DMA Rx request if enabled */
<> 144:ef7eb2e8f9f7 961 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 144:ef7eb2e8f9f7 962 {
<> 144:ef7eb2e8f9f7 963 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /* Abort the IRDA DMA Rx channel */
<> 144:ef7eb2e8f9f7 966 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 967 {
<> 144:ef7eb2e8f9f7 968 /* Set the IRDA DMA Abort callback :
<> 144:ef7eb2e8f9f7 969 will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
<> 144:ef7eb2e8f9f7 970 hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /* Abort DMA RX */
<> 144:ef7eb2e8f9f7 973 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<> 144:ef7eb2e8f9f7 974 {
<> 144:ef7eb2e8f9f7 975 /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
<> 144:ef7eb2e8f9f7 976 hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 977 }
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979 else
<> 144:ef7eb2e8f9f7 980 {
<> 144:ef7eb2e8f9f7 981 /* Call user error callback */
<> 144:ef7eb2e8f9f7 982 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984 }
<> 144:ef7eb2e8f9f7 985 else
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Call user error callback */
<> 144:ef7eb2e8f9f7 988 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 989 }
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 else
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* Non Blocking error : transfer could go on.
<> 144:ef7eb2e8f9f7 994 Error is notified to user through user error callback */
<> 144:ef7eb2e8f9f7 995 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 996 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999 return;
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 } /* End if some error occurs */
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* IRDA in mode Transmitter ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1004 if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<> 144:ef7eb2e8f9f7 1005 {
<> 144:ef7eb2e8f9f7 1006 IRDA_Transmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1007 return;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* IRDA in mode Transmitter (transmission end) -----------------------------*/
<> 144:ef7eb2e8f9f7 1011 if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<> 144:ef7eb2e8f9f7 1012 {
<> 144:ef7eb2e8f9f7 1013 IRDA_EndTransmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1014 return;
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /**
<> 144:ef7eb2e8f9f7 1019 * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
<> 144:ef7eb2e8f9f7 1020 * @param hirda: IRDA handle.
<> 144:ef7eb2e8f9f7 1021 * @retval None
<> 144:ef7eb2e8f9f7 1022 */
<> 144:ef7eb2e8f9f7 1023 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1024 {
<> 144:ef7eb2e8f9f7 1025 /* Disable TXEIE and TCIE interrupts */
<> 144:ef7eb2e8f9f7 1026 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 1029 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1030 }
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /**
<> 144:ef7eb2e8f9f7 1033 * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
<> 144:ef7eb2e8f9f7 1034 * @param hirda: IRDA handle.
<> 144:ef7eb2e8f9f7 1035 * @retval None
<> 144:ef7eb2e8f9f7 1036 */
<> 144:ef7eb2e8f9f7 1037 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 1040 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 1041 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* At end of Rx process, restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 1044 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /**
<> 144:ef7eb2e8f9f7 1048 * @brief Tx Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1049 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1050 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1051 * @retval None
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1056 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1059 the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1060 */
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /**
<> 144:ef7eb2e8f9f7 1064 * @brief Tx Half Transfer completed callbacks.
<> 144:ef7eb2e8f9f7 1065 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1066 * the configuration information for the specified USART module.
<> 144:ef7eb2e8f9f7 1067 * @retval None
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1072 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1075 the HAL_IRDA_TxCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1076 */
<> 144:ef7eb2e8f9f7 1077 }
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /**
<> 144:ef7eb2e8f9f7 1080 * @brief Rx Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1081 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1082 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1083 * @retval None
<> 144:ef7eb2e8f9f7 1084 */
<> 144:ef7eb2e8f9f7 1085 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1086 {
<> 144:ef7eb2e8f9f7 1087 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1088 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1091 the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1092 */
<> 144:ef7eb2e8f9f7 1093 }
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 /**
<> 144:ef7eb2e8f9f7 1096 * @brief Rx Half Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1097 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1098 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1099 * @retval None
<> 144:ef7eb2e8f9f7 1100 */
<> 144:ef7eb2e8f9f7 1101 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1102 {
<> 144:ef7eb2e8f9f7 1103 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1104 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1107 the HAL_IRDA_RxCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1108 */
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /**
<> 144:ef7eb2e8f9f7 1112 * @brief IRDA error callbacks.
<> 144:ef7eb2e8f9f7 1113 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1114 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1115 * @retval None
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1120 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1123 the HAL_IRDA_ErrorCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /**
<> 144:ef7eb2e8f9f7 1128 * @}
<> 144:ef7eb2e8f9f7 1129 */
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1132 * @brief IRDA control functions
<> 144:ef7eb2e8f9f7 1133 *
<> 144:ef7eb2e8f9f7 1134 @verbatim
<> 144:ef7eb2e8f9f7 1135 ===============================================================================
<> 144:ef7eb2e8f9f7 1136 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1137 ===============================================================================
<> 144:ef7eb2e8f9f7 1138 [..]
<> 144:ef7eb2e8f9f7 1139 This subsection provides a set of functions allowing to control the IRDA.
<> 144:ef7eb2e8f9f7 1140 (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.
<> 144:ef7eb2e8f9f7 1141 (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.
<> 144:ef7eb2e8f9f7 1142 @endverbatim
<> 144:ef7eb2e8f9f7 1143 * @{
<> 144:ef7eb2e8f9f7 1144 */
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /**
<> 144:ef7eb2e8f9f7 1147 * @brief Returns the IRDA state.
<> 144:ef7eb2e8f9f7 1148 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1149 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1150 * @retval HAL state
<> 144:ef7eb2e8f9f7 1151 */
<> 144:ef7eb2e8f9f7 1152 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1153 {
<> 144:ef7eb2e8f9f7 1154 uint32_t temp1 = 0x00U, temp2 = 0x00U;
<> 144:ef7eb2e8f9f7 1155 temp1 = hirda->gState;
<> 144:ef7eb2e8f9f7 1156 temp2 = hirda->RxState;
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /**
<> 144:ef7eb2e8f9f7 1162 * @brief Return the IRDA error code
<> 144:ef7eb2e8f9f7 1163 * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1164 * the configuration information for the specified IRDA.
<> 144:ef7eb2e8f9f7 1165 * @retval IRDA Error Code
<> 144:ef7eb2e8f9f7 1166 */
<> 144:ef7eb2e8f9f7 1167 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1168 {
<> 144:ef7eb2e8f9f7 1169 uint32_t temp1 = 0x00U, temp2 = 0x00U;
<> 144:ef7eb2e8f9f7 1170 temp1 = hirda->gState;
<> 144:ef7eb2e8f9f7 1171 temp2 = hirda->RxState;
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 1174 }
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /**
<> 144:ef7eb2e8f9f7 1177 * @}
<> 144:ef7eb2e8f9f7 1178 */
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 /**
<> 144:ef7eb2e8f9f7 1181 * @brief Configure the IRDA peripheral
<> 144:ef7eb2e8f9f7 1182 * @param hirda: irda handle
<> 144:ef7eb2e8f9f7 1183 * @retval None
<> 144:ef7eb2e8f9f7 1184 */
<> 144:ef7eb2e8f9f7 1185 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1186 {
<> 144:ef7eb2e8f9f7 1187 uint32_t tmpreg = 0x00000000U;
<> 144:ef7eb2e8f9f7 1188 uint32_t clocksource = 0x00000000U;
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Check the communication parameters */
<> 144:ef7eb2e8f9f7 1191 assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 1192 assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
<> 144:ef7eb2e8f9f7 1193 assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
<> 144:ef7eb2e8f9f7 1194 assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
<> 144:ef7eb2e8f9f7 1195 assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
<> 144:ef7eb2e8f9f7 1196 assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
<> 144:ef7eb2e8f9f7 1197 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1198 /* Configure the IRDA Word Length, Parity and transfer Mode:
<> 144:ef7eb2e8f9f7 1199 Set the M bits according to hirda->Init.WordLength value
<> 144:ef7eb2e8f9f7 1200 Set PCE and PS bits according to hirda->Init.Parity value
<> 144:ef7eb2e8f9f7 1201 Set TE and RE bits according to hirda->Init.Mode value */
<> 144:ef7eb2e8f9f7 1202 tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1207 MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /*-------------------------- USART GTPR Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 1210 MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler);
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1213 IRDA_GETCLOCKSOURCE(hirda, clocksource);
<> 144:ef7eb2e8f9f7 1214 switch (clocksource)
<> 144:ef7eb2e8f9f7 1215 {
<> 144:ef7eb2e8f9f7 1216 case IRDA_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 1217 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1218 break;
<> 144:ef7eb2e8f9f7 1219 case IRDA_CLOCKSOURCE_PCLK2:
<> 144:ef7eb2e8f9f7 1220 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1221 break;
<> 144:ef7eb2e8f9f7 1222 case IRDA_CLOCKSOURCE_HSI:
<> 144:ef7eb2e8f9f7 1223 hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1224 break;
<> 144:ef7eb2e8f9f7 1225 case IRDA_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 1226 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1227 break;
<> 144:ef7eb2e8f9f7 1228 case IRDA_CLOCKSOURCE_LSE:
<> 144:ef7eb2e8f9f7 1229 hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1230 break;
<> 144:ef7eb2e8f9f7 1231 default:
<> 144:ef7eb2e8f9f7 1232 break;
<> 144:ef7eb2e8f9f7 1233 }
<> 144:ef7eb2e8f9f7 1234 }
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /**
<> 144:ef7eb2e8f9f7 1237 * @brief Check the IRDA Idle State
<> 144:ef7eb2e8f9f7 1238 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1239 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1240 * @retval HAL status
<> 144:ef7eb2e8f9f7 1241 */
<> 144:ef7eb2e8f9f7 1242 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1243 {
<> 144:ef7eb2e8f9f7 1244 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /* Initialize the IRDA ErrorCode */
<> 144:ef7eb2e8f9f7 1247 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /* Init tickstart for timeout managment*/
<> 144:ef7eb2e8f9f7 1250 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* Check if the Transmitter is enabled */
<> 144:ef7eb2e8f9f7 1253 if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<> 144:ef7eb2e8f9f7 1254 {
<> 144:ef7eb2e8f9f7 1255 /* Wait until TEACK flag is set */
<> 144:ef7eb2e8f9f7 1256 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1257 {
<> 144:ef7eb2e8f9f7 1258 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261 /* Check if the Receiver is enabled */
<> 144:ef7eb2e8f9f7 1262 if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<> 144:ef7eb2e8f9f7 1263 {
<> 144:ef7eb2e8f9f7 1264 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1265 {
<> 144:ef7eb2e8f9f7 1266 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1267 }
<> 144:ef7eb2e8f9f7 1268 }
<> 144:ef7eb2e8f9f7 1269 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1270 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Initialize the IRDA state*/
<> 144:ef7eb2e8f9f7 1273 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1274 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 return HAL_OK;
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /**
<> 144:ef7eb2e8f9f7 1280 * @brief This function handles IRDA Communication Timeout.
<> 144:ef7eb2e8f9f7 1281 * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1282 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1283 * @param Flag specifies the IRDA flag to check.
<> 144:ef7eb2e8f9f7 1284 * @param Status The new Flag status (SET or RESET).
<> 144:ef7eb2e8f9f7 1285 * @param Tickstart Tick start value
<> 144:ef7eb2e8f9f7 1286 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 1287 * @retval HAL status
<> 144:ef7eb2e8f9f7 1288 */
<> 144:ef7eb2e8f9f7 1289 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1290 {
<> 144:ef7eb2e8f9f7 1291 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1292 while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
<> 144:ef7eb2e8f9f7 1293 {
<> 144:ef7eb2e8f9f7 1294 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1295 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1296 {
<> 144:ef7eb2e8f9f7 1297 if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1298 {
<> 144:ef7eb2e8f9f7 1299 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 1300 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
<> 144:ef7eb2e8f9f7 1301 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1304 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1307 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1310 }
<> 144:ef7eb2e8f9f7 1311 }
<> 144:ef7eb2e8f9f7 1312 }
<> 144:ef7eb2e8f9f7 1313 return HAL_OK;
<> 144:ef7eb2e8f9f7 1314 }
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /**
<> 144:ef7eb2e8f9f7 1317 * @brief Send an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1318 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1319 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1320 * @retval HAL status
<> 144:ef7eb2e8f9f7 1321 */
<> 144:ef7eb2e8f9f7 1322 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1323 {
<> 144:ef7eb2e8f9f7 1324 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 1327 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1328 {
<> 144:ef7eb2e8f9f7 1329 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 1330 {
<> 144:ef7eb2e8f9f7 1331 tmp = (uint16_t*) hirda->pTxBuffPtr;
<> 144:ef7eb2e8f9f7 1332 hirda->Instance->RDR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 1333 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 1334 {
<> 144:ef7eb2e8f9f7 1335 hirda->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 1336 }
<> 144:ef7eb2e8f9f7 1337 else
<> 144:ef7eb2e8f9f7 1338 {
<> 144:ef7eb2e8f9f7 1339 hirda->pTxBuffPtr += 1U;
<> 144:ef7eb2e8f9f7 1340 }
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342 else
<> 144:ef7eb2e8f9f7 1343 {
<> 144:ef7eb2e8f9f7 1344 hirda->Instance->RDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU);
<> 144:ef7eb2e8f9f7 1345 }
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 if(--hirda->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 /* Disable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 1350 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1353 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1354 }
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 return HAL_OK;
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358 else
<> 144:ef7eb2e8f9f7 1359 {
<> 144:ef7eb2e8f9f7 1360 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362 }
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /**
<> 144:ef7eb2e8f9f7 1365 * @brief Wraps up transmission in non blocking mode.
<> 144:ef7eb2e8f9f7 1366 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1367 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1368 * @retval HAL status
<> 144:ef7eb2e8f9f7 1369 */
<> 144:ef7eb2e8f9f7 1370 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1371 {
<> 144:ef7eb2e8f9f7 1372 /* Disable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1373 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 1376 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /* Tx process is ended, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 1379 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 return HAL_OK;
<> 144:ef7eb2e8f9f7 1384 }
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /**
<> 144:ef7eb2e8f9f7 1387 * @brief Receive an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1388 * Function called under interruption only, once
<> 144:ef7eb2e8f9f7 1389 * interruptions have been enabled by HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 1390 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1391 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1392 * @retval HAL status
<> 144:ef7eb2e8f9f7 1393 */
<> 144:ef7eb2e8f9f7 1394 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1395 {
<> 144:ef7eb2e8f9f7 1396 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1397 uint16_t uhdata;
<> 144:ef7eb2e8f9f7 1398 uint16_t uhMask = hirda->Mask;
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1401 {
<> 144:ef7eb2e8f9f7 1402 uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
<> 144:ef7eb2e8f9f7 1403 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1404 {
<> 144:ef7eb2e8f9f7 1405 tmp = (uint16_t*) hirda->pRxBuffPtr ;
<> 144:ef7eb2e8f9f7 1406 *tmp = (uint16_t)(uhdata & uhMask);
<> 144:ef7eb2e8f9f7 1407 hirda->pRxBuffPtr +=2U;
<> 144:ef7eb2e8f9f7 1408 }
<> 144:ef7eb2e8f9f7 1409 else
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 1412 }
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 if(--hirda->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1415 {
<> 144:ef7eb2e8f9f7 1416 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* Disable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 1419 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 1422 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /* Rx process is completed, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1425 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 return HAL_OK;
<> 144:ef7eb2e8f9f7 1430 }
<> 144:ef7eb2e8f9f7 1431 return HAL_OK;
<> 144:ef7eb2e8f9f7 1432 }
<> 144:ef7eb2e8f9f7 1433 else
<> 144:ef7eb2e8f9f7 1434 {
<> 144:ef7eb2e8f9f7 1435 /* Clear RXNE interrupt flag */
<> 144:ef7eb2e8f9f7 1436 __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
<> 144:ef7eb2e8f9f7 1437 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /**
<> 144:ef7eb2e8f9f7 1442 * @brief DMA IRDA Tx transfer completed callback
<> 144:ef7eb2e8f9f7 1443 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1444 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1445 * @retval None
<> 144:ef7eb2e8f9f7 1446 */
<> 144:ef7eb2e8f9f7 1447 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1448 {
<> 144:ef7eb2e8f9f7 1449 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /* DMA Normal mode*/
<> 144:ef7eb2e8f9f7 1452 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1453 {
<> 144:ef7eb2e8f9f7 1454 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 /* Disable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1457 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1458 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1459
<> 144:ef7eb2e8f9f7 1460 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1461 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1462 }
<> 144:ef7eb2e8f9f7 1463 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 1464 else
<> 144:ef7eb2e8f9f7 1465 {
<> 144:ef7eb2e8f9f7 1466 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1467 }
<> 144:ef7eb2e8f9f7 1468 }
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 /**
<> 144:ef7eb2e8f9f7 1471 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1472 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1473 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1474 * @retval None
<> 144:ef7eb2e8f9f7 1475 */
<> 144:ef7eb2e8f9f7 1476 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1477 {
<> 144:ef7eb2e8f9f7 1478 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 HAL_IRDA_TxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1481 }
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 /**
<> 144:ef7eb2e8f9f7 1484 * @brief DMA IRDA Rx Transfer completed callback
<> 144:ef7eb2e8f9f7 1485 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1486 * @retval None
<> 144:ef7eb2e8f9f7 1487 */
<> 144:ef7eb2e8f9f7 1488 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1489 {
<> 144:ef7eb2e8f9f7 1490 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1493 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1494 {
<> 144:ef7eb2e8f9f7 1495 hirda->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 1498 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 1499 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /* Disable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1502 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1503 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1506 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1507 }
<> 144:ef7eb2e8f9f7 1508
<> 144:ef7eb2e8f9f7 1509 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1510 }
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 /**
<> 144:ef7eb2e8f9f7 1513 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1514 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1515 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1516 * @retval None
<> 144:ef7eb2e8f9f7 1517 */
<> 144:ef7eb2e8f9f7 1518 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1519 {
<> 144:ef7eb2e8f9f7 1520 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 HAL_IRDA_RxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1523 }
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /**
<> 144:ef7eb2e8f9f7 1526 * @brief DMA IRDA communication error callback
<> 144:ef7eb2e8f9f7 1527 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1528 * @retval None
<> 144:ef7eb2e8f9f7 1529 */
<> 144:ef7eb2e8f9f7 1530 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1531 {
<> 144:ef7eb2e8f9f7 1532 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 hirda->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1535 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 /* Stop IRDA DMA Tx request if ongoing */
<> 144:ef7eb2e8f9f7 1538 if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1539 &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
<> 144:ef7eb2e8f9f7 1540 {
<> 144:ef7eb2e8f9f7 1541 IRDA_EndTxTransfer(hirda);
<> 144:ef7eb2e8f9f7 1542 }
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Stop IRDA DMA Rx request if ongoing */
<> 144:ef7eb2e8f9f7 1545 if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1546 &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
<> 144:ef7eb2e8f9f7 1547 {
<> 144:ef7eb2e8f9f7 1548 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 1549 }
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1554 }
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /**
<> 144:ef7eb2e8f9f7 1557 * @}
<> 144:ef7eb2e8f9f7 1558 */
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /**
<> 144:ef7eb2e8f9f7 1561 * @}
<> 144:ef7eb2e8f9f7 1562 */
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 #endif /* HAL_IRDA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /**
<> 144:ef7eb2e8f9f7 1567 * @}
<> 144:ef7eb2e8f9f7 1568 */
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1571