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targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f303xe.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/stm32f303xe.h@147:30b64687e01f
Child:
154:37f96f9d4de2
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 147:30b64687e01f 1 /**
<> 147:30b64687e01f 2 ******************************************************************************
<> 147:30b64687e01f 3 * @file stm32f303xe.h
<> 147:30b64687e01f 4 * @author MCD Application Team
<> 147:30b64687e01f 5 * @version V2.3.0
<> 147:30b64687e01f 6 * @date 29-April-2015
<> 147:30b64687e01f 7 * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
<> 147:30b64687e01f 8 *
<> 147:30b64687e01f 9 * This file contains:
<> 147:30b64687e01f 10 * - Data structures and the address mapping for all peripherals
<> 147:30b64687e01f 11 * - Peripheral's registers declarations and bits definition
<> 147:30b64687e01f 12 * - Macros to access peripheral’s registers hardware
<> 147:30b64687e01f 13 *
<> 147:30b64687e01f 14 ******************************************************************************
<> 147:30b64687e01f 15 * @attention
<> 147:30b64687e01f 16 *
<> 147:30b64687e01f 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 147:30b64687e01f 18 *
<> 147:30b64687e01f 19 * Redistribution and use in source and binary forms, with or without modification,
<> 147:30b64687e01f 20 * are permitted provided that the following conditions are met:
<> 147:30b64687e01f 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 147:30b64687e01f 22 * this list of conditions and the following disclaimer.
<> 147:30b64687e01f 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 147:30b64687e01f 24 * this list of conditions and the following disclaimer in the documentation
<> 147:30b64687e01f 25 * and/or other materials provided with the distribution.
<> 147:30b64687e01f 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 147:30b64687e01f 27 * may be used to endorse or promote products derived from this software
<> 147:30b64687e01f 28 * without specific prior written permission.
<> 147:30b64687e01f 29 *
<> 147:30b64687e01f 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 147:30b64687e01f 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 147:30b64687e01f 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 147:30b64687e01f 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 147:30b64687e01f 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 147:30b64687e01f 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 147:30b64687e01f 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 147:30b64687e01f 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 147:30b64687e01f 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 147:30b64687e01f 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 147:30b64687e01f 40 *
<> 147:30b64687e01f 41 ******************************************************************************
<> 147:30b64687e01f 42 */
<> 147:30b64687e01f 43
<> 147:30b64687e01f 44 /** @addtogroup CMSIS_Device
<> 147:30b64687e01f 45 * @{
<> 147:30b64687e01f 46 */
<> 147:30b64687e01f 47
<> 147:30b64687e01f 48 /** @addtogroup stm32f303xe
<> 147:30b64687e01f 49 * @{
<> 147:30b64687e01f 50 */
<> 147:30b64687e01f 51
<> 147:30b64687e01f 52 #ifndef __STM32F303xE_H
<> 147:30b64687e01f 53 #define __STM32F303xE_H
<> 147:30b64687e01f 54
<> 147:30b64687e01f 55 #ifdef __cplusplus
<> 147:30b64687e01f 56 extern "C" {
<> 147:30b64687e01f 57 #endif /* __cplusplus */
<> 147:30b64687e01f 58
<> 147:30b64687e01f 59 /** @addtogroup Configuration_section_for_CMSIS
<> 147:30b64687e01f 60 * @{
<> 147:30b64687e01f 61 */
<> 147:30b64687e01f 62
<> 147:30b64687e01f 63 /**
<> 147:30b64687e01f 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
<> 147:30b64687e01f 65 */
<> 147:30b64687e01f 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
<> 147:30b64687e01f 67 #define __MPU_PRESENT 1U /*!< STM32F303xE devices provide an MPU */
<> 147:30b64687e01f 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
<> 147:30b64687e01f 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 147:30b64687e01f 70 #ifndef __FPU_PRESENT
<> 147:30b64687e01f 71 #define __FPU_PRESENT 1U /*!< STM32F303xE devices provide an FPU */
<> 147:30b64687e01f 72 #endif
<> 147:30b64687e01f 73 /**
<> 147:30b64687e01f 74 * @}
<> 147:30b64687e01f 75 */
<> 147:30b64687e01f 76
<> 147:30b64687e01f 77 /** @addtogroup Peripheral_interrupt_number_definition
<> 147:30b64687e01f 78 * @{
<> 147:30b64687e01f 79 */
<> 147:30b64687e01f 80
<> 147:30b64687e01f 81 /**
<> 147:30b64687e01f 82 * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
<> 147:30b64687e01f 83 * in @ref Library_configuration_section
<> 147:30b64687e01f 84 */
<> 147:30b64687e01f 85 typedef enum
<> 147:30b64687e01f 86 {
<> 147:30b64687e01f 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
<> 147:30b64687e01f 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 147:30b64687e01f 89 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
<> 147:30b64687e01f 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
<> 147:30b64687e01f 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
<> 147:30b64687e01f 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
<> 147:30b64687e01f 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
<> 147:30b64687e01f 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
<> 147:30b64687e01f 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
<> 147:30b64687e01f 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
<> 147:30b64687e01f 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 147:30b64687e01f 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 147:30b64687e01f 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 147:30b64687e01f 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
<> 147:30b64687e01f 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
<> 147:30b64687e01f 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 147:30b64687e01f 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 147:30b64687e01f 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 147:30b64687e01f 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 147:30b64687e01f 106 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
<> 147:30b64687e01f 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 147:30b64687e01f 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 147:30b64687e01f 109 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
<> 147:30b64687e01f 110 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
<> 147:30b64687e01f 111 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
<> 147:30b64687e01f 112 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
<> 147:30b64687e01f 113 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
<> 147:30b64687e01f 114 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
<> 147:30b64687e01f 115 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
<> 147:30b64687e01f 116 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
<> 147:30b64687e01f 117 USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
<> 147:30b64687e01f 118 USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
<> 147:30b64687e01f 119 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
<> 147:30b64687e01f 120 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
<> 147:30b64687e01f 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 147:30b64687e01f 122 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
<> 147:30b64687e01f 123 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
<> 147:30b64687e01f 124 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
<> 147:30b64687e01f 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 147:30b64687e01f 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 147:30b64687e01f 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 147:30b64687e01f 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 147:30b64687e01f 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
<> 147:30b64687e01f 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 147:30b64687e01f 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
<> 147:30b64687e01f 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 147:30b64687e01f 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 147:30b64687e01f 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 147:30b64687e01f 135 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
<> 147:30b64687e01f 136 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
<> 147:30b64687e01f 137 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
<> 147:30b64687e01f 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 147:30b64687e01f 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
<> 147:30b64687e01f 140 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
<> 147:30b64687e01f 141 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
<> 147:30b64687e01f 142 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
<> 147:30b64687e01f 143 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
<> 147:30b64687e01f 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
<> 147:30b64687e01f 145 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
<> 147:30b64687e01f 146 FMC_IRQn = 48, /*!< FMC global Interrupt */
<> 147:30b64687e01f 147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 147:30b64687e01f 148 UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
<> 147:30b64687e01f 149 UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
<> 147:30b64687e01f 150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
<> 147:30b64687e01f 151 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
<> 147:30b64687e01f 152 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
<> 147:30b64687e01f 153 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
<> 147:30b64687e01f 154 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
<> 147:30b64687e01f 155 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
<> 147:30b64687e01f 156 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
<> 147:30b64687e01f 157 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
<> 147:30b64687e01f 158 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
<> 147:30b64687e01f 159 COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
<> 147:30b64687e01f 160 COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
<> 147:30b64687e01f 161 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 147:30b64687e01f 162 I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
<> 147:30b64687e01f 163 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
<> 147:30b64687e01f 164 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
<> 147:30b64687e01f 165 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
<> 147:30b64687e01f 166 TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
<> 147:30b64687e01f 167 TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
<> 147:30b64687e01f 168 TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
<> 147:30b64687e01f 169 TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
<> 147:30b64687e01f 170 FPU_IRQn = 81, /*!< Floating point Interrupt */
<> 147:30b64687e01f 171 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
<> 147:30b64687e01f 172 } IRQn_Type;
<> 147:30b64687e01f 173
<> 147:30b64687e01f 174 /**
<> 147:30b64687e01f 175 * @}
<> 147:30b64687e01f 176 */
<> 147:30b64687e01f 177
<> 147:30b64687e01f 178 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 147:30b64687e01f 179 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
<> 147:30b64687e01f 180 #include <stdint.h>
<> 147:30b64687e01f 181
<> 147:30b64687e01f 182 /** @addtogroup Peripheral_registers_structures
<> 147:30b64687e01f 183 * @{
<> 147:30b64687e01f 184 */
<> 147:30b64687e01f 185
<> 147:30b64687e01f 186 /**
<> 147:30b64687e01f 187 * @brief Analog to Digital Converter
<> 147:30b64687e01f 188 */
<> 147:30b64687e01f 189
<> 147:30b64687e01f 190 typedef struct
<> 147:30b64687e01f 191 {
<> 147:30b64687e01f 192 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
<> 147:30b64687e01f 193 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
<> 147:30b64687e01f 194 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
<> 147:30b64687e01f 195 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
<> 147:30b64687e01f 196 uint32_t RESERVED0; /*!< Reserved, 0x010 */
<> 147:30b64687e01f 197 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
<> 147:30b64687e01f 198 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
<> 147:30b64687e01f 199 uint32_t RESERVED1; /*!< Reserved, 0x01C */
<> 147:30b64687e01f 200 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
<> 147:30b64687e01f 201 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
<> 147:30b64687e01f 202 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
<> 147:30b64687e01f 203 uint32_t RESERVED2; /*!< Reserved, 0x02C */
<> 147:30b64687e01f 204 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
<> 147:30b64687e01f 205 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
<> 147:30b64687e01f 206 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
<> 147:30b64687e01f 207 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
<> 147:30b64687e01f 208 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
<> 147:30b64687e01f 209 uint32_t RESERVED3; /*!< Reserved, 0x044 */
<> 147:30b64687e01f 210 uint32_t RESERVED4; /*!< Reserved, 0x048 */
<> 147:30b64687e01f 211 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
<> 147:30b64687e01f 212 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
<> 147:30b64687e01f 213 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
<> 147:30b64687e01f 214 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
<> 147:30b64687e01f 215 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
<> 147:30b64687e01f 216 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
<> 147:30b64687e01f 217 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
<> 147:30b64687e01f 218 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
<> 147:30b64687e01f 219 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
<> 147:30b64687e01f 220 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
<> 147:30b64687e01f 221 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
<> 147:30b64687e01f 222 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
<> 147:30b64687e01f 223 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
<> 147:30b64687e01f 224 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
<> 147:30b64687e01f 225 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
<> 147:30b64687e01f 226 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
<> 147:30b64687e01f 227 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
<> 147:30b64687e01f 228 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
<> 147:30b64687e01f 229
<> 147:30b64687e01f 230 } ADC_TypeDef;
<> 147:30b64687e01f 231
<> 147:30b64687e01f 232 typedef struct
<> 147:30b64687e01f 233 {
<> 147:30b64687e01f 234 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
<> 147:30b64687e01f 235 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
<> 147:30b64687e01f 236 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
<> 147:30b64687e01f 237 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 147:30b64687e01f 238 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
<> 147:30b64687e01f 239 } ADC_Common_TypeDef;
<> 147:30b64687e01f 240
<> 147:30b64687e01f 241 /**
<> 147:30b64687e01f 242 * @brief Controller Area Network TxMailBox
<> 147:30b64687e01f 243 */
<> 147:30b64687e01f 244 typedef struct
<> 147:30b64687e01f 245 {
<> 147:30b64687e01f 246 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
<> 147:30b64687e01f 247 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
<> 147:30b64687e01f 248 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
<> 147:30b64687e01f 249 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
<> 147:30b64687e01f 250 } CAN_TxMailBox_TypeDef;
<> 147:30b64687e01f 251
<> 147:30b64687e01f 252 /**
<> 147:30b64687e01f 253 * @brief Controller Area Network FIFOMailBox
<> 147:30b64687e01f 254 */
<> 147:30b64687e01f 255 typedef struct
<> 147:30b64687e01f 256 {
<> 147:30b64687e01f 257 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
<> 147:30b64687e01f 258 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
<> 147:30b64687e01f 259 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
<> 147:30b64687e01f 260 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
<> 147:30b64687e01f 261 } CAN_FIFOMailBox_TypeDef;
<> 147:30b64687e01f 262
<> 147:30b64687e01f 263 /**
<> 147:30b64687e01f 264 * @brief Controller Area Network FilterRegister
<> 147:30b64687e01f 265 */
<> 147:30b64687e01f 266 typedef struct
<> 147:30b64687e01f 267 {
<> 147:30b64687e01f 268 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
<> 147:30b64687e01f 269 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
<> 147:30b64687e01f 270 } CAN_FilterRegister_TypeDef;
<> 147:30b64687e01f 271
<> 147:30b64687e01f 272 /**
<> 147:30b64687e01f 273 * @brief Controller Area Network
<> 147:30b64687e01f 274 */
<> 147:30b64687e01f 275 typedef struct
<> 147:30b64687e01f 276 {
<> 147:30b64687e01f 277 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
<> 147:30b64687e01f 278 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
<> 147:30b64687e01f 279 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
<> 147:30b64687e01f 280 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
<> 147:30b64687e01f 281 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
<> 147:30b64687e01f 282 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
<> 147:30b64687e01f 283 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
<> 147:30b64687e01f 284 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
<> 147:30b64687e01f 285 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
<> 147:30b64687e01f 286 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
<> 147:30b64687e01f 287 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
<> 147:30b64687e01f 288 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
<> 147:30b64687e01f 289 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
<> 147:30b64687e01f 290 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
<> 147:30b64687e01f 291 uint32_t RESERVED2; /*!< Reserved, 0x208 */
<> 147:30b64687e01f 292 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
<> 147:30b64687e01f 293 uint32_t RESERVED3; /*!< Reserved, 0x210 */
<> 147:30b64687e01f 294 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
<> 147:30b64687e01f 295 uint32_t RESERVED4; /*!< Reserved, 0x218 */
<> 147:30b64687e01f 296 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
<> 147:30b64687e01f 297 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
<> 147:30b64687e01f 298 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
<> 147:30b64687e01f 299 } CAN_TypeDef;
<> 147:30b64687e01f 300
<> 147:30b64687e01f 301 /**
<> 147:30b64687e01f 302 * @brief Analog Comparators
<> 147:30b64687e01f 303 */
<> 147:30b64687e01f 304 typedef struct
<> 147:30b64687e01f 305 {
<> 147:30b64687e01f 306 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
<> 147:30b64687e01f 307 } COMP_TypeDef;
<> 147:30b64687e01f 308
<> 147:30b64687e01f 309 typedef struct
<> 147:30b64687e01f 310 {
<> 147:30b64687e01f 311 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
<> 147:30b64687e01f 312 } COMP_Common_TypeDef;
<> 147:30b64687e01f 313
<> 147:30b64687e01f 314 /**
<> 147:30b64687e01f 315 * @brief CRC calculation unit
<> 147:30b64687e01f 316 */
<> 147:30b64687e01f 317
<> 147:30b64687e01f 318 typedef struct
<> 147:30b64687e01f 319 {
<> 147:30b64687e01f 320 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 147:30b64687e01f 321 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 147:30b64687e01f 322 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 147:30b64687e01f 323 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 147:30b64687e01f 324 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 147:30b64687e01f 325 uint32_t RESERVED2; /*!< Reserved, 0x0C */
<> 147:30b64687e01f 326 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
<> 147:30b64687e01f 327 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
<> 147:30b64687e01f 328 } CRC_TypeDef;
<> 147:30b64687e01f 329
<> 147:30b64687e01f 330 /**
<> 147:30b64687e01f 331 * @brief Digital to Analog Converter
<> 147:30b64687e01f 332 */
<> 147:30b64687e01f 333
<> 147:30b64687e01f 334 typedef struct
<> 147:30b64687e01f 335 {
<> 147:30b64687e01f 336 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 147:30b64687e01f 337 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 147:30b64687e01f 338 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 147:30b64687e01f 339 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 147:30b64687e01f 340 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 147:30b64687e01f 341 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 147:30b64687e01f 342 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 147:30b64687e01f 343 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 147:30b64687e01f 344 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 147:30b64687e01f 345 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 147:30b64687e01f 346 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 147:30b64687e01f 347 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 147:30b64687e01f 348 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 147:30b64687e01f 349 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 147:30b64687e01f 350 } DAC_TypeDef;
<> 147:30b64687e01f 351
<> 147:30b64687e01f 352 /**
<> 147:30b64687e01f 353 * @brief Debug MCU
<> 147:30b64687e01f 354 */
<> 147:30b64687e01f 355
<> 147:30b64687e01f 356 typedef struct
<> 147:30b64687e01f 357 {
<> 147:30b64687e01f 358 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 147:30b64687e01f 359 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 360 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 147:30b64687e01f 361 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 147:30b64687e01f 362 }DBGMCU_TypeDef;
<> 147:30b64687e01f 363
<> 147:30b64687e01f 364 /**
<> 147:30b64687e01f 365 * @brief DMA Controller
<> 147:30b64687e01f 366 */
<> 147:30b64687e01f 367
<> 147:30b64687e01f 368 typedef struct
<> 147:30b64687e01f 369 {
<> 147:30b64687e01f 370 __IO uint32_t CCR; /*!< DMA channel x configuration register */
<> 147:30b64687e01f 371 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
<> 147:30b64687e01f 372 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
<> 147:30b64687e01f 373 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
<> 147:30b64687e01f 374 } DMA_Channel_TypeDef;
<> 147:30b64687e01f 375
<> 147:30b64687e01f 376 typedef struct
<> 147:30b64687e01f 377 {
<> 147:30b64687e01f 378 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
<> 147:30b64687e01f 379 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
<> 147:30b64687e01f 380 } DMA_TypeDef;
<> 147:30b64687e01f 381
<> 147:30b64687e01f 382 /**
<> 147:30b64687e01f 383 * @brief External Interrupt/Event Controller
<> 147:30b64687e01f 384 */
<> 147:30b64687e01f 385
<> 147:30b64687e01f 386 typedef struct
<> 147:30b64687e01f 387 {
<> 147:30b64687e01f 388 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
<> 147:30b64687e01f 389 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
<> 147:30b64687e01f 390 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
<> 147:30b64687e01f 391 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
<> 147:30b64687e01f 392 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
<> 147:30b64687e01f 393 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
<> 147:30b64687e01f 394 uint32_t RESERVED1; /*!< Reserved, 0x18 */
<> 147:30b64687e01f 395 uint32_t RESERVED2; /*!< Reserved, 0x1C */
<> 147:30b64687e01f 396 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
<> 147:30b64687e01f 397 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
<> 147:30b64687e01f 398 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
<> 147:30b64687e01f 399 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
<> 147:30b64687e01f 400 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
<> 147:30b64687e01f 401 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
<> 147:30b64687e01f 402 }EXTI_TypeDef;
<> 147:30b64687e01f 403
<> 147:30b64687e01f 404 /**
<> 147:30b64687e01f 405 * @brief FLASH Registers
<> 147:30b64687e01f 406 */
<> 147:30b64687e01f 407
<> 147:30b64687e01f 408 typedef struct
<> 147:30b64687e01f 409 {
<> 147:30b64687e01f 410 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 147:30b64687e01f 411 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 147:30b64687e01f 412 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 147:30b64687e01f 413 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 147:30b64687e01f 414 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 147:30b64687e01f 415 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
<> 147:30b64687e01f 416 uint32_t RESERVED; /*!< Reserved, 0x18 */
<> 147:30b64687e01f 417 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
<> 147:30b64687e01f 418 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
<> 147:30b64687e01f 419
<> 147:30b64687e01f 420 } FLASH_TypeDef;
<> 147:30b64687e01f 421
<> 147:30b64687e01f 422 /**
<> 147:30b64687e01f 423 * @brief Flexible Memory Controller
<> 147:30b64687e01f 424 */
<> 147:30b64687e01f 425
<> 147:30b64687e01f 426 typedef struct
<> 147:30b64687e01f 427 {
<> 147:30b64687e01f 428 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
<> 147:30b64687e01f 429 } FMC_Bank1_TypeDef;
<> 147:30b64687e01f 430
<> 147:30b64687e01f 431 /**
<> 147:30b64687e01f 432 * @brief Flexible Memory Controller Bank1E
<> 147:30b64687e01f 433 */
<> 147:30b64687e01f 434
<> 147:30b64687e01f 435 typedef struct
<> 147:30b64687e01f 436 {
<> 147:30b64687e01f 437 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
<> 147:30b64687e01f 438 } FMC_Bank1E_TypeDef;
<> 147:30b64687e01f 439
<> 147:30b64687e01f 440 /**
<> 147:30b64687e01f 441 * @brief Flexible Memory Controller Bank2
<> 147:30b64687e01f 442 */
<> 147:30b64687e01f 443
<> 147:30b64687e01f 444 typedef struct
<> 147:30b64687e01f 445 {
<> 147:30b64687e01f 446 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
<> 147:30b64687e01f 447 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
<> 147:30b64687e01f 448 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
<> 147:30b64687e01f 449 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
<> 147:30b64687e01f 450 uint32_t RESERVED0; /*!< Reserved, 0x70 */
<> 147:30b64687e01f 451 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
<> 147:30b64687e01f 452 uint32_t RESERVED1; /*!< Reserved, 0x78 */
<> 147:30b64687e01f 453 uint32_t RESERVED2; /*!< Reserved, 0x7C */
<> 147:30b64687e01f 454 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
<> 147:30b64687e01f 455 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
<> 147:30b64687e01f 456 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
<> 147:30b64687e01f 457 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
<> 147:30b64687e01f 458 uint32_t RESERVED3; /*!< Reserved, 0x90 */
<> 147:30b64687e01f 459 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
<> 147:30b64687e01f 460 } FMC_Bank2_3_TypeDef;
<> 147:30b64687e01f 461
<> 147:30b64687e01f 462 /**
<> 147:30b64687e01f 463 * @brief Flexible Memory Controller Bank4
<> 147:30b64687e01f 464 */
<> 147:30b64687e01f 465
<> 147:30b64687e01f 466 typedef struct
<> 147:30b64687e01f 467 {
<> 147:30b64687e01f 468 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
<> 147:30b64687e01f 469 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
<> 147:30b64687e01f 470 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
<> 147:30b64687e01f 471 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
<> 147:30b64687e01f 472 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
<> 147:30b64687e01f 473 } FMC_Bank4_TypeDef;
<> 147:30b64687e01f 474
<> 147:30b64687e01f 475 /**
<> 147:30b64687e01f 476 * @brief Option Bytes Registers
<> 147:30b64687e01f 477 */
<> 147:30b64687e01f 478 typedef struct
<> 147:30b64687e01f 479 {
<> 147:30b64687e01f 480 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
<> 147:30b64687e01f 481 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
<> 147:30b64687e01f 482 uint16_t RESERVED0; /*!< Reserved, 0x04 */
<> 147:30b64687e01f 483 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 147:30b64687e01f 484 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
<> 147:30b64687e01f 485 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
<> 147:30b64687e01f 486 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
<> 147:30b64687e01f 487 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
<> 147:30b64687e01f 488 } OB_TypeDef;
<> 147:30b64687e01f 489
<> 147:30b64687e01f 490 /**
<> 147:30b64687e01f 491 * @brief General Purpose I/O
<> 147:30b64687e01f 492 */
<> 147:30b64687e01f 493
<> 147:30b64687e01f 494 typedef struct
<> 147:30b64687e01f 495 {
<> 147:30b64687e01f 496 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 147:30b64687e01f 497 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 147:30b64687e01f 498 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 147:30b64687e01f 499 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 147:30b64687e01f 500 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 147:30b64687e01f 501 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 147:30b64687e01f 502 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
<> 147:30b64687e01f 503 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 147:30b64687e01f 504 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 147:30b64687e01f 505 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
<> 147:30b64687e01f 506 }GPIO_TypeDef;
<> 147:30b64687e01f 507
<> 147:30b64687e01f 508 /**
<> 147:30b64687e01f 509 * @brief Operational Amplifier (OPAMP)
<> 147:30b64687e01f 510 */
<> 147:30b64687e01f 511
<> 147:30b64687e01f 512 typedef struct
<> 147:30b64687e01f 513 {
<> 147:30b64687e01f 514 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
<> 147:30b64687e01f 515 } OPAMP_TypeDef;
<> 147:30b64687e01f 516
<> 147:30b64687e01f 517 /**
<> 147:30b64687e01f 518 * @brief System configuration controller
<> 147:30b64687e01f 519 */
<> 147:30b64687e01f 520
<> 147:30b64687e01f 521 typedef struct
<> 147:30b64687e01f 522 {
<> 147:30b64687e01f 523 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
<> 147:30b64687e01f 524 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
<> 147:30b64687e01f 525 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
<> 147:30b64687e01f 526 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
<> 147:30b64687e01f 527 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 147:30b64687e01f 528 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
<> 147:30b64687e01f 529 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
<> 147:30b64687e01f 530 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
<> 147:30b64687e01f 531 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
<> 147:30b64687e01f 532 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
<> 147:30b64687e01f 533 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
<> 147:30b64687e01f 534 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
<> 147:30b64687e01f 535 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
<> 147:30b64687e01f 536 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
<> 147:30b64687e01f 537 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
<> 147:30b64687e01f 538 __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */
<> 147:30b64687e01f 539 __IO uint32_t RESERVED12; /*!< Reserved, 0x4C */
<> 147:30b64687e01f 540 __IO uint32_t RESERVED13; /*!< Reserved, 0x50 */
<> 147:30b64687e01f 541 } SYSCFG_TypeDef;
<> 147:30b64687e01f 542
<> 147:30b64687e01f 543 /**
<> 147:30b64687e01f 544 * @brief Inter-integrated Circuit Interface
<> 147:30b64687e01f 545 */
<> 147:30b64687e01f 546
<> 147:30b64687e01f 547 typedef struct
<> 147:30b64687e01f 548 {
<> 147:30b64687e01f 549 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 550 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 551 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
<> 147:30b64687e01f 552 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
<> 147:30b64687e01f 553 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
<> 147:30b64687e01f 554 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
<> 147:30b64687e01f 555 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
<> 147:30b64687e01f 556 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
<> 147:30b64687e01f 557 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
<> 147:30b64687e01f 558 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
<> 147:30b64687e01f 559 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
<> 147:30b64687e01f 560 }I2C_TypeDef;
<> 147:30b64687e01f 561
<> 147:30b64687e01f 562 /**
<> 147:30b64687e01f 563 * @brief Independent WATCHDOG
<> 147:30b64687e01f 564 */
<> 147:30b64687e01f 565
<> 147:30b64687e01f 566 typedef struct
<> 147:30b64687e01f 567 {
<> 147:30b64687e01f 568 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 147:30b64687e01f 569 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 147:30b64687e01f 570 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 147:30b64687e01f 571 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 147:30b64687e01f 572 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
<> 147:30b64687e01f 573 } IWDG_TypeDef;
<> 147:30b64687e01f 574
<> 147:30b64687e01f 575 /**
<> 147:30b64687e01f 576 * @brief Power Control
<> 147:30b64687e01f 577 */
<> 147:30b64687e01f 578
<> 147:30b64687e01f 579 typedef struct
<> 147:30b64687e01f 580 {
<> 147:30b64687e01f 581 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 147:30b64687e01f 582 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 147:30b64687e01f 583 } PWR_TypeDef;
<> 147:30b64687e01f 584
<> 147:30b64687e01f 585 /**
<> 147:30b64687e01f 586 * @brief Reset and Clock Control
<> 147:30b64687e01f 587 */
<> 147:30b64687e01f 588 typedef struct
<> 147:30b64687e01f 589 {
<> 147:30b64687e01f 590 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 147:30b64687e01f 591 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 592 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
<> 147:30b64687e01f 593 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
<> 147:30b64687e01f 594 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
<> 147:30b64687e01f 595 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
<> 147:30b64687e01f 596 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
<> 147:30b64687e01f 597 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
<> 147:30b64687e01f 598 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
<> 147:30b64687e01f 599 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
<> 147:30b64687e01f 600 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
<> 147:30b64687e01f 601 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
<> 147:30b64687e01f 602 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
<> 147:30b64687e01f 603 } RCC_TypeDef;
<> 147:30b64687e01f 604
<> 147:30b64687e01f 605 /**
<> 147:30b64687e01f 606 * @brief Real-Time Clock
<> 147:30b64687e01f 607 */
<> 147:30b64687e01f 608
<> 147:30b64687e01f 609 typedef struct
<> 147:30b64687e01f 610 {
<> 147:30b64687e01f 611 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 147:30b64687e01f 612 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 147:30b64687e01f 613 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 147:30b64687e01f 614 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 147:30b64687e01f 615 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 147:30b64687e01f 616 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 147:30b64687e01f 617 uint32_t RESERVED0; /*!< Reserved, 0x18 */
<> 147:30b64687e01f 618 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 147:30b64687e01f 619 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 147:30b64687e01f 620 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 147:30b64687e01f 621 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 147:30b64687e01f 622 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 147:30b64687e01f 623 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 147:30b64687e01f 624 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 147:30b64687e01f 625 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 147:30b64687e01f 626 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 147:30b64687e01f 627 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 147:30b64687e01f 628 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 147:30b64687e01f 629 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 147:30b64687e01f 630 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 147:30b64687e01f 631 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
<> 147:30b64687e01f 632 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 147:30b64687e01f 633 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 147:30b64687e01f 634 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 147:30b64687e01f 635 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 147:30b64687e01f 636 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 147:30b64687e01f 637 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 147:30b64687e01f 638 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 147:30b64687e01f 639 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 147:30b64687e01f 640 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 147:30b64687e01f 641 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 147:30b64687e01f 642 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 147:30b64687e01f 643 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 147:30b64687e01f 644 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 147:30b64687e01f 645 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 147:30b64687e01f 646 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 147:30b64687e01f 647 } RTC_TypeDef;
<> 147:30b64687e01f 648
<> 147:30b64687e01f 649
<> 147:30b64687e01f 650 /**
<> 147:30b64687e01f 651 * @brief Serial Peripheral Interface
<> 147:30b64687e01f 652 */
<> 147:30b64687e01f 653
<> 147:30b64687e01f 654 typedef struct
<> 147:30b64687e01f 655 {
<> 147:30b64687e01f 656 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 657 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 658 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
<> 147:30b64687e01f 659 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 147:30b64687e01f 660 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
<> 147:30b64687e01f 661 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
<> 147:30b64687e01f 662 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
<> 147:30b64687e01f 663 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 147:30b64687e01f 664 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 147:30b64687e01f 665 } SPI_TypeDef;
<> 147:30b64687e01f 666
<> 147:30b64687e01f 667 /**
<> 147:30b64687e01f 668 * @brief TIM
<> 147:30b64687e01f 669 */
<> 147:30b64687e01f 670 typedef struct
<> 147:30b64687e01f 671 {
<> 147:30b64687e01f 672 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 673 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 674 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 147:30b64687e01f 675 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 147:30b64687e01f 676 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 147:30b64687e01f 677 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 147:30b64687e01f 678 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 147:30b64687e01f 679 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 147:30b64687e01f 680 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 147:30b64687e01f 681 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 147:30b64687e01f 682 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 147:30b64687e01f 683 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 147:30b64687e01f 684 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 147:30b64687e01f 685 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 147:30b64687e01f 686 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 147:30b64687e01f 687 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 147:30b64687e01f 688 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 147:30b64687e01f 689 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 147:30b64687e01f 690 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 147:30b64687e01f 691 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 147:30b64687e01f 692 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 147:30b64687e01f 693 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
<> 147:30b64687e01f 694 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
<> 147:30b64687e01f 695 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
<> 147:30b64687e01f 696 } TIM_TypeDef;
<> 147:30b64687e01f 697
<> 147:30b64687e01f 698 /**
<> 147:30b64687e01f 699 * @brief Touch Sensing Controller (TSC)
<> 147:30b64687e01f 700 */
<> 147:30b64687e01f 701 typedef struct
<> 147:30b64687e01f 702 {
<> 147:30b64687e01f 703 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
<> 147:30b64687e01f 704 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
<> 147:30b64687e01f 705 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
<> 147:30b64687e01f 706 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
<> 147:30b64687e01f 707 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
<> 147:30b64687e01f 708 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
<> 147:30b64687e01f 709 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
<> 147:30b64687e01f 710 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
<> 147:30b64687e01f 711 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
<> 147:30b64687e01f 712 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
<> 147:30b64687e01f 713 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
<> 147:30b64687e01f 714 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
<> 147:30b64687e01f 715 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
<> 147:30b64687e01f 716 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
<> 147:30b64687e01f 717 } TSC_TypeDef;
<> 147:30b64687e01f 718
<> 147:30b64687e01f 719 /**
<> 147:30b64687e01f 720 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 147:30b64687e01f 721 */
<> 147:30b64687e01f 722
<> 147:30b64687e01f 723 typedef struct
<> 147:30b64687e01f 724 {
<> 147:30b64687e01f 725 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 726 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 727 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
<> 147:30b64687e01f 728 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
<> 147:30b64687e01f 729 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
<> 147:30b64687e01f 730 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
<> 147:30b64687e01f 731 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
<> 147:30b64687e01f 732 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
<> 147:30b64687e01f 733 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
<> 147:30b64687e01f 734 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
<> 147:30b64687e01f 735 uint16_t RESERVED1; /*!< Reserved, 0x26 */
<> 147:30b64687e01f 736 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
<> 147:30b64687e01f 737 uint16_t RESERVED2; /*!< Reserved, 0x2A */
<> 147:30b64687e01f 738 } USART_TypeDef;
<> 147:30b64687e01f 739
<> 147:30b64687e01f 740 /**
<> 147:30b64687e01f 741 * @brief Universal Serial Bus Full Speed Device
<> 147:30b64687e01f 742 */
<> 147:30b64687e01f 743
<> 147:30b64687e01f 744 typedef struct
<> 147:30b64687e01f 745 {
<> 147:30b64687e01f 746 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
<> 147:30b64687e01f 747 __IO uint16_t RESERVED0; /*!< Reserved */
<> 147:30b64687e01f 748 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
<> 147:30b64687e01f 749 __IO uint16_t RESERVED1; /*!< Reserved */
<> 147:30b64687e01f 750 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
<> 147:30b64687e01f 751 __IO uint16_t RESERVED2; /*!< Reserved */
<> 147:30b64687e01f 752 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
<> 147:30b64687e01f 753 __IO uint16_t RESERVED3; /*!< Reserved */
<> 147:30b64687e01f 754 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
<> 147:30b64687e01f 755 __IO uint16_t RESERVED4; /*!< Reserved */
<> 147:30b64687e01f 756 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
<> 147:30b64687e01f 757 __IO uint16_t RESERVED5; /*!< Reserved */
<> 147:30b64687e01f 758 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
<> 147:30b64687e01f 759 __IO uint16_t RESERVED6; /*!< Reserved */
<> 147:30b64687e01f 760 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
<> 147:30b64687e01f 761 __IO uint16_t RESERVED7[17]; /*!< Reserved */
<> 147:30b64687e01f 762 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
<> 147:30b64687e01f 763 __IO uint16_t RESERVED8; /*!< Reserved */
<> 147:30b64687e01f 764 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
<> 147:30b64687e01f 765 __IO uint16_t RESERVED9; /*!< Reserved */
<> 147:30b64687e01f 766 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
<> 147:30b64687e01f 767 __IO uint16_t RESERVEDA; /*!< Reserved */
<> 147:30b64687e01f 768 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
<> 147:30b64687e01f 769 __IO uint16_t RESERVEDB; /*!< Reserved */
<> 147:30b64687e01f 770 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
<> 147:30b64687e01f 771 __IO uint16_t RESERVEDC; /*!< Reserved */
<> 147:30b64687e01f 772 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
<> 147:30b64687e01f 773 __IO uint16_t RESERVEDD; /*!< Reserved */
<> 147:30b64687e01f 774 } USB_TypeDef;
<> 147:30b64687e01f 775
<> 147:30b64687e01f 776 /**
<> 147:30b64687e01f 777 * @brief Window WATCHDOG
<> 147:30b64687e01f 778 */
<> 147:30b64687e01f 779 typedef struct
<> 147:30b64687e01f 780 {
<> 147:30b64687e01f 781 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 147:30b64687e01f 782 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 783 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 147:30b64687e01f 784 } WWDG_TypeDef;
<> 147:30b64687e01f 785
<> 147:30b64687e01f 786 /** @addtogroup Peripheral_memory_map
<> 147:30b64687e01f 787 * @{
<> 147:30b64687e01f 788 */
<> 147:30b64687e01f 789
<> 147:30b64687e01f 790 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
<> 147:30b64687e01f 791 #define CCMDATARAM_BASE ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM base address in the alias region */
<> 147:30b64687e01f 792 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
<> 147:30b64687e01f 793 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
<> 147:30b64687e01f 794 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
<> 147:30b64687e01f 795 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC registers base address */
<> 147:30b64687e01f 796
<> 147:30b64687e01f 797 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
<> 147:30b64687e01f 798 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
<> 147:30b64687e01f 799
<> 147:30b64687e01f 800
<> 147:30b64687e01f 801 /*!< Peripheral memory map */
<> 147:30b64687e01f 802 #define APB1PERIPH_BASE PERIPH_BASE
<> 147:30b64687e01f 803 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 147:30b64687e01f 804 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 147:30b64687e01f 805 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
<> 147:30b64687e01f 806 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 147:30b64687e01f 807
<> 147:30b64687e01f 808 /*!< APB1 peripherals */
<> 147:30b64687e01f 809 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
<> 147:30b64687e01f 810 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
<> 147:30b64687e01f 811 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
<> 147:30b64687e01f 812 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
<> 147:30b64687e01f 813 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
<> 147:30b64687e01f 814 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
<> 147:30b64687e01f 815 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
<> 147:30b64687e01f 816 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
<> 147:30b64687e01f 817 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400U)
<> 147:30b64687e01f 818 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
<> 147:30b64687e01f 819 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
<> 147:30b64687e01f 820 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000U)
<> 147:30b64687e01f 821 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
<> 147:30b64687e01f 822 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
<> 147:30b64687e01f 823 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
<> 147:30b64687e01f 824 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
<> 147:30b64687e01f 825 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
<> 147:30b64687e01f 826 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
<> 147:30b64687e01f 827 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
<> 147:30b64687e01f 828 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
<> 147:30b64687e01f 829 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400U)
<> 147:30b64687e01f 830 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
<> 147:30b64687e01f 831 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400U)
<> 147:30b64687e01f 832 #define DAC_BASE DAC1_BASE
<> 147:30b64687e01f 833 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800U)
<> 147:30b64687e01f 834
<> 147:30b64687e01f 835 /*!< APB2 peripherals */
<> 147:30b64687e01f 836 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
<> 147:30b64687e01f 837 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001CU)
<> 147:30b64687e01f 838 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020U)
<> 147:30b64687e01f 839 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024U)
<> 147:30b64687e01f 840 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028U)
<> 147:30b64687e01f 841 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002CU)
<> 147:30b64687e01f 842 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030U)
<> 147:30b64687e01f 843 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034U)
<> 147:30b64687e01f 844 #define COMP_BASE COMP1_BASE
<> 147:30b64687e01f 845 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038U)
<> 147:30b64687e01f 846 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CU)
<> 147:30b64687e01f 847 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040U)
<> 147:30b64687e01f 848 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044U)
<> 147:30b64687e01f 849 #define OPAMP_BASE OPAMP1_BASE
<> 147:30b64687e01f 850 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
<> 147:30b64687e01f 851 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
<> 147:30b64687e01f 852 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
<> 147:30b64687e01f 853 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400U)
<> 147:30b64687e01f 854 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
<> 147:30b64687e01f 855 #define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00U)
<> 147:30b64687e01f 856 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U)
<> 147:30b64687e01f 857 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U)
<> 147:30b64687e01f 858 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U)
<> 147:30b64687e01f 859 #define TIM20_BASE (APB2PERIPH_BASE + 0x00005000U)
<> 147:30b64687e01f 860
<> 147:30b64687e01f 861 /*!< AHB1 peripherals */
<> 147:30b64687e01f 862 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000U)
<> 147:30b64687e01f 863 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008U)
<> 147:30b64687e01f 864 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CU)
<> 147:30b64687e01f 865 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030U)
<> 147:30b64687e01f 866 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044U)
<> 147:30b64687e01f 867 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058U)
<> 147:30b64687e01f 868 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CU)
<> 147:30b64687e01f 869 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080U)
<> 147:30b64687e01f 870 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400U)
<> 147:30b64687e01f 871 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408U)
<> 147:30b64687e01f 872 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CU)
<> 147:30b64687e01f 873 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430U)
<> 147:30b64687e01f 874 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444U)
<> 147:30b64687e01f 875 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458U)
<> 147:30b64687e01f 876 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000U)
<> 147:30b64687e01f 877 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
<> 147:30b64687e01f 878 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< Flash Option Bytes base address */
<> 147:30b64687e01f 879 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
<> 147:30b64687e01f 880 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
<> 147:30b64687e01f 881 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000U)
<> 147:30b64687e01f 882 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000U)
<> 147:30b64687e01f 883
<> 147:30b64687e01f 884 /*!< AHB2 peripherals */
<> 147:30b64687e01f 885 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000U)
<> 147:30b64687e01f 886 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400U)
<> 147:30b64687e01f 887 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800U)
<> 147:30b64687e01f 888 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00U)
<> 147:30b64687e01f 889 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000U)
<> 147:30b64687e01f 890 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400U)
<> 147:30b64687e01f 891 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800U)
<> 147:30b64687e01f 892 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00U)
<> 147:30b64687e01f 893
<> 147:30b64687e01f 894 /*!< AHB3 peripherals */
<> 147:30b64687e01f 895 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000U)
<> 147:30b64687e01f 896 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100U)
<> 147:30b64687e01f 897 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300U)
<> 147:30b64687e01f 898 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400U)
<> 147:30b64687e01f 899 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500U)
<> 147:30b64687e01f 900 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700U)
<> 147:30b64687e01f 901
<> 147:30b64687e01f 902 /*!< FMC Bankx base address */
<> 147:30b64687e01f 903 #define FMC_BANK1 (FMC_BASE) /*!< FMC Bank1 base address */
<> 147:30b64687e01f 904 #define FMC_BANK1_1 (FMC_BANK1) /*!< FMC Bank1_1 base address */
<> 147:30b64687e01f 905 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) /*!< FMC Bank1_2 base address */
<> 147:30b64687e01f 906 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) /*!< FMC Bank1_3 base address */
<> 147:30b64687e01f 907 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) /*!< FMC Bank1_4 base address */
<> 147:30b64687e01f 908
<> 147:30b64687e01f 909 #define FMC_BANK2 (FMC_BASE + 0x10000000U) /*!< FMC Bank2 base address */
<> 147:30b64687e01f 910 #define FMC_BANK3 (FMC_BASE + 0x20000000U) /*!< FMC Bank3 base address */
<> 147:30b64687e01f 911 #define FMC_BANK4 (FMC_BASE + 0x30000000U) /*!< FMC Bank4 base address */
<> 147:30b64687e01f 912
<> 147:30b64687e01f 913 /*!< FMC Bankx registers base address */
<> 147:30b64687e01f 914 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
<> 147:30b64687e01f 915 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
<> 147:30b64687e01f 916 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
<> 147:30b64687e01f 917 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
<> 147:30b64687e01f 918
<> 147:30b64687e01f 919 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
<> 147:30b64687e01f 920 /**
<> 147:30b64687e01f 921 * @}
<> 147:30b64687e01f 922 */
<> 147:30b64687e01f 923
<> 147:30b64687e01f 924 /** @addtogroup Peripheral_declaration
<> 147:30b64687e01f 925 * @{
<> 147:30b64687e01f 926 */
<> 147:30b64687e01f 927 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 147:30b64687e01f 928 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 147:30b64687e01f 929 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 147:30b64687e01f 930 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 147:30b64687e01f 931 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 147:30b64687e01f 932 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 147:30b64687e01f 933 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 147:30b64687e01f 934 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 147:30b64687e01f 935 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
<> 147:30b64687e01f 936 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 147:30b64687e01f 937 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 147:30b64687e01f 938 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
<> 147:30b64687e01f 939 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 147:30b64687e01f 940 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 147:30b64687e01f 941 #define UART4 ((USART_TypeDef *) UART4_BASE)
<> 147:30b64687e01f 942 #define UART5 ((USART_TypeDef *) UART5_BASE)
<> 147:30b64687e01f 943 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 147:30b64687e01f 944 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 147:30b64687e01f 945 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 147:30b64687e01f 946 #define CAN1 ((CAN_TypeDef *) CAN_BASE)
<> 147:30b64687e01f 947 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 147:30b64687e01f 948 #define DAC ((DAC_TypeDef *) DAC_BASE)
<> 147:30b64687e01f 949 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
<> 147:30b64687e01f 950 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
<> 147:30b64687e01f 951 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
<> 147:30b64687e01f 952 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
<> 147:30b64687e01f 953 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
<> 147:30b64687e01f 954 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
<> 147:30b64687e01f 955 #define COMP34_COMMON ((COMP_Common_TypeDef *) COMP4_BASE)
<> 147:30b64687e01f 956 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
<> 147:30b64687e01f 957 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
<> 147:30b64687e01f 958 #define COMP56_COMMON ((COMP_Common_TypeDef *) COMP6_BASE)
<> 147:30b64687e01f 959 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
<> 147:30b64687e01f 960 /* Legacy define */
<> 147:30b64687e01f 961 #define COMP ((COMP_TypeDef *) COMP_BASE)
<> 147:30b64687e01f 962 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
<> 147:30b64687e01f 963 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
<> 147:30b64687e01f 964 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
<> 147:30b64687e01f 965 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
<> 147:30b64687e01f 966 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
<> 147:30b64687e01f 967 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 147:30b64687e01f 968 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 147:30b64687e01f 969 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 147:30b64687e01f 970 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 147:30b64687e01f 971 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
<> 147:30b64687e01f 972 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 147:30b64687e01f 973 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
<> 147:30b64687e01f 974 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
<> 147:30b64687e01f 975 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
<> 147:30b64687e01f 976 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
<> 147:30b64687e01f 977 #define TIM20 ((TIM_TypeDef *) TIM20_BASE)
<> 147:30b64687e01f 978 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 147:30b64687e01f 979 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 147:30b64687e01f 980 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
<> 147:30b64687e01f 981 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
<> 147:30b64687e01f 982 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
<> 147:30b64687e01f 983 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
<> 147:30b64687e01f 984 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
<> 147:30b64687e01f 985 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
<> 147:30b64687e01f 986 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
<> 147:30b64687e01f 987 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 147:30b64687e01f 988 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
<> 147:30b64687e01f 989 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
<> 147:30b64687e01f 990 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
<> 147:30b64687e01f 991 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
<> 147:30b64687e01f 992 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
<> 147:30b64687e01f 993 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 147:30b64687e01f 994 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 147:30b64687e01f 995 #define OB ((OB_TypeDef *) OB_BASE)
<> 147:30b64687e01f 996 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 147:30b64687e01f 997 #define TSC ((TSC_TypeDef *) TSC_BASE)
<> 147:30b64687e01f 998 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 147:30b64687e01f 999 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 147:30b64687e01f 1000 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 147:30b64687e01f 1001 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 147:30b64687e01f 1002 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 147:30b64687e01f 1003 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 147:30b64687e01f 1004 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
<> 147:30b64687e01f 1005 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 147:30b64687e01f 1006 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 147:30b64687e01f 1007 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
<> 147:30b64687e01f 1008 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
<> 147:30b64687e01f 1009 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
<> 147:30b64687e01f 1010 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
<> 147:30b64687e01f 1011 #define ADC34_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
<> 147:30b64687e01f 1012 /* Legacy defines */
<> 147:30b64687e01f 1013 #define ADC1_2_COMMON ADC12_COMMON
<> 147:30b64687e01f 1014 #define ADC3_4_COMMON ADC34_COMMON
<> 147:30b64687e01f 1015 #define USB ((USB_TypeDef *) USB_BASE)
<> 147:30b64687e01f 1016 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
<> 147:30b64687e01f 1017 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
<> 147:30b64687e01f 1018 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
<> 147:30b64687e01f 1019 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
<> 147:30b64687e01f 1020
<> 147:30b64687e01f 1021 /**
<> 147:30b64687e01f 1022 * @}
<> 147:30b64687e01f 1023 */
<> 147:30b64687e01f 1024
<> 147:30b64687e01f 1025 /** @addtogroup Exported_constants
<> 147:30b64687e01f 1026 * @{
<> 147:30b64687e01f 1027 */
<> 147:30b64687e01f 1028
<> 147:30b64687e01f 1029 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 147:30b64687e01f 1030 * @{
<> 147:30b64687e01f 1031 */
<> 147:30b64687e01f 1032
<> 147:30b64687e01f 1033 /******************************************************************************/
<> 147:30b64687e01f 1034 /* Peripheral Registers_Bits_Definition */
<> 147:30b64687e01f 1035 /******************************************************************************/
<> 147:30b64687e01f 1036
<> 147:30b64687e01f 1037 /******************************************************************************/
<> 147:30b64687e01f 1038 /* */
<> 147:30b64687e01f 1039 /* Analog to Digital Converter SAR (ADC) */
<> 147:30b64687e01f 1040 /* */
<> 147:30b64687e01f 1041 /******************************************************************************/
<> 147:30b64687e01f 1042
<> 147:30b64687e01f 1043 #define ADC5_V1_1 /*!< ADC IP version */
<> 147:30b64687e01f 1044
<> 147:30b64687e01f 1045 /*
<> 147:30b64687e01f 1046 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 147:30b64687e01f 1047 */
<> 147:30b64687e01f 1048 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
<> 147:30b64687e01f 1049
<> 147:30b64687e01f 1050 /******************** Bit definition for ADC_ISR register ********************/
<> 147:30b64687e01f 1051 #define ADC_ISR_ADRDY_Pos (0U)
<> 147:30b64687e01f 1052 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1053 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
<> 147:30b64687e01f 1054 #define ADC_ISR_EOSMP_Pos (1U)
<> 147:30b64687e01f 1055 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1056 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
<> 147:30b64687e01f 1057 #define ADC_ISR_EOC_Pos (2U)
<> 147:30b64687e01f 1058 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1059 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
<> 147:30b64687e01f 1060 #define ADC_ISR_EOS_Pos (3U)
<> 147:30b64687e01f 1061 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1062 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
<> 147:30b64687e01f 1063 #define ADC_ISR_OVR_Pos (4U)
<> 147:30b64687e01f 1064 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1065 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
<> 147:30b64687e01f 1066 #define ADC_ISR_JEOC_Pos (5U)
<> 147:30b64687e01f 1067 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1068 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
<> 147:30b64687e01f 1069 #define ADC_ISR_JEOS_Pos (6U)
<> 147:30b64687e01f 1070 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1071 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
<> 147:30b64687e01f 1072 #define ADC_ISR_AWD1_Pos (7U)
<> 147:30b64687e01f 1073 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1074 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
<> 147:30b64687e01f 1075 #define ADC_ISR_AWD2_Pos (8U)
<> 147:30b64687e01f 1076 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1077 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
<> 147:30b64687e01f 1078 #define ADC_ISR_AWD3_Pos (9U)
<> 147:30b64687e01f 1079 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1080 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
<> 147:30b64687e01f 1081 #define ADC_ISR_JQOVF_Pos (10U)
<> 147:30b64687e01f 1082 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1083 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
<> 147:30b64687e01f 1084
<> 147:30b64687e01f 1085 /* Legacy defines */
<> 147:30b64687e01f 1086 #define ADC_ISR_ADRD (ADC_ISR_ADRDY)
<> 147:30b64687e01f 1087
<> 147:30b64687e01f 1088 /******************** Bit definition for ADC_IER register ********************/
<> 147:30b64687e01f 1089 #define ADC_IER_ADRDYIE_Pos (0U)
<> 147:30b64687e01f 1090 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1091 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
<> 147:30b64687e01f 1092 #define ADC_IER_EOSMPIE_Pos (1U)
<> 147:30b64687e01f 1093 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1094 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
<> 147:30b64687e01f 1095 #define ADC_IER_EOCIE_Pos (2U)
<> 147:30b64687e01f 1096 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1097 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
<> 147:30b64687e01f 1098 #define ADC_IER_EOSIE_Pos (3U)
<> 147:30b64687e01f 1099 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1100 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
<> 147:30b64687e01f 1101 #define ADC_IER_OVRIE_Pos (4U)
<> 147:30b64687e01f 1102 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1103 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
<> 147:30b64687e01f 1104 #define ADC_IER_JEOCIE_Pos (5U)
<> 147:30b64687e01f 1105 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1106 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
<> 147:30b64687e01f 1107 #define ADC_IER_JEOSIE_Pos (6U)
<> 147:30b64687e01f 1108 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1109 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
<> 147:30b64687e01f 1110 #define ADC_IER_AWD1IE_Pos (7U)
<> 147:30b64687e01f 1111 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1112 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
<> 147:30b64687e01f 1113 #define ADC_IER_AWD2IE_Pos (8U)
<> 147:30b64687e01f 1114 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1115 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
<> 147:30b64687e01f 1116 #define ADC_IER_AWD3IE_Pos (9U)
<> 147:30b64687e01f 1117 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1118 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
<> 147:30b64687e01f 1119 #define ADC_IER_JQOVFIE_Pos (10U)
<> 147:30b64687e01f 1120 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1121 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
<> 147:30b64687e01f 1122
<> 147:30b64687e01f 1123 /* Legacy defines */
<> 147:30b64687e01f 1124 #define ADC_IER_RDY (ADC_IER_ADRDYIE)
<> 147:30b64687e01f 1125 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
<> 147:30b64687e01f 1126 #define ADC_IER_EOC (ADC_IER_EOCIE)
<> 147:30b64687e01f 1127 #define ADC_IER_EOS (ADC_IER_EOSIE)
<> 147:30b64687e01f 1128 #define ADC_IER_OVR (ADC_IER_OVRIE)
<> 147:30b64687e01f 1129 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
<> 147:30b64687e01f 1130 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
<> 147:30b64687e01f 1131 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
<> 147:30b64687e01f 1132 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
<> 147:30b64687e01f 1133 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
<> 147:30b64687e01f 1134 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
<> 147:30b64687e01f 1135
<> 147:30b64687e01f 1136 /******************** Bit definition for ADC_CR register ********************/
<> 147:30b64687e01f 1137 #define ADC_CR_ADEN_Pos (0U)
<> 147:30b64687e01f 1138 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1139 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
<> 147:30b64687e01f 1140 #define ADC_CR_ADDIS_Pos (1U)
<> 147:30b64687e01f 1141 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1142 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
<> 147:30b64687e01f 1143 #define ADC_CR_ADSTART_Pos (2U)
<> 147:30b64687e01f 1144 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1145 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
<> 147:30b64687e01f 1146 #define ADC_CR_JADSTART_Pos (3U)
<> 147:30b64687e01f 1147 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1148 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
<> 147:30b64687e01f 1149 #define ADC_CR_ADSTP_Pos (4U)
<> 147:30b64687e01f 1150 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1151 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
<> 147:30b64687e01f 1152 #define ADC_CR_JADSTP_Pos (5U)
<> 147:30b64687e01f 1153 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1154 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
<> 147:30b64687e01f 1155 #define ADC_CR_ADVREGEN_Pos (28U)
<> 147:30b64687e01f 1156 #define ADC_CR_ADVREGEN_Msk (0x3U << ADC_CR_ADVREGEN_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 1157 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
<> 147:30b64687e01f 1158 #define ADC_CR_ADVREGEN_0 (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1159 #define ADC_CR_ADVREGEN_1 (0x2U << ADC_CR_ADVREGEN_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1160 #define ADC_CR_ADCALDIF_Pos (30U)
<> 147:30b64687e01f 1161 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 1162 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
<> 147:30b64687e01f 1163 #define ADC_CR_ADCAL_Pos (31U)
<> 147:30b64687e01f 1164 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 1165 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
<> 147:30b64687e01f 1166
<> 147:30b64687e01f 1167 /******************** Bit definition for ADC_CFGR register ******************/
<> 147:30b64687e01f 1168 #define ADC_CFGR_DMAEN_Pos (0U)
<> 147:30b64687e01f 1169 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1170 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */
<> 147:30b64687e01f 1171 #define ADC_CFGR_DMACFG_Pos (1U)
<> 147:30b64687e01f 1172 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1173 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */
<> 147:30b64687e01f 1174
<> 147:30b64687e01f 1175 #define ADC_CFGR_RES_Pos (3U)
<> 147:30b64687e01f 1176 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
<> 147:30b64687e01f 1177 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
<> 147:30b64687e01f 1178 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1179 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1180
<> 147:30b64687e01f 1181 #define ADC_CFGR_ALIGN_Pos (5U)
<> 147:30b64687e01f 1182 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1183 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
<> 147:30b64687e01f 1184
<> 147:30b64687e01f 1185 #define ADC_CFGR_EXTSEL_Pos (6U)
<> 147:30b64687e01f 1186 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
<> 147:30b64687e01f 1187 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
<> 147:30b64687e01f 1188 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1189 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1190 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1191 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1192
<> 147:30b64687e01f 1193 #define ADC_CFGR_EXTEN_Pos (10U)
<> 147:30b64687e01f 1194 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
<> 147:30b64687e01f 1195 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
<> 147:30b64687e01f 1196 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1197 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1198
<> 147:30b64687e01f 1199 #define ADC_CFGR_OVRMOD_Pos (12U)
<> 147:30b64687e01f 1200 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1201 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
<> 147:30b64687e01f 1202 #define ADC_CFGR_CONT_Pos (13U)
<> 147:30b64687e01f 1203 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1204 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
<> 147:30b64687e01f 1205 #define ADC_CFGR_AUTDLY_Pos (14U)
<> 147:30b64687e01f 1206 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1207 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
<> 147:30b64687e01f 1208
<> 147:30b64687e01f 1209 #define ADC_CFGR_DISCEN_Pos (16U)
<> 147:30b64687e01f 1210 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1211 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
<> 147:30b64687e01f 1212
<> 147:30b64687e01f 1213 #define ADC_CFGR_DISCNUM_Pos (17U)
<> 147:30b64687e01f 1214 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
<> 147:30b64687e01f 1215 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
<> 147:30b64687e01f 1216 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1217 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1218 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1219
<> 147:30b64687e01f 1220 #define ADC_CFGR_JDISCEN_Pos (20U)
<> 147:30b64687e01f 1221 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1222 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
<> 147:30b64687e01f 1223 #define ADC_CFGR_JQM_Pos (21U)
<> 147:30b64687e01f 1224 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1225 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
<> 147:30b64687e01f 1226 #define ADC_CFGR_AWD1SGL_Pos (22U)
<> 147:30b64687e01f 1227 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1228 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
<> 147:30b64687e01f 1229 #define ADC_CFGR_AWD1EN_Pos (23U)
<> 147:30b64687e01f 1230 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 1231 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
<> 147:30b64687e01f 1232 #define ADC_CFGR_JAWD1EN_Pos (24U)
<> 147:30b64687e01f 1233 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1234 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
<> 147:30b64687e01f 1235 #define ADC_CFGR_JAUTO_Pos (25U)
<> 147:30b64687e01f 1236 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 1237 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
<> 147:30b64687e01f 1238
<> 147:30b64687e01f 1239 #define ADC_CFGR_AWD1CH_Pos (26U)
<> 147:30b64687e01f 1240 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
<> 147:30b64687e01f 1241 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
<> 147:30b64687e01f 1242 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1243 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1244 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1245 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1246 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 1247
<> 147:30b64687e01f 1248 /* Legacy defines */
<> 147:30b64687e01f 1249 #define ADC_CFGR_AUTOFF_Pos (15U)
<> 147:30b64687e01f 1250 #define ADC_CFGR_AUTOFF_Msk (0x1U << ADC_CFGR_AUTOFF_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1251 #define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk /*!< ADC low power auto power off */
<> 147:30b64687e01f 1252
<> 147:30b64687e01f 1253 /******************** Bit definition for ADC_SMPR1 register *****************/
<> 147:30b64687e01f 1254 #define ADC_SMPR1_SMP0_Pos (0U)
<> 147:30b64687e01f 1255 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
<> 147:30b64687e01f 1256 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
<> 147:30b64687e01f 1257 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1258 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1259 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1260
<> 147:30b64687e01f 1261 #define ADC_SMPR1_SMP1_Pos (3U)
<> 147:30b64687e01f 1262 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
<> 147:30b64687e01f 1263 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
<> 147:30b64687e01f 1264 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1265 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1266 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1267
<> 147:30b64687e01f 1268 #define ADC_SMPR1_SMP2_Pos (6U)
<> 147:30b64687e01f 1269 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
<> 147:30b64687e01f 1270 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
<> 147:30b64687e01f 1271 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1272 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1273 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1274
<> 147:30b64687e01f 1275 #define ADC_SMPR1_SMP3_Pos (9U)
<> 147:30b64687e01f 1276 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
<> 147:30b64687e01f 1277 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
<> 147:30b64687e01f 1278 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1279 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1280 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1281
<> 147:30b64687e01f 1282 #define ADC_SMPR1_SMP4_Pos (12U)
<> 147:30b64687e01f 1283 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
<> 147:30b64687e01f 1284 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
<> 147:30b64687e01f 1285 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1286 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1287 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1288
<> 147:30b64687e01f 1289 #define ADC_SMPR1_SMP5_Pos (15U)
<> 147:30b64687e01f 1290 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
<> 147:30b64687e01f 1291 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
<> 147:30b64687e01f 1292 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1293 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1294 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1295
<> 147:30b64687e01f 1296 #define ADC_SMPR1_SMP6_Pos (18U)
<> 147:30b64687e01f 1297 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
<> 147:30b64687e01f 1298 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
<> 147:30b64687e01f 1299 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1300 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1301 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1302
<> 147:30b64687e01f 1303 #define ADC_SMPR1_SMP7_Pos (21U)
<> 147:30b64687e01f 1304 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
<> 147:30b64687e01f 1305 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
<> 147:30b64687e01f 1306 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1307 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1308 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 1309
<> 147:30b64687e01f 1310 #define ADC_SMPR1_SMP8_Pos (24U)
<> 147:30b64687e01f 1311 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
<> 147:30b64687e01f 1312 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
<> 147:30b64687e01f 1313 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1314 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 1315 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1316
<> 147:30b64687e01f 1317 #define ADC_SMPR1_SMP9_Pos (27U)
<> 147:30b64687e01f 1318 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
<> 147:30b64687e01f 1319 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
<> 147:30b64687e01f 1320 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1321 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1322 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1323
<> 147:30b64687e01f 1324 /******************** Bit definition for ADC_SMPR2 register *****************/
<> 147:30b64687e01f 1325 #define ADC_SMPR2_SMP10_Pos (0U)
<> 147:30b64687e01f 1326 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
<> 147:30b64687e01f 1327 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
<> 147:30b64687e01f 1328 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1329 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1330 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1331
<> 147:30b64687e01f 1332 #define ADC_SMPR2_SMP11_Pos (3U)
<> 147:30b64687e01f 1333 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
<> 147:30b64687e01f 1334 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
<> 147:30b64687e01f 1335 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1336 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1337 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1338
<> 147:30b64687e01f 1339 #define ADC_SMPR2_SMP12_Pos (6U)
<> 147:30b64687e01f 1340 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
<> 147:30b64687e01f 1341 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
<> 147:30b64687e01f 1342 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1343 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1344 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1345
<> 147:30b64687e01f 1346 #define ADC_SMPR2_SMP13_Pos (9U)
<> 147:30b64687e01f 1347 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
<> 147:30b64687e01f 1348 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
<> 147:30b64687e01f 1349 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1350 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1351 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1352
<> 147:30b64687e01f 1353 #define ADC_SMPR2_SMP14_Pos (12U)
<> 147:30b64687e01f 1354 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
<> 147:30b64687e01f 1355 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
<> 147:30b64687e01f 1356 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1357 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1358 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1359
<> 147:30b64687e01f 1360 #define ADC_SMPR2_SMP15_Pos (15U)
<> 147:30b64687e01f 1361 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
<> 147:30b64687e01f 1362 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
<> 147:30b64687e01f 1363 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1364 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1365 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1366
<> 147:30b64687e01f 1367 #define ADC_SMPR2_SMP16_Pos (18U)
<> 147:30b64687e01f 1368 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
<> 147:30b64687e01f 1369 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
<> 147:30b64687e01f 1370 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1371 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1372 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1373
<> 147:30b64687e01f 1374 #define ADC_SMPR2_SMP17_Pos (21U)
<> 147:30b64687e01f 1375 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
<> 147:30b64687e01f 1376 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
<> 147:30b64687e01f 1377 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1378 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1379 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 1380
<> 147:30b64687e01f 1381 #define ADC_SMPR2_SMP18_Pos (24U)
<> 147:30b64687e01f 1382 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
<> 147:30b64687e01f 1383 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
<> 147:30b64687e01f 1384 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1385 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 1386 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1387
<> 147:30b64687e01f 1388 /******************** Bit definition for ADC_TR1 register *******************/
<> 147:30b64687e01f 1389 #define ADC_TR1_LT1_Pos (0U)
<> 147:30b64687e01f 1390 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 1391 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
<> 147:30b64687e01f 1392 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1393 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1394 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1395 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1396 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1397 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1398 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1399 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1400 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1401 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1402 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1403 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1404
<> 147:30b64687e01f 1405 #define ADC_TR1_HT1_Pos (16U)
<> 147:30b64687e01f 1406 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
<> 147:30b64687e01f 1407 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
<> 147:30b64687e01f 1408 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1409 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1410 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1411 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1412 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1413 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1414 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1415 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 1416 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1417 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 1418 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1419 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1420
<> 147:30b64687e01f 1421 /******************** Bit definition for ADC_TR2 register *******************/
<> 147:30b64687e01f 1422 #define ADC_TR2_LT2_Pos (0U)
<> 147:30b64687e01f 1423 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 1424 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
<> 147:30b64687e01f 1425 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1426 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1427 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1428 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1429 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1430 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1431 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1432 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1433
<> 147:30b64687e01f 1434 #define ADC_TR2_HT2_Pos (16U)
<> 147:30b64687e01f 1435 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 1436 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
<> 147:30b64687e01f 1437 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1438 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1439 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1440 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1441 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1442 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1443 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1444 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 1445
<> 147:30b64687e01f 1446 /******************** Bit definition for ADC_TR3 register *******************/
<> 147:30b64687e01f 1447 #define ADC_TR3_LT3_Pos (0U)
<> 147:30b64687e01f 1448 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 1449 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
<> 147:30b64687e01f 1450 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1451 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1452 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1453 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1454 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1455 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1456 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1457 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1458
<> 147:30b64687e01f 1459 #define ADC_TR3_HT3_Pos (16U)
<> 147:30b64687e01f 1460 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 1461 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
<> 147:30b64687e01f 1462 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1463 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1464 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1465 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1466 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1467 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1468 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1469 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 1470
<> 147:30b64687e01f 1471 /******************** Bit definition for ADC_SQR1 register ******************/
<> 147:30b64687e01f 1472 #define ADC_SQR1_L_Pos (0U)
<> 147:30b64687e01f 1473 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 1474 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
<> 147:30b64687e01f 1475 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1476 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1477 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1478 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1479
<> 147:30b64687e01f 1480 #define ADC_SQR1_SQ1_Pos (6U)
<> 147:30b64687e01f 1481 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
<> 147:30b64687e01f 1482 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
<> 147:30b64687e01f 1483 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1484 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1485 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1486 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1487 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1488
<> 147:30b64687e01f 1489 #define ADC_SQR1_SQ2_Pos (12U)
<> 147:30b64687e01f 1490 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
<> 147:30b64687e01f 1491 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
<> 147:30b64687e01f 1492 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1493 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1494 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1495 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1496 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1497
<> 147:30b64687e01f 1498 #define ADC_SQR1_SQ3_Pos (18U)
<> 147:30b64687e01f 1499 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
<> 147:30b64687e01f 1500 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
<> 147:30b64687e01f 1501 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1502 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1503 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1504 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1505 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1506
<> 147:30b64687e01f 1507 #define ADC_SQR1_SQ4_Pos (24U)
<> 147:30b64687e01f 1508 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 1509 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
<> 147:30b64687e01f 1510 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1511 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 1512 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1513 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1514 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1515
<> 147:30b64687e01f 1516 /******************** Bit definition for ADC_SQR2 register ******************/
<> 147:30b64687e01f 1517 #define ADC_SQR2_SQ5_Pos (0U)
<> 147:30b64687e01f 1518 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
<> 147:30b64687e01f 1519 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
<> 147:30b64687e01f 1520 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1521 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1522 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1523 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1524 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1525
<> 147:30b64687e01f 1526 #define ADC_SQR2_SQ6_Pos (6U)
<> 147:30b64687e01f 1527 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
<> 147:30b64687e01f 1528 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
<> 147:30b64687e01f 1529 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1530 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1531 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1532 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1533 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1534
<> 147:30b64687e01f 1535 #define ADC_SQR2_SQ7_Pos (12U)
<> 147:30b64687e01f 1536 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
<> 147:30b64687e01f 1537 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
<> 147:30b64687e01f 1538 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1539 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1540 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1541 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1542 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1543
<> 147:30b64687e01f 1544 #define ADC_SQR2_SQ8_Pos (18U)
<> 147:30b64687e01f 1545 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
<> 147:30b64687e01f 1546 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
<> 147:30b64687e01f 1547 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1548 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1549 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1550 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1551 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1552
<> 147:30b64687e01f 1553 #define ADC_SQR2_SQ9_Pos (24U)
<> 147:30b64687e01f 1554 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 1555 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
<> 147:30b64687e01f 1556 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1557 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 1558 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1559 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1560 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1561
<> 147:30b64687e01f 1562 /******************** Bit definition for ADC_SQR3 register ******************/
<> 147:30b64687e01f 1563 #define ADC_SQR3_SQ10_Pos (0U)
<> 147:30b64687e01f 1564 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
<> 147:30b64687e01f 1565 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
<> 147:30b64687e01f 1566 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1567 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1568 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1569 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1570 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1571
<> 147:30b64687e01f 1572 #define ADC_SQR3_SQ11_Pos (6U)
<> 147:30b64687e01f 1573 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
<> 147:30b64687e01f 1574 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
<> 147:30b64687e01f 1575 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1576 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1577 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1578 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1579 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1580
<> 147:30b64687e01f 1581 #define ADC_SQR3_SQ12_Pos (12U)
<> 147:30b64687e01f 1582 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
<> 147:30b64687e01f 1583 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
<> 147:30b64687e01f 1584 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1585 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1586 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1587 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1588 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1589
<> 147:30b64687e01f 1590 #define ADC_SQR3_SQ13_Pos (18U)
<> 147:30b64687e01f 1591 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
<> 147:30b64687e01f 1592 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
<> 147:30b64687e01f 1593 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1594 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 1595 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1596 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1597 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1598
<> 147:30b64687e01f 1599 #define ADC_SQR3_SQ14_Pos (24U)
<> 147:30b64687e01f 1600 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 1601 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
<> 147:30b64687e01f 1602 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1603 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 1604 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1605 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1606 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1607
<> 147:30b64687e01f 1608 /******************** Bit definition for ADC_SQR4 register ******************/
<> 147:30b64687e01f 1609 #define ADC_SQR4_SQ15_Pos (0U)
<> 147:30b64687e01f 1610 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
<> 147:30b64687e01f 1611 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
<> 147:30b64687e01f 1612 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1613 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1614 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1615 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1616 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1617
<> 147:30b64687e01f 1618 #define ADC_SQR4_SQ16_Pos (6U)
<> 147:30b64687e01f 1619 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
<> 147:30b64687e01f 1620 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
<> 147:30b64687e01f 1621 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1622 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1623 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1624 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1625 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1626
<> 147:30b64687e01f 1627 /******************** Bit definition for ADC_DR register ********************/
<> 147:30b64687e01f 1628 #define ADC_DR_RDATA_Pos (0U)
<> 147:30b64687e01f 1629 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 1630 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
<> 147:30b64687e01f 1631 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1632 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1633 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1634 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1635 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1636 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1637 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1638 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1639 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1640 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1641 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1642 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1643 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1644 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1645 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1646 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1647
<> 147:30b64687e01f 1648 /******************** Bit definition for ADC_JSQR register ******************/
<> 147:30b64687e01f 1649 #define ADC_JSQR_JL_Pos (0U)
<> 147:30b64687e01f 1650 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 1651 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
<> 147:30b64687e01f 1652 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1653 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1654
<> 147:30b64687e01f 1655 #define ADC_JSQR_JEXTSEL_Pos (2U)
<> 147:30b64687e01f 1656 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
<> 147:30b64687e01f 1657 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
<> 147:30b64687e01f 1658 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1659 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1660 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1661 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1662
<> 147:30b64687e01f 1663 #define ADC_JSQR_JEXTEN_Pos (6U)
<> 147:30b64687e01f 1664 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
<> 147:30b64687e01f 1665 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
<> 147:30b64687e01f 1666 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1667 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1668
<> 147:30b64687e01f 1669 #define ADC_JSQR_JSQ1_Pos (8U)
<> 147:30b64687e01f 1670 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
<> 147:30b64687e01f 1671 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
<> 147:30b64687e01f 1672 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1673 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1674 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1675 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1676 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1677
<> 147:30b64687e01f 1678 #define ADC_JSQR_JSQ2_Pos (14U)
<> 147:30b64687e01f 1679 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
<> 147:30b64687e01f 1680 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
<> 147:30b64687e01f 1681 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1682 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1683 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1684 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1685 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1686
<> 147:30b64687e01f 1687 #define ADC_JSQR_JSQ3_Pos (20U)
<> 147:30b64687e01f 1688 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
<> 147:30b64687e01f 1689 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
<> 147:30b64687e01f 1690 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 1691 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 1692 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 1693 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 1694 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 1695
<> 147:30b64687e01f 1696 #define ADC_JSQR_JSQ4_Pos (26U)
<> 147:30b64687e01f 1697 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
<> 147:30b64687e01f 1698 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
<> 147:30b64687e01f 1699 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1700 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1701 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1702 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1703 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 1704
<> 147:30b64687e01f 1705
<> 147:30b64687e01f 1706 /******************** Bit definition for ADC_OFR1 register ******************/
<> 147:30b64687e01f 1707 #define ADC_OFR1_OFFSET1_Pos (0U)
<> 147:30b64687e01f 1708 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 1709 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
<> 147:30b64687e01f 1710 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1711 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1712 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1713 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1714 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1715 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1716 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1717 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1718 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1719 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1720 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1721 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1722
<> 147:30b64687e01f 1723 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
<> 147:30b64687e01f 1724 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
<> 147:30b64687e01f 1725 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
<> 147:30b64687e01f 1726 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1727 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1728 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1729 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1730 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 1731
<> 147:30b64687e01f 1732 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
<> 147:30b64687e01f 1733 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 1734 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
<> 147:30b64687e01f 1735
<> 147:30b64687e01f 1736 /******************** Bit definition for ADC_OFR2 register ******************/
<> 147:30b64687e01f 1737 #define ADC_OFR2_OFFSET2_Pos (0U)
<> 147:30b64687e01f 1738 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 1739 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
<> 147:30b64687e01f 1740 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1741 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1742 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1743 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1744 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1745 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1746 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1747 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1748 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1749 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1750 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1751 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1752
<> 147:30b64687e01f 1753 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
<> 147:30b64687e01f 1754 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
<> 147:30b64687e01f 1755 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
<> 147:30b64687e01f 1756 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1757 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1758 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1759 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1760 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 1761
<> 147:30b64687e01f 1762 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
<> 147:30b64687e01f 1763 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 1764 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
<> 147:30b64687e01f 1765
<> 147:30b64687e01f 1766 /******************** Bit definition for ADC_OFR3 register ******************/
<> 147:30b64687e01f 1767 #define ADC_OFR3_OFFSET3_Pos (0U)
<> 147:30b64687e01f 1768 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 1769 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
<> 147:30b64687e01f 1770 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1771 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1772 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1773 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1774 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1775 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1776 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1777 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1778 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1779 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1780 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1781 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1782
<> 147:30b64687e01f 1783 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
<> 147:30b64687e01f 1784 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
<> 147:30b64687e01f 1785 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
<> 147:30b64687e01f 1786 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1787 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1788 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1789 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1790 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 1791
<> 147:30b64687e01f 1792 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
<> 147:30b64687e01f 1793 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 1794 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
<> 147:30b64687e01f 1795
<> 147:30b64687e01f 1796 /******************** Bit definition for ADC_OFR4 register ******************/
<> 147:30b64687e01f 1797 #define ADC_OFR4_OFFSET4_Pos (0U)
<> 147:30b64687e01f 1798 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 1799 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
<> 147:30b64687e01f 1800 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1801 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1802 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1803 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1804 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1805 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1806 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1807 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1808 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1809 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1810 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1811 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1812
<> 147:30b64687e01f 1813 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
<> 147:30b64687e01f 1814 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
<> 147:30b64687e01f 1815 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
<> 147:30b64687e01f 1816 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 1817 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 1818 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 1819 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 1820 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 1821
<> 147:30b64687e01f 1822 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
<> 147:30b64687e01f 1823 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 1824 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
<> 147:30b64687e01f 1825
<> 147:30b64687e01f 1826 /******************** Bit definition for ADC_JDR1 register ******************/
<> 147:30b64687e01f 1827 #define ADC_JDR1_JDATA_Pos (0U)
<> 147:30b64687e01f 1828 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 1829 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
<> 147:30b64687e01f 1830 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1831 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1832 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1833 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1834 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1835 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1836 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1837 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1838 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1839 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1840 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1841 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1842 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1843 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1844 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1845 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1846
<> 147:30b64687e01f 1847 /******************** Bit definition for ADC_JDR2 register ******************/
<> 147:30b64687e01f 1848 #define ADC_JDR2_JDATA_Pos (0U)
<> 147:30b64687e01f 1849 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 1850 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
<> 147:30b64687e01f 1851 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1852 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1853 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1854 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1855 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1856 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1857 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1858 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1859 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1860 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1861 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1862 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1863 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1864 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1865 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1866 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1867
<> 147:30b64687e01f 1868 /******************** Bit definition for ADC_JDR3 register ******************/
<> 147:30b64687e01f 1869 #define ADC_JDR3_JDATA_Pos (0U)
<> 147:30b64687e01f 1870 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 1871 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
<> 147:30b64687e01f 1872 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1873 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1874 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1875 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1876 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1877 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1878 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1879 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1880 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1881 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1882 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1883 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1884 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1885 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1886 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1887 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1888
<> 147:30b64687e01f 1889 /******************** Bit definition for ADC_JDR4 register ******************/
<> 147:30b64687e01f 1890 #define ADC_JDR4_JDATA_Pos (0U)
<> 147:30b64687e01f 1891 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 1892 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
<> 147:30b64687e01f 1893 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1894 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1895 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1896 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1897 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1898 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1899 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1900 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1901 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1902 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1903 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1904 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1905 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1906 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1907 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1908 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1909
<> 147:30b64687e01f 1910 /******************** Bit definition for ADC_AWD2CR register ****************/
<> 147:30b64687e01f 1911 #define ADC_AWD2CR_AWD2CH_Pos (0U)
<> 147:30b64687e01f 1912 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
<> 147:30b64687e01f 1913 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
<> 147:30b64687e01f 1914 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1915 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1916 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1917 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1918 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1919 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1920 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1921 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1922 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1923 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1924 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1925 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1926 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1927 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1928 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1929 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1930 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1931 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1932 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1933
<> 147:30b64687e01f 1934 /******************** Bit definition for ADC_AWD3CR register ****************/
<> 147:30b64687e01f 1935 #define ADC_AWD3CR_AWD3CH_Pos (0U)
<> 147:30b64687e01f 1936 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
<> 147:30b64687e01f 1937 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
<> 147:30b64687e01f 1938 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1939 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1940 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1941 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1942 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1943 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1944 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1945 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1946 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1947 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1948 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1949 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1950 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1951 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1952 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1953 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1954 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1955 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1956 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1957
<> 147:30b64687e01f 1958 /******************** Bit definition for ADC_DIFSEL register ****************/
<> 147:30b64687e01f 1959 #define ADC_DIFSEL_DIFSEL_Pos (0U)
<> 147:30b64687e01f 1960 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
<> 147:30b64687e01f 1961 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
<> 147:30b64687e01f 1962 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1963 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1964 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1965 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1966 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1967 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1968 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1969 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 1970 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 1971 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 1972 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 1973 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 1974 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 1975 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 1976 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 1977 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 1978 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1979 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1980 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 1981
<> 147:30b64687e01f 1982 /******************** Bit definition for ADC_CALFACT register ***************/
<> 147:30b64687e01f 1983 #define ADC_CALFACT_CALFACT_S_Pos (0U)
<> 147:30b64687e01f 1984 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
<> 147:30b64687e01f 1985 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
<> 147:30b64687e01f 1986 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 1987 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 1988 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 1989 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 1990 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 1991 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 1992 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 1993
<> 147:30b64687e01f 1994 #define ADC_CALFACT_CALFACT_D_Pos (16U)
<> 147:30b64687e01f 1995 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
<> 147:30b64687e01f 1996 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
<> 147:30b64687e01f 1997 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 1998 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 1999 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2000 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2001 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2002 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 2003 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2004
<> 147:30b64687e01f 2005 /************************* ADC Common registers *****************************/
<> 147:30b64687e01f 2006 /*************** Bit definition for ADC12_COMMON_CSR register ***************/
<> 147:30b64687e01f 2007 #define ADC12_CSR_ADRDY_MST_Pos (0U)
<> 147:30b64687e01f 2008 #define ADC12_CSR_ADRDY_MST_Msk (0x1U << ADC12_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2009 #define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
<> 147:30b64687e01f 2010 #define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)
<> 147:30b64687e01f 2011 #define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2012 #define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
<> 147:30b64687e01f 2013 #define ADC12_CSR_ADRDY_EOC_MST_Pos (2U)
<> 147:30b64687e01f 2014 #define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2015 #define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
<> 147:30b64687e01f 2016 #define ADC12_CSR_ADRDY_EOS_MST_Pos (3U)
<> 147:30b64687e01f 2017 #define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2018 #define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
<> 147:30b64687e01f 2019 #define ADC12_CSR_ADRDY_OVR_MST_Pos (4U)
<> 147:30b64687e01f 2020 #define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2021 #define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
<> 147:30b64687e01f 2022 #define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)
<> 147:30b64687e01f 2023 #define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2024 #define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
<> 147:30b64687e01f 2025 #define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)
<> 147:30b64687e01f 2026 #define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2027 #define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
<> 147:30b64687e01f 2028 #define ADC12_CSR_AWD1_MST_Pos (7U)
<> 147:30b64687e01f 2029 #define ADC12_CSR_AWD1_MST_Msk (0x1U << ADC12_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2030 #define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
<> 147:30b64687e01f 2031 #define ADC12_CSR_AWD2_MST_Pos (8U)
<> 147:30b64687e01f 2032 #define ADC12_CSR_AWD2_MST_Msk (0x1U << ADC12_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2033 #define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
<> 147:30b64687e01f 2034 #define ADC12_CSR_AWD3_MST_Pos (9U)
<> 147:30b64687e01f 2035 #define ADC12_CSR_AWD3_MST_Msk (0x1U << ADC12_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2036 #define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
<> 147:30b64687e01f 2037 #define ADC12_CSR_JQOVF_MST_Pos (10U)
<> 147:30b64687e01f 2038 #define ADC12_CSR_JQOVF_MST_Msk (0x1U << ADC12_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2039 #define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
<> 147:30b64687e01f 2040 #define ADC12_CSR_ADRDY_SLV_Pos (16U)
<> 147:30b64687e01f 2041 #define ADC12_CSR_ADRDY_SLV_Msk (0x1U << ADC12_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2042 #define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
<> 147:30b64687e01f 2043 #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)
<> 147:30b64687e01f 2044 #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2045 #define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
<> 147:30b64687e01f 2046 #define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)
<> 147:30b64687e01f 2047 #define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2048 #define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
<> 147:30b64687e01f 2049 #define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)
<> 147:30b64687e01f 2050 #define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2051 #define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
<> 147:30b64687e01f 2052 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
<> 147:30b64687e01f 2053 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2054 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
<> 147:30b64687e01f 2055 #define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)
<> 147:30b64687e01f 2056 #define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 2057 #define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
<> 147:30b64687e01f 2058 #define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)
<> 147:30b64687e01f 2059 #define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2060 #define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
<> 147:30b64687e01f 2061 #define ADC12_CSR_AWD1_SLV_Pos (23U)
<> 147:30b64687e01f 2062 #define ADC12_CSR_AWD1_SLV_Msk (0x1U << ADC12_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2063 #define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
<> 147:30b64687e01f 2064 #define ADC12_CSR_AWD2_SLV_Pos (24U)
<> 147:30b64687e01f 2065 #define ADC12_CSR_AWD2_SLV_Msk (0x1U << ADC12_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2066 #define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
<> 147:30b64687e01f 2067 #define ADC12_CSR_AWD3_SLV_Pos (25U)
<> 147:30b64687e01f 2068 #define ADC12_CSR_AWD3_SLV_Msk (0x1U << ADC12_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 2069 #define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
<> 147:30b64687e01f 2070 #define ADC12_CSR_JQOVF_SLV_Pos (26U)
<> 147:30b64687e01f 2071 #define ADC12_CSR_JQOVF_SLV_Msk (0x1U << ADC12_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 2072 #define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
<> 147:30b64687e01f 2073
<> 147:30b64687e01f 2074 /*************** Bit definition for ADC34_COMMON_CSR register ***************/
<> 147:30b64687e01f 2075 #define ADC34_CSR_ADRDY_MST_Pos (0U)
<> 147:30b64687e01f 2076 #define ADC34_CSR_ADRDY_MST_Msk (0x1U << ADC34_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2077 #define ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
<> 147:30b64687e01f 2078 #define ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)
<> 147:30b64687e01f 2079 #define ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2080 #define ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
<> 147:30b64687e01f 2081 #define ADC34_CSR_ADRDY_EOC_MST_Pos (2U)
<> 147:30b64687e01f 2082 #define ADC34_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2083 #define ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
<> 147:30b64687e01f 2084 #define ADC34_CSR_ADRDY_EOS_MST_Pos (3U)
<> 147:30b64687e01f 2085 #define ADC34_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2086 #define ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
<> 147:30b64687e01f 2087 #define ADC34_CSR_ADRDY_OVR_MST_Pos (4U)
<> 147:30b64687e01f 2088 #define ADC34_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2089 #define ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
<> 147:30b64687e01f 2090 #define ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)
<> 147:30b64687e01f 2091 #define ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2092 #define ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
<> 147:30b64687e01f 2093 #define ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)
<> 147:30b64687e01f 2094 #define ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2095 #define ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
<> 147:30b64687e01f 2096 #define ADC34_CSR_AWD1_MST_Pos (7U)
<> 147:30b64687e01f 2097 #define ADC34_CSR_AWD1_MST_Msk (0x1U << ADC34_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2098 #define ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
<> 147:30b64687e01f 2099 #define ADC34_CSR_AWD2_MST_Pos (8U)
<> 147:30b64687e01f 2100 #define ADC34_CSR_AWD2_MST_Msk (0x1U << ADC34_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2101 #define ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
<> 147:30b64687e01f 2102 #define ADC34_CSR_AWD3_MST_Pos (9U)
<> 147:30b64687e01f 2103 #define ADC34_CSR_AWD3_MST_Msk (0x1U << ADC34_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2104 #define ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
<> 147:30b64687e01f 2105 #define ADC34_CSR_JQOVF_MST_Pos (10U)
<> 147:30b64687e01f 2106 #define ADC34_CSR_JQOVF_MST_Msk (0x1U << ADC34_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2107 #define ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
<> 147:30b64687e01f 2108 #define ADC34_CSR_ADRDY_SLV_Pos (16U)
<> 147:30b64687e01f 2109 #define ADC34_CSR_ADRDY_SLV_Msk (0x1U << ADC34_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2110 #define ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
<> 147:30b64687e01f 2111 #define ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)
<> 147:30b64687e01f 2112 #define ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2113 #define ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
<> 147:30b64687e01f 2114 #define ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)
<> 147:30b64687e01f 2115 #define ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2116 #define ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
<> 147:30b64687e01f 2117 #define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
<> 147:30b64687e01f 2118 #define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2119 #define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
<> 147:30b64687e01f 2120 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
<> 147:30b64687e01f 2121 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2122 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
<> 147:30b64687e01f 2123 #define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
<> 147:30b64687e01f 2124 #define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 2125 #define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
<> 147:30b64687e01f 2126 #define ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)
<> 147:30b64687e01f 2127 #define ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2128 #define ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
<> 147:30b64687e01f 2129 #define ADC34_CSR_AWD1_SLV_Pos (23U)
<> 147:30b64687e01f 2130 #define ADC34_CSR_AWD1_SLV_Msk (0x1U << ADC34_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2131 #define ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
<> 147:30b64687e01f 2132 #define ADC34_CSR_AWD2_SLV_Pos (24U)
<> 147:30b64687e01f 2133 #define ADC34_CSR_AWD2_SLV_Msk (0x1U << ADC34_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2134 #define ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
<> 147:30b64687e01f 2135 #define ADC34_CSR_AWD3_SLV_Pos (25U)
<> 147:30b64687e01f 2136 #define ADC34_CSR_AWD3_SLV_Msk (0x1U << ADC34_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 2137 #define ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
<> 147:30b64687e01f 2138 #define ADC34_CSR_JQOVF_SLV_Pos (26U)
<> 147:30b64687e01f 2139 #define ADC34_CSR_JQOVF_SLV_Msk (0x1U << ADC34_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 2140 #define ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
<> 147:30b64687e01f 2141
<> 147:30b64687e01f 2142 /*************** Bit definition for ADC12_COMMON_CCR register ***************/
<> 147:30b64687e01f 2143 #define ADC12_CCR_MULTI_Pos (0U)
<> 147:30b64687e01f 2144 #define ADC12_CCR_MULTI_Msk (0x1FU << ADC12_CCR_MULTI_Pos) /*!< 0x0000001F */
<> 147:30b64687e01f 2145 #define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk /*!< Multi ADC mode selection */
<> 147:30b64687e01f 2146 #define ADC12_CCR_MULTI_0 (0x01U << ADC12_CCR_MULTI_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2147 #define ADC12_CCR_MULTI_1 (0x02U << ADC12_CCR_MULTI_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2148 #define ADC12_CCR_MULTI_2 (0x04U << ADC12_CCR_MULTI_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2149 #define ADC12_CCR_MULTI_3 (0x08U << ADC12_CCR_MULTI_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2150 #define ADC12_CCR_MULTI_4 (0x10U << ADC12_CCR_MULTI_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2151 #define ADC12_CCR_DELAY_Pos (8U)
<> 147:30b64687e01f 2152 #define ADC12_CCR_DELAY_Msk (0xFU << ADC12_CCR_DELAY_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 2153 #define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
<> 147:30b64687e01f 2154 #define ADC12_CCR_DELAY_0 (0x1U << ADC12_CCR_DELAY_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2155 #define ADC12_CCR_DELAY_1 (0x2U << ADC12_CCR_DELAY_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2156 #define ADC12_CCR_DELAY_2 (0x4U << ADC12_CCR_DELAY_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2157 #define ADC12_CCR_DELAY_3 (0x8U << ADC12_CCR_DELAY_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2158 #define ADC12_CCR_DMACFG_Pos (13U)
<> 147:30b64687e01f 2159 #define ADC12_CCR_DMACFG_Msk (0x1U << ADC12_CCR_DMACFG_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2160 #define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */
<> 147:30b64687e01f 2161 #define ADC12_CCR_MDMA_Pos (14U)
<> 147:30b64687e01f 2162 #define ADC12_CCR_MDMA_Msk (0x3U << ADC12_CCR_MDMA_Pos) /*!< 0x0000C000 */
<> 147:30b64687e01f 2163 #define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */
<> 147:30b64687e01f 2164 #define ADC12_CCR_MDMA_0 (0x1U << ADC12_CCR_MDMA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2165 #define ADC12_CCR_MDMA_1 (0x2U << ADC12_CCR_MDMA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2166 #define ADC12_CCR_CKMODE_Pos (16U)
<> 147:30b64687e01f 2167 #define ADC12_CCR_CKMODE_Msk (0x3U << ADC12_CCR_CKMODE_Pos) /*!< 0x00030000 */
<> 147:30b64687e01f 2168 #define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk /*!< ADC clock mode */
<> 147:30b64687e01f 2169 #define ADC12_CCR_CKMODE_0 (0x1U << ADC12_CCR_CKMODE_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2170 #define ADC12_CCR_CKMODE_1 (0x2U << ADC12_CCR_CKMODE_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2171 #define ADC12_CCR_VREFEN_Pos (22U)
<> 147:30b64687e01f 2172 #define ADC12_CCR_VREFEN_Msk (0x1U << ADC12_CCR_VREFEN_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2173 #define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk /*!< VREFINT enable */
<> 147:30b64687e01f 2174 #define ADC12_CCR_TSEN_Pos (23U)
<> 147:30b64687e01f 2175 #define ADC12_CCR_TSEN_Msk (0x1U << ADC12_CCR_TSEN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2176 #define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk /*!< Temperature sensor enable */
<> 147:30b64687e01f 2177 #define ADC12_CCR_VBATEN_Pos (24U)
<> 147:30b64687e01f 2178 #define ADC12_CCR_VBATEN_Msk (0x1U << ADC12_CCR_VBATEN_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2179 #define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk /*!< VBAT enable */
<> 147:30b64687e01f 2180
<> 147:30b64687e01f 2181 /*************** Bit definition for ADC34_COMMON_CCR register ***************/
<> 147:30b64687e01f 2182 #define ADC34_CCR_MULTI_Pos (0U)
<> 147:30b64687e01f 2183 #define ADC34_CCR_MULTI_Msk (0x1FU << ADC34_CCR_MULTI_Pos) /*!< 0x0000001F */
<> 147:30b64687e01f 2184 #define ADC34_CCR_MULTI ADC34_CCR_MULTI_Msk /*!< Multi ADC mode selection */
<> 147:30b64687e01f 2185 #define ADC34_CCR_MULTI_0 (0x01U << ADC34_CCR_MULTI_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2186 #define ADC34_CCR_MULTI_1 (0x02U << ADC34_CCR_MULTI_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2187 #define ADC34_CCR_MULTI_2 (0x04U << ADC34_CCR_MULTI_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2188 #define ADC34_CCR_MULTI_3 (0x08U << ADC34_CCR_MULTI_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2189 #define ADC34_CCR_MULTI_4 (0x10U << ADC34_CCR_MULTI_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2190
<> 147:30b64687e01f 2191 #define ADC34_CCR_DELAY_Pos (8U)
<> 147:30b64687e01f 2192 #define ADC34_CCR_DELAY_Msk (0xFU << ADC34_CCR_DELAY_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 2193 #define ADC34_CCR_DELAY ADC34_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
<> 147:30b64687e01f 2194 #define ADC34_CCR_DELAY_0 (0x1U << ADC34_CCR_DELAY_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2195 #define ADC34_CCR_DELAY_1 (0x2U << ADC34_CCR_DELAY_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2196 #define ADC34_CCR_DELAY_2 (0x4U << ADC34_CCR_DELAY_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2197 #define ADC34_CCR_DELAY_3 (0x8U << ADC34_CCR_DELAY_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2198
<> 147:30b64687e01f 2199 #define ADC34_CCR_DMACFG_Pos (13U)
<> 147:30b64687e01f 2200 #define ADC34_CCR_DMACFG_Msk (0x1U << ADC34_CCR_DMACFG_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2201 #define ADC34_CCR_DMACFG ADC34_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */
<> 147:30b64687e01f 2202 #define ADC34_CCR_MDMA_Pos (14U)
<> 147:30b64687e01f 2203 #define ADC34_CCR_MDMA_Msk (0x3U << ADC34_CCR_MDMA_Pos) /*!< 0x0000C000 */
<> 147:30b64687e01f 2204 #define ADC34_CCR_MDMA ADC34_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */
<> 147:30b64687e01f 2205 #define ADC34_CCR_MDMA_0 (0x1U << ADC34_CCR_MDMA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2206 #define ADC34_CCR_MDMA_1 (0x2U << ADC34_CCR_MDMA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2207
<> 147:30b64687e01f 2208 #define ADC34_CCR_CKMODE_Pos (16U)
<> 147:30b64687e01f 2209 #define ADC34_CCR_CKMODE_Msk (0x3U << ADC34_CCR_CKMODE_Pos) /*!< 0x00030000 */
<> 147:30b64687e01f 2210 #define ADC34_CCR_CKMODE ADC34_CCR_CKMODE_Msk /*!< ADC clock mode */
<> 147:30b64687e01f 2211 #define ADC34_CCR_CKMODE_0 (0x1U << ADC34_CCR_CKMODE_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2212 #define ADC34_CCR_CKMODE_1 (0x2U << ADC34_CCR_CKMODE_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2213
<> 147:30b64687e01f 2214 #define ADC34_CCR_VREFEN_Pos (22U)
<> 147:30b64687e01f 2215 #define ADC34_CCR_VREFEN_Msk (0x1U << ADC34_CCR_VREFEN_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2216 #define ADC34_CCR_VREFEN ADC34_CCR_VREFEN_Msk /*!< VREFINT enable */
<> 147:30b64687e01f 2217 #define ADC34_CCR_TSEN_Pos (23U)
<> 147:30b64687e01f 2218 #define ADC34_CCR_TSEN_Msk (0x1U << ADC34_CCR_TSEN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2219 #define ADC34_CCR_TSEN ADC34_CCR_TSEN_Msk /*!< Temperature sensor enable */
<> 147:30b64687e01f 2220 #define ADC34_CCR_VBATEN_Pos (24U)
<> 147:30b64687e01f 2221 #define ADC34_CCR_VBATEN_Msk (0x1U << ADC34_CCR_VBATEN_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2222 #define ADC34_CCR_VBATEN ADC34_CCR_VBATEN_Msk /*!< VBAT enable */
<> 147:30b64687e01f 2223
<> 147:30b64687e01f 2224 /*************** Bit definition for ADC12_COMMON_CDR register ***************/
<> 147:30b64687e01f 2225 #define ADC12_CDR_RDATA_MST_Pos (0U)
<> 147:30b64687e01f 2226 #define ADC12_CDR_RDATA_MST_Msk (0xFFFFU << ADC12_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 2227 #define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
<> 147:30b64687e01f 2228 #define ADC12_CDR_RDATA_MST_0 (0x0001U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2229 #define ADC12_CDR_RDATA_MST_1 (0x0002U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2230 #define ADC12_CDR_RDATA_MST_2 (0x0004U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2231 #define ADC12_CDR_RDATA_MST_3 (0x0008U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2232 #define ADC12_CDR_RDATA_MST_4 (0x0010U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2233 #define ADC12_CDR_RDATA_MST_5 (0x0020U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2234 #define ADC12_CDR_RDATA_MST_6 (0x0040U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2235 #define ADC12_CDR_RDATA_MST_7 (0x0080U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2236 #define ADC12_CDR_RDATA_MST_8 (0x0100U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2237 #define ADC12_CDR_RDATA_MST_9 (0x0200U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2238 #define ADC12_CDR_RDATA_MST_10 (0x0400U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2239 #define ADC12_CDR_RDATA_MST_11 (0x0800U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2240 #define ADC12_CDR_RDATA_MST_12 (0x1000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2241 #define ADC12_CDR_RDATA_MST_13 (0x2000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2242 #define ADC12_CDR_RDATA_MST_14 (0x4000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2243 #define ADC12_CDR_RDATA_MST_15 (0x8000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2244
<> 147:30b64687e01f 2245 #define ADC12_CDR_RDATA_SLV_Pos (16U)
<> 147:30b64687e01f 2246 #define ADC12_CDR_RDATA_SLV_Msk (0xFFFFU << ADC12_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 2247 #define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
<> 147:30b64687e01f 2248 #define ADC12_CDR_RDATA_SLV_0 (0x0001U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2249 #define ADC12_CDR_RDATA_SLV_1 (0x0002U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2250 #define ADC12_CDR_RDATA_SLV_2 (0x0004U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2251 #define ADC12_CDR_RDATA_SLV_3 (0x0008U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2252 #define ADC12_CDR_RDATA_SLV_4 (0x0010U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2253 #define ADC12_CDR_RDATA_SLV_5 (0x0020U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 2254 #define ADC12_CDR_RDATA_SLV_6 (0x0040U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2255 #define ADC12_CDR_RDATA_SLV_7 (0x0080U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2256 #define ADC12_CDR_RDATA_SLV_8 (0x0100U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2257 #define ADC12_CDR_RDATA_SLV_9 (0x0200U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 2258 #define ADC12_CDR_RDATA_SLV_10 (0x0400U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 2259 #define ADC12_CDR_RDATA_SLV_11 (0x0800U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 2260 #define ADC12_CDR_RDATA_SLV_12 (0x1000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 2261 #define ADC12_CDR_RDATA_SLV_13 (0x2000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 2262 #define ADC12_CDR_RDATA_SLV_14 (0x4000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2263 #define ADC12_CDR_RDATA_SLV_15 (0x8000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2264
<> 147:30b64687e01f 2265 /*************** Bit definition for ADC34_COMMON_CDR register ***************/
<> 147:30b64687e01f 2266 #define ADC34_CDR_RDATA_MST_Pos (0U)
<> 147:30b64687e01f 2267 #define ADC34_CDR_RDATA_MST_Msk (0xFFFFU << ADC34_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 2268 #define ADC34_CDR_RDATA_MST ADC34_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
<> 147:30b64687e01f 2269 #define ADC34_CDR_RDATA_MST_0 (0x0001U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2270 #define ADC34_CDR_RDATA_MST_1 (0x0002U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2271 #define ADC34_CDR_RDATA_MST_2 (0x0004U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2272 #define ADC34_CDR_RDATA_MST_3 (0x0008U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2273 #define ADC34_CDR_RDATA_MST_4 (0x0010U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2274 #define ADC34_CDR_RDATA_MST_5 (0x0020U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2275 #define ADC34_CDR_RDATA_MST_6 (0x0040U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2276 #define ADC34_CDR_RDATA_MST_7 (0x0080U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2277 #define ADC34_CDR_RDATA_MST_8 (0x0100U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2278 #define ADC34_CDR_RDATA_MST_9 (0x0200U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2279 #define ADC34_CDR_RDATA_MST_10 (0x0400U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2280 #define ADC34_CDR_RDATA_MST_11 (0x0800U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2281 #define ADC34_CDR_RDATA_MST_12 (0x1000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2282 #define ADC34_CDR_RDATA_MST_13 (0x2000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2283 #define ADC34_CDR_RDATA_MST_14 (0x4000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2284 #define ADC34_CDR_RDATA_MST_15 (0x8000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2285
<> 147:30b64687e01f 2286 #define ADC34_CDR_RDATA_SLV_Pos (16U)
<> 147:30b64687e01f 2287 #define ADC34_CDR_RDATA_SLV_Msk (0xFFFFU << ADC34_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 2288 #define ADC34_CDR_RDATA_SLV ADC34_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
<> 147:30b64687e01f 2289 #define ADC34_CDR_RDATA_SLV_0 (0x0001U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2290 #define ADC34_CDR_RDATA_SLV_1 (0x0002U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2291 #define ADC34_CDR_RDATA_SLV_2 (0x0004U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2292 #define ADC34_CDR_RDATA_SLV_3 (0x0008U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2293 #define ADC34_CDR_RDATA_SLV_4 (0x0010U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2294 #define ADC34_CDR_RDATA_SLV_5 (0x0020U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 2295 #define ADC34_CDR_RDATA_SLV_6 (0x0040U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2296 #define ADC34_CDR_RDATA_SLV_7 (0x0080U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2297 #define ADC34_CDR_RDATA_SLV_8 (0x0100U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2298 #define ADC34_CDR_RDATA_SLV_9 (0x0200U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 2299 #define ADC34_CDR_RDATA_SLV_10 (0x0400U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 2300 #define ADC34_CDR_RDATA_SLV_11 (0x0800U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 2301 #define ADC34_CDR_RDATA_SLV_12 (0x1000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 2302 #define ADC34_CDR_RDATA_SLV_13 (0x2000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 2303 #define ADC34_CDR_RDATA_SLV_14 (0x4000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2304 #define ADC34_CDR_RDATA_SLV_15 (0x8000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2305
<> 147:30b64687e01f 2306 /******************** Bit definition for ADC_CSR register *******************/
<> 147:30b64687e01f 2307 #define ADC_CSR_ADRDY_MST_Pos (0U)
<> 147:30b64687e01f 2308 #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2309 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
<> 147:30b64687e01f 2310 #define ADC_CSR_EOSMP_MST_Pos (1U)
<> 147:30b64687e01f 2311 #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2312 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
<> 147:30b64687e01f 2313 #define ADC_CSR_EOC_MST_Pos (2U)
<> 147:30b64687e01f 2314 #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2315 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
<> 147:30b64687e01f 2316 #define ADC_CSR_EOS_MST_Pos (3U)
<> 147:30b64687e01f 2317 #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2318 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
<> 147:30b64687e01f 2319 #define ADC_CSR_OVR_MST_Pos (4U)
<> 147:30b64687e01f 2320 #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2321 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
<> 147:30b64687e01f 2322 #define ADC_CSR_JEOC_MST_Pos (5U)
<> 147:30b64687e01f 2323 #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2324 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
<> 147:30b64687e01f 2325 #define ADC_CSR_JEOS_MST_Pos (6U)
<> 147:30b64687e01f 2326 #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2327 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
<> 147:30b64687e01f 2328 #define ADC_CSR_AWD1_MST_Pos (7U)
<> 147:30b64687e01f 2329 #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2330 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
<> 147:30b64687e01f 2331 #define ADC_CSR_AWD2_MST_Pos (8U)
<> 147:30b64687e01f 2332 #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2333 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
<> 147:30b64687e01f 2334 #define ADC_CSR_AWD3_MST_Pos (9U)
<> 147:30b64687e01f 2335 #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2336 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
<> 147:30b64687e01f 2337 #define ADC_CSR_JQOVF_MST_Pos (10U)
<> 147:30b64687e01f 2338 #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2339 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
<> 147:30b64687e01f 2340
<> 147:30b64687e01f 2341 #define ADC_CSR_ADRDY_SLV_Pos (16U)
<> 147:30b64687e01f 2342 #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2343 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
<> 147:30b64687e01f 2344 #define ADC_CSR_EOSMP_SLV_Pos (17U)
<> 147:30b64687e01f 2345 #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2346 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
<> 147:30b64687e01f 2347 #define ADC_CSR_EOC_SLV_Pos (18U)
<> 147:30b64687e01f 2348 #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2349 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
<> 147:30b64687e01f 2350 #define ADC_CSR_EOS_SLV_Pos (19U)
<> 147:30b64687e01f 2351 #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2352 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
<> 147:30b64687e01f 2353 #define ADC_CSR_OVR_SLV_Pos (20U)
<> 147:30b64687e01f 2354 #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2355 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
<> 147:30b64687e01f 2356 #define ADC_CSR_JEOC_SLV_Pos (21U)
<> 147:30b64687e01f 2357 #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 2358 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
<> 147:30b64687e01f 2359 #define ADC_CSR_JEOS_SLV_Pos (22U)
<> 147:30b64687e01f 2360 #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2361 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
<> 147:30b64687e01f 2362 #define ADC_CSR_AWD1_SLV_Pos (23U)
<> 147:30b64687e01f 2363 #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2364 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
<> 147:30b64687e01f 2365 #define ADC_CSR_AWD2_SLV_Pos (24U)
<> 147:30b64687e01f 2366 #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2367 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
<> 147:30b64687e01f 2368 #define ADC_CSR_AWD3_SLV_Pos (25U)
<> 147:30b64687e01f 2369 #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 2370 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
<> 147:30b64687e01f 2371 #define ADC_CSR_JQOVF_SLV_Pos (26U)
<> 147:30b64687e01f 2372 #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 2373 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
<> 147:30b64687e01f 2374
<> 147:30b64687e01f 2375 /* Legacy defines */
<> 147:30b64687e01f 2376 #define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST
<> 147:30b64687e01f 2377 #define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST
<> 147:30b64687e01f 2378 #define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST
<> 147:30b64687e01f 2379 #define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST
<> 147:30b64687e01f 2380 #define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST
<> 147:30b64687e01f 2381 #define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST
<> 147:30b64687e01f 2382
<> 147:30b64687e01f 2383 #define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV
<> 147:30b64687e01f 2384 #define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV
<> 147:30b64687e01f 2385 #define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV
<> 147:30b64687e01f 2386 #define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV
<> 147:30b64687e01f 2387 #define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV
<> 147:30b64687e01f 2388 #define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV
<> 147:30b64687e01f 2389
<> 147:30b64687e01f 2390 /******************** Bit definition for ADC_CCR register *******************/
<> 147:30b64687e01f 2391 #define ADC_CCR_DUAL_Pos (0U)
<> 147:30b64687e01f 2392 #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
<> 147:30b64687e01f 2393 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
<> 147:30b64687e01f 2394 #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2395 #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2396 #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2397 #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2398 #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2399
<> 147:30b64687e01f 2400 #define ADC_CCR_DELAY_Pos (8U)
<> 147:30b64687e01f 2401 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 2402 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
<> 147:30b64687e01f 2403 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2404 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2405 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2406 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2407
<> 147:30b64687e01f 2408 #define ADC_CCR_DMACFG_Pos (13U)
<> 147:30b64687e01f 2409 #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2410 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
<> 147:30b64687e01f 2411
<> 147:30b64687e01f 2412 #define ADC_CCR_MDMA_Pos (14U)
<> 147:30b64687e01f 2413 #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
<> 147:30b64687e01f 2414 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
<> 147:30b64687e01f 2415 #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2416 #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2417
<> 147:30b64687e01f 2418 #define ADC_CCR_CKMODE_Pos (16U)
<> 147:30b64687e01f 2419 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
<> 147:30b64687e01f 2420 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
<> 147:30b64687e01f 2421 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2422 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2423
<> 147:30b64687e01f 2424 #define ADC_CCR_VREFEN_Pos (22U)
<> 147:30b64687e01f 2425 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2426 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
<> 147:30b64687e01f 2427 #define ADC_CCR_TSEN_Pos (23U)
<> 147:30b64687e01f 2428 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2429 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
<> 147:30b64687e01f 2430 #define ADC_CCR_VBATEN_Pos (24U)
<> 147:30b64687e01f 2431 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2432 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
<> 147:30b64687e01f 2433
<> 147:30b64687e01f 2434 /* Legacy defines */
<> 147:30b64687e01f 2435 #define ADC_CCR_MULTI (ADC_CCR_DUAL)
<> 147:30b64687e01f 2436 #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)
<> 147:30b64687e01f 2437 #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)
<> 147:30b64687e01f 2438 #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)
<> 147:30b64687e01f 2439 #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)
<> 147:30b64687e01f 2440 #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)
<> 147:30b64687e01f 2441
<> 147:30b64687e01f 2442 /******************** Bit definition for ADC_CDR register *******************/
<> 147:30b64687e01f 2443 #define ADC_CDR_RDATA_MST_Pos (0U)
<> 147:30b64687e01f 2444 #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 2445 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
<> 147:30b64687e01f 2446 #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2447 #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2448 #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2449 #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2450 #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2451 #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2452 #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2453 #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2454 #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2455 #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2456 #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2457 #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2458 #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2459 #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2460 #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2461 #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2462
<> 147:30b64687e01f 2463 #define ADC_CDR_RDATA_SLV_Pos (16U)
<> 147:30b64687e01f 2464 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 2465 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
<> 147:30b64687e01f 2466 #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2467 #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2468 #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2469 #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2470 #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2471 #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 2472 #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 2473 #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 2474 #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 2475 #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 2476 #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 2477 #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 2478 #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 2479 #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 2480 #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2481 #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2482
<> 147:30b64687e01f 2483 /******************************************************************************/
<> 147:30b64687e01f 2484 /* */
<> 147:30b64687e01f 2485 /* Analog Comparators (COMP) */
<> 147:30b64687e01f 2486 /* */
<> 147:30b64687e01f 2487 /******************************************************************************/
<> 147:30b64687e01f 2488
<> 147:30b64687e01f 2489 #define COMP_V1_3_0_0 /*!< Comparator IP version */
<> 147:30b64687e01f 2490
<> 147:30b64687e01f 2491 /********************** Bit definition for COMP1_CSR register ***************/
<> 147:30b64687e01f 2492 #define COMP1_CSR_COMP1EN_Pos (0U)
<> 147:30b64687e01f 2493 #define COMP1_CSR_COMP1EN_Msk (0x1U << COMP1_CSR_COMP1EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2494 #define COMP1_CSR_COMP1EN COMP1_CSR_COMP1EN_Msk /*!< COMP1 enable */
<> 147:30b64687e01f 2495 #define COMP1_CSR_COMP1SW1_Pos (1U)
<> 147:30b64687e01f 2496 #define COMP1_CSR_COMP1SW1_Msk (0x1U << COMP1_CSR_COMP1SW1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2497 #define COMP1_CSR_COMP1SW1 COMP1_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */
<> 147:30b64687e01f 2498 /* Legacy defines */
<> 147:30b64687e01f 2499 #define COMP_CSR_COMP1SW1 COMP1_CSR_COMP1SW1
<> 147:30b64687e01f 2500 #define COMP1_CSR_COMP1INSEL_Pos (4U)
<> 147:30b64687e01f 2501 #define COMP1_CSR_COMP1INSEL_Msk (0x7U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 2502 #define COMP1_CSR_COMP1INSEL COMP1_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */
<> 147:30b64687e01f 2503 #define COMP1_CSR_COMP1INSEL_0 (0x1U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2504 #define COMP1_CSR_COMP1INSEL_1 (0x2U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2505 #define COMP1_CSR_COMP1INSEL_2 (0x4U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2506 #define COMP1_CSR_COMP1OUTSEL_Pos (10U)
<> 147:30b64687e01f 2507 #define COMP1_CSR_COMP1OUTSEL_Msk (0xFU << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2508 #define COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */
<> 147:30b64687e01f 2509 #define COMP1_CSR_COMP1OUTSEL_0 (0x1U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2510 #define COMP1_CSR_COMP1OUTSEL_1 (0x2U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2511 #define COMP1_CSR_COMP1OUTSEL_2 (0x4U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2512 #define COMP1_CSR_COMP1OUTSEL_3 (0x8U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2513 #define COMP1_CSR_COMP1POL_Pos (15U)
<> 147:30b64687e01f 2514 #define COMP1_CSR_COMP1POL_Msk (0x1U << COMP1_CSR_COMP1POL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2515 #define COMP1_CSR_COMP1POL COMP1_CSR_COMP1POL_Msk /*!< COMP1 output polarity */
<> 147:30b64687e01f 2516 #define COMP1_CSR_COMP1BLANKING_Pos (18U)
<> 147:30b64687e01f 2517 #define COMP1_CSR_COMP1BLANKING_Msk (0x3U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2518 #define COMP1_CSR_COMP1BLANKING COMP1_CSR_COMP1BLANKING_Msk /*!< COMP1 blanking */
<> 147:30b64687e01f 2519 #define COMP1_CSR_COMP1BLANKING_0 (0x1U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2520 #define COMP1_CSR_COMP1BLANKING_1 (0x2U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2521 #define COMP1_CSR_COMP1BLANKING_2 (0x4U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2522 #define COMP1_CSR_COMP1OUT_Pos (30U)
<> 147:30b64687e01f 2523 #define COMP1_CSR_COMP1OUT_Msk (0x1U << COMP1_CSR_COMP1OUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2524 #define COMP1_CSR_COMP1OUT COMP1_CSR_COMP1OUT_Msk /*!< COMP1 output level */
<> 147:30b64687e01f 2525 #define COMP1_CSR_COMP1LOCK_Pos (31U)
<> 147:30b64687e01f 2526 #define COMP1_CSR_COMP1LOCK_Msk (0x1U << COMP1_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2527 #define COMP1_CSR_COMP1LOCK COMP1_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
<> 147:30b64687e01f 2528
<> 147:30b64687e01f 2529 /********************** Bit definition for COMP2_CSR register ***************/
<> 147:30b64687e01f 2530 #define COMP2_CSR_COMP2EN_Pos (0U)
<> 147:30b64687e01f 2531 #define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2532 #define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
<> 147:30b64687e01f 2533 #define COMP2_CSR_COMP2INSEL_Pos (4U)
<> 147:30b64687e01f 2534 #define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
<> 147:30b64687e01f 2535 #define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
<> 147:30b64687e01f 2536 #define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
<> 147:30b64687e01f 2537 #define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
<> 147:30b64687e01f 2538 #define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
<> 147:30b64687e01f 2539 #define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
<> 147:30b64687e01f 2540 #define COMP2_CSR_COMP2NONINSEL_Pos (7U)
<> 147:30b64687e01f 2541 #define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2542 #define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */
<> 147:30b64687e01f 2543 #define COMP2_CSR_COMP2WNDWEN_Pos (9U)
<> 147:30b64687e01f 2544 #define COMP2_CSR_COMP2WNDWEN_Msk (0x1U << COMP2_CSR_COMP2WNDWEN_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2545 #define COMP2_CSR_COMP2WNDWEN COMP2_CSR_COMP2WNDWEN_Msk /*!< COMP2 window mode enable */
<> 147:30b64687e01f 2546 #define COMP2_CSR_COMP2OUTSEL_Pos (10U)
<> 147:30b64687e01f 2547 #define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2548 #define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
<> 147:30b64687e01f 2549 #define COMP2_CSR_COMP2OUTSEL_0 (0x1U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2550 #define COMP2_CSR_COMP2OUTSEL_1 (0x2U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2551 #define COMP2_CSR_COMP2OUTSEL_2 (0x4U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2552 #define COMP2_CSR_COMP2OUTSEL_3 (0x8U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2553 #define COMP2_CSR_COMP2POL_Pos (15U)
<> 147:30b64687e01f 2554 #define COMP2_CSR_COMP2POL_Msk (0x1U << COMP2_CSR_COMP2POL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2555 #define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk /*!< COMP2 output polarity */
<> 147:30b64687e01f 2556 #define COMP2_CSR_COMP2BLANKING_Pos (18U)
<> 147:30b64687e01f 2557 #define COMP2_CSR_COMP2BLANKING_Msk (0x3U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2558 #define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk /*!< COMP2 blanking */
<> 147:30b64687e01f 2559 #define COMP2_CSR_COMP2BLANKING_0 (0x1U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2560 #define COMP2_CSR_COMP2BLANKING_1 (0x2U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2561 #define COMP2_CSR_COMP2BLANKING_2 (0x4U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2562 #define COMP2_CSR_COMP2OUT_Pos (30U)
<> 147:30b64687e01f 2563 #define COMP2_CSR_COMP2OUT_Msk (0x1U << COMP2_CSR_COMP2OUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2564 #define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk /*!< COMP2 output level */
<> 147:30b64687e01f 2565 #define COMP2_CSR_COMP2LOCK_Pos (31U)
<> 147:30b64687e01f 2566 #define COMP2_CSR_COMP2LOCK_Msk (0x1U << COMP2_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2567 #define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
<> 147:30b64687e01f 2568
<> 147:30b64687e01f 2569 /********************** Bit definition for COMP3_CSR register ***************/
<> 147:30b64687e01f 2570 #define COMP3_CSR_COMP3EN_Pos (0U)
<> 147:30b64687e01f 2571 #define COMP3_CSR_COMP3EN_Msk (0x1U << COMP3_CSR_COMP3EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2572 #define COMP3_CSR_COMP3EN COMP3_CSR_COMP3EN_Msk /*!< COMP3 enable */
<> 147:30b64687e01f 2573 #define COMP3_CSR_COMP3INSEL_Pos (4U)
<> 147:30b64687e01f 2574 #define COMP3_CSR_COMP3INSEL_Msk (0x7U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 2575 #define COMP3_CSR_COMP3INSEL COMP3_CSR_COMP3INSEL_Msk /*!< COMP3 inverting input select */
<> 147:30b64687e01f 2576 #define COMP3_CSR_COMP3INSEL_0 (0x1U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2577 #define COMP3_CSR_COMP3INSEL_1 (0x2U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2578 #define COMP3_CSR_COMP3INSEL_2 (0x4U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2579 #define COMP3_CSR_COMP3OUTSEL_Pos (10U)
<> 147:30b64687e01f 2580 #define COMP3_CSR_COMP3OUTSEL_Msk (0xFU << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2581 #define COMP3_CSR_COMP3OUTSEL COMP3_CSR_COMP3OUTSEL_Msk /*!< COMP3 output select */
<> 147:30b64687e01f 2582 #define COMP3_CSR_COMP3OUTSEL_0 (0x1U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2583 #define COMP3_CSR_COMP3OUTSEL_1 (0x2U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2584 #define COMP3_CSR_COMP3OUTSEL_2 (0x4U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2585 #define COMP3_CSR_COMP3OUTSEL_3 (0x8U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2586 #define COMP3_CSR_COMP3POL_Pos (15U)
<> 147:30b64687e01f 2587 #define COMP3_CSR_COMP3POL_Msk (0x1U << COMP3_CSR_COMP3POL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2588 #define COMP3_CSR_COMP3POL COMP3_CSR_COMP3POL_Msk /*!< COMP3 output polarity */
<> 147:30b64687e01f 2589 #define COMP3_CSR_COMP3BLANKING_Pos (18U)
<> 147:30b64687e01f 2590 #define COMP3_CSR_COMP3BLANKING_Msk (0x3U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2591 #define COMP3_CSR_COMP3BLANKING COMP3_CSR_COMP3BLANKING_Msk /*!< COMP3 blanking */
<> 147:30b64687e01f 2592 #define COMP3_CSR_COMP3BLANKING_0 (0x1U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2593 #define COMP3_CSR_COMP3BLANKING_1 (0x2U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2594 #define COMP3_CSR_COMP3BLANKING_2 (0x4U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2595 #define COMP3_CSR_COMP3OUT_Pos (30U)
<> 147:30b64687e01f 2596 #define COMP3_CSR_COMP3OUT_Msk (0x1U << COMP3_CSR_COMP3OUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2597 #define COMP3_CSR_COMP3OUT COMP3_CSR_COMP3OUT_Msk /*!< COMP3 output level */
<> 147:30b64687e01f 2598 #define COMP3_CSR_COMP3LOCK_Pos (31U)
<> 147:30b64687e01f 2599 #define COMP3_CSR_COMP3LOCK_Msk (0x1U << COMP3_CSR_COMP3LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2600 #define COMP3_CSR_COMP3LOCK COMP3_CSR_COMP3LOCK_Msk /*!< COMP3 lock */
<> 147:30b64687e01f 2601
<> 147:30b64687e01f 2602 /********************** Bit definition for COMP4_CSR register ***************/
<> 147:30b64687e01f 2603 #define COMP4_CSR_COMP4EN_Pos (0U)
<> 147:30b64687e01f 2604 #define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2605 #define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
<> 147:30b64687e01f 2606 #define COMP4_CSR_COMP4INSEL_Pos (4U)
<> 147:30b64687e01f 2607 #define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
<> 147:30b64687e01f 2608 #define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
<> 147:30b64687e01f 2609 #define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
<> 147:30b64687e01f 2610 #define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
<> 147:30b64687e01f 2611 #define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
<> 147:30b64687e01f 2612 #define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
<> 147:30b64687e01f 2613 #define COMP4_CSR_COMP4NONINSEL_Pos (7U)
<> 147:30b64687e01f 2614 #define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2615 #define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */
<> 147:30b64687e01f 2616 #define COMP4_CSR_COMP4WNDWEN_Pos (9U)
<> 147:30b64687e01f 2617 #define COMP4_CSR_COMP4WNDWEN_Msk (0x1U << COMP4_CSR_COMP4WNDWEN_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2618 #define COMP4_CSR_COMP4WNDWEN COMP4_CSR_COMP4WNDWEN_Msk /*!< COMP4 window mode enable */
<> 147:30b64687e01f 2619 #define COMP4_CSR_COMP4OUTSEL_Pos (10U)
<> 147:30b64687e01f 2620 #define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2621 #define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
<> 147:30b64687e01f 2622 #define COMP4_CSR_COMP4OUTSEL_0 (0x1U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2623 #define COMP4_CSR_COMP4OUTSEL_1 (0x2U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2624 #define COMP4_CSR_COMP4OUTSEL_2 (0x4U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2625 #define COMP4_CSR_COMP4OUTSEL_3 (0x8U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2626 #define COMP4_CSR_COMP4POL_Pos (15U)
<> 147:30b64687e01f 2627 #define COMP4_CSR_COMP4POL_Msk (0x1U << COMP4_CSR_COMP4POL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2628 #define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk /*!< COMP4 output polarity */
<> 147:30b64687e01f 2629 #define COMP4_CSR_COMP4BLANKING_Pos (18U)
<> 147:30b64687e01f 2630 #define COMP4_CSR_COMP4BLANKING_Msk (0x3U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2631 #define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk /*!< COMP4 blanking */
<> 147:30b64687e01f 2632 #define COMP4_CSR_COMP4BLANKING_0 (0x1U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2633 #define COMP4_CSR_COMP4BLANKING_1 (0x2U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2634 #define COMP4_CSR_COMP4BLANKING_2 (0x4U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2635 #define COMP4_CSR_COMP4OUT_Pos (30U)
<> 147:30b64687e01f 2636 #define COMP4_CSR_COMP4OUT_Msk (0x1U << COMP4_CSR_COMP4OUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2637 #define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk /*!< COMP4 output level */
<> 147:30b64687e01f 2638 #define COMP4_CSR_COMP4LOCK_Pos (31U)
<> 147:30b64687e01f 2639 #define COMP4_CSR_COMP4LOCK_Msk (0x1U << COMP4_CSR_COMP4LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2640 #define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk /*!< COMP4 lock */
<> 147:30b64687e01f 2641
<> 147:30b64687e01f 2642 /********************** Bit definition for COMP5_CSR register ***************/
<> 147:30b64687e01f 2643 #define COMP5_CSR_COMP5EN_Pos (0U)
<> 147:30b64687e01f 2644 #define COMP5_CSR_COMP5EN_Msk (0x1U << COMP5_CSR_COMP5EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2645 #define COMP5_CSR_COMP5EN COMP5_CSR_COMP5EN_Msk /*!< COMP5 enable */
<> 147:30b64687e01f 2646 #define COMP5_CSR_COMP5INSEL_Pos (4U)
<> 147:30b64687e01f 2647 #define COMP5_CSR_COMP5INSEL_Msk (0x7U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 2648 #define COMP5_CSR_COMP5INSEL COMP5_CSR_COMP5INSEL_Msk /*!< COMP5 inverting input select */
<> 147:30b64687e01f 2649 #define COMP5_CSR_COMP5INSEL_0 (0x1U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2650 #define COMP5_CSR_COMP5INSEL_1 (0x2U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2651 #define COMP5_CSR_COMP5INSEL_2 (0x4U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2652 #define COMP5_CSR_COMP5OUTSEL_Pos (10U)
<> 147:30b64687e01f 2653 #define COMP5_CSR_COMP5OUTSEL_Msk (0xFU << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2654 #define COMP5_CSR_COMP5OUTSEL COMP5_CSR_COMP5OUTSEL_Msk /*!< COMP5 output select */
<> 147:30b64687e01f 2655 #define COMP5_CSR_COMP5OUTSEL_0 (0x1U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2656 #define COMP5_CSR_COMP5OUTSEL_1 (0x2U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2657 #define COMP5_CSR_COMP5OUTSEL_2 (0x4U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2658 #define COMP5_CSR_COMP5OUTSEL_3 (0x8U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2659 #define COMP5_CSR_COMP5POL_Pos (15U)
<> 147:30b64687e01f 2660 #define COMP5_CSR_COMP5POL_Msk (0x1U << COMP5_CSR_COMP5POL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2661 #define COMP5_CSR_COMP5POL COMP5_CSR_COMP5POL_Msk /*!< COMP5 output polarity */
<> 147:30b64687e01f 2662 #define COMP5_CSR_COMP5BLANKING_Pos (18U)
<> 147:30b64687e01f 2663 #define COMP5_CSR_COMP5BLANKING_Msk (0x3U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2664 #define COMP5_CSR_COMP5BLANKING COMP5_CSR_COMP5BLANKING_Msk /*!< COMP5 blanking */
<> 147:30b64687e01f 2665 #define COMP5_CSR_COMP5BLANKING_0 (0x1U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2666 #define COMP5_CSR_COMP5BLANKING_1 (0x2U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2667 #define COMP5_CSR_COMP5BLANKING_2 (0x4U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2668 #define COMP5_CSR_COMP5OUT_Pos (30U)
<> 147:30b64687e01f 2669 #define COMP5_CSR_COMP5OUT_Msk (0x1U << COMP5_CSR_COMP5OUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2670 #define COMP5_CSR_COMP5OUT COMP5_CSR_COMP5OUT_Msk /*!< COMP5 output level */
<> 147:30b64687e01f 2671 #define COMP5_CSR_COMP5LOCK_Pos (31U)
<> 147:30b64687e01f 2672 #define COMP5_CSR_COMP5LOCK_Msk (0x1U << COMP5_CSR_COMP5LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2673 #define COMP5_CSR_COMP5LOCK COMP5_CSR_COMP5LOCK_Msk /*!< COMP5 lock */
<> 147:30b64687e01f 2674
<> 147:30b64687e01f 2675 /********************** Bit definition for COMP6_CSR register ***************/
<> 147:30b64687e01f 2676 #define COMP6_CSR_COMP6EN_Pos (0U)
<> 147:30b64687e01f 2677 #define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2678 #define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
<> 147:30b64687e01f 2679 #define COMP6_CSR_COMP6INSEL_Pos (4U)
<> 147:30b64687e01f 2680 #define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
<> 147:30b64687e01f 2681 #define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
<> 147:30b64687e01f 2682 #define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
<> 147:30b64687e01f 2683 #define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
<> 147:30b64687e01f 2684 #define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
<> 147:30b64687e01f 2685 #define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
<> 147:30b64687e01f 2686 #if defined(STM32F303xE)
<> 147:30b64687e01f 2687 #define COMP6_CSR_COMP6NONINSEL_Pos (7U)
<> 147:30b64687e01f 2688 #define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2689 #define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */
<> 147:30b64687e01f 2690 #endif
<> 147:30b64687e01f 2691 #define COMP6_CSR_COMP6WNDWEN_Pos (9U)
<> 147:30b64687e01f 2692 #define COMP6_CSR_COMP6WNDWEN_Msk (0x1U << COMP6_CSR_COMP6WNDWEN_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2693 #define COMP6_CSR_COMP6WNDWEN COMP6_CSR_COMP6WNDWEN_Msk /*!< COMP6 window mode enable */
<> 147:30b64687e01f 2694 #define COMP6_CSR_COMP6OUTSEL_Pos (10U)
<> 147:30b64687e01f 2695 #define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2696 #define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
<> 147:30b64687e01f 2697 #define COMP6_CSR_COMP6OUTSEL_0 (0x1U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2698 #define COMP6_CSR_COMP6OUTSEL_1 (0x2U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2699 #define COMP6_CSR_COMP6OUTSEL_2 (0x4U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2700 #define COMP6_CSR_COMP6OUTSEL_3 (0x8U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2701 #define COMP6_CSR_COMP6POL_Pos (15U)
<> 147:30b64687e01f 2702 #define COMP6_CSR_COMP6POL_Msk (0x1U << COMP6_CSR_COMP6POL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2703 #define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk /*!< COMP6 output polarity */
<> 147:30b64687e01f 2704 #define COMP6_CSR_COMP6BLANKING_Pos (18U)
<> 147:30b64687e01f 2705 #define COMP6_CSR_COMP6BLANKING_Msk (0x3U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2706 #define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk /*!< COMP6 blanking */
<> 147:30b64687e01f 2707 #define COMP6_CSR_COMP6BLANKING_0 (0x1U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2708 #define COMP6_CSR_COMP6BLANKING_1 (0x2U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2709 #define COMP6_CSR_COMP6BLANKING_2 (0x4U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2710 #define COMP6_CSR_COMP6OUT_Pos (30U)
<> 147:30b64687e01f 2711 #define COMP6_CSR_COMP6OUT_Msk (0x1U << COMP6_CSR_COMP6OUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2712 #define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk /*!< COMP6 output level */
<> 147:30b64687e01f 2713 #define COMP6_CSR_COMP6LOCK_Pos (31U)
<> 147:30b64687e01f 2714 #define COMP6_CSR_COMP6LOCK_Msk (0x1U << COMP6_CSR_COMP6LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2715 #define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk /*!< COMP6 lock */
<> 147:30b64687e01f 2716
<> 147:30b64687e01f 2717 /********************** Bit definition for COMP7_CSR register ***************/
<> 147:30b64687e01f 2718 #define COMP7_CSR_COMP7EN_Pos (0U)
<> 147:30b64687e01f 2719 #define COMP7_CSR_COMP7EN_Msk (0x1U << COMP7_CSR_COMP7EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2720 #define COMP7_CSR_COMP7EN COMP7_CSR_COMP7EN_Msk /*!< COMP7 enable */
<> 147:30b64687e01f 2721 #define COMP7_CSR_COMP7INSEL_Pos (4U)
<> 147:30b64687e01f 2722 #define COMP7_CSR_COMP7INSEL_Msk (0x7U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 2723 #define COMP7_CSR_COMP7INSEL COMP7_CSR_COMP7INSEL_Msk /*!< COMP7 inverting input select */
<> 147:30b64687e01f 2724 #define COMP7_CSR_COMP7INSEL_0 (0x1U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 2725 #define COMP7_CSR_COMP7INSEL_1 (0x2U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2726 #define COMP7_CSR_COMP7INSEL_2 (0x4U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2727 #define COMP7_CSR_COMP7OUTSEL_Pos (10U)
<> 147:30b64687e01f 2728 #define COMP7_CSR_COMP7OUTSEL_Msk (0xFU << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2729 #define COMP7_CSR_COMP7OUTSEL COMP7_CSR_COMP7OUTSEL_Msk /*!< COMP7 output select */
<> 147:30b64687e01f 2730 #define COMP7_CSR_COMP7OUTSEL_0 (0x1U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2731 #define COMP7_CSR_COMP7OUTSEL_1 (0x2U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2732 #define COMP7_CSR_COMP7OUTSEL_2 (0x4U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2733 #define COMP7_CSR_COMP7OUTSEL_3 (0x8U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2734 #define COMP7_CSR_COMP7POL_Pos (15U)
<> 147:30b64687e01f 2735 #define COMP7_CSR_COMP7POL_Msk (0x1U << COMP7_CSR_COMP7POL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2736 #define COMP7_CSR_COMP7POL COMP7_CSR_COMP7POL_Msk /*!< COMP7 output polarity */
<> 147:30b64687e01f 2737 #define COMP7_CSR_COMP7BLANKING_Pos (18U)
<> 147:30b64687e01f 2738 #define COMP7_CSR_COMP7BLANKING_Msk (0x3U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2739 #define COMP7_CSR_COMP7BLANKING COMP7_CSR_COMP7BLANKING_Msk /*!< COMP7 blanking */
<> 147:30b64687e01f 2740 #define COMP7_CSR_COMP7BLANKING_0 (0x1U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2741 #define COMP7_CSR_COMP7BLANKING_1 (0x2U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2742 #define COMP7_CSR_COMP7BLANKING_2 (0x4U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2743 #define COMP7_CSR_COMP7OUT_Pos (30U)
<> 147:30b64687e01f 2744 #define COMP7_CSR_COMP7OUT_Msk (0x1U << COMP7_CSR_COMP7OUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2745 #define COMP7_CSR_COMP7OUT COMP7_CSR_COMP7OUT_Msk /*!< COMP7 output level */
<> 147:30b64687e01f 2746 #define COMP7_CSR_COMP7LOCK_Pos (31U)
<> 147:30b64687e01f 2747 #define COMP7_CSR_COMP7LOCK_Msk (0x1U << COMP7_CSR_COMP7LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2748 #define COMP7_CSR_COMP7LOCK COMP7_CSR_COMP7LOCK_Msk /*!< COMP7 lock */
<> 147:30b64687e01f 2749
<> 147:30b64687e01f 2750 /********************** Bit definition for COMP_CSR register ****************/
<> 147:30b64687e01f 2751 #define COMP_CSR_COMPxEN_Pos (0U)
<> 147:30b64687e01f 2752 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2753 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
<> 147:30b64687e01f 2754 #define COMP_CSR_COMPxSW1_Pos (1U)
<> 147:30b64687e01f 2755 #define COMP_CSR_COMPxSW1_Msk (0x1U << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2756 #define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */
<> 147:30b64687e01f 2757 #define COMP_CSR_COMPxINSEL_Pos (4U)
<> 147:30b64687e01f 2758 #define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
<> 147:30b64687e01f 2759 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
<> 147:30b64687e01f 2760 #define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
<> 147:30b64687e01f 2761 #define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
<> 147:30b64687e01f 2762 #define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
<> 147:30b64687e01f 2763 #define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
<> 147:30b64687e01f 2764 #define COMP_CSR_COMPxNONINSEL_Pos (7U)
<> 147:30b64687e01f 2765 #define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2766 #define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
<> 147:30b64687e01f 2767 #define COMP_CSR_COMPxWNDWEN_Pos (9U)
<> 147:30b64687e01f 2768 #define COMP_CSR_COMPxWNDWEN_Msk (0x1U << COMP_CSR_COMPxWNDWEN_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2769 #define COMP_CSR_COMPxWNDWEN COMP_CSR_COMPxWNDWEN_Msk /*!< COMPx window mode enable */
<> 147:30b64687e01f 2770 #define COMP_CSR_COMPxOUTSEL_Pos (10U)
<> 147:30b64687e01f 2771 #define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
<> 147:30b64687e01f 2772 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
<> 147:30b64687e01f 2773 #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2774 #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2775 #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2776 #define COMP_CSR_COMPxOUTSEL_3 (0x8U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2777 #define COMP_CSR_COMPxPOL_Pos (15U)
<> 147:30b64687e01f 2778 #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2779 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */
<> 147:30b64687e01f 2780 #define COMP_CSR_COMPxBLANKING_Pos (18U)
<> 147:30b64687e01f 2781 #define COMP_CSR_COMPxBLANKING_Msk (0x3U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 2782 #define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk /*!< COMPx blanking */
<> 147:30b64687e01f 2783 #define COMP_CSR_COMPxBLANKING_0 (0x1U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2784 #define COMP_CSR_COMPxBLANKING_1 (0x2U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 2785 #define COMP_CSR_COMPxBLANKING_2 (0x4U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 2786 #define COMP_CSR_COMPxOUT_Pos (30U)
<> 147:30b64687e01f 2787 #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2788 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */
<> 147:30b64687e01f 2789 #define COMP_CSR_COMPxLOCK_Pos (31U)
<> 147:30b64687e01f 2790 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2791 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
<> 147:30b64687e01f 2792
<> 147:30b64687e01f 2793 /******************************************************************************/
<> 147:30b64687e01f 2794 /* */
<> 147:30b64687e01f 2795 /* Operational Amplifier (OPAMP) */
<> 147:30b64687e01f 2796 /* */
<> 147:30b64687e01f 2797 /******************************************************************************/
<> 147:30b64687e01f 2798 /********************* Bit definition for OPAMP1_CSR register ***************/
<> 147:30b64687e01f 2799 #define OPAMP1_CSR_OPAMP1EN_Pos (0U)
<> 147:30b64687e01f 2800 #define OPAMP1_CSR_OPAMP1EN_Msk (0x1U << OPAMP1_CSR_OPAMP1EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2801 #define OPAMP1_CSR_OPAMP1EN OPAMP1_CSR_OPAMP1EN_Msk /*!< OPAMP1 enable */
<> 147:30b64687e01f 2802 #define OPAMP1_CSR_FORCEVP_Pos (1U)
<> 147:30b64687e01f 2803 #define OPAMP1_CSR_FORCEVP_Msk (0x1U << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2804 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
<> 147:30b64687e01f 2805 #define OPAMP1_CSR_VPSEL_Pos (2U)
<> 147:30b64687e01f 2806 #define OPAMP1_CSR_VPSEL_Msk (0x3U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 2807 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverting input selection */
<> 147:30b64687e01f 2808 #define OPAMP1_CSR_VPSEL_0 (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2809 #define OPAMP1_CSR_VPSEL_1 (0x2U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2810 #define OPAMP1_CSR_VMSEL_Pos (5U)
<> 147:30b64687e01f 2811 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
<> 147:30b64687e01f 2812 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 147:30b64687e01f 2813 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2814 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2815 #define OPAMP1_CSR_TCMEN_Pos (7U)
<> 147:30b64687e01f 2816 #define OPAMP1_CSR_TCMEN_Msk (0x1U << OPAMP1_CSR_TCMEN_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2817 #define OPAMP1_CSR_TCMEN OPAMP1_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
<> 147:30b64687e01f 2818 #define OPAMP1_CSR_VMSSEL_Pos (8U)
<> 147:30b64687e01f 2819 #define OPAMP1_CSR_VMSSEL_Msk (0x1U << OPAMP1_CSR_VMSSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2820 #define OPAMP1_CSR_VMSSEL OPAMP1_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
<> 147:30b64687e01f 2821 #define OPAMP1_CSR_VPSSEL_Pos (9U)
<> 147:30b64687e01f 2822 #define OPAMP1_CSR_VPSSEL_Msk (0x3U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000600 */
<> 147:30b64687e01f 2823 #define OPAMP1_CSR_VPSSEL OPAMP1_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
<> 147:30b64687e01f 2824 #define OPAMP1_CSR_VPSSEL_0 (0x1U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2825 #define OPAMP1_CSR_VPSSEL_1 (0x2U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2826 #define OPAMP1_CSR_CALON_Pos (11U)
<> 147:30b64687e01f 2827 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2828 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
<> 147:30b64687e01f 2829 #define OPAMP1_CSR_CALSEL_Pos (12U)
<> 147:30b64687e01f 2830 #define OPAMP1_CSR_CALSEL_Msk (0x3U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 2831 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
<> 147:30b64687e01f 2832 #define OPAMP1_CSR_CALSEL_0 (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2833 #define OPAMP1_CSR_CALSEL_1 (0x2U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2834 #define OPAMP1_CSR_PGGAIN_Pos (14U)
<> 147:30b64687e01f 2835 #define OPAMP1_CSR_PGGAIN_Msk (0xFU << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
<> 147:30b64687e01f 2836 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
<> 147:30b64687e01f 2837 #define OPAMP1_CSR_PGGAIN_0 (0x1U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2838 #define OPAMP1_CSR_PGGAIN_1 (0x2U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2839 #define OPAMP1_CSR_PGGAIN_2 (0x4U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2840 #define OPAMP1_CSR_PGGAIN_3 (0x8U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2841 #define OPAMP1_CSR_USERTRIM_Pos (18U)
<> 147:30b64687e01f 2842 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2843 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 147:30b64687e01f 2844 #define OPAMP1_CSR_TRIMOFFSETP_Pos (19U)
<> 147:30b64687e01f 2845 #define OPAMP1_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
<> 147:30b64687e01f 2846 #define OPAMP1_CSR_TRIMOFFSETP OPAMP1_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
<> 147:30b64687e01f 2847 #define OPAMP1_CSR_TRIMOFFSETN_Pos (24U)
<> 147:30b64687e01f 2848 #define OPAMP1_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 2849 #define OPAMP1_CSR_TRIMOFFSETN OPAMP1_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
<> 147:30b64687e01f 2850 #define OPAMP1_CSR_TSTREF_Pos (29U)
<> 147:30b64687e01f 2851 #define OPAMP1_CSR_TSTREF_Msk (0x1U << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 2852 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
<> 147:30b64687e01f 2853 #define OPAMP1_CSR_OUTCAL_Pos (30U)
<> 147:30b64687e01f 2854 #define OPAMP1_CSR_OUTCAL_Msk (0x1U << OPAMP1_CSR_OUTCAL_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2855 #define OPAMP1_CSR_OUTCAL OPAMP1_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
<> 147:30b64687e01f 2856 #define OPAMP1_CSR_LOCK_Pos (31U)
<> 147:30b64687e01f 2857 #define OPAMP1_CSR_LOCK_Msk (0x1U << OPAMP1_CSR_LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2858 #define OPAMP1_CSR_LOCK OPAMP1_CSR_LOCK_Msk /*!< OPAMP lock */
<> 147:30b64687e01f 2859
<> 147:30b64687e01f 2860 /********************* Bit definition for OPAMP2_CSR register ***************/
<> 147:30b64687e01f 2861 #define OPAMP2_CSR_OPAMP2EN_Pos (0U)
<> 147:30b64687e01f 2862 #define OPAMP2_CSR_OPAMP2EN_Msk (0x1U << OPAMP2_CSR_OPAMP2EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2863 #define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk /*!< OPAMP2 enable */
<> 147:30b64687e01f 2864 #define OPAMP2_CSR_FORCEVP_Pos (1U)
<> 147:30b64687e01f 2865 #define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2866 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
<> 147:30b64687e01f 2867 #define OPAMP2_CSR_VPSEL_Pos (2U)
<> 147:30b64687e01f 2868 #define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 2869 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverting input selection */
<> 147:30b64687e01f 2870 #define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2871 #define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2872 #define OPAMP2_CSR_VMSEL_Pos (5U)
<> 147:30b64687e01f 2873 #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
<> 147:30b64687e01f 2874 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 147:30b64687e01f 2875 #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2876 #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2877 #define OPAMP2_CSR_TCMEN_Pos (7U)
<> 147:30b64687e01f 2878 #define OPAMP2_CSR_TCMEN_Msk (0x1U << OPAMP2_CSR_TCMEN_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2879 #define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
<> 147:30b64687e01f 2880 #define OPAMP2_CSR_VMSSEL_Pos (8U)
<> 147:30b64687e01f 2881 #define OPAMP2_CSR_VMSSEL_Msk (0x1U << OPAMP2_CSR_VMSSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2882 #define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
<> 147:30b64687e01f 2883 #define OPAMP2_CSR_VPSSEL_Pos (9U)
<> 147:30b64687e01f 2884 #define OPAMP2_CSR_VPSSEL_Msk (0x3U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000600 */
<> 147:30b64687e01f 2885 #define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
<> 147:30b64687e01f 2886 #define OPAMP2_CSR_VPSSEL_0 (0x1U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2887 #define OPAMP2_CSR_VPSSEL_1 (0x2U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2888 #define OPAMP2_CSR_CALON_Pos (11U)
<> 147:30b64687e01f 2889 #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2890 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
<> 147:30b64687e01f 2891 #define OPAMP2_CSR_CALSEL_Pos (12U)
<> 147:30b64687e01f 2892 #define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 2893 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
<> 147:30b64687e01f 2894 #define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2895 #define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2896 #define OPAMP2_CSR_PGGAIN_Pos (14U)
<> 147:30b64687e01f 2897 #define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
<> 147:30b64687e01f 2898 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
<> 147:30b64687e01f 2899 #define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2900 #define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2901 #define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2902 #define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2903 #define OPAMP2_CSR_USERTRIM_Pos (18U)
<> 147:30b64687e01f 2904 #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2905 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 147:30b64687e01f 2906 #define OPAMP2_CSR_TRIMOFFSETP_Pos (19U)
<> 147:30b64687e01f 2907 #define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
<> 147:30b64687e01f 2908 #define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
<> 147:30b64687e01f 2909 #define OPAMP2_CSR_TRIMOFFSETN_Pos (24U)
<> 147:30b64687e01f 2910 #define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 2911 #define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
<> 147:30b64687e01f 2912 #define OPAMP2_CSR_TSTREF_Pos (29U)
<> 147:30b64687e01f 2913 #define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 2914 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
<> 147:30b64687e01f 2915 #define OPAMP2_CSR_OUTCAL_Pos (30U)
<> 147:30b64687e01f 2916 #define OPAMP2_CSR_OUTCAL_Msk (0x1U << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2917 #define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
<> 147:30b64687e01f 2918 #define OPAMP2_CSR_LOCK_Pos (31U)
<> 147:30b64687e01f 2919 #define OPAMP2_CSR_LOCK_Msk (0x1U << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2920 #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */
<> 147:30b64687e01f 2921
<> 147:30b64687e01f 2922 /********************* Bit definition for OPAMP3_CSR register ***************/
<> 147:30b64687e01f 2923 #define OPAMP3_CSR_OPAMP3EN_Pos (0U)
<> 147:30b64687e01f 2924 #define OPAMP3_CSR_OPAMP3EN_Msk (0x1U << OPAMP3_CSR_OPAMP3EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2925 #define OPAMP3_CSR_OPAMP3EN OPAMP3_CSR_OPAMP3EN_Msk /*!< OPAMP3 enable */
<> 147:30b64687e01f 2926 #define OPAMP3_CSR_FORCEVP_Pos (1U)
<> 147:30b64687e01f 2927 #define OPAMP3_CSR_FORCEVP_Msk (0x1U << OPAMP3_CSR_FORCEVP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2928 #define OPAMP3_CSR_FORCEVP OPAMP3_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
<> 147:30b64687e01f 2929 #define OPAMP3_CSR_VPSEL_Pos (2U)
<> 147:30b64687e01f 2930 #define OPAMP3_CSR_VPSEL_Msk (0x3U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 2931 #define OPAMP3_CSR_VPSEL OPAMP3_CSR_VPSEL_Msk /*!< Non inverting input selection */
<> 147:30b64687e01f 2932 #define OPAMP3_CSR_VPSEL_0 (0x1U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2933 #define OPAMP3_CSR_VPSEL_1 (0x2U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2934 #define OPAMP3_CSR_VMSEL_Pos (5U)
<> 147:30b64687e01f 2935 #define OPAMP3_CSR_VMSEL_Msk (0x3U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000060 */
<> 147:30b64687e01f 2936 #define OPAMP3_CSR_VMSEL OPAMP3_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 147:30b64687e01f 2937 #define OPAMP3_CSR_VMSEL_0 (0x1U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 2938 #define OPAMP3_CSR_VMSEL_1 (0x2U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 2939 #define OPAMP3_CSR_TCMEN_Pos (7U)
<> 147:30b64687e01f 2940 #define OPAMP3_CSR_TCMEN_Msk (0x1U << OPAMP3_CSR_TCMEN_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 2941 #define OPAMP3_CSR_TCMEN OPAMP3_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
<> 147:30b64687e01f 2942 #define OPAMP3_CSR_VMSSEL_Pos (8U)
<> 147:30b64687e01f 2943 #define OPAMP3_CSR_VMSSEL_Msk (0x1U << OPAMP3_CSR_VMSSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 2944 #define OPAMP3_CSR_VMSSEL OPAMP3_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
<> 147:30b64687e01f 2945 #define OPAMP3_CSR_VPSSEL_Pos (9U)
<> 147:30b64687e01f 2946 #define OPAMP3_CSR_VPSSEL_Msk (0x3U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000600 */
<> 147:30b64687e01f 2947 #define OPAMP3_CSR_VPSSEL OPAMP3_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
<> 147:30b64687e01f 2948 #define OPAMP3_CSR_VPSSEL_0 (0x1U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 2949 #define OPAMP3_CSR_VPSSEL_1 (0x2U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 2950 #define OPAMP3_CSR_CALON_Pos (11U)
<> 147:30b64687e01f 2951 #define OPAMP3_CSR_CALON_Msk (0x1U << OPAMP3_CSR_CALON_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 2952 #define OPAMP3_CSR_CALON OPAMP3_CSR_CALON_Msk /*!< Calibration mode enable */
<> 147:30b64687e01f 2953 #define OPAMP3_CSR_CALSEL_Pos (12U)
<> 147:30b64687e01f 2954 #define OPAMP3_CSR_CALSEL_Msk (0x3U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 2955 #define OPAMP3_CSR_CALSEL OPAMP3_CSR_CALSEL_Msk /*!< Calibration selection */
<> 147:30b64687e01f 2956 #define OPAMP3_CSR_CALSEL_0 (0x1U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 2957 #define OPAMP3_CSR_CALSEL_1 (0x2U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 2958 #define OPAMP3_CSR_PGGAIN_Pos (14U)
<> 147:30b64687e01f 2959 #define OPAMP3_CSR_PGGAIN_Msk (0xFU << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
<> 147:30b64687e01f 2960 #define OPAMP3_CSR_PGGAIN OPAMP3_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
<> 147:30b64687e01f 2961 #define OPAMP3_CSR_PGGAIN_0 (0x1U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 2962 #define OPAMP3_CSR_PGGAIN_1 (0x2U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 2963 #define OPAMP3_CSR_PGGAIN_2 (0x4U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 2964 #define OPAMP3_CSR_PGGAIN_3 (0x8U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 2965 #define OPAMP3_CSR_USERTRIM_Pos (18U)
<> 147:30b64687e01f 2966 #define OPAMP3_CSR_USERTRIM_Msk (0x1U << OPAMP3_CSR_USERTRIM_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 2967 #define OPAMP3_CSR_USERTRIM OPAMP3_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 147:30b64687e01f 2968 #define OPAMP3_CSR_TRIMOFFSETP_Pos (19U)
<> 147:30b64687e01f 2969 #define OPAMP3_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP3_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
<> 147:30b64687e01f 2970 #define OPAMP3_CSR_TRIMOFFSETP OPAMP3_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
<> 147:30b64687e01f 2971 #define OPAMP3_CSR_TRIMOFFSETN_Pos (24U)
<> 147:30b64687e01f 2972 #define OPAMP3_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP3_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 2973 #define OPAMP3_CSR_TRIMOFFSETN OPAMP3_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
<> 147:30b64687e01f 2974 #define OPAMP3_CSR_TSTREF_Pos (29U)
<> 147:30b64687e01f 2975 #define OPAMP3_CSR_TSTREF_Msk (0x1U << OPAMP3_CSR_TSTREF_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 2976 #define OPAMP3_CSR_TSTREF OPAMP3_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
<> 147:30b64687e01f 2977 #define OPAMP3_CSR_OUTCAL_Pos (30U)
<> 147:30b64687e01f 2978 #define OPAMP3_CSR_OUTCAL_Msk (0x1U << OPAMP3_CSR_OUTCAL_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 2979 #define OPAMP3_CSR_OUTCAL OPAMP3_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
<> 147:30b64687e01f 2980 #define OPAMP3_CSR_LOCK_Pos (31U)
<> 147:30b64687e01f 2981 #define OPAMP3_CSR_LOCK_Msk (0x1U << OPAMP3_CSR_LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 2982 #define OPAMP3_CSR_LOCK OPAMP3_CSR_LOCK_Msk /*!< OPAMP lock */
<> 147:30b64687e01f 2983
<> 147:30b64687e01f 2984 /********************* Bit definition for OPAMP4_CSR register ***************/
<> 147:30b64687e01f 2985 #define OPAMP4_CSR_OPAMP4EN_Pos (0U)
<> 147:30b64687e01f 2986 #define OPAMP4_CSR_OPAMP4EN_Msk (0x1U << OPAMP4_CSR_OPAMP4EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 2987 #define OPAMP4_CSR_OPAMP4EN OPAMP4_CSR_OPAMP4EN_Msk /*!< OPAMP4 enable */
<> 147:30b64687e01f 2988 #define OPAMP4_CSR_FORCEVP_Pos (1U)
<> 147:30b64687e01f 2989 #define OPAMP4_CSR_FORCEVP_Msk (0x1U << OPAMP4_CSR_FORCEVP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 2990 #define OPAMP4_CSR_FORCEVP OPAMP4_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
<> 147:30b64687e01f 2991 #define OPAMP4_CSR_VPSEL_Pos (2U)
<> 147:30b64687e01f 2992 #define OPAMP4_CSR_VPSEL_Msk (0x3U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 2993 #define OPAMP4_CSR_VPSEL OPAMP4_CSR_VPSEL_Msk /*!< Non inverting input selection */
<> 147:30b64687e01f 2994 #define OPAMP4_CSR_VPSEL_0 (0x1U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 2995 #define OPAMP4_CSR_VPSEL_1 (0x2U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 2996 #define OPAMP4_CSR_VMSEL_Pos (5U)
<> 147:30b64687e01f 2997 #define OPAMP4_CSR_VMSEL_Msk (0x3U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000060 */
<> 147:30b64687e01f 2998 #define OPAMP4_CSR_VMSEL OPAMP4_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 147:30b64687e01f 2999 #define OPAMP4_CSR_VMSEL_0 (0x1U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3000 #define OPAMP4_CSR_VMSEL_1 (0x2U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3001 #define OPAMP4_CSR_TCMEN_Pos (7U)
<> 147:30b64687e01f 3002 #define OPAMP4_CSR_TCMEN_Msk (0x1U << OPAMP4_CSR_TCMEN_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3003 #define OPAMP4_CSR_TCMEN OPAMP4_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
<> 147:30b64687e01f 3004 #define OPAMP4_CSR_VMSSEL_Pos (8U)
<> 147:30b64687e01f 3005 #define OPAMP4_CSR_VMSSEL_Msk (0x1U << OPAMP4_CSR_VMSSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3006 #define OPAMP4_CSR_VMSSEL OPAMP4_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
<> 147:30b64687e01f 3007 #define OPAMP4_CSR_VPSSEL_Pos (9U)
<> 147:30b64687e01f 3008 #define OPAMP4_CSR_VPSSEL_Msk (0x3U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000600 */
<> 147:30b64687e01f 3009 #define OPAMP4_CSR_VPSSEL OPAMP4_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
<> 147:30b64687e01f 3010 #define OPAMP4_CSR_VPSSEL_0 (0x1U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3011 #define OPAMP4_CSR_VPSSEL_1 (0x2U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3012 #define OPAMP4_CSR_CALON_Pos (11U)
<> 147:30b64687e01f 3013 #define OPAMP4_CSR_CALON_Msk (0x1U << OPAMP4_CSR_CALON_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3014 #define OPAMP4_CSR_CALON OPAMP4_CSR_CALON_Msk /*!< Calibration mode enable */
<> 147:30b64687e01f 3015 #define OPAMP4_CSR_CALSEL_Pos (12U)
<> 147:30b64687e01f 3016 #define OPAMP4_CSR_CALSEL_Msk (0x3U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 3017 #define OPAMP4_CSR_CALSEL OPAMP4_CSR_CALSEL_Msk /*!< Calibration selection */
<> 147:30b64687e01f 3018 #define OPAMP4_CSR_CALSEL_0 (0x1U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3019 #define OPAMP4_CSR_CALSEL_1 (0x2U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3020 #define OPAMP4_CSR_PGGAIN_Pos (14U)
<> 147:30b64687e01f 3021 #define OPAMP4_CSR_PGGAIN_Msk (0xFU << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
<> 147:30b64687e01f 3022 #define OPAMP4_CSR_PGGAIN OPAMP4_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
<> 147:30b64687e01f 3023 #define OPAMP4_CSR_PGGAIN_0 (0x1U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 3024 #define OPAMP4_CSR_PGGAIN_1 (0x2U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 3025 #define OPAMP4_CSR_PGGAIN_2 (0x4U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 3026 #define OPAMP4_CSR_PGGAIN_3 (0x8U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 3027 #define OPAMP4_CSR_USERTRIM_Pos (18U)
<> 147:30b64687e01f 3028 #define OPAMP4_CSR_USERTRIM_Msk (0x1U << OPAMP4_CSR_USERTRIM_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 3029 #define OPAMP4_CSR_USERTRIM OPAMP4_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 147:30b64687e01f 3030 #define OPAMP4_CSR_TRIMOFFSETP_Pos (19U)
<> 147:30b64687e01f 3031 #define OPAMP4_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP4_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
<> 147:30b64687e01f 3032 #define OPAMP4_CSR_TRIMOFFSETP OPAMP4_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
<> 147:30b64687e01f 3033 #define OPAMP4_CSR_TRIMOFFSETN_Pos (24U)
<> 147:30b64687e01f 3034 #define OPAMP4_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP4_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 3035 #define OPAMP4_CSR_TRIMOFFSETN OPAMP4_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
<> 147:30b64687e01f 3036 #define OPAMP4_CSR_TSTREF_Pos (29U)
<> 147:30b64687e01f 3037 #define OPAMP4_CSR_TSTREF_Msk (0x1U << OPAMP4_CSR_TSTREF_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 3038 #define OPAMP4_CSR_TSTREF OPAMP4_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
<> 147:30b64687e01f 3039 #define OPAMP4_CSR_OUTCAL_Pos (30U)
<> 147:30b64687e01f 3040 #define OPAMP4_CSR_OUTCAL_Msk (0x1U << OPAMP4_CSR_OUTCAL_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 3041 #define OPAMP4_CSR_OUTCAL OPAMP4_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
<> 147:30b64687e01f 3042 #define OPAMP4_CSR_LOCK_Pos (31U)
<> 147:30b64687e01f 3043 #define OPAMP4_CSR_LOCK_Msk (0x1U << OPAMP4_CSR_LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 3044 #define OPAMP4_CSR_LOCK OPAMP4_CSR_LOCK_Msk /*!< OPAMP lock */
<> 147:30b64687e01f 3045
<> 147:30b64687e01f 3046 /********************* Bit definition for OPAMPx_CSR register ***************/
<> 147:30b64687e01f 3047 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
<> 147:30b64687e01f 3048 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3049 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
<> 147:30b64687e01f 3050 #define OPAMP_CSR_FORCEVP_Pos (1U)
<> 147:30b64687e01f 3051 #define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3052 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
<> 147:30b64687e01f 3053 #define OPAMP_CSR_VPSEL_Pos (2U)
<> 147:30b64687e01f 3054 #define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 3055 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
<> 147:30b64687e01f 3056 #define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3057 #define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3058 #define OPAMP_CSR_VMSEL_Pos (5U)
<> 147:30b64687e01f 3059 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
<> 147:30b64687e01f 3060 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 147:30b64687e01f 3061 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3062 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3063 #define OPAMP_CSR_TCMEN_Pos (7U)
<> 147:30b64687e01f 3064 #define OPAMP_CSR_TCMEN_Msk (0x1U << OPAMP_CSR_TCMEN_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3065 #define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
<> 147:30b64687e01f 3066 #define OPAMP_CSR_VMSSEL_Pos (8U)
<> 147:30b64687e01f 3067 #define OPAMP_CSR_VMSSEL_Msk (0x1U << OPAMP_CSR_VMSSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3068 #define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
<> 147:30b64687e01f 3069 #define OPAMP_CSR_VPSSEL_Pos (9U)
<> 147:30b64687e01f 3070 #define OPAMP_CSR_VPSSEL_Msk (0x3U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000600 */
<> 147:30b64687e01f 3071 #define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
<> 147:30b64687e01f 3072 #define OPAMP_CSR_VPSSEL_0 (0x1U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3073 #define OPAMP_CSR_VPSSEL_1 (0x2U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3074 #define OPAMP_CSR_CALON_Pos (11U)
<> 147:30b64687e01f 3075 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3076 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
<> 147:30b64687e01f 3077 #define OPAMP_CSR_CALSEL_Pos (12U)
<> 147:30b64687e01f 3078 #define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 3079 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
<> 147:30b64687e01f 3080 #define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3081 #define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3082 #define OPAMP_CSR_PGGAIN_Pos (14U)
<> 147:30b64687e01f 3083 #define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
<> 147:30b64687e01f 3084 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
<> 147:30b64687e01f 3085 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 3086 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 3087 #define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 3088 #define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 3089 #define OPAMP_CSR_USERTRIM_Pos (18U)
<> 147:30b64687e01f 3090 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 3091 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 147:30b64687e01f 3092 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
<> 147:30b64687e01f 3093 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
<> 147:30b64687e01f 3094 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
<> 147:30b64687e01f 3095 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
<> 147:30b64687e01f 3096 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
<> 147:30b64687e01f 3097 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
<> 147:30b64687e01f 3098 #define OPAMP_CSR_TSTREF_Pos (29U)
<> 147:30b64687e01f 3099 #define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 3100 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
<> 147:30b64687e01f 3101 #define OPAMP_CSR_OUTCAL_Pos (30U)
<> 147:30b64687e01f 3102 #define OPAMP_CSR_OUTCAL_Msk (0x1U << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 3103 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
<> 147:30b64687e01f 3104 #define OPAMP_CSR_LOCK_Pos (31U)
<> 147:30b64687e01f 3105 #define OPAMP_CSR_LOCK_Msk (0x1U << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 3106 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */
<> 147:30b64687e01f 3107
<> 147:30b64687e01f 3108 /******************************************************************************/
<> 147:30b64687e01f 3109 /* */
<> 147:30b64687e01f 3110 /* Controller Area Network (CAN ) */
<> 147:30b64687e01f 3111 /* */
<> 147:30b64687e01f 3112 /******************************************************************************/
<> 147:30b64687e01f 3113 /******************* Bit definition for CAN_MCR register ********************/
<> 147:30b64687e01f 3114 #define CAN_MCR_INRQ_Pos (0U)
<> 147:30b64687e01f 3115 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3116 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
<> 147:30b64687e01f 3117 #define CAN_MCR_SLEEP_Pos (1U)
<> 147:30b64687e01f 3118 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3119 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
<> 147:30b64687e01f 3120 #define CAN_MCR_TXFP_Pos (2U)
<> 147:30b64687e01f 3121 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3122 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
<> 147:30b64687e01f 3123 #define CAN_MCR_RFLM_Pos (3U)
<> 147:30b64687e01f 3124 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3125 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
<> 147:30b64687e01f 3126 #define CAN_MCR_NART_Pos (4U)
<> 147:30b64687e01f 3127 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3128 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
<> 147:30b64687e01f 3129 #define CAN_MCR_AWUM_Pos (5U)
<> 147:30b64687e01f 3130 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3131 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
<> 147:30b64687e01f 3132 #define CAN_MCR_ABOM_Pos (6U)
<> 147:30b64687e01f 3133 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3134 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
<> 147:30b64687e01f 3135 #define CAN_MCR_TTCM_Pos (7U)
<> 147:30b64687e01f 3136 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3137 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
<> 147:30b64687e01f 3138 #define CAN_MCR_RESET_Pos (15U)
<> 147:30b64687e01f 3139 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 3140 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
<> 147:30b64687e01f 3141
<> 147:30b64687e01f 3142 /******************* Bit definition for CAN_MSR register ********************/
<> 147:30b64687e01f 3143 #define CAN_MSR_INAK_Pos (0U)
<> 147:30b64687e01f 3144 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3145 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
<> 147:30b64687e01f 3146 #define CAN_MSR_SLAK_Pos (1U)
<> 147:30b64687e01f 3147 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3148 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
<> 147:30b64687e01f 3149 #define CAN_MSR_ERRI_Pos (2U)
<> 147:30b64687e01f 3150 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3151 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
<> 147:30b64687e01f 3152 #define CAN_MSR_WKUI_Pos (3U)
<> 147:30b64687e01f 3153 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3154 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
<> 147:30b64687e01f 3155 #define CAN_MSR_SLAKI_Pos (4U)
<> 147:30b64687e01f 3156 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3157 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
<> 147:30b64687e01f 3158 #define CAN_MSR_TXM_Pos (8U)
<> 147:30b64687e01f 3159 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3160 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
<> 147:30b64687e01f 3161 #define CAN_MSR_RXM_Pos (9U)
<> 147:30b64687e01f 3162 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3163 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
<> 147:30b64687e01f 3164 #define CAN_MSR_SAMP_Pos (10U)
<> 147:30b64687e01f 3165 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3166 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
<> 147:30b64687e01f 3167 #define CAN_MSR_RX_Pos (11U)
<> 147:30b64687e01f 3168 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3169 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
<> 147:30b64687e01f 3170
<> 147:30b64687e01f 3171 /******************* Bit definition for CAN_TSR register ********************/
<> 147:30b64687e01f 3172 #define CAN_TSR_RQCP0_Pos (0U)
<> 147:30b64687e01f 3173 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3174 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
<> 147:30b64687e01f 3175 #define CAN_TSR_TXOK0_Pos (1U)
<> 147:30b64687e01f 3176 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3177 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
<> 147:30b64687e01f 3178 #define CAN_TSR_ALST0_Pos (2U)
<> 147:30b64687e01f 3179 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3180 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
<> 147:30b64687e01f 3181 #define CAN_TSR_TERR0_Pos (3U)
<> 147:30b64687e01f 3182 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3183 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
<> 147:30b64687e01f 3184 #define CAN_TSR_ABRQ0_Pos (7U)
<> 147:30b64687e01f 3185 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3186 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
<> 147:30b64687e01f 3187 #define CAN_TSR_RQCP1_Pos (8U)
<> 147:30b64687e01f 3188 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3189 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
<> 147:30b64687e01f 3190 #define CAN_TSR_TXOK1_Pos (9U)
<> 147:30b64687e01f 3191 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3192 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
<> 147:30b64687e01f 3193 #define CAN_TSR_ALST1_Pos (10U)
<> 147:30b64687e01f 3194 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3195 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
<> 147:30b64687e01f 3196 #define CAN_TSR_TERR1_Pos (11U)
<> 147:30b64687e01f 3197 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3198 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
<> 147:30b64687e01f 3199 #define CAN_TSR_ABRQ1_Pos (15U)
<> 147:30b64687e01f 3200 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 3201 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
<> 147:30b64687e01f 3202 #define CAN_TSR_RQCP2_Pos (16U)
<> 147:30b64687e01f 3203 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 3204 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
<> 147:30b64687e01f 3205 #define CAN_TSR_TXOK2_Pos (17U)
<> 147:30b64687e01f 3206 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 3207 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
<> 147:30b64687e01f 3208 #define CAN_TSR_ALST2_Pos (18U)
<> 147:30b64687e01f 3209 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 3210 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
<> 147:30b64687e01f 3211 #define CAN_TSR_TERR2_Pos (19U)
<> 147:30b64687e01f 3212 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 3213 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
<> 147:30b64687e01f 3214 #define CAN_TSR_ABRQ2_Pos (23U)
<> 147:30b64687e01f 3215 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 3216 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
<> 147:30b64687e01f 3217 #define CAN_TSR_CODE_Pos (24U)
<> 147:30b64687e01f 3218 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
<> 147:30b64687e01f 3219 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
<> 147:30b64687e01f 3220
<> 147:30b64687e01f 3221 #define CAN_TSR_TME_Pos (26U)
<> 147:30b64687e01f 3222 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
<> 147:30b64687e01f 3223 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
<> 147:30b64687e01f 3224 #define CAN_TSR_TME0_Pos (26U)
<> 147:30b64687e01f 3225 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 3226 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
<> 147:30b64687e01f 3227 #define CAN_TSR_TME1_Pos (27U)
<> 147:30b64687e01f 3228 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 3229 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
<> 147:30b64687e01f 3230 #define CAN_TSR_TME2_Pos (28U)
<> 147:30b64687e01f 3231 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 3232 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
<> 147:30b64687e01f 3233
<> 147:30b64687e01f 3234 #define CAN_TSR_LOW_Pos (29U)
<> 147:30b64687e01f 3235 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
<> 147:30b64687e01f 3236 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
<> 147:30b64687e01f 3237 #define CAN_TSR_LOW0_Pos (29U)
<> 147:30b64687e01f 3238 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 3239 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
<> 147:30b64687e01f 3240 #define CAN_TSR_LOW1_Pos (30U)
<> 147:30b64687e01f 3241 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 3242 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
<> 147:30b64687e01f 3243 #define CAN_TSR_LOW2_Pos (31U)
<> 147:30b64687e01f 3244 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 3245 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
<> 147:30b64687e01f 3246
<> 147:30b64687e01f 3247 /******************* Bit definition for CAN_RF0R register *******************/
<> 147:30b64687e01f 3248 #define CAN_RF0R_FMP0_Pos (0U)
<> 147:30b64687e01f 3249 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 3250 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
<> 147:30b64687e01f 3251 #define CAN_RF0R_FULL0_Pos (3U)
<> 147:30b64687e01f 3252 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3253 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
<> 147:30b64687e01f 3254 #define CAN_RF0R_FOVR0_Pos (4U)
<> 147:30b64687e01f 3255 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3256 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
<> 147:30b64687e01f 3257 #define CAN_RF0R_RFOM0_Pos (5U)
<> 147:30b64687e01f 3258 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3259 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
<> 147:30b64687e01f 3260
<> 147:30b64687e01f 3261 /******************* Bit definition for CAN_RF1R register *******************/
<> 147:30b64687e01f 3262 #define CAN_RF1R_FMP1_Pos (0U)
<> 147:30b64687e01f 3263 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 3264 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
<> 147:30b64687e01f 3265 #define CAN_RF1R_FULL1_Pos (3U)
<> 147:30b64687e01f 3266 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3267 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
<> 147:30b64687e01f 3268 #define CAN_RF1R_FOVR1_Pos (4U)
<> 147:30b64687e01f 3269 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3270 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
<> 147:30b64687e01f 3271 #define CAN_RF1R_RFOM1_Pos (5U)
<> 147:30b64687e01f 3272 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3273 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
<> 147:30b64687e01f 3274
<> 147:30b64687e01f 3275 /******************** Bit definition for CAN_IER register *******************/
<> 147:30b64687e01f 3276 #define CAN_IER_TMEIE_Pos (0U)
<> 147:30b64687e01f 3277 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3278 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
<> 147:30b64687e01f 3279 #define CAN_IER_FMPIE0_Pos (1U)
<> 147:30b64687e01f 3280 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3281 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 147:30b64687e01f 3282 #define CAN_IER_FFIE0_Pos (2U)
<> 147:30b64687e01f 3283 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3284 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
<> 147:30b64687e01f 3285 #define CAN_IER_FOVIE0_Pos (3U)
<> 147:30b64687e01f 3286 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3287 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
<> 147:30b64687e01f 3288 #define CAN_IER_FMPIE1_Pos (4U)
<> 147:30b64687e01f 3289 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3290 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 147:30b64687e01f 3291 #define CAN_IER_FFIE1_Pos (5U)
<> 147:30b64687e01f 3292 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3293 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
<> 147:30b64687e01f 3294 #define CAN_IER_FOVIE1_Pos (6U)
<> 147:30b64687e01f 3295 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3296 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
<> 147:30b64687e01f 3297 #define CAN_IER_EWGIE_Pos (8U)
<> 147:30b64687e01f 3298 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3299 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
<> 147:30b64687e01f 3300 #define CAN_IER_EPVIE_Pos (9U)
<> 147:30b64687e01f 3301 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3302 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
<> 147:30b64687e01f 3303 #define CAN_IER_BOFIE_Pos (10U)
<> 147:30b64687e01f 3304 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3305 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
<> 147:30b64687e01f 3306 #define CAN_IER_LECIE_Pos (11U)
<> 147:30b64687e01f 3307 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3308 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
<> 147:30b64687e01f 3309 #define CAN_IER_ERRIE_Pos (15U)
<> 147:30b64687e01f 3310 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 3311 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
<> 147:30b64687e01f 3312 #define CAN_IER_WKUIE_Pos (16U)
<> 147:30b64687e01f 3313 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 3314 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
<> 147:30b64687e01f 3315 #define CAN_IER_SLKIE_Pos (17U)
<> 147:30b64687e01f 3316 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 3317 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
<> 147:30b64687e01f 3318
<> 147:30b64687e01f 3319 /******************** Bit definition for CAN_ESR register *******************/
<> 147:30b64687e01f 3320 #define CAN_ESR_EWGF_Pos (0U)
<> 147:30b64687e01f 3321 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3322 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
<> 147:30b64687e01f 3323 #define CAN_ESR_EPVF_Pos (1U)
<> 147:30b64687e01f 3324 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3325 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
<> 147:30b64687e01f 3326 #define CAN_ESR_BOFF_Pos (2U)
<> 147:30b64687e01f 3327 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3328 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
<> 147:30b64687e01f 3329
<> 147:30b64687e01f 3330 #define CAN_ESR_LEC_Pos (4U)
<> 147:30b64687e01f 3331 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 3332 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
<> 147:30b64687e01f 3333 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3334 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3335 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3336
<> 147:30b64687e01f 3337 #define CAN_ESR_TEC_Pos (16U)
<> 147:30b64687e01f 3338 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3339 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
<> 147:30b64687e01f 3340 #define CAN_ESR_REC_Pos (24U)
<> 147:30b64687e01f 3341 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3342 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
<> 147:30b64687e01f 3343
<> 147:30b64687e01f 3344 /******************* Bit definition for CAN_BTR register ********************/
<> 147:30b64687e01f 3345 #define CAN_BTR_BRP_Pos (0U)
<> 147:30b64687e01f 3346 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
<> 147:30b64687e01f 3347 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
<> 147:30b64687e01f 3348 #define CAN_BTR_TS1_Pos (16U)
<> 147:30b64687e01f 3349 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 3350 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
<> 147:30b64687e01f 3351 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 3352 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 3353 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 3354 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 3355 #define CAN_BTR_TS2_Pos (20U)
<> 147:30b64687e01f 3356 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
<> 147:30b64687e01f 3357 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
<> 147:30b64687e01f 3358 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 3359 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 3360 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 3361 #define CAN_BTR_SJW_Pos (24U)
<> 147:30b64687e01f 3362 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
<> 147:30b64687e01f 3363 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
<> 147:30b64687e01f 3364 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 3365 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 3366 #define CAN_BTR_LBKM_Pos (30U)
<> 147:30b64687e01f 3367 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 3368 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
<> 147:30b64687e01f 3369 #define CAN_BTR_SILM_Pos (31U)
<> 147:30b64687e01f 3370 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 3371 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
<> 147:30b64687e01f 3372
<> 147:30b64687e01f 3373 /*!<Mailbox registers */
<> 147:30b64687e01f 3374 /****************** Bit definition for CAN_TI0R register ********************/
<> 147:30b64687e01f 3375 #define CAN_TI0R_TXRQ_Pos (0U)
<> 147:30b64687e01f 3376 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3377 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 147:30b64687e01f 3378 #define CAN_TI0R_RTR_Pos (1U)
<> 147:30b64687e01f 3379 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3380 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
<> 147:30b64687e01f 3381 #define CAN_TI0R_IDE_Pos (2U)
<> 147:30b64687e01f 3382 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3383 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
<> 147:30b64687e01f 3384 #define CAN_TI0R_EXID_Pos (3U)
<> 147:30b64687e01f 3385 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 147:30b64687e01f 3386 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
<> 147:30b64687e01f 3387 #define CAN_TI0R_STID_Pos (21U)
<> 147:30b64687e01f 3388 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
<> 147:30b64687e01f 3389 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 3390
<> 147:30b64687e01f 3391 /****************** Bit definition for CAN_TDT0R register *******************/
<> 147:30b64687e01f 3392 #define CAN_TDT0R_DLC_Pos (0U)
<> 147:30b64687e01f 3393 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 3394 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
<> 147:30b64687e01f 3395 #define CAN_TDT0R_TGT_Pos (8U)
<> 147:30b64687e01f 3396 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3397 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
<> 147:30b64687e01f 3398 #define CAN_TDT0R_TIME_Pos (16U)
<> 147:30b64687e01f 3399 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 3400 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
<> 147:30b64687e01f 3401
<> 147:30b64687e01f 3402 /****************** Bit definition for CAN_TDL0R register *******************/
<> 147:30b64687e01f 3403 #define CAN_TDL0R_DATA0_Pos (0U)
<> 147:30b64687e01f 3404 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3405 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
<> 147:30b64687e01f 3406 #define CAN_TDL0R_DATA1_Pos (8U)
<> 147:30b64687e01f 3407 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3408 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
<> 147:30b64687e01f 3409 #define CAN_TDL0R_DATA2_Pos (16U)
<> 147:30b64687e01f 3410 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3411 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
<> 147:30b64687e01f 3412 #define CAN_TDL0R_DATA3_Pos (24U)
<> 147:30b64687e01f 3413 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3414 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
<> 147:30b64687e01f 3415
<> 147:30b64687e01f 3416 /****************** Bit definition for CAN_TDH0R register *******************/
<> 147:30b64687e01f 3417 #define CAN_TDH0R_DATA4_Pos (0U)
<> 147:30b64687e01f 3418 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3419 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
<> 147:30b64687e01f 3420 #define CAN_TDH0R_DATA5_Pos (8U)
<> 147:30b64687e01f 3421 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3422 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
<> 147:30b64687e01f 3423 #define CAN_TDH0R_DATA6_Pos (16U)
<> 147:30b64687e01f 3424 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3425 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
<> 147:30b64687e01f 3426 #define CAN_TDH0R_DATA7_Pos (24U)
<> 147:30b64687e01f 3427 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3428 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
<> 147:30b64687e01f 3429
<> 147:30b64687e01f 3430 /******************* Bit definition for CAN_TI1R register *******************/
<> 147:30b64687e01f 3431 #define CAN_TI1R_TXRQ_Pos (0U)
<> 147:30b64687e01f 3432 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3433 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 147:30b64687e01f 3434 #define CAN_TI1R_RTR_Pos (1U)
<> 147:30b64687e01f 3435 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3436 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
<> 147:30b64687e01f 3437 #define CAN_TI1R_IDE_Pos (2U)
<> 147:30b64687e01f 3438 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3439 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
<> 147:30b64687e01f 3440 #define CAN_TI1R_EXID_Pos (3U)
<> 147:30b64687e01f 3441 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 147:30b64687e01f 3442 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
<> 147:30b64687e01f 3443 #define CAN_TI1R_STID_Pos (21U)
<> 147:30b64687e01f 3444 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
<> 147:30b64687e01f 3445 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 3446
<> 147:30b64687e01f 3447 /******************* Bit definition for CAN_TDT1R register ******************/
<> 147:30b64687e01f 3448 #define CAN_TDT1R_DLC_Pos (0U)
<> 147:30b64687e01f 3449 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 3450 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
<> 147:30b64687e01f 3451 #define CAN_TDT1R_TGT_Pos (8U)
<> 147:30b64687e01f 3452 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3453 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
<> 147:30b64687e01f 3454 #define CAN_TDT1R_TIME_Pos (16U)
<> 147:30b64687e01f 3455 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 3456 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
<> 147:30b64687e01f 3457
<> 147:30b64687e01f 3458 /******************* Bit definition for CAN_TDL1R register ******************/
<> 147:30b64687e01f 3459 #define CAN_TDL1R_DATA0_Pos (0U)
<> 147:30b64687e01f 3460 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3461 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
<> 147:30b64687e01f 3462 #define CAN_TDL1R_DATA1_Pos (8U)
<> 147:30b64687e01f 3463 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3464 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
<> 147:30b64687e01f 3465 #define CAN_TDL1R_DATA2_Pos (16U)
<> 147:30b64687e01f 3466 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3467 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
<> 147:30b64687e01f 3468 #define CAN_TDL1R_DATA3_Pos (24U)
<> 147:30b64687e01f 3469 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3470 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
<> 147:30b64687e01f 3471
<> 147:30b64687e01f 3472 /******************* Bit definition for CAN_TDH1R register ******************/
<> 147:30b64687e01f 3473 #define CAN_TDH1R_DATA4_Pos (0U)
<> 147:30b64687e01f 3474 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3475 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
<> 147:30b64687e01f 3476 #define CAN_TDH1R_DATA5_Pos (8U)
<> 147:30b64687e01f 3477 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3478 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
<> 147:30b64687e01f 3479 #define CAN_TDH1R_DATA6_Pos (16U)
<> 147:30b64687e01f 3480 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3481 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
<> 147:30b64687e01f 3482 #define CAN_TDH1R_DATA7_Pos (24U)
<> 147:30b64687e01f 3483 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3484 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
<> 147:30b64687e01f 3485
<> 147:30b64687e01f 3486 /******************* Bit definition for CAN_TI2R register *******************/
<> 147:30b64687e01f 3487 #define CAN_TI2R_TXRQ_Pos (0U)
<> 147:30b64687e01f 3488 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3489 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 147:30b64687e01f 3490 #define CAN_TI2R_RTR_Pos (1U)
<> 147:30b64687e01f 3491 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3492 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
<> 147:30b64687e01f 3493 #define CAN_TI2R_IDE_Pos (2U)
<> 147:30b64687e01f 3494 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3495 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
<> 147:30b64687e01f 3496 #define CAN_TI2R_EXID_Pos (3U)
<> 147:30b64687e01f 3497 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
<> 147:30b64687e01f 3498 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
<> 147:30b64687e01f 3499 #define CAN_TI2R_STID_Pos (21U)
<> 147:30b64687e01f 3500 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
<> 147:30b64687e01f 3501 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 3502
<> 147:30b64687e01f 3503 /******************* Bit definition for CAN_TDT2R register ******************/
<> 147:30b64687e01f 3504 #define CAN_TDT2R_DLC_Pos (0U)
<> 147:30b64687e01f 3505 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 3506 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
<> 147:30b64687e01f 3507 #define CAN_TDT2R_TGT_Pos (8U)
<> 147:30b64687e01f 3508 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3509 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
<> 147:30b64687e01f 3510 #define CAN_TDT2R_TIME_Pos (16U)
<> 147:30b64687e01f 3511 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 3512 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
<> 147:30b64687e01f 3513
<> 147:30b64687e01f 3514 /******************* Bit definition for CAN_TDL2R register ******************/
<> 147:30b64687e01f 3515 #define CAN_TDL2R_DATA0_Pos (0U)
<> 147:30b64687e01f 3516 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3517 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
<> 147:30b64687e01f 3518 #define CAN_TDL2R_DATA1_Pos (8U)
<> 147:30b64687e01f 3519 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3520 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
<> 147:30b64687e01f 3521 #define CAN_TDL2R_DATA2_Pos (16U)
<> 147:30b64687e01f 3522 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3523 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
<> 147:30b64687e01f 3524 #define CAN_TDL2R_DATA3_Pos (24U)
<> 147:30b64687e01f 3525 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3526 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
<> 147:30b64687e01f 3527
<> 147:30b64687e01f 3528 /******************* Bit definition for CAN_TDH2R register ******************/
<> 147:30b64687e01f 3529 #define CAN_TDH2R_DATA4_Pos (0U)
<> 147:30b64687e01f 3530 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3531 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
<> 147:30b64687e01f 3532 #define CAN_TDH2R_DATA5_Pos (8U)
<> 147:30b64687e01f 3533 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3534 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
<> 147:30b64687e01f 3535 #define CAN_TDH2R_DATA6_Pos (16U)
<> 147:30b64687e01f 3536 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3537 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
<> 147:30b64687e01f 3538 #define CAN_TDH2R_DATA7_Pos (24U)
<> 147:30b64687e01f 3539 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3540 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
<> 147:30b64687e01f 3541
<> 147:30b64687e01f 3542 /******************* Bit definition for CAN_RI0R register *******************/
<> 147:30b64687e01f 3543 #define CAN_RI0R_RTR_Pos (1U)
<> 147:30b64687e01f 3544 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3545 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
<> 147:30b64687e01f 3546 #define CAN_RI0R_IDE_Pos (2U)
<> 147:30b64687e01f 3547 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3548 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
<> 147:30b64687e01f 3549 #define CAN_RI0R_EXID_Pos (3U)
<> 147:30b64687e01f 3550 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 147:30b64687e01f 3551 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
<> 147:30b64687e01f 3552 #define CAN_RI0R_STID_Pos (21U)
<> 147:30b64687e01f 3553 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
<> 147:30b64687e01f 3554 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 3555
<> 147:30b64687e01f 3556 /******************* Bit definition for CAN_RDT0R register ******************/
<> 147:30b64687e01f 3557 #define CAN_RDT0R_DLC_Pos (0U)
<> 147:30b64687e01f 3558 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 3559 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
<> 147:30b64687e01f 3560 #define CAN_RDT0R_FMI_Pos (8U)
<> 147:30b64687e01f 3561 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3562 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
<> 147:30b64687e01f 3563 #define CAN_RDT0R_TIME_Pos (16U)
<> 147:30b64687e01f 3564 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 3565 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
<> 147:30b64687e01f 3566
<> 147:30b64687e01f 3567 /******************* Bit definition for CAN_RDL0R register ******************/
<> 147:30b64687e01f 3568 #define CAN_RDL0R_DATA0_Pos (0U)
<> 147:30b64687e01f 3569 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3570 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
<> 147:30b64687e01f 3571 #define CAN_RDL0R_DATA1_Pos (8U)
<> 147:30b64687e01f 3572 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3573 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
<> 147:30b64687e01f 3574 #define CAN_RDL0R_DATA2_Pos (16U)
<> 147:30b64687e01f 3575 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3576 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
<> 147:30b64687e01f 3577 #define CAN_RDL0R_DATA3_Pos (24U)
<> 147:30b64687e01f 3578 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3579 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
<> 147:30b64687e01f 3580
<> 147:30b64687e01f 3581 /******************* Bit definition for CAN_RDH0R register ******************/
<> 147:30b64687e01f 3582 #define CAN_RDH0R_DATA4_Pos (0U)
<> 147:30b64687e01f 3583 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3584 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
<> 147:30b64687e01f 3585 #define CAN_RDH0R_DATA5_Pos (8U)
<> 147:30b64687e01f 3586 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3587 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
<> 147:30b64687e01f 3588 #define CAN_RDH0R_DATA6_Pos (16U)
<> 147:30b64687e01f 3589 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3590 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
<> 147:30b64687e01f 3591 #define CAN_RDH0R_DATA7_Pos (24U)
<> 147:30b64687e01f 3592 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3593 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
<> 147:30b64687e01f 3594
<> 147:30b64687e01f 3595 /******************* Bit definition for CAN_RI1R register *******************/
<> 147:30b64687e01f 3596 #define CAN_RI1R_RTR_Pos (1U)
<> 147:30b64687e01f 3597 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3598 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
<> 147:30b64687e01f 3599 #define CAN_RI1R_IDE_Pos (2U)
<> 147:30b64687e01f 3600 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3601 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
<> 147:30b64687e01f 3602 #define CAN_RI1R_EXID_Pos (3U)
<> 147:30b64687e01f 3603 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 147:30b64687e01f 3604 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
<> 147:30b64687e01f 3605 #define CAN_RI1R_STID_Pos (21U)
<> 147:30b64687e01f 3606 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
<> 147:30b64687e01f 3607 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 3608
<> 147:30b64687e01f 3609 /******************* Bit definition for CAN_RDT1R register ******************/
<> 147:30b64687e01f 3610 #define CAN_RDT1R_DLC_Pos (0U)
<> 147:30b64687e01f 3611 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 3612 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
<> 147:30b64687e01f 3613 #define CAN_RDT1R_FMI_Pos (8U)
<> 147:30b64687e01f 3614 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3615 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
<> 147:30b64687e01f 3616 #define CAN_RDT1R_TIME_Pos (16U)
<> 147:30b64687e01f 3617 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 3618 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
<> 147:30b64687e01f 3619
<> 147:30b64687e01f 3620 /******************* Bit definition for CAN_RDL1R register ******************/
<> 147:30b64687e01f 3621 #define CAN_RDL1R_DATA0_Pos (0U)
<> 147:30b64687e01f 3622 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3623 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
<> 147:30b64687e01f 3624 #define CAN_RDL1R_DATA1_Pos (8U)
<> 147:30b64687e01f 3625 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3626 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
<> 147:30b64687e01f 3627 #define CAN_RDL1R_DATA2_Pos (16U)
<> 147:30b64687e01f 3628 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3629 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
<> 147:30b64687e01f 3630 #define CAN_RDL1R_DATA3_Pos (24U)
<> 147:30b64687e01f 3631 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3632 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
<> 147:30b64687e01f 3633
<> 147:30b64687e01f 3634 /******************* Bit definition for CAN_RDH1R register ******************/
<> 147:30b64687e01f 3635 #define CAN_RDH1R_DATA4_Pos (0U)
<> 147:30b64687e01f 3636 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 3637 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
<> 147:30b64687e01f 3638 #define CAN_RDH1R_DATA5_Pos (8U)
<> 147:30b64687e01f 3639 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 3640 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
<> 147:30b64687e01f 3641 #define CAN_RDH1R_DATA6_Pos (16U)
<> 147:30b64687e01f 3642 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 3643 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
<> 147:30b64687e01f 3644 #define CAN_RDH1R_DATA7_Pos (24U)
<> 147:30b64687e01f 3645 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 3646 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
<> 147:30b64687e01f 3647
<> 147:30b64687e01f 3648 /*!<CAN filter registers */
<> 147:30b64687e01f 3649 /******************* Bit definition for CAN_FMR register ********************/
<> 147:30b64687e01f 3650 #define CAN_FMR_FINIT_Pos (0U)
<> 147:30b64687e01f 3651 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3652 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
<> 147:30b64687e01f 3653
<> 147:30b64687e01f 3654 /******************* Bit definition for CAN_FM1R register *******************/
<> 147:30b64687e01f 3655 #define CAN_FM1R_FBM_Pos (0U)
<> 147:30b64687e01f 3656 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
<> 147:30b64687e01f 3657 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
<> 147:30b64687e01f 3658 #define CAN_FM1R_FBM0_Pos (0U)
<> 147:30b64687e01f 3659 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3660 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
<> 147:30b64687e01f 3661 #define CAN_FM1R_FBM1_Pos (1U)
<> 147:30b64687e01f 3662 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3663 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
<> 147:30b64687e01f 3664 #define CAN_FM1R_FBM2_Pos (2U)
<> 147:30b64687e01f 3665 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3666 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
<> 147:30b64687e01f 3667 #define CAN_FM1R_FBM3_Pos (3U)
<> 147:30b64687e01f 3668 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3669 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
<> 147:30b64687e01f 3670 #define CAN_FM1R_FBM4_Pos (4U)
<> 147:30b64687e01f 3671 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3672 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
<> 147:30b64687e01f 3673 #define CAN_FM1R_FBM5_Pos (5U)
<> 147:30b64687e01f 3674 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3675 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
<> 147:30b64687e01f 3676 #define CAN_FM1R_FBM6_Pos (6U)
<> 147:30b64687e01f 3677 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3678 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
<> 147:30b64687e01f 3679 #define CAN_FM1R_FBM7_Pos (7U)
<> 147:30b64687e01f 3680 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3681 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
<> 147:30b64687e01f 3682 #define CAN_FM1R_FBM8_Pos (8U)
<> 147:30b64687e01f 3683 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3684 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
<> 147:30b64687e01f 3685 #define CAN_FM1R_FBM9_Pos (9U)
<> 147:30b64687e01f 3686 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3687 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
<> 147:30b64687e01f 3688 #define CAN_FM1R_FBM10_Pos (10U)
<> 147:30b64687e01f 3689 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3690 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
<> 147:30b64687e01f 3691 #define CAN_FM1R_FBM11_Pos (11U)
<> 147:30b64687e01f 3692 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3693 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
<> 147:30b64687e01f 3694 #define CAN_FM1R_FBM12_Pos (12U)
<> 147:30b64687e01f 3695 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3696 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
<> 147:30b64687e01f 3697 #define CAN_FM1R_FBM13_Pos (13U)
<> 147:30b64687e01f 3698 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3699 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
<> 147:30b64687e01f 3700
<> 147:30b64687e01f 3701 /******************* Bit definition for CAN_FS1R register *******************/
<> 147:30b64687e01f 3702 #define CAN_FS1R_FSC_Pos (0U)
<> 147:30b64687e01f 3703 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
<> 147:30b64687e01f 3704 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
<> 147:30b64687e01f 3705 #define CAN_FS1R_FSC0_Pos (0U)
<> 147:30b64687e01f 3706 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3707 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
<> 147:30b64687e01f 3708 #define CAN_FS1R_FSC1_Pos (1U)
<> 147:30b64687e01f 3709 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3710 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
<> 147:30b64687e01f 3711 #define CAN_FS1R_FSC2_Pos (2U)
<> 147:30b64687e01f 3712 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3713 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
<> 147:30b64687e01f 3714 #define CAN_FS1R_FSC3_Pos (3U)
<> 147:30b64687e01f 3715 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3716 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
<> 147:30b64687e01f 3717 #define CAN_FS1R_FSC4_Pos (4U)
<> 147:30b64687e01f 3718 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3719 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
<> 147:30b64687e01f 3720 #define CAN_FS1R_FSC5_Pos (5U)
<> 147:30b64687e01f 3721 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3722 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
<> 147:30b64687e01f 3723 #define CAN_FS1R_FSC6_Pos (6U)
<> 147:30b64687e01f 3724 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3725 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
<> 147:30b64687e01f 3726 #define CAN_FS1R_FSC7_Pos (7U)
<> 147:30b64687e01f 3727 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3728 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
<> 147:30b64687e01f 3729 #define CAN_FS1R_FSC8_Pos (8U)
<> 147:30b64687e01f 3730 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3731 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
<> 147:30b64687e01f 3732 #define CAN_FS1R_FSC9_Pos (9U)
<> 147:30b64687e01f 3733 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3734 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
<> 147:30b64687e01f 3735 #define CAN_FS1R_FSC10_Pos (10U)
<> 147:30b64687e01f 3736 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3737 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
<> 147:30b64687e01f 3738 #define CAN_FS1R_FSC11_Pos (11U)
<> 147:30b64687e01f 3739 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3740 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
<> 147:30b64687e01f 3741 #define CAN_FS1R_FSC12_Pos (12U)
<> 147:30b64687e01f 3742 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3743 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
<> 147:30b64687e01f 3744 #define CAN_FS1R_FSC13_Pos (13U)
<> 147:30b64687e01f 3745 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3746 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
<> 147:30b64687e01f 3747
<> 147:30b64687e01f 3748 /****************** Bit definition for CAN_FFA1R register *******************/
<> 147:30b64687e01f 3749 #define CAN_FFA1R_FFA_Pos (0U)
<> 147:30b64687e01f 3750 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
<> 147:30b64687e01f 3751 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
<> 147:30b64687e01f 3752 #define CAN_FFA1R_FFA0_Pos (0U)
<> 147:30b64687e01f 3753 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3754 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
<> 147:30b64687e01f 3755 #define CAN_FFA1R_FFA1_Pos (1U)
<> 147:30b64687e01f 3756 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3757 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
<> 147:30b64687e01f 3758 #define CAN_FFA1R_FFA2_Pos (2U)
<> 147:30b64687e01f 3759 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3760 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
<> 147:30b64687e01f 3761 #define CAN_FFA1R_FFA3_Pos (3U)
<> 147:30b64687e01f 3762 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3763 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
<> 147:30b64687e01f 3764 #define CAN_FFA1R_FFA4_Pos (4U)
<> 147:30b64687e01f 3765 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3766 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
<> 147:30b64687e01f 3767 #define CAN_FFA1R_FFA5_Pos (5U)
<> 147:30b64687e01f 3768 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3769 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
<> 147:30b64687e01f 3770 #define CAN_FFA1R_FFA6_Pos (6U)
<> 147:30b64687e01f 3771 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3772 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
<> 147:30b64687e01f 3773 #define CAN_FFA1R_FFA7_Pos (7U)
<> 147:30b64687e01f 3774 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3775 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
<> 147:30b64687e01f 3776 #define CAN_FFA1R_FFA8_Pos (8U)
<> 147:30b64687e01f 3777 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3778 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
<> 147:30b64687e01f 3779 #define CAN_FFA1R_FFA9_Pos (9U)
<> 147:30b64687e01f 3780 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3781 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
<> 147:30b64687e01f 3782 #define CAN_FFA1R_FFA10_Pos (10U)
<> 147:30b64687e01f 3783 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3784 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
<> 147:30b64687e01f 3785 #define CAN_FFA1R_FFA11_Pos (11U)
<> 147:30b64687e01f 3786 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3787 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
<> 147:30b64687e01f 3788 #define CAN_FFA1R_FFA12_Pos (12U)
<> 147:30b64687e01f 3789 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3790 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
<> 147:30b64687e01f 3791 #define CAN_FFA1R_FFA13_Pos (13U)
<> 147:30b64687e01f 3792 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3793 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
<> 147:30b64687e01f 3794
<> 147:30b64687e01f 3795 /******************* Bit definition for CAN_FA1R register *******************/
<> 147:30b64687e01f 3796 #define CAN_FA1R_FACT_Pos (0U)
<> 147:30b64687e01f 3797 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
<> 147:30b64687e01f 3798 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
<> 147:30b64687e01f 3799 #define CAN_FA1R_FACT0_Pos (0U)
<> 147:30b64687e01f 3800 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3801 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
<> 147:30b64687e01f 3802 #define CAN_FA1R_FACT1_Pos (1U)
<> 147:30b64687e01f 3803 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3804 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
<> 147:30b64687e01f 3805 #define CAN_FA1R_FACT2_Pos (2U)
<> 147:30b64687e01f 3806 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3807 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
<> 147:30b64687e01f 3808 #define CAN_FA1R_FACT3_Pos (3U)
<> 147:30b64687e01f 3809 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3810 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
<> 147:30b64687e01f 3811 #define CAN_FA1R_FACT4_Pos (4U)
<> 147:30b64687e01f 3812 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3813 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
<> 147:30b64687e01f 3814 #define CAN_FA1R_FACT5_Pos (5U)
<> 147:30b64687e01f 3815 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3816 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
<> 147:30b64687e01f 3817 #define CAN_FA1R_FACT6_Pos (6U)
<> 147:30b64687e01f 3818 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3819 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
<> 147:30b64687e01f 3820 #define CAN_FA1R_FACT7_Pos (7U)
<> 147:30b64687e01f 3821 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3822 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
<> 147:30b64687e01f 3823 #define CAN_FA1R_FACT8_Pos (8U)
<> 147:30b64687e01f 3824 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3825 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
<> 147:30b64687e01f 3826 #define CAN_FA1R_FACT9_Pos (9U)
<> 147:30b64687e01f 3827 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3828 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
<> 147:30b64687e01f 3829 #define CAN_FA1R_FACT10_Pos (10U)
<> 147:30b64687e01f 3830 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3831 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
<> 147:30b64687e01f 3832 #define CAN_FA1R_FACT11_Pos (11U)
<> 147:30b64687e01f 3833 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3834 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
<> 147:30b64687e01f 3835 #define CAN_FA1R_FACT12_Pos (12U)
<> 147:30b64687e01f 3836 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3837 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
<> 147:30b64687e01f 3838 #define CAN_FA1R_FACT13_Pos (13U)
<> 147:30b64687e01f 3839 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3840 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
<> 147:30b64687e01f 3841
<> 147:30b64687e01f 3842 /******************* Bit definition for CAN_F0R1 register *******************/
<> 147:30b64687e01f 3843 #define CAN_F0R1_FB0_Pos (0U)
<> 147:30b64687e01f 3844 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3845 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 3846 #define CAN_F0R1_FB1_Pos (1U)
<> 147:30b64687e01f 3847 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3848 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 3849 #define CAN_F0R1_FB2_Pos (2U)
<> 147:30b64687e01f 3850 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3851 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 3852 #define CAN_F0R1_FB3_Pos (3U)
<> 147:30b64687e01f 3853 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3854 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 3855 #define CAN_F0R1_FB4_Pos (4U)
<> 147:30b64687e01f 3856 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3857 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 3858 #define CAN_F0R1_FB5_Pos (5U)
<> 147:30b64687e01f 3859 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3860 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 3861 #define CAN_F0R1_FB6_Pos (6U)
<> 147:30b64687e01f 3862 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3863 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 3864 #define CAN_F0R1_FB7_Pos (7U)
<> 147:30b64687e01f 3865 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3866 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 3867 #define CAN_F0R1_FB8_Pos (8U)
<> 147:30b64687e01f 3868 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3869 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 3870 #define CAN_F0R1_FB9_Pos (9U)
<> 147:30b64687e01f 3871 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3872 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 3873 #define CAN_F0R1_FB10_Pos (10U)
<> 147:30b64687e01f 3874 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3875 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 3876 #define CAN_F0R1_FB11_Pos (11U)
<> 147:30b64687e01f 3877 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3878 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 3879 #define CAN_F0R1_FB12_Pos (12U)
<> 147:30b64687e01f 3880 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3881 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 3882 #define CAN_F0R1_FB13_Pos (13U)
<> 147:30b64687e01f 3883 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3884 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 3885 #define CAN_F0R1_FB14_Pos (14U)
<> 147:30b64687e01f 3886 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 3887 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 3888 #define CAN_F0R1_FB15_Pos (15U)
<> 147:30b64687e01f 3889 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 3890 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 3891 #define CAN_F0R1_FB16_Pos (16U)
<> 147:30b64687e01f 3892 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 3893 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 3894 #define CAN_F0R1_FB17_Pos (17U)
<> 147:30b64687e01f 3895 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 3896 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 3897 #define CAN_F0R1_FB18_Pos (18U)
<> 147:30b64687e01f 3898 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 3899 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 3900 #define CAN_F0R1_FB19_Pos (19U)
<> 147:30b64687e01f 3901 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 3902 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 3903 #define CAN_F0R1_FB20_Pos (20U)
<> 147:30b64687e01f 3904 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 3905 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 3906 #define CAN_F0R1_FB21_Pos (21U)
<> 147:30b64687e01f 3907 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 3908 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 3909 #define CAN_F0R1_FB22_Pos (22U)
<> 147:30b64687e01f 3910 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 3911 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 3912 #define CAN_F0R1_FB23_Pos (23U)
<> 147:30b64687e01f 3913 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 3914 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 3915 #define CAN_F0R1_FB24_Pos (24U)
<> 147:30b64687e01f 3916 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 3917 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 3918 #define CAN_F0R1_FB25_Pos (25U)
<> 147:30b64687e01f 3919 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 3920 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 3921 #define CAN_F0R1_FB26_Pos (26U)
<> 147:30b64687e01f 3922 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 3923 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 3924 #define CAN_F0R1_FB27_Pos (27U)
<> 147:30b64687e01f 3925 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 3926 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 3927 #define CAN_F0R1_FB28_Pos (28U)
<> 147:30b64687e01f 3928 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 3929 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 3930 #define CAN_F0R1_FB29_Pos (29U)
<> 147:30b64687e01f 3931 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 3932 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 3933 #define CAN_F0R1_FB30_Pos (30U)
<> 147:30b64687e01f 3934 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 3935 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 3936 #define CAN_F0R1_FB31_Pos (31U)
<> 147:30b64687e01f 3937 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 3938 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 3939
<> 147:30b64687e01f 3940 /******************* Bit definition for CAN_F1R1 register *******************/
<> 147:30b64687e01f 3941 #define CAN_F1R1_FB0_Pos (0U)
<> 147:30b64687e01f 3942 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 3943 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 3944 #define CAN_F1R1_FB1_Pos (1U)
<> 147:30b64687e01f 3945 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 3946 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 3947 #define CAN_F1R1_FB2_Pos (2U)
<> 147:30b64687e01f 3948 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 3949 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 3950 #define CAN_F1R1_FB3_Pos (3U)
<> 147:30b64687e01f 3951 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 3952 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 3953 #define CAN_F1R1_FB4_Pos (4U)
<> 147:30b64687e01f 3954 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 3955 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 3956 #define CAN_F1R1_FB5_Pos (5U)
<> 147:30b64687e01f 3957 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 3958 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 3959 #define CAN_F1R1_FB6_Pos (6U)
<> 147:30b64687e01f 3960 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 3961 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 3962 #define CAN_F1R1_FB7_Pos (7U)
<> 147:30b64687e01f 3963 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 3964 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 3965 #define CAN_F1R1_FB8_Pos (8U)
<> 147:30b64687e01f 3966 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 3967 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 3968 #define CAN_F1R1_FB9_Pos (9U)
<> 147:30b64687e01f 3969 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 3970 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 3971 #define CAN_F1R1_FB10_Pos (10U)
<> 147:30b64687e01f 3972 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 3973 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 3974 #define CAN_F1R1_FB11_Pos (11U)
<> 147:30b64687e01f 3975 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 3976 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 3977 #define CAN_F1R1_FB12_Pos (12U)
<> 147:30b64687e01f 3978 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 3979 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 3980 #define CAN_F1R1_FB13_Pos (13U)
<> 147:30b64687e01f 3981 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 3982 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 3983 #define CAN_F1R1_FB14_Pos (14U)
<> 147:30b64687e01f 3984 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 3985 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 3986 #define CAN_F1R1_FB15_Pos (15U)
<> 147:30b64687e01f 3987 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 3988 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 3989 #define CAN_F1R1_FB16_Pos (16U)
<> 147:30b64687e01f 3990 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 3991 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 3992 #define CAN_F1R1_FB17_Pos (17U)
<> 147:30b64687e01f 3993 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 3994 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 3995 #define CAN_F1R1_FB18_Pos (18U)
<> 147:30b64687e01f 3996 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 3997 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 3998 #define CAN_F1R1_FB19_Pos (19U)
<> 147:30b64687e01f 3999 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4000 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4001 #define CAN_F1R1_FB20_Pos (20U)
<> 147:30b64687e01f 4002 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4003 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4004 #define CAN_F1R1_FB21_Pos (21U)
<> 147:30b64687e01f 4005 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4006 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4007 #define CAN_F1R1_FB22_Pos (22U)
<> 147:30b64687e01f 4008 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4009 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4010 #define CAN_F1R1_FB23_Pos (23U)
<> 147:30b64687e01f 4011 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4012 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4013 #define CAN_F1R1_FB24_Pos (24U)
<> 147:30b64687e01f 4014 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4015 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4016 #define CAN_F1R1_FB25_Pos (25U)
<> 147:30b64687e01f 4017 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4018 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4019 #define CAN_F1R1_FB26_Pos (26U)
<> 147:30b64687e01f 4020 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4021 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4022 #define CAN_F1R1_FB27_Pos (27U)
<> 147:30b64687e01f 4023 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4024 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4025 #define CAN_F1R1_FB28_Pos (28U)
<> 147:30b64687e01f 4026 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4027 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4028 #define CAN_F1R1_FB29_Pos (29U)
<> 147:30b64687e01f 4029 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4030 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4031 #define CAN_F1R1_FB30_Pos (30U)
<> 147:30b64687e01f 4032 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4033 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4034 #define CAN_F1R1_FB31_Pos (31U)
<> 147:30b64687e01f 4035 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4036 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4037
<> 147:30b64687e01f 4038 /******************* Bit definition for CAN_F2R1 register *******************/
<> 147:30b64687e01f 4039 #define CAN_F2R1_FB0_Pos (0U)
<> 147:30b64687e01f 4040 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4041 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4042 #define CAN_F2R1_FB1_Pos (1U)
<> 147:30b64687e01f 4043 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4044 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4045 #define CAN_F2R1_FB2_Pos (2U)
<> 147:30b64687e01f 4046 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4047 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4048 #define CAN_F2R1_FB3_Pos (3U)
<> 147:30b64687e01f 4049 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4050 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4051 #define CAN_F2R1_FB4_Pos (4U)
<> 147:30b64687e01f 4052 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4053 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4054 #define CAN_F2R1_FB5_Pos (5U)
<> 147:30b64687e01f 4055 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4056 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4057 #define CAN_F2R1_FB6_Pos (6U)
<> 147:30b64687e01f 4058 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4059 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4060 #define CAN_F2R1_FB7_Pos (7U)
<> 147:30b64687e01f 4061 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4062 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4063 #define CAN_F2R1_FB8_Pos (8U)
<> 147:30b64687e01f 4064 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4065 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4066 #define CAN_F2R1_FB9_Pos (9U)
<> 147:30b64687e01f 4067 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4068 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4069 #define CAN_F2R1_FB10_Pos (10U)
<> 147:30b64687e01f 4070 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4071 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4072 #define CAN_F2R1_FB11_Pos (11U)
<> 147:30b64687e01f 4073 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4074 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4075 #define CAN_F2R1_FB12_Pos (12U)
<> 147:30b64687e01f 4076 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4077 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4078 #define CAN_F2R1_FB13_Pos (13U)
<> 147:30b64687e01f 4079 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4080 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4081 #define CAN_F2R1_FB14_Pos (14U)
<> 147:30b64687e01f 4082 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4083 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4084 #define CAN_F2R1_FB15_Pos (15U)
<> 147:30b64687e01f 4085 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4086 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4087 #define CAN_F2R1_FB16_Pos (16U)
<> 147:30b64687e01f 4088 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4089 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4090 #define CAN_F2R1_FB17_Pos (17U)
<> 147:30b64687e01f 4091 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4092 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4093 #define CAN_F2R1_FB18_Pos (18U)
<> 147:30b64687e01f 4094 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4095 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4096 #define CAN_F2R1_FB19_Pos (19U)
<> 147:30b64687e01f 4097 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4098 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4099 #define CAN_F2R1_FB20_Pos (20U)
<> 147:30b64687e01f 4100 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4101 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4102 #define CAN_F2R1_FB21_Pos (21U)
<> 147:30b64687e01f 4103 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4104 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4105 #define CAN_F2R1_FB22_Pos (22U)
<> 147:30b64687e01f 4106 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4107 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4108 #define CAN_F2R1_FB23_Pos (23U)
<> 147:30b64687e01f 4109 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4110 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4111 #define CAN_F2R1_FB24_Pos (24U)
<> 147:30b64687e01f 4112 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4113 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4114 #define CAN_F2R1_FB25_Pos (25U)
<> 147:30b64687e01f 4115 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4116 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4117 #define CAN_F2R1_FB26_Pos (26U)
<> 147:30b64687e01f 4118 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4119 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4120 #define CAN_F2R1_FB27_Pos (27U)
<> 147:30b64687e01f 4121 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4122 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4123 #define CAN_F2R1_FB28_Pos (28U)
<> 147:30b64687e01f 4124 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4125 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4126 #define CAN_F2R1_FB29_Pos (29U)
<> 147:30b64687e01f 4127 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4128 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4129 #define CAN_F2R1_FB30_Pos (30U)
<> 147:30b64687e01f 4130 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4131 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4132 #define CAN_F2R1_FB31_Pos (31U)
<> 147:30b64687e01f 4133 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4134 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4135
<> 147:30b64687e01f 4136 /******************* Bit definition for CAN_F3R1 register *******************/
<> 147:30b64687e01f 4137 #define CAN_F3R1_FB0_Pos (0U)
<> 147:30b64687e01f 4138 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4139 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4140 #define CAN_F3R1_FB1_Pos (1U)
<> 147:30b64687e01f 4141 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4142 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4143 #define CAN_F3R1_FB2_Pos (2U)
<> 147:30b64687e01f 4144 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4145 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4146 #define CAN_F3R1_FB3_Pos (3U)
<> 147:30b64687e01f 4147 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4148 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4149 #define CAN_F3R1_FB4_Pos (4U)
<> 147:30b64687e01f 4150 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4151 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4152 #define CAN_F3R1_FB5_Pos (5U)
<> 147:30b64687e01f 4153 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4154 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4155 #define CAN_F3R1_FB6_Pos (6U)
<> 147:30b64687e01f 4156 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4157 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4158 #define CAN_F3R1_FB7_Pos (7U)
<> 147:30b64687e01f 4159 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4160 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4161 #define CAN_F3R1_FB8_Pos (8U)
<> 147:30b64687e01f 4162 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4163 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4164 #define CAN_F3R1_FB9_Pos (9U)
<> 147:30b64687e01f 4165 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4166 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4167 #define CAN_F3R1_FB10_Pos (10U)
<> 147:30b64687e01f 4168 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4169 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4170 #define CAN_F3R1_FB11_Pos (11U)
<> 147:30b64687e01f 4171 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4172 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4173 #define CAN_F3R1_FB12_Pos (12U)
<> 147:30b64687e01f 4174 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4175 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4176 #define CAN_F3R1_FB13_Pos (13U)
<> 147:30b64687e01f 4177 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4178 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4179 #define CAN_F3R1_FB14_Pos (14U)
<> 147:30b64687e01f 4180 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4181 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4182 #define CAN_F3R1_FB15_Pos (15U)
<> 147:30b64687e01f 4183 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4184 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4185 #define CAN_F3R1_FB16_Pos (16U)
<> 147:30b64687e01f 4186 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4187 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4188 #define CAN_F3R1_FB17_Pos (17U)
<> 147:30b64687e01f 4189 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4190 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4191 #define CAN_F3R1_FB18_Pos (18U)
<> 147:30b64687e01f 4192 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4193 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4194 #define CAN_F3R1_FB19_Pos (19U)
<> 147:30b64687e01f 4195 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4196 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4197 #define CAN_F3R1_FB20_Pos (20U)
<> 147:30b64687e01f 4198 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4199 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4200 #define CAN_F3R1_FB21_Pos (21U)
<> 147:30b64687e01f 4201 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4202 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4203 #define CAN_F3R1_FB22_Pos (22U)
<> 147:30b64687e01f 4204 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4205 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4206 #define CAN_F3R1_FB23_Pos (23U)
<> 147:30b64687e01f 4207 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4208 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4209 #define CAN_F3R1_FB24_Pos (24U)
<> 147:30b64687e01f 4210 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4211 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4212 #define CAN_F3R1_FB25_Pos (25U)
<> 147:30b64687e01f 4213 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4214 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4215 #define CAN_F3R1_FB26_Pos (26U)
<> 147:30b64687e01f 4216 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4217 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4218 #define CAN_F3R1_FB27_Pos (27U)
<> 147:30b64687e01f 4219 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4220 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4221 #define CAN_F3R1_FB28_Pos (28U)
<> 147:30b64687e01f 4222 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4223 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4224 #define CAN_F3R1_FB29_Pos (29U)
<> 147:30b64687e01f 4225 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4226 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4227 #define CAN_F3R1_FB30_Pos (30U)
<> 147:30b64687e01f 4228 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4229 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4230 #define CAN_F3R1_FB31_Pos (31U)
<> 147:30b64687e01f 4231 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4232 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4233
<> 147:30b64687e01f 4234 /******************* Bit definition for CAN_F4R1 register *******************/
<> 147:30b64687e01f 4235 #define CAN_F4R1_FB0_Pos (0U)
<> 147:30b64687e01f 4236 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4237 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4238 #define CAN_F4R1_FB1_Pos (1U)
<> 147:30b64687e01f 4239 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4240 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4241 #define CAN_F4R1_FB2_Pos (2U)
<> 147:30b64687e01f 4242 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4243 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4244 #define CAN_F4R1_FB3_Pos (3U)
<> 147:30b64687e01f 4245 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4246 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4247 #define CAN_F4R1_FB4_Pos (4U)
<> 147:30b64687e01f 4248 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4249 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4250 #define CAN_F4R1_FB5_Pos (5U)
<> 147:30b64687e01f 4251 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4252 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4253 #define CAN_F4R1_FB6_Pos (6U)
<> 147:30b64687e01f 4254 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4255 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4256 #define CAN_F4R1_FB7_Pos (7U)
<> 147:30b64687e01f 4257 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4258 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4259 #define CAN_F4R1_FB8_Pos (8U)
<> 147:30b64687e01f 4260 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4261 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4262 #define CAN_F4R1_FB9_Pos (9U)
<> 147:30b64687e01f 4263 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4264 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4265 #define CAN_F4R1_FB10_Pos (10U)
<> 147:30b64687e01f 4266 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4267 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4268 #define CAN_F4R1_FB11_Pos (11U)
<> 147:30b64687e01f 4269 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4270 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4271 #define CAN_F4R1_FB12_Pos (12U)
<> 147:30b64687e01f 4272 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4273 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4274 #define CAN_F4R1_FB13_Pos (13U)
<> 147:30b64687e01f 4275 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4276 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4277 #define CAN_F4R1_FB14_Pos (14U)
<> 147:30b64687e01f 4278 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4279 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4280 #define CAN_F4R1_FB15_Pos (15U)
<> 147:30b64687e01f 4281 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4282 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4283 #define CAN_F4R1_FB16_Pos (16U)
<> 147:30b64687e01f 4284 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4285 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4286 #define CAN_F4R1_FB17_Pos (17U)
<> 147:30b64687e01f 4287 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4288 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4289 #define CAN_F4R1_FB18_Pos (18U)
<> 147:30b64687e01f 4290 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4291 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4292 #define CAN_F4R1_FB19_Pos (19U)
<> 147:30b64687e01f 4293 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4294 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4295 #define CAN_F4R1_FB20_Pos (20U)
<> 147:30b64687e01f 4296 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4297 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4298 #define CAN_F4R1_FB21_Pos (21U)
<> 147:30b64687e01f 4299 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4300 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4301 #define CAN_F4R1_FB22_Pos (22U)
<> 147:30b64687e01f 4302 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4303 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4304 #define CAN_F4R1_FB23_Pos (23U)
<> 147:30b64687e01f 4305 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4306 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4307 #define CAN_F4R1_FB24_Pos (24U)
<> 147:30b64687e01f 4308 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4309 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4310 #define CAN_F4R1_FB25_Pos (25U)
<> 147:30b64687e01f 4311 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4312 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4313 #define CAN_F4R1_FB26_Pos (26U)
<> 147:30b64687e01f 4314 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4315 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4316 #define CAN_F4R1_FB27_Pos (27U)
<> 147:30b64687e01f 4317 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4318 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4319 #define CAN_F4R1_FB28_Pos (28U)
<> 147:30b64687e01f 4320 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4321 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4322 #define CAN_F4R1_FB29_Pos (29U)
<> 147:30b64687e01f 4323 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4324 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4325 #define CAN_F4R1_FB30_Pos (30U)
<> 147:30b64687e01f 4326 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4327 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4328 #define CAN_F4R1_FB31_Pos (31U)
<> 147:30b64687e01f 4329 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4330 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4331
<> 147:30b64687e01f 4332 /******************* Bit definition for CAN_F5R1 register *******************/
<> 147:30b64687e01f 4333 #define CAN_F5R1_FB0_Pos (0U)
<> 147:30b64687e01f 4334 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4335 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4336 #define CAN_F5R1_FB1_Pos (1U)
<> 147:30b64687e01f 4337 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4338 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4339 #define CAN_F5R1_FB2_Pos (2U)
<> 147:30b64687e01f 4340 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4341 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4342 #define CAN_F5R1_FB3_Pos (3U)
<> 147:30b64687e01f 4343 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4344 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4345 #define CAN_F5R1_FB4_Pos (4U)
<> 147:30b64687e01f 4346 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4347 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4348 #define CAN_F5R1_FB5_Pos (5U)
<> 147:30b64687e01f 4349 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4350 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4351 #define CAN_F5R1_FB6_Pos (6U)
<> 147:30b64687e01f 4352 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4353 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4354 #define CAN_F5R1_FB7_Pos (7U)
<> 147:30b64687e01f 4355 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4356 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4357 #define CAN_F5R1_FB8_Pos (8U)
<> 147:30b64687e01f 4358 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4359 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4360 #define CAN_F5R1_FB9_Pos (9U)
<> 147:30b64687e01f 4361 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4362 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4363 #define CAN_F5R1_FB10_Pos (10U)
<> 147:30b64687e01f 4364 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4365 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4366 #define CAN_F5R1_FB11_Pos (11U)
<> 147:30b64687e01f 4367 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4368 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4369 #define CAN_F5R1_FB12_Pos (12U)
<> 147:30b64687e01f 4370 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4371 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4372 #define CAN_F5R1_FB13_Pos (13U)
<> 147:30b64687e01f 4373 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4374 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4375 #define CAN_F5R1_FB14_Pos (14U)
<> 147:30b64687e01f 4376 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4377 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4378 #define CAN_F5R1_FB15_Pos (15U)
<> 147:30b64687e01f 4379 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4380 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4381 #define CAN_F5R1_FB16_Pos (16U)
<> 147:30b64687e01f 4382 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4383 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4384 #define CAN_F5R1_FB17_Pos (17U)
<> 147:30b64687e01f 4385 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4386 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4387 #define CAN_F5R1_FB18_Pos (18U)
<> 147:30b64687e01f 4388 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4389 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4390 #define CAN_F5R1_FB19_Pos (19U)
<> 147:30b64687e01f 4391 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4392 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4393 #define CAN_F5R1_FB20_Pos (20U)
<> 147:30b64687e01f 4394 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4395 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4396 #define CAN_F5R1_FB21_Pos (21U)
<> 147:30b64687e01f 4397 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4398 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4399 #define CAN_F5R1_FB22_Pos (22U)
<> 147:30b64687e01f 4400 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4401 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4402 #define CAN_F5R1_FB23_Pos (23U)
<> 147:30b64687e01f 4403 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4404 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4405 #define CAN_F5R1_FB24_Pos (24U)
<> 147:30b64687e01f 4406 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4407 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4408 #define CAN_F5R1_FB25_Pos (25U)
<> 147:30b64687e01f 4409 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4410 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4411 #define CAN_F5R1_FB26_Pos (26U)
<> 147:30b64687e01f 4412 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4413 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4414 #define CAN_F5R1_FB27_Pos (27U)
<> 147:30b64687e01f 4415 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4416 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4417 #define CAN_F5R1_FB28_Pos (28U)
<> 147:30b64687e01f 4418 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4419 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4420 #define CAN_F5R1_FB29_Pos (29U)
<> 147:30b64687e01f 4421 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4422 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4423 #define CAN_F5R1_FB30_Pos (30U)
<> 147:30b64687e01f 4424 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4425 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4426 #define CAN_F5R1_FB31_Pos (31U)
<> 147:30b64687e01f 4427 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4428 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4429
<> 147:30b64687e01f 4430 /******************* Bit definition for CAN_F6R1 register *******************/
<> 147:30b64687e01f 4431 #define CAN_F6R1_FB0_Pos (0U)
<> 147:30b64687e01f 4432 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4433 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4434 #define CAN_F6R1_FB1_Pos (1U)
<> 147:30b64687e01f 4435 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4436 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4437 #define CAN_F6R1_FB2_Pos (2U)
<> 147:30b64687e01f 4438 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4439 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4440 #define CAN_F6R1_FB3_Pos (3U)
<> 147:30b64687e01f 4441 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4442 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4443 #define CAN_F6R1_FB4_Pos (4U)
<> 147:30b64687e01f 4444 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4445 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4446 #define CAN_F6R1_FB5_Pos (5U)
<> 147:30b64687e01f 4447 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4448 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4449 #define CAN_F6R1_FB6_Pos (6U)
<> 147:30b64687e01f 4450 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4451 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4452 #define CAN_F6R1_FB7_Pos (7U)
<> 147:30b64687e01f 4453 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4454 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4455 #define CAN_F6R1_FB8_Pos (8U)
<> 147:30b64687e01f 4456 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4457 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4458 #define CAN_F6R1_FB9_Pos (9U)
<> 147:30b64687e01f 4459 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4460 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4461 #define CAN_F6R1_FB10_Pos (10U)
<> 147:30b64687e01f 4462 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4463 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4464 #define CAN_F6R1_FB11_Pos (11U)
<> 147:30b64687e01f 4465 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4466 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4467 #define CAN_F6R1_FB12_Pos (12U)
<> 147:30b64687e01f 4468 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4469 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4470 #define CAN_F6R1_FB13_Pos (13U)
<> 147:30b64687e01f 4471 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4472 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4473 #define CAN_F6R1_FB14_Pos (14U)
<> 147:30b64687e01f 4474 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4475 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4476 #define CAN_F6R1_FB15_Pos (15U)
<> 147:30b64687e01f 4477 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4478 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4479 #define CAN_F6R1_FB16_Pos (16U)
<> 147:30b64687e01f 4480 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4481 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4482 #define CAN_F6R1_FB17_Pos (17U)
<> 147:30b64687e01f 4483 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4484 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4485 #define CAN_F6R1_FB18_Pos (18U)
<> 147:30b64687e01f 4486 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4487 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4488 #define CAN_F6R1_FB19_Pos (19U)
<> 147:30b64687e01f 4489 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4490 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4491 #define CAN_F6R1_FB20_Pos (20U)
<> 147:30b64687e01f 4492 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4493 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4494 #define CAN_F6R1_FB21_Pos (21U)
<> 147:30b64687e01f 4495 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4496 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4497 #define CAN_F6R1_FB22_Pos (22U)
<> 147:30b64687e01f 4498 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4499 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4500 #define CAN_F6R1_FB23_Pos (23U)
<> 147:30b64687e01f 4501 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4502 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4503 #define CAN_F6R1_FB24_Pos (24U)
<> 147:30b64687e01f 4504 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4505 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4506 #define CAN_F6R1_FB25_Pos (25U)
<> 147:30b64687e01f 4507 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4508 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4509 #define CAN_F6R1_FB26_Pos (26U)
<> 147:30b64687e01f 4510 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4511 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4512 #define CAN_F6R1_FB27_Pos (27U)
<> 147:30b64687e01f 4513 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4514 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4515 #define CAN_F6R1_FB28_Pos (28U)
<> 147:30b64687e01f 4516 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4517 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4518 #define CAN_F6R1_FB29_Pos (29U)
<> 147:30b64687e01f 4519 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4520 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4521 #define CAN_F6R1_FB30_Pos (30U)
<> 147:30b64687e01f 4522 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4523 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4524 #define CAN_F6R1_FB31_Pos (31U)
<> 147:30b64687e01f 4525 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4526 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4527
<> 147:30b64687e01f 4528 /******************* Bit definition for CAN_F7R1 register *******************/
<> 147:30b64687e01f 4529 #define CAN_F7R1_FB0_Pos (0U)
<> 147:30b64687e01f 4530 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4531 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4532 #define CAN_F7R1_FB1_Pos (1U)
<> 147:30b64687e01f 4533 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4534 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4535 #define CAN_F7R1_FB2_Pos (2U)
<> 147:30b64687e01f 4536 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4537 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4538 #define CAN_F7R1_FB3_Pos (3U)
<> 147:30b64687e01f 4539 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4540 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4541 #define CAN_F7R1_FB4_Pos (4U)
<> 147:30b64687e01f 4542 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4543 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4544 #define CAN_F7R1_FB5_Pos (5U)
<> 147:30b64687e01f 4545 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4546 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4547 #define CAN_F7R1_FB6_Pos (6U)
<> 147:30b64687e01f 4548 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4549 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4550 #define CAN_F7R1_FB7_Pos (7U)
<> 147:30b64687e01f 4551 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4552 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4553 #define CAN_F7R1_FB8_Pos (8U)
<> 147:30b64687e01f 4554 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4555 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4556 #define CAN_F7R1_FB9_Pos (9U)
<> 147:30b64687e01f 4557 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4558 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4559 #define CAN_F7R1_FB10_Pos (10U)
<> 147:30b64687e01f 4560 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4561 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4562 #define CAN_F7R1_FB11_Pos (11U)
<> 147:30b64687e01f 4563 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4564 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4565 #define CAN_F7R1_FB12_Pos (12U)
<> 147:30b64687e01f 4566 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4567 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4568 #define CAN_F7R1_FB13_Pos (13U)
<> 147:30b64687e01f 4569 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4570 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4571 #define CAN_F7R1_FB14_Pos (14U)
<> 147:30b64687e01f 4572 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4573 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4574 #define CAN_F7R1_FB15_Pos (15U)
<> 147:30b64687e01f 4575 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4576 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4577 #define CAN_F7R1_FB16_Pos (16U)
<> 147:30b64687e01f 4578 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4579 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4580 #define CAN_F7R1_FB17_Pos (17U)
<> 147:30b64687e01f 4581 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4582 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4583 #define CAN_F7R1_FB18_Pos (18U)
<> 147:30b64687e01f 4584 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4585 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4586 #define CAN_F7R1_FB19_Pos (19U)
<> 147:30b64687e01f 4587 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4588 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4589 #define CAN_F7R1_FB20_Pos (20U)
<> 147:30b64687e01f 4590 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4591 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4592 #define CAN_F7R1_FB21_Pos (21U)
<> 147:30b64687e01f 4593 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4594 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4595 #define CAN_F7R1_FB22_Pos (22U)
<> 147:30b64687e01f 4596 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4597 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4598 #define CAN_F7R1_FB23_Pos (23U)
<> 147:30b64687e01f 4599 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4600 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4601 #define CAN_F7R1_FB24_Pos (24U)
<> 147:30b64687e01f 4602 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4603 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4604 #define CAN_F7R1_FB25_Pos (25U)
<> 147:30b64687e01f 4605 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4606 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4607 #define CAN_F7R1_FB26_Pos (26U)
<> 147:30b64687e01f 4608 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4609 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4610 #define CAN_F7R1_FB27_Pos (27U)
<> 147:30b64687e01f 4611 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4612 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4613 #define CAN_F7R1_FB28_Pos (28U)
<> 147:30b64687e01f 4614 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4615 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4616 #define CAN_F7R1_FB29_Pos (29U)
<> 147:30b64687e01f 4617 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4618 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4619 #define CAN_F7R1_FB30_Pos (30U)
<> 147:30b64687e01f 4620 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4621 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4622 #define CAN_F7R1_FB31_Pos (31U)
<> 147:30b64687e01f 4623 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4624 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4625
<> 147:30b64687e01f 4626 /******************* Bit definition for CAN_F8R1 register *******************/
<> 147:30b64687e01f 4627 #define CAN_F8R1_FB0_Pos (0U)
<> 147:30b64687e01f 4628 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4629 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4630 #define CAN_F8R1_FB1_Pos (1U)
<> 147:30b64687e01f 4631 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4632 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4633 #define CAN_F8R1_FB2_Pos (2U)
<> 147:30b64687e01f 4634 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4635 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4636 #define CAN_F8R1_FB3_Pos (3U)
<> 147:30b64687e01f 4637 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4638 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4639 #define CAN_F8R1_FB4_Pos (4U)
<> 147:30b64687e01f 4640 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4641 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4642 #define CAN_F8R1_FB5_Pos (5U)
<> 147:30b64687e01f 4643 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4644 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4645 #define CAN_F8R1_FB6_Pos (6U)
<> 147:30b64687e01f 4646 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4647 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4648 #define CAN_F8R1_FB7_Pos (7U)
<> 147:30b64687e01f 4649 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4650 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4651 #define CAN_F8R1_FB8_Pos (8U)
<> 147:30b64687e01f 4652 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4653 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4654 #define CAN_F8R1_FB9_Pos (9U)
<> 147:30b64687e01f 4655 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4656 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4657 #define CAN_F8R1_FB10_Pos (10U)
<> 147:30b64687e01f 4658 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4659 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4660 #define CAN_F8R1_FB11_Pos (11U)
<> 147:30b64687e01f 4661 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4662 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4663 #define CAN_F8R1_FB12_Pos (12U)
<> 147:30b64687e01f 4664 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4665 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4666 #define CAN_F8R1_FB13_Pos (13U)
<> 147:30b64687e01f 4667 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4668 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4669 #define CAN_F8R1_FB14_Pos (14U)
<> 147:30b64687e01f 4670 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4671 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4672 #define CAN_F8R1_FB15_Pos (15U)
<> 147:30b64687e01f 4673 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4674 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4675 #define CAN_F8R1_FB16_Pos (16U)
<> 147:30b64687e01f 4676 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4677 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4678 #define CAN_F8R1_FB17_Pos (17U)
<> 147:30b64687e01f 4679 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4680 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4681 #define CAN_F8R1_FB18_Pos (18U)
<> 147:30b64687e01f 4682 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4683 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4684 #define CAN_F8R1_FB19_Pos (19U)
<> 147:30b64687e01f 4685 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4686 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4687 #define CAN_F8R1_FB20_Pos (20U)
<> 147:30b64687e01f 4688 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4689 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4690 #define CAN_F8R1_FB21_Pos (21U)
<> 147:30b64687e01f 4691 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4692 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4693 #define CAN_F8R1_FB22_Pos (22U)
<> 147:30b64687e01f 4694 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4695 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4696 #define CAN_F8R1_FB23_Pos (23U)
<> 147:30b64687e01f 4697 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4698 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4699 #define CAN_F8R1_FB24_Pos (24U)
<> 147:30b64687e01f 4700 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4701 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4702 #define CAN_F8R1_FB25_Pos (25U)
<> 147:30b64687e01f 4703 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4704 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4705 #define CAN_F8R1_FB26_Pos (26U)
<> 147:30b64687e01f 4706 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4707 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4708 #define CAN_F8R1_FB27_Pos (27U)
<> 147:30b64687e01f 4709 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4710 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4711 #define CAN_F8R1_FB28_Pos (28U)
<> 147:30b64687e01f 4712 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4713 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4714 #define CAN_F8R1_FB29_Pos (29U)
<> 147:30b64687e01f 4715 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4716 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4717 #define CAN_F8R1_FB30_Pos (30U)
<> 147:30b64687e01f 4718 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4719 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4720 #define CAN_F8R1_FB31_Pos (31U)
<> 147:30b64687e01f 4721 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4722 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4723
<> 147:30b64687e01f 4724 /******************* Bit definition for CAN_F9R1 register *******************/
<> 147:30b64687e01f 4725 #define CAN_F9R1_FB0_Pos (0U)
<> 147:30b64687e01f 4726 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4727 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4728 #define CAN_F9R1_FB1_Pos (1U)
<> 147:30b64687e01f 4729 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4730 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4731 #define CAN_F9R1_FB2_Pos (2U)
<> 147:30b64687e01f 4732 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4733 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4734 #define CAN_F9R1_FB3_Pos (3U)
<> 147:30b64687e01f 4735 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4736 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4737 #define CAN_F9R1_FB4_Pos (4U)
<> 147:30b64687e01f 4738 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4739 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4740 #define CAN_F9R1_FB5_Pos (5U)
<> 147:30b64687e01f 4741 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4742 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4743 #define CAN_F9R1_FB6_Pos (6U)
<> 147:30b64687e01f 4744 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4745 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4746 #define CAN_F9R1_FB7_Pos (7U)
<> 147:30b64687e01f 4747 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4748 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4749 #define CAN_F9R1_FB8_Pos (8U)
<> 147:30b64687e01f 4750 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4751 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4752 #define CAN_F9R1_FB9_Pos (9U)
<> 147:30b64687e01f 4753 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4754 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4755 #define CAN_F9R1_FB10_Pos (10U)
<> 147:30b64687e01f 4756 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4757 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4758 #define CAN_F9R1_FB11_Pos (11U)
<> 147:30b64687e01f 4759 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4760 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4761 #define CAN_F9R1_FB12_Pos (12U)
<> 147:30b64687e01f 4762 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4763 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4764 #define CAN_F9R1_FB13_Pos (13U)
<> 147:30b64687e01f 4765 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4766 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4767 #define CAN_F9R1_FB14_Pos (14U)
<> 147:30b64687e01f 4768 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4769 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4770 #define CAN_F9R1_FB15_Pos (15U)
<> 147:30b64687e01f 4771 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4772 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4773 #define CAN_F9R1_FB16_Pos (16U)
<> 147:30b64687e01f 4774 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4775 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4776 #define CAN_F9R1_FB17_Pos (17U)
<> 147:30b64687e01f 4777 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4778 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4779 #define CAN_F9R1_FB18_Pos (18U)
<> 147:30b64687e01f 4780 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4781 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4782 #define CAN_F9R1_FB19_Pos (19U)
<> 147:30b64687e01f 4783 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4784 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4785 #define CAN_F9R1_FB20_Pos (20U)
<> 147:30b64687e01f 4786 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4787 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4788 #define CAN_F9R1_FB21_Pos (21U)
<> 147:30b64687e01f 4789 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4790 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4791 #define CAN_F9R1_FB22_Pos (22U)
<> 147:30b64687e01f 4792 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4793 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4794 #define CAN_F9R1_FB23_Pos (23U)
<> 147:30b64687e01f 4795 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4796 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4797 #define CAN_F9R1_FB24_Pos (24U)
<> 147:30b64687e01f 4798 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4799 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4800 #define CAN_F9R1_FB25_Pos (25U)
<> 147:30b64687e01f 4801 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4802 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4803 #define CAN_F9R1_FB26_Pos (26U)
<> 147:30b64687e01f 4804 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4805 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4806 #define CAN_F9R1_FB27_Pos (27U)
<> 147:30b64687e01f 4807 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4808 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4809 #define CAN_F9R1_FB28_Pos (28U)
<> 147:30b64687e01f 4810 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4811 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4812 #define CAN_F9R1_FB29_Pos (29U)
<> 147:30b64687e01f 4813 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4814 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4815 #define CAN_F9R1_FB30_Pos (30U)
<> 147:30b64687e01f 4816 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4817 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4818 #define CAN_F9R1_FB31_Pos (31U)
<> 147:30b64687e01f 4819 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4820 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4821
<> 147:30b64687e01f 4822 /******************* Bit definition for CAN_F10R1 register ******************/
<> 147:30b64687e01f 4823 #define CAN_F10R1_FB0_Pos (0U)
<> 147:30b64687e01f 4824 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4825 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4826 #define CAN_F10R1_FB1_Pos (1U)
<> 147:30b64687e01f 4827 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4828 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4829 #define CAN_F10R1_FB2_Pos (2U)
<> 147:30b64687e01f 4830 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4831 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4832 #define CAN_F10R1_FB3_Pos (3U)
<> 147:30b64687e01f 4833 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4834 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4835 #define CAN_F10R1_FB4_Pos (4U)
<> 147:30b64687e01f 4836 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4837 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4838 #define CAN_F10R1_FB5_Pos (5U)
<> 147:30b64687e01f 4839 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4840 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4841 #define CAN_F10R1_FB6_Pos (6U)
<> 147:30b64687e01f 4842 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4843 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4844 #define CAN_F10R1_FB7_Pos (7U)
<> 147:30b64687e01f 4845 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4846 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4847 #define CAN_F10R1_FB8_Pos (8U)
<> 147:30b64687e01f 4848 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4849 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4850 #define CAN_F10R1_FB9_Pos (9U)
<> 147:30b64687e01f 4851 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4852 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4853 #define CAN_F10R1_FB10_Pos (10U)
<> 147:30b64687e01f 4854 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4855 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4856 #define CAN_F10R1_FB11_Pos (11U)
<> 147:30b64687e01f 4857 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4858 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4859 #define CAN_F10R1_FB12_Pos (12U)
<> 147:30b64687e01f 4860 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4861 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4862 #define CAN_F10R1_FB13_Pos (13U)
<> 147:30b64687e01f 4863 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4864 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4865 #define CAN_F10R1_FB14_Pos (14U)
<> 147:30b64687e01f 4866 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4867 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4868 #define CAN_F10R1_FB15_Pos (15U)
<> 147:30b64687e01f 4869 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4870 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4871 #define CAN_F10R1_FB16_Pos (16U)
<> 147:30b64687e01f 4872 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4873 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4874 #define CAN_F10R1_FB17_Pos (17U)
<> 147:30b64687e01f 4875 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4876 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4877 #define CAN_F10R1_FB18_Pos (18U)
<> 147:30b64687e01f 4878 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4879 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4880 #define CAN_F10R1_FB19_Pos (19U)
<> 147:30b64687e01f 4881 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4882 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4883 #define CAN_F10R1_FB20_Pos (20U)
<> 147:30b64687e01f 4884 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4885 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4886 #define CAN_F10R1_FB21_Pos (21U)
<> 147:30b64687e01f 4887 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4888 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4889 #define CAN_F10R1_FB22_Pos (22U)
<> 147:30b64687e01f 4890 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4891 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4892 #define CAN_F10R1_FB23_Pos (23U)
<> 147:30b64687e01f 4893 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4894 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4895 #define CAN_F10R1_FB24_Pos (24U)
<> 147:30b64687e01f 4896 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4897 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4898 #define CAN_F10R1_FB25_Pos (25U)
<> 147:30b64687e01f 4899 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4900 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4901 #define CAN_F10R1_FB26_Pos (26U)
<> 147:30b64687e01f 4902 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 4903 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 4904 #define CAN_F10R1_FB27_Pos (27U)
<> 147:30b64687e01f 4905 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 4906 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 4907 #define CAN_F10R1_FB28_Pos (28U)
<> 147:30b64687e01f 4908 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 4909 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 4910 #define CAN_F10R1_FB29_Pos (29U)
<> 147:30b64687e01f 4911 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 4912 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 4913 #define CAN_F10R1_FB30_Pos (30U)
<> 147:30b64687e01f 4914 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 4915 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 4916 #define CAN_F10R1_FB31_Pos (31U)
<> 147:30b64687e01f 4917 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 4918 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 4919
<> 147:30b64687e01f 4920 /******************* Bit definition for CAN_F11R1 register ******************/
<> 147:30b64687e01f 4921 #define CAN_F11R1_FB0_Pos (0U)
<> 147:30b64687e01f 4922 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 4923 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 4924 #define CAN_F11R1_FB1_Pos (1U)
<> 147:30b64687e01f 4925 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 4926 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 4927 #define CAN_F11R1_FB2_Pos (2U)
<> 147:30b64687e01f 4928 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 4929 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 4930 #define CAN_F11R1_FB3_Pos (3U)
<> 147:30b64687e01f 4931 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 4932 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 4933 #define CAN_F11R1_FB4_Pos (4U)
<> 147:30b64687e01f 4934 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 4935 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 4936 #define CAN_F11R1_FB5_Pos (5U)
<> 147:30b64687e01f 4937 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 4938 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 4939 #define CAN_F11R1_FB6_Pos (6U)
<> 147:30b64687e01f 4940 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 4941 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 4942 #define CAN_F11R1_FB7_Pos (7U)
<> 147:30b64687e01f 4943 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 4944 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 4945 #define CAN_F11R1_FB8_Pos (8U)
<> 147:30b64687e01f 4946 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 4947 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 4948 #define CAN_F11R1_FB9_Pos (9U)
<> 147:30b64687e01f 4949 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 4950 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 4951 #define CAN_F11R1_FB10_Pos (10U)
<> 147:30b64687e01f 4952 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 4953 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 4954 #define CAN_F11R1_FB11_Pos (11U)
<> 147:30b64687e01f 4955 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 4956 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 4957 #define CAN_F11R1_FB12_Pos (12U)
<> 147:30b64687e01f 4958 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 4959 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 4960 #define CAN_F11R1_FB13_Pos (13U)
<> 147:30b64687e01f 4961 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 4962 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 4963 #define CAN_F11R1_FB14_Pos (14U)
<> 147:30b64687e01f 4964 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 4965 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 4966 #define CAN_F11R1_FB15_Pos (15U)
<> 147:30b64687e01f 4967 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 4968 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 4969 #define CAN_F11R1_FB16_Pos (16U)
<> 147:30b64687e01f 4970 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 4971 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 4972 #define CAN_F11R1_FB17_Pos (17U)
<> 147:30b64687e01f 4973 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 4974 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 4975 #define CAN_F11R1_FB18_Pos (18U)
<> 147:30b64687e01f 4976 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 4977 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 4978 #define CAN_F11R1_FB19_Pos (19U)
<> 147:30b64687e01f 4979 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 4980 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 4981 #define CAN_F11R1_FB20_Pos (20U)
<> 147:30b64687e01f 4982 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 4983 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 4984 #define CAN_F11R1_FB21_Pos (21U)
<> 147:30b64687e01f 4985 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 4986 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 4987 #define CAN_F11R1_FB22_Pos (22U)
<> 147:30b64687e01f 4988 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 4989 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 4990 #define CAN_F11R1_FB23_Pos (23U)
<> 147:30b64687e01f 4991 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 4992 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 4993 #define CAN_F11R1_FB24_Pos (24U)
<> 147:30b64687e01f 4994 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 4995 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 4996 #define CAN_F11R1_FB25_Pos (25U)
<> 147:30b64687e01f 4997 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 4998 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 4999 #define CAN_F11R1_FB26_Pos (26U)
<> 147:30b64687e01f 5000 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5001 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5002 #define CAN_F11R1_FB27_Pos (27U)
<> 147:30b64687e01f 5003 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5004 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5005 #define CAN_F11R1_FB28_Pos (28U)
<> 147:30b64687e01f 5006 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5007 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5008 #define CAN_F11R1_FB29_Pos (29U)
<> 147:30b64687e01f 5009 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5010 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5011 #define CAN_F11R1_FB30_Pos (30U)
<> 147:30b64687e01f 5012 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5013 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5014 #define CAN_F11R1_FB31_Pos (31U)
<> 147:30b64687e01f 5015 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5016 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5017
<> 147:30b64687e01f 5018 /******************* Bit definition for CAN_F12R1 register ******************/
<> 147:30b64687e01f 5019 #define CAN_F12R1_FB0_Pos (0U)
<> 147:30b64687e01f 5020 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5021 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5022 #define CAN_F12R1_FB1_Pos (1U)
<> 147:30b64687e01f 5023 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5024 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5025 #define CAN_F12R1_FB2_Pos (2U)
<> 147:30b64687e01f 5026 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5027 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5028 #define CAN_F12R1_FB3_Pos (3U)
<> 147:30b64687e01f 5029 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5030 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5031 #define CAN_F12R1_FB4_Pos (4U)
<> 147:30b64687e01f 5032 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5033 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5034 #define CAN_F12R1_FB5_Pos (5U)
<> 147:30b64687e01f 5035 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5036 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5037 #define CAN_F12R1_FB6_Pos (6U)
<> 147:30b64687e01f 5038 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5039 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5040 #define CAN_F12R1_FB7_Pos (7U)
<> 147:30b64687e01f 5041 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5042 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5043 #define CAN_F12R1_FB8_Pos (8U)
<> 147:30b64687e01f 5044 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5045 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5046 #define CAN_F12R1_FB9_Pos (9U)
<> 147:30b64687e01f 5047 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5048 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5049 #define CAN_F12R1_FB10_Pos (10U)
<> 147:30b64687e01f 5050 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5051 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5052 #define CAN_F12R1_FB11_Pos (11U)
<> 147:30b64687e01f 5053 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5054 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5055 #define CAN_F12R1_FB12_Pos (12U)
<> 147:30b64687e01f 5056 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5057 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5058 #define CAN_F12R1_FB13_Pos (13U)
<> 147:30b64687e01f 5059 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5060 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5061 #define CAN_F12R1_FB14_Pos (14U)
<> 147:30b64687e01f 5062 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5063 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5064 #define CAN_F12R1_FB15_Pos (15U)
<> 147:30b64687e01f 5065 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5066 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5067 #define CAN_F12R1_FB16_Pos (16U)
<> 147:30b64687e01f 5068 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5069 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5070 #define CAN_F12R1_FB17_Pos (17U)
<> 147:30b64687e01f 5071 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5072 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5073 #define CAN_F12R1_FB18_Pos (18U)
<> 147:30b64687e01f 5074 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5075 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5076 #define CAN_F12R1_FB19_Pos (19U)
<> 147:30b64687e01f 5077 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5078 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5079 #define CAN_F12R1_FB20_Pos (20U)
<> 147:30b64687e01f 5080 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5081 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5082 #define CAN_F12R1_FB21_Pos (21U)
<> 147:30b64687e01f 5083 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5084 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5085 #define CAN_F12R1_FB22_Pos (22U)
<> 147:30b64687e01f 5086 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5087 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5088 #define CAN_F12R1_FB23_Pos (23U)
<> 147:30b64687e01f 5089 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5090 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5091 #define CAN_F12R1_FB24_Pos (24U)
<> 147:30b64687e01f 5092 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5093 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5094 #define CAN_F12R1_FB25_Pos (25U)
<> 147:30b64687e01f 5095 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5096 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5097 #define CAN_F12R1_FB26_Pos (26U)
<> 147:30b64687e01f 5098 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5099 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5100 #define CAN_F12R1_FB27_Pos (27U)
<> 147:30b64687e01f 5101 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5102 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5103 #define CAN_F12R1_FB28_Pos (28U)
<> 147:30b64687e01f 5104 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5105 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5106 #define CAN_F12R1_FB29_Pos (29U)
<> 147:30b64687e01f 5107 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5108 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5109 #define CAN_F12R1_FB30_Pos (30U)
<> 147:30b64687e01f 5110 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5111 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5112 #define CAN_F12R1_FB31_Pos (31U)
<> 147:30b64687e01f 5113 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5114 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5115
<> 147:30b64687e01f 5116 /******************* Bit definition for CAN_F13R1 register ******************/
<> 147:30b64687e01f 5117 #define CAN_F13R1_FB0_Pos (0U)
<> 147:30b64687e01f 5118 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5119 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5120 #define CAN_F13R1_FB1_Pos (1U)
<> 147:30b64687e01f 5121 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5122 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5123 #define CAN_F13R1_FB2_Pos (2U)
<> 147:30b64687e01f 5124 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5125 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5126 #define CAN_F13R1_FB3_Pos (3U)
<> 147:30b64687e01f 5127 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5128 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5129 #define CAN_F13R1_FB4_Pos (4U)
<> 147:30b64687e01f 5130 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5131 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5132 #define CAN_F13R1_FB5_Pos (5U)
<> 147:30b64687e01f 5133 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5134 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5135 #define CAN_F13R1_FB6_Pos (6U)
<> 147:30b64687e01f 5136 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5137 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5138 #define CAN_F13R1_FB7_Pos (7U)
<> 147:30b64687e01f 5139 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5140 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5141 #define CAN_F13R1_FB8_Pos (8U)
<> 147:30b64687e01f 5142 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5143 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5144 #define CAN_F13R1_FB9_Pos (9U)
<> 147:30b64687e01f 5145 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5146 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5147 #define CAN_F13R1_FB10_Pos (10U)
<> 147:30b64687e01f 5148 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5149 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5150 #define CAN_F13R1_FB11_Pos (11U)
<> 147:30b64687e01f 5151 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5152 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5153 #define CAN_F13R1_FB12_Pos (12U)
<> 147:30b64687e01f 5154 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5155 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5156 #define CAN_F13R1_FB13_Pos (13U)
<> 147:30b64687e01f 5157 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5158 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5159 #define CAN_F13R1_FB14_Pos (14U)
<> 147:30b64687e01f 5160 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5161 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5162 #define CAN_F13R1_FB15_Pos (15U)
<> 147:30b64687e01f 5163 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5164 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5165 #define CAN_F13R1_FB16_Pos (16U)
<> 147:30b64687e01f 5166 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5167 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5168 #define CAN_F13R1_FB17_Pos (17U)
<> 147:30b64687e01f 5169 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5170 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5171 #define CAN_F13R1_FB18_Pos (18U)
<> 147:30b64687e01f 5172 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5173 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5174 #define CAN_F13R1_FB19_Pos (19U)
<> 147:30b64687e01f 5175 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5176 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5177 #define CAN_F13R1_FB20_Pos (20U)
<> 147:30b64687e01f 5178 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5179 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5180 #define CAN_F13R1_FB21_Pos (21U)
<> 147:30b64687e01f 5181 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5182 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5183 #define CAN_F13R1_FB22_Pos (22U)
<> 147:30b64687e01f 5184 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5185 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5186 #define CAN_F13R1_FB23_Pos (23U)
<> 147:30b64687e01f 5187 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5188 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5189 #define CAN_F13R1_FB24_Pos (24U)
<> 147:30b64687e01f 5190 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5191 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5192 #define CAN_F13R1_FB25_Pos (25U)
<> 147:30b64687e01f 5193 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5194 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5195 #define CAN_F13R1_FB26_Pos (26U)
<> 147:30b64687e01f 5196 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5197 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5198 #define CAN_F13R1_FB27_Pos (27U)
<> 147:30b64687e01f 5199 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5200 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5201 #define CAN_F13R1_FB28_Pos (28U)
<> 147:30b64687e01f 5202 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5203 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5204 #define CAN_F13R1_FB29_Pos (29U)
<> 147:30b64687e01f 5205 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5206 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5207 #define CAN_F13R1_FB30_Pos (30U)
<> 147:30b64687e01f 5208 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5209 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5210 #define CAN_F13R1_FB31_Pos (31U)
<> 147:30b64687e01f 5211 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5212 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5213
<> 147:30b64687e01f 5214 /******************* Bit definition for CAN_F0R2 register *******************/
<> 147:30b64687e01f 5215 #define CAN_F0R2_FB0_Pos (0U)
<> 147:30b64687e01f 5216 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5217 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5218 #define CAN_F0R2_FB1_Pos (1U)
<> 147:30b64687e01f 5219 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5220 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5221 #define CAN_F0R2_FB2_Pos (2U)
<> 147:30b64687e01f 5222 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5223 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5224 #define CAN_F0R2_FB3_Pos (3U)
<> 147:30b64687e01f 5225 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5226 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5227 #define CAN_F0R2_FB4_Pos (4U)
<> 147:30b64687e01f 5228 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5229 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5230 #define CAN_F0R2_FB5_Pos (5U)
<> 147:30b64687e01f 5231 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5232 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5233 #define CAN_F0R2_FB6_Pos (6U)
<> 147:30b64687e01f 5234 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5235 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5236 #define CAN_F0R2_FB7_Pos (7U)
<> 147:30b64687e01f 5237 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5238 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5239 #define CAN_F0R2_FB8_Pos (8U)
<> 147:30b64687e01f 5240 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5241 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5242 #define CAN_F0R2_FB9_Pos (9U)
<> 147:30b64687e01f 5243 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5244 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5245 #define CAN_F0R2_FB10_Pos (10U)
<> 147:30b64687e01f 5246 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5247 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5248 #define CAN_F0R2_FB11_Pos (11U)
<> 147:30b64687e01f 5249 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5250 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5251 #define CAN_F0R2_FB12_Pos (12U)
<> 147:30b64687e01f 5252 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5253 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5254 #define CAN_F0R2_FB13_Pos (13U)
<> 147:30b64687e01f 5255 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5256 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5257 #define CAN_F0R2_FB14_Pos (14U)
<> 147:30b64687e01f 5258 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5259 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5260 #define CAN_F0R2_FB15_Pos (15U)
<> 147:30b64687e01f 5261 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5262 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5263 #define CAN_F0R2_FB16_Pos (16U)
<> 147:30b64687e01f 5264 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5265 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5266 #define CAN_F0R2_FB17_Pos (17U)
<> 147:30b64687e01f 5267 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5268 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5269 #define CAN_F0R2_FB18_Pos (18U)
<> 147:30b64687e01f 5270 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5271 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5272 #define CAN_F0R2_FB19_Pos (19U)
<> 147:30b64687e01f 5273 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5274 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5275 #define CAN_F0R2_FB20_Pos (20U)
<> 147:30b64687e01f 5276 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5277 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5278 #define CAN_F0R2_FB21_Pos (21U)
<> 147:30b64687e01f 5279 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5280 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5281 #define CAN_F0R2_FB22_Pos (22U)
<> 147:30b64687e01f 5282 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5283 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5284 #define CAN_F0R2_FB23_Pos (23U)
<> 147:30b64687e01f 5285 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5286 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5287 #define CAN_F0R2_FB24_Pos (24U)
<> 147:30b64687e01f 5288 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5289 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5290 #define CAN_F0R2_FB25_Pos (25U)
<> 147:30b64687e01f 5291 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5292 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5293 #define CAN_F0R2_FB26_Pos (26U)
<> 147:30b64687e01f 5294 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5295 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5296 #define CAN_F0R2_FB27_Pos (27U)
<> 147:30b64687e01f 5297 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5298 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5299 #define CAN_F0R2_FB28_Pos (28U)
<> 147:30b64687e01f 5300 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5301 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5302 #define CAN_F0R2_FB29_Pos (29U)
<> 147:30b64687e01f 5303 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5304 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5305 #define CAN_F0R2_FB30_Pos (30U)
<> 147:30b64687e01f 5306 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5307 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5308 #define CAN_F0R2_FB31_Pos (31U)
<> 147:30b64687e01f 5309 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5310 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5311
<> 147:30b64687e01f 5312 /******************* Bit definition for CAN_F1R2 register *******************/
<> 147:30b64687e01f 5313 #define CAN_F1R2_FB0_Pos (0U)
<> 147:30b64687e01f 5314 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5315 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5316 #define CAN_F1R2_FB1_Pos (1U)
<> 147:30b64687e01f 5317 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5318 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5319 #define CAN_F1R2_FB2_Pos (2U)
<> 147:30b64687e01f 5320 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5321 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5322 #define CAN_F1R2_FB3_Pos (3U)
<> 147:30b64687e01f 5323 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5324 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5325 #define CAN_F1R2_FB4_Pos (4U)
<> 147:30b64687e01f 5326 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5327 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5328 #define CAN_F1R2_FB5_Pos (5U)
<> 147:30b64687e01f 5329 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5330 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5331 #define CAN_F1R2_FB6_Pos (6U)
<> 147:30b64687e01f 5332 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5333 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5334 #define CAN_F1R2_FB7_Pos (7U)
<> 147:30b64687e01f 5335 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5336 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5337 #define CAN_F1R2_FB8_Pos (8U)
<> 147:30b64687e01f 5338 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5339 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5340 #define CAN_F1R2_FB9_Pos (9U)
<> 147:30b64687e01f 5341 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5342 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5343 #define CAN_F1R2_FB10_Pos (10U)
<> 147:30b64687e01f 5344 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5345 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5346 #define CAN_F1R2_FB11_Pos (11U)
<> 147:30b64687e01f 5347 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5348 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5349 #define CAN_F1R2_FB12_Pos (12U)
<> 147:30b64687e01f 5350 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5351 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5352 #define CAN_F1R2_FB13_Pos (13U)
<> 147:30b64687e01f 5353 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5354 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5355 #define CAN_F1R2_FB14_Pos (14U)
<> 147:30b64687e01f 5356 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5357 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5358 #define CAN_F1R2_FB15_Pos (15U)
<> 147:30b64687e01f 5359 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5360 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5361 #define CAN_F1R2_FB16_Pos (16U)
<> 147:30b64687e01f 5362 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5363 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5364 #define CAN_F1R2_FB17_Pos (17U)
<> 147:30b64687e01f 5365 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5366 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5367 #define CAN_F1R2_FB18_Pos (18U)
<> 147:30b64687e01f 5368 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5369 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5370 #define CAN_F1R2_FB19_Pos (19U)
<> 147:30b64687e01f 5371 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5372 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5373 #define CAN_F1R2_FB20_Pos (20U)
<> 147:30b64687e01f 5374 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5375 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5376 #define CAN_F1R2_FB21_Pos (21U)
<> 147:30b64687e01f 5377 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5378 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5379 #define CAN_F1R2_FB22_Pos (22U)
<> 147:30b64687e01f 5380 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5381 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5382 #define CAN_F1R2_FB23_Pos (23U)
<> 147:30b64687e01f 5383 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5384 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5385 #define CAN_F1R2_FB24_Pos (24U)
<> 147:30b64687e01f 5386 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5387 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5388 #define CAN_F1R2_FB25_Pos (25U)
<> 147:30b64687e01f 5389 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5390 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5391 #define CAN_F1R2_FB26_Pos (26U)
<> 147:30b64687e01f 5392 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5393 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5394 #define CAN_F1R2_FB27_Pos (27U)
<> 147:30b64687e01f 5395 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5396 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5397 #define CAN_F1R2_FB28_Pos (28U)
<> 147:30b64687e01f 5398 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5399 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5400 #define CAN_F1R2_FB29_Pos (29U)
<> 147:30b64687e01f 5401 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5402 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5403 #define CAN_F1R2_FB30_Pos (30U)
<> 147:30b64687e01f 5404 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5405 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5406 #define CAN_F1R2_FB31_Pos (31U)
<> 147:30b64687e01f 5407 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5408 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5409
<> 147:30b64687e01f 5410 /******************* Bit definition for CAN_F2R2 register *******************/
<> 147:30b64687e01f 5411 #define CAN_F2R2_FB0_Pos (0U)
<> 147:30b64687e01f 5412 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5413 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5414 #define CAN_F2R2_FB1_Pos (1U)
<> 147:30b64687e01f 5415 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5416 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5417 #define CAN_F2R2_FB2_Pos (2U)
<> 147:30b64687e01f 5418 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5419 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5420 #define CAN_F2R2_FB3_Pos (3U)
<> 147:30b64687e01f 5421 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5422 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5423 #define CAN_F2R2_FB4_Pos (4U)
<> 147:30b64687e01f 5424 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5425 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5426 #define CAN_F2R2_FB5_Pos (5U)
<> 147:30b64687e01f 5427 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5428 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5429 #define CAN_F2R2_FB6_Pos (6U)
<> 147:30b64687e01f 5430 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5431 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5432 #define CAN_F2R2_FB7_Pos (7U)
<> 147:30b64687e01f 5433 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5434 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5435 #define CAN_F2R2_FB8_Pos (8U)
<> 147:30b64687e01f 5436 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5437 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5438 #define CAN_F2R2_FB9_Pos (9U)
<> 147:30b64687e01f 5439 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5440 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5441 #define CAN_F2R2_FB10_Pos (10U)
<> 147:30b64687e01f 5442 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5443 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5444 #define CAN_F2R2_FB11_Pos (11U)
<> 147:30b64687e01f 5445 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5446 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5447 #define CAN_F2R2_FB12_Pos (12U)
<> 147:30b64687e01f 5448 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5449 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5450 #define CAN_F2R2_FB13_Pos (13U)
<> 147:30b64687e01f 5451 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5452 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5453 #define CAN_F2R2_FB14_Pos (14U)
<> 147:30b64687e01f 5454 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5455 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5456 #define CAN_F2R2_FB15_Pos (15U)
<> 147:30b64687e01f 5457 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5458 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5459 #define CAN_F2R2_FB16_Pos (16U)
<> 147:30b64687e01f 5460 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5461 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5462 #define CAN_F2R2_FB17_Pos (17U)
<> 147:30b64687e01f 5463 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5464 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5465 #define CAN_F2R2_FB18_Pos (18U)
<> 147:30b64687e01f 5466 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5467 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5468 #define CAN_F2R2_FB19_Pos (19U)
<> 147:30b64687e01f 5469 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5470 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5471 #define CAN_F2R2_FB20_Pos (20U)
<> 147:30b64687e01f 5472 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5473 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5474 #define CAN_F2R2_FB21_Pos (21U)
<> 147:30b64687e01f 5475 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5476 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5477 #define CAN_F2R2_FB22_Pos (22U)
<> 147:30b64687e01f 5478 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5479 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5480 #define CAN_F2R2_FB23_Pos (23U)
<> 147:30b64687e01f 5481 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5482 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5483 #define CAN_F2R2_FB24_Pos (24U)
<> 147:30b64687e01f 5484 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5485 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5486 #define CAN_F2R2_FB25_Pos (25U)
<> 147:30b64687e01f 5487 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5488 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5489 #define CAN_F2R2_FB26_Pos (26U)
<> 147:30b64687e01f 5490 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5491 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5492 #define CAN_F2R2_FB27_Pos (27U)
<> 147:30b64687e01f 5493 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5494 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5495 #define CAN_F2R2_FB28_Pos (28U)
<> 147:30b64687e01f 5496 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5497 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5498 #define CAN_F2R2_FB29_Pos (29U)
<> 147:30b64687e01f 5499 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5500 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5501 #define CAN_F2R2_FB30_Pos (30U)
<> 147:30b64687e01f 5502 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5503 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5504 #define CAN_F2R2_FB31_Pos (31U)
<> 147:30b64687e01f 5505 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5506 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5507
<> 147:30b64687e01f 5508 /******************* Bit definition for CAN_F3R2 register *******************/
<> 147:30b64687e01f 5509 #define CAN_F3R2_FB0_Pos (0U)
<> 147:30b64687e01f 5510 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5511 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5512 #define CAN_F3R2_FB1_Pos (1U)
<> 147:30b64687e01f 5513 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5514 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5515 #define CAN_F3R2_FB2_Pos (2U)
<> 147:30b64687e01f 5516 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5517 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5518 #define CAN_F3R2_FB3_Pos (3U)
<> 147:30b64687e01f 5519 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5520 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5521 #define CAN_F3R2_FB4_Pos (4U)
<> 147:30b64687e01f 5522 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5523 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5524 #define CAN_F3R2_FB5_Pos (5U)
<> 147:30b64687e01f 5525 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5526 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5527 #define CAN_F3R2_FB6_Pos (6U)
<> 147:30b64687e01f 5528 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5529 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5530 #define CAN_F3R2_FB7_Pos (7U)
<> 147:30b64687e01f 5531 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5532 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5533 #define CAN_F3R2_FB8_Pos (8U)
<> 147:30b64687e01f 5534 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5535 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5536 #define CAN_F3R2_FB9_Pos (9U)
<> 147:30b64687e01f 5537 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5538 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5539 #define CAN_F3R2_FB10_Pos (10U)
<> 147:30b64687e01f 5540 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5541 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5542 #define CAN_F3R2_FB11_Pos (11U)
<> 147:30b64687e01f 5543 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5544 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5545 #define CAN_F3R2_FB12_Pos (12U)
<> 147:30b64687e01f 5546 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5547 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5548 #define CAN_F3R2_FB13_Pos (13U)
<> 147:30b64687e01f 5549 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5550 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5551 #define CAN_F3R2_FB14_Pos (14U)
<> 147:30b64687e01f 5552 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5553 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5554 #define CAN_F3R2_FB15_Pos (15U)
<> 147:30b64687e01f 5555 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5556 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5557 #define CAN_F3R2_FB16_Pos (16U)
<> 147:30b64687e01f 5558 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5559 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5560 #define CAN_F3R2_FB17_Pos (17U)
<> 147:30b64687e01f 5561 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5562 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5563 #define CAN_F3R2_FB18_Pos (18U)
<> 147:30b64687e01f 5564 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5565 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5566 #define CAN_F3R2_FB19_Pos (19U)
<> 147:30b64687e01f 5567 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5568 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5569 #define CAN_F3R2_FB20_Pos (20U)
<> 147:30b64687e01f 5570 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5571 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5572 #define CAN_F3R2_FB21_Pos (21U)
<> 147:30b64687e01f 5573 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5574 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5575 #define CAN_F3R2_FB22_Pos (22U)
<> 147:30b64687e01f 5576 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5577 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5578 #define CAN_F3R2_FB23_Pos (23U)
<> 147:30b64687e01f 5579 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5580 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5581 #define CAN_F3R2_FB24_Pos (24U)
<> 147:30b64687e01f 5582 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5583 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5584 #define CAN_F3R2_FB25_Pos (25U)
<> 147:30b64687e01f 5585 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5586 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5587 #define CAN_F3R2_FB26_Pos (26U)
<> 147:30b64687e01f 5588 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5589 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5590 #define CAN_F3R2_FB27_Pos (27U)
<> 147:30b64687e01f 5591 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5592 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5593 #define CAN_F3R2_FB28_Pos (28U)
<> 147:30b64687e01f 5594 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5595 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5596 #define CAN_F3R2_FB29_Pos (29U)
<> 147:30b64687e01f 5597 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5598 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5599 #define CAN_F3R2_FB30_Pos (30U)
<> 147:30b64687e01f 5600 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5601 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5602 #define CAN_F3R2_FB31_Pos (31U)
<> 147:30b64687e01f 5603 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5604 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5605
<> 147:30b64687e01f 5606 /******************* Bit definition for CAN_F4R2 register *******************/
<> 147:30b64687e01f 5607 #define CAN_F4R2_FB0_Pos (0U)
<> 147:30b64687e01f 5608 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5609 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5610 #define CAN_F4R2_FB1_Pos (1U)
<> 147:30b64687e01f 5611 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5612 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5613 #define CAN_F4R2_FB2_Pos (2U)
<> 147:30b64687e01f 5614 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5615 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5616 #define CAN_F4R2_FB3_Pos (3U)
<> 147:30b64687e01f 5617 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5618 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5619 #define CAN_F4R2_FB4_Pos (4U)
<> 147:30b64687e01f 5620 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5621 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5622 #define CAN_F4R2_FB5_Pos (5U)
<> 147:30b64687e01f 5623 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5624 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5625 #define CAN_F4R2_FB6_Pos (6U)
<> 147:30b64687e01f 5626 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5627 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5628 #define CAN_F4R2_FB7_Pos (7U)
<> 147:30b64687e01f 5629 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5630 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5631 #define CAN_F4R2_FB8_Pos (8U)
<> 147:30b64687e01f 5632 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5633 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5634 #define CAN_F4R2_FB9_Pos (9U)
<> 147:30b64687e01f 5635 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5636 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5637 #define CAN_F4R2_FB10_Pos (10U)
<> 147:30b64687e01f 5638 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5639 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5640 #define CAN_F4R2_FB11_Pos (11U)
<> 147:30b64687e01f 5641 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5642 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5643 #define CAN_F4R2_FB12_Pos (12U)
<> 147:30b64687e01f 5644 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5645 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5646 #define CAN_F4R2_FB13_Pos (13U)
<> 147:30b64687e01f 5647 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5648 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5649 #define CAN_F4R2_FB14_Pos (14U)
<> 147:30b64687e01f 5650 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5651 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5652 #define CAN_F4R2_FB15_Pos (15U)
<> 147:30b64687e01f 5653 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5654 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5655 #define CAN_F4R2_FB16_Pos (16U)
<> 147:30b64687e01f 5656 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5657 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5658 #define CAN_F4R2_FB17_Pos (17U)
<> 147:30b64687e01f 5659 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5660 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5661 #define CAN_F4R2_FB18_Pos (18U)
<> 147:30b64687e01f 5662 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5663 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5664 #define CAN_F4R2_FB19_Pos (19U)
<> 147:30b64687e01f 5665 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5666 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5667 #define CAN_F4R2_FB20_Pos (20U)
<> 147:30b64687e01f 5668 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5669 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5670 #define CAN_F4R2_FB21_Pos (21U)
<> 147:30b64687e01f 5671 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5672 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5673 #define CAN_F4R2_FB22_Pos (22U)
<> 147:30b64687e01f 5674 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5675 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5676 #define CAN_F4R2_FB23_Pos (23U)
<> 147:30b64687e01f 5677 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5678 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5679 #define CAN_F4R2_FB24_Pos (24U)
<> 147:30b64687e01f 5680 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5681 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5682 #define CAN_F4R2_FB25_Pos (25U)
<> 147:30b64687e01f 5683 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5684 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5685 #define CAN_F4R2_FB26_Pos (26U)
<> 147:30b64687e01f 5686 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5687 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5688 #define CAN_F4R2_FB27_Pos (27U)
<> 147:30b64687e01f 5689 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5690 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5691 #define CAN_F4R2_FB28_Pos (28U)
<> 147:30b64687e01f 5692 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5693 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5694 #define CAN_F4R2_FB29_Pos (29U)
<> 147:30b64687e01f 5695 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5696 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5697 #define CAN_F4R2_FB30_Pos (30U)
<> 147:30b64687e01f 5698 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5699 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5700 #define CAN_F4R2_FB31_Pos (31U)
<> 147:30b64687e01f 5701 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5702 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5703
<> 147:30b64687e01f 5704 /******************* Bit definition for CAN_F5R2 register *******************/
<> 147:30b64687e01f 5705 #define CAN_F5R2_FB0_Pos (0U)
<> 147:30b64687e01f 5706 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5707 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5708 #define CAN_F5R2_FB1_Pos (1U)
<> 147:30b64687e01f 5709 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5710 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5711 #define CAN_F5R2_FB2_Pos (2U)
<> 147:30b64687e01f 5712 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5713 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5714 #define CAN_F5R2_FB3_Pos (3U)
<> 147:30b64687e01f 5715 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5716 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5717 #define CAN_F5R2_FB4_Pos (4U)
<> 147:30b64687e01f 5718 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5719 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5720 #define CAN_F5R2_FB5_Pos (5U)
<> 147:30b64687e01f 5721 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5722 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5723 #define CAN_F5R2_FB6_Pos (6U)
<> 147:30b64687e01f 5724 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5725 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5726 #define CAN_F5R2_FB7_Pos (7U)
<> 147:30b64687e01f 5727 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5728 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5729 #define CAN_F5R2_FB8_Pos (8U)
<> 147:30b64687e01f 5730 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5731 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5732 #define CAN_F5R2_FB9_Pos (9U)
<> 147:30b64687e01f 5733 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5734 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5735 #define CAN_F5R2_FB10_Pos (10U)
<> 147:30b64687e01f 5736 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5737 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5738 #define CAN_F5R2_FB11_Pos (11U)
<> 147:30b64687e01f 5739 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5740 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5741 #define CAN_F5R2_FB12_Pos (12U)
<> 147:30b64687e01f 5742 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5743 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5744 #define CAN_F5R2_FB13_Pos (13U)
<> 147:30b64687e01f 5745 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5746 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5747 #define CAN_F5R2_FB14_Pos (14U)
<> 147:30b64687e01f 5748 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5749 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5750 #define CAN_F5R2_FB15_Pos (15U)
<> 147:30b64687e01f 5751 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5752 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5753 #define CAN_F5R2_FB16_Pos (16U)
<> 147:30b64687e01f 5754 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5755 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5756 #define CAN_F5R2_FB17_Pos (17U)
<> 147:30b64687e01f 5757 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5758 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5759 #define CAN_F5R2_FB18_Pos (18U)
<> 147:30b64687e01f 5760 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5761 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5762 #define CAN_F5R2_FB19_Pos (19U)
<> 147:30b64687e01f 5763 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5764 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5765 #define CAN_F5R2_FB20_Pos (20U)
<> 147:30b64687e01f 5766 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5767 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5768 #define CAN_F5R2_FB21_Pos (21U)
<> 147:30b64687e01f 5769 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5770 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5771 #define CAN_F5R2_FB22_Pos (22U)
<> 147:30b64687e01f 5772 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5773 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5774 #define CAN_F5R2_FB23_Pos (23U)
<> 147:30b64687e01f 5775 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5776 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5777 #define CAN_F5R2_FB24_Pos (24U)
<> 147:30b64687e01f 5778 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5779 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5780 #define CAN_F5R2_FB25_Pos (25U)
<> 147:30b64687e01f 5781 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5782 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5783 #define CAN_F5R2_FB26_Pos (26U)
<> 147:30b64687e01f 5784 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5785 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5786 #define CAN_F5R2_FB27_Pos (27U)
<> 147:30b64687e01f 5787 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5788 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5789 #define CAN_F5R2_FB28_Pos (28U)
<> 147:30b64687e01f 5790 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5791 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5792 #define CAN_F5R2_FB29_Pos (29U)
<> 147:30b64687e01f 5793 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5794 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5795 #define CAN_F5R2_FB30_Pos (30U)
<> 147:30b64687e01f 5796 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5797 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5798 #define CAN_F5R2_FB31_Pos (31U)
<> 147:30b64687e01f 5799 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5800 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5801
<> 147:30b64687e01f 5802 /******************* Bit definition for CAN_F6R2 register *******************/
<> 147:30b64687e01f 5803 #define CAN_F6R2_FB0_Pos (0U)
<> 147:30b64687e01f 5804 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5805 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5806 #define CAN_F6R2_FB1_Pos (1U)
<> 147:30b64687e01f 5807 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5808 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5809 #define CAN_F6R2_FB2_Pos (2U)
<> 147:30b64687e01f 5810 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5811 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5812 #define CAN_F6R2_FB3_Pos (3U)
<> 147:30b64687e01f 5813 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5814 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5815 #define CAN_F6R2_FB4_Pos (4U)
<> 147:30b64687e01f 5816 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5817 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5818 #define CAN_F6R2_FB5_Pos (5U)
<> 147:30b64687e01f 5819 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5820 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5821 #define CAN_F6R2_FB6_Pos (6U)
<> 147:30b64687e01f 5822 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5823 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5824 #define CAN_F6R2_FB7_Pos (7U)
<> 147:30b64687e01f 5825 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5826 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5827 #define CAN_F6R2_FB8_Pos (8U)
<> 147:30b64687e01f 5828 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5829 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5830 #define CAN_F6R2_FB9_Pos (9U)
<> 147:30b64687e01f 5831 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5832 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5833 #define CAN_F6R2_FB10_Pos (10U)
<> 147:30b64687e01f 5834 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5835 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5836 #define CAN_F6R2_FB11_Pos (11U)
<> 147:30b64687e01f 5837 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5838 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5839 #define CAN_F6R2_FB12_Pos (12U)
<> 147:30b64687e01f 5840 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5841 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5842 #define CAN_F6R2_FB13_Pos (13U)
<> 147:30b64687e01f 5843 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5844 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5845 #define CAN_F6R2_FB14_Pos (14U)
<> 147:30b64687e01f 5846 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5847 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5848 #define CAN_F6R2_FB15_Pos (15U)
<> 147:30b64687e01f 5849 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5850 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5851 #define CAN_F6R2_FB16_Pos (16U)
<> 147:30b64687e01f 5852 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5853 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5854 #define CAN_F6R2_FB17_Pos (17U)
<> 147:30b64687e01f 5855 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5856 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5857 #define CAN_F6R2_FB18_Pos (18U)
<> 147:30b64687e01f 5858 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5859 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5860 #define CAN_F6R2_FB19_Pos (19U)
<> 147:30b64687e01f 5861 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5862 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5863 #define CAN_F6R2_FB20_Pos (20U)
<> 147:30b64687e01f 5864 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5865 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5866 #define CAN_F6R2_FB21_Pos (21U)
<> 147:30b64687e01f 5867 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5868 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5869 #define CAN_F6R2_FB22_Pos (22U)
<> 147:30b64687e01f 5870 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5871 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5872 #define CAN_F6R2_FB23_Pos (23U)
<> 147:30b64687e01f 5873 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5874 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5875 #define CAN_F6R2_FB24_Pos (24U)
<> 147:30b64687e01f 5876 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5877 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5878 #define CAN_F6R2_FB25_Pos (25U)
<> 147:30b64687e01f 5879 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5880 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5881 #define CAN_F6R2_FB26_Pos (26U)
<> 147:30b64687e01f 5882 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5883 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5884 #define CAN_F6R2_FB27_Pos (27U)
<> 147:30b64687e01f 5885 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5886 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5887 #define CAN_F6R2_FB28_Pos (28U)
<> 147:30b64687e01f 5888 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5889 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5890 #define CAN_F6R2_FB29_Pos (29U)
<> 147:30b64687e01f 5891 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5892 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5893 #define CAN_F6R2_FB30_Pos (30U)
<> 147:30b64687e01f 5894 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5895 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5896 #define CAN_F6R2_FB31_Pos (31U)
<> 147:30b64687e01f 5897 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5898 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5899
<> 147:30b64687e01f 5900 /******************* Bit definition for CAN_F7R2 register *******************/
<> 147:30b64687e01f 5901 #define CAN_F7R2_FB0_Pos (0U)
<> 147:30b64687e01f 5902 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 5903 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 5904 #define CAN_F7R2_FB1_Pos (1U)
<> 147:30b64687e01f 5905 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 5906 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 5907 #define CAN_F7R2_FB2_Pos (2U)
<> 147:30b64687e01f 5908 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 5909 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 5910 #define CAN_F7R2_FB3_Pos (3U)
<> 147:30b64687e01f 5911 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 5912 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 5913 #define CAN_F7R2_FB4_Pos (4U)
<> 147:30b64687e01f 5914 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 5915 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 5916 #define CAN_F7R2_FB5_Pos (5U)
<> 147:30b64687e01f 5917 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 5918 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 5919 #define CAN_F7R2_FB6_Pos (6U)
<> 147:30b64687e01f 5920 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 5921 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 5922 #define CAN_F7R2_FB7_Pos (7U)
<> 147:30b64687e01f 5923 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 5924 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 5925 #define CAN_F7R2_FB8_Pos (8U)
<> 147:30b64687e01f 5926 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 5927 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 5928 #define CAN_F7R2_FB9_Pos (9U)
<> 147:30b64687e01f 5929 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 5930 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 5931 #define CAN_F7R2_FB10_Pos (10U)
<> 147:30b64687e01f 5932 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 5933 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 5934 #define CAN_F7R2_FB11_Pos (11U)
<> 147:30b64687e01f 5935 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 5936 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 5937 #define CAN_F7R2_FB12_Pos (12U)
<> 147:30b64687e01f 5938 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 5939 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 5940 #define CAN_F7R2_FB13_Pos (13U)
<> 147:30b64687e01f 5941 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 5942 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 5943 #define CAN_F7R2_FB14_Pos (14U)
<> 147:30b64687e01f 5944 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 5945 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 5946 #define CAN_F7R2_FB15_Pos (15U)
<> 147:30b64687e01f 5947 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 5948 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 5949 #define CAN_F7R2_FB16_Pos (16U)
<> 147:30b64687e01f 5950 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 5951 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 5952 #define CAN_F7R2_FB17_Pos (17U)
<> 147:30b64687e01f 5953 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 5954 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 5955 #define CAN_F7R2_FB18_Pos (18U)
<> 147:30b64687e01f 5956 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 5957 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 5958 #define CAN_F7R2_FB19_Pos (19U)
<> 147:30b64687e01f 5959 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 5960 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 5961 #define CAN_F7R2_FB20_Pos (20U)
<> 147:30b64687e01f 5962 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 5963 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 5964 #define CAN_F7R2_FB21_Pos (21U)
<> 147:30b64687e01f 5965 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 5966 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 5967 #define CAN_F7R2_FB22_Pos (22U)
<> 147:30b64687e01f 5968 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 5969 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 5970 #define CAN_F7R2_FB23_Pos (23U)
<> 147:30b64687e01f 5971 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 5972 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 5973 #define CAN_F7R2_FB24_Pos (24U)
<> 147:30b64687e01f 5974 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 5975 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 5976 #define CAN_F7R2_FB25_Pos (25U)
<> 147:30b64687e01f 5977 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 5978 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 5979 #define CAN_F7R2_FB26_Pos (26U)
<> 147:30b64687e01f 5980 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 5981 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 5982 #define CAN_F7R2_FB27_Pos (27U)
<> 147:30b64687e01f 5983 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 5984 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 5985 #define CAN_F7R2_FB28_Pos (28U)
<> 147:30b64687e01f 5986 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 5987 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 5988 #define CAN_F7R2_FB29_Pos (29U)
<> 147:30b64687e01f 5989 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 5990 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 5991 #define CAN_F7R2_FB30_Pos (30U)
<> 147:30b64687e01f 5992 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 5993 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 5994 #define CAN_F7R2_FB31_Pos (31U)
<> 147:30b64687e01f 5995 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 5996 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 5997
<> 147:30b64687e01f 5998 /******************* Bit definition for CAN_F8R2 register *******************/
<> 147:30b64687e01f 5999 #define CAN_F8R2_FB0_Pos (0U)
<> 147:30b64687e01f 6000 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6001 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 6002 #define CAN_F8R2_FB1_Pos (1U)
<> 147:30b64687e01f 6003 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6004 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 6005 #define CAN_F8R2_FB2_Pos (2U)
<> 147:30b64687e01f 6006 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6007 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 6008 #define CAN_F8R2_FB3_Pos (3U)
<> 147:30b64687e01f 6009 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6010 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 6011 #define CAN_F8R2_FB4_Pos (4U)
<> 147:30b64687e01f 6012 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6013 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 6014 #define CAN_F8R2_FB5_Pos (5U)
<> 147:30b64687e01f 6015 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6016 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 6017 #define CAN_F8R2_FB6_Pos (6U)
<> 147:30b64687e01f 6018 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6019 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 6020 #define CAN_F8R2_FB7_Pos (7U)
<> 147:30b64687e01f 6021 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6022 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 6023 #define CAN_F8R2_FB8_Pos (8U)
<> 147:30b64687e01f 6024 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6025 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 6026 #define CAN_F8R2_FB9_Pos (9U)
<> 147:30b64687e01f 6027 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6028 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 6029 #define CAN_F8R2_FB10_Pos (10U)
<> 147:30b64687e01f 6030 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6031 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 6032 #define CAN_F8R2_FB11_Pos (11U)
<> 147:30b64687e01f 6033 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6034 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 6035 #define CAN_F8R2_FB12_Pos (12U)
<> 147:30b64687e01f 6036 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6037 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 6038 #define CAN_F8R2_FB13_Pos (13U)
<> 147:30b64687e01f 6039 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6040 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 6041 #define CAN_F8R2_FB14_Pos (14U)
<> 147:30b64687e01f 6042 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 6043 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 6044 #define CAN_F8R2_FB15_Pos (15U)
<> 147:30b64687e01f 6045 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 6046 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 6047 #define CAN_F8R2_FB16_Pos (16U)
<> 147:30b64687e01f 6048 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6049 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 6050 #define CAN_F8R2_FB17_Pos (17U)
<> 147:30b64687e01f 6051 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6052 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 6053 #define CAN_F8R2_FB18_Pos (18U)
<> 147:30b64687e01f 6054 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6055 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 6056 #define CAN_F8R2_FB19_Pos (19U)
<> 147:30b64687e01f 6057 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6058 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 6059 #define CAN_F8R2_FB20_Pos (20U)
<> 147:30b64687e01f 6060 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6061 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 6062 #define CAN_F8R2_FB21_Pos (21U)
<> 147:30b64687e01f 6063 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6064 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 6065 #define CAN_F8R2_FB22_Pos (22U)
<> 147:30b64687e01f 6066 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6067 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 6068 #define CAN_F8R2_FB23_Pos (23U)
<> 147:30b64687e01f 6069 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6070 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 6071 #define CAN_F8R2_FB24_Pos (24U)
<> 147:30b64687e01f 6072 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6073 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 6074 #define CAN_F8R2_FB25_Pos (25U)
<> 147:30b64687e01f 6075 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6076 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 6077 #define CAN_F8R2_FB26_Pos (26U)
<> 147:30b64687e01f 6078 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6079 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 6080 #define CAN_F8R2_FB27_Pos (27U)
<> 147:30b64687e01f 6081 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6082 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 6083 #define CAN_F8R2_FB28_Pos (28U)
<> 147:30b64687e01f 6084 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 6085 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 6086 #define CAN_F8R2_FB29_Pos (29U)
<> 147:30b64687e01f 6087 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6088 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 6089 #define CAN_F8R2_FB30_Pos (30U)
<> 147:30b64687e01f 6090 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 6091 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 6092 #define CAN_F8R2_FB31_Pos (31U)
<> 147:30b64687e01f 6093 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 6094 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 6095
<> 147:30b64687e01f 6096 /******************* Bit definition for CAN_F9R2 register *******************/
<> 147:30b64687e01f 6097 #define CAN_F9R2_FB0_Pos (0U)
<> 147:30b64687e01f 6098 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6099 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 6100 #define CAN_F9R2_FB1_Pos (1U)
<> 147:30b64687e01f 6101 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6102 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 6103 #define CAN_F9R2_FB2_Pos (2U)
<> 147:30b64687e01f 6104 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6105 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 6106 #define CAN_F9R2_FB3_Pos (3U)
<> 147:30b64687e01f 6107 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6108 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 6109 #define CAN_F9R2_FB4_Pos (4U)
<> 147:30b64687e01f 6110 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6111 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 6112 #define CAN_F9R2_FB5_Pos (5U)
<> 147:30b64687e01f 6113 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6114 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 6115 #define CAN_F9R2_FB6_Pos (6U)
<> 147:30b64687e01f 6116 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6117 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 6118 #define CAN_F9R2_FB7_Pos (7U)
<> 147:30b64687e01f 6119 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6120 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 6121 #define CAN_F9R2_FB8_Pos (8U)
<> 147:30b64687e01f 6122 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6123 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 6124 #define CAN_F9R2_FB9_Pos (9U)
<> 147:30b64687e01f 6125 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6126 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 6127 #define CAN_F9R2_FB10_Pos (10U)
<> 147:30b64687e01f 6128 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6129 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 6130 #define CAN_F9R2_FB11_Pos (11U)
<> 147:30b64687e01f 6131 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6132 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 6133 #define CAN_F9R2_FB12_Pos (12U)
<> 147:30b64687e01f 6134 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6135 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 6136 #define CAN_F9R2_FB13_Pos (13U)
<> 147:30b64687e01f 6137 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6138 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 6139 #define CAN_F9R2_FB14_Pos (14U)
<> 147:30b64687e01f 6140 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 6141 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 6142 #define CAN_F9R2_FB15_Pos (15U)
<> 147:30b64687e01f 6143 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 6144 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 6145 #define CAN_F9R2_FB16_Pos (16U)
<> 147:30b64687e01f 6146 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6147 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 6148 #define CAN_F9R2_FB17_Pos (17U)
<> 147:30b64687e01f 6149 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6150 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 6151 #define CAN_F9R2_FB18_Pos (18U)
<> 147:30b64687e01f 6152 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6153 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 6154 #define CAN_F9R2_FB19_Pos (19U)
<> 147:30b64687e01f 6155 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6156 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 6157 #define CAN_F9R2_FB20_Pos (20U)
<> 147:30b64687e01f 6158 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6159 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 6160 #define CAN_F9R2_FB21_Pos (21U)
<> 147:30b64687e01f 6161 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6162 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 6163 #define CAN_F9R2_FB22_Pos (22U)
<> 147:30b64687e01f 6164 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6165 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 6166 #define CAN_F9R2_FB23_Pos (23U)
<> 147:30b64687e01f 6167 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6168 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 6169 #define CAN_F9R2_FB24_Pos (24U)
<> 147:30b64687e01f 6170 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6171 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 6172 #define CAN_F9R2_FB25_Pos (25U)
<> 147:30b64687e01f 6173 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6174 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 6175 #define CAN_F9R2_FB26_Pos (26U)
<> 147:30b64687e01f 6176 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6177 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 6178 #define CAN_F9R2_FB27_Pos (27U)
<> 147:30b64687e01f 6179 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6180 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 6181 #define CAN_F9R2_FB28_Pos (28U)
<> 147:30b64687e01f 6182 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 6183 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 6184 #define CAN_F9R2_FB29_Pos (29U)
<> 147:30b64687e01f 6185 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6186 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 6187 #define CAN_F9R2_FB30_Pos (30U)
<> 147:30b64687e01f 6188 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 6189 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 6190 #define CAN_F9R2_FB31_Pos (31U)
<> 147:30b64687e01f 6191 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 6192 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 6193
<> 147:30b64687e01f 6194 /******************* Bit definition for CAN_F10R2 register ******************/
<> 147:30b64687e01f 6195 #define CAN_F10R2_FB0_Pos (0U)
<> 147:30b64687e01f 6196 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6197 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 6198 #define CAN_F10R2_FB1_Pos (1U)
<> 147:30b64687e01f 6199 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6200 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 6201 #define CAN_F10R2_FB2_Pos (2U)
<> 147:30b64687e01f 6202 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6203 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 6204 #define CAN_F10R2_FB3_Pos (3U)
<> 147:30b64687e01f 6205 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6206 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 6207 #define CAN_F10R2_FB4_Pos (4U)
<> 147:30b64687e01f 6208 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6209 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 6210 #define CAN_F10R2_FB5_Pos (5U)
<> 147:30b64687e01f 6211 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6212 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 6213 #define CAN_F10R2_FB6_Pos (6U)
<> 147:30b64687e01f 6214 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6215 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 6216 #define CAN_F10R2_FB7_Pos (7U)
<> 147:30b64687e01f 6217 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6218 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 6219 #define CAN_F10R2_FB8_Pos (8U)
<> 147:30b64687e01f 6220 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6221 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 6222 #define CAN_F10R2_FB9_Pos (9U)
<> 147:30b64687e01f 6223 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6224 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 6225 #define CAN_F10R2_FB10_Pos (10U)
<> 147:30b64687e01f 6226 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6227 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 6228 #define CAN_F10R2_FB11_Pos (11U)
<> 147:30b64687e01f 6229 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6230 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 6231 #define CAN_F10R2_FB12_Pos (12U)
<> 147:30b64687e01f 6232 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6233 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 6234 #define CAN_F10R2_FB13_Pos (13U)
<> 147:30b64687e01f 6235 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6236 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 6237 #define CAN_F10R2_FB14_Pos (14U)
<> 147:30b64687e01f 6238 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 6239 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 6240 #define CAN_F10R2_FB15_Pos (15U)
<> 147:30b64687e01f 6241 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 6242 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 6243 #define CAN_F10R2_FB16_Pos (16U)
<> 147:30b64687e01f 6244 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6245 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 6246 #define CAN_F10R2_FB17_Pos (17U)
<> 147:30b64687e01f 6247 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6248 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 6249 #define CAN_F10R2_FB18_Pos (18U)
<> 147:30b64687e01f 6250 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6251 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 6252 #define CAN_F10R2_FB19_Pos (19U)
<> 147:30b64687e01f 6253 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6254 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 6255 #define CAN_F10R2_FB20_Pos (20U)
<> 147:30b64687e01f 6256 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6257 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 6258 #define CAN_F10R2_FB21_Pos (21U)
<> 147:30b64687e01f 6259 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6260 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 6261 #define CAN_F10R2_FB22_Pos (22U)
<> 147:30b64687e01f 6262 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6263 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 6264 #define CAN_F10R2_FB23_Pos (23U)
<> 147:30b64687e01f 6265 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6266 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 6267 #define CAN_F10R2_FB24_Pos (24U)
<> 147:30b64687e01f 6268 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6269 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 6270 #define CAN_F10R2_FB25_Pos (25U)
<> 147:30b64687e01f 6271 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6272 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 6273 #define CAN_F10R2_FB26_Pos (26U)
<> 147:30b64687e01f 6274 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6275 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 6276 #define CAN_F10R2_FB27_Pos (27U)
<> 147:30b64687e01f 6277 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6278 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 6279 #define CAN_F10R2_FB28_Pos (28U)
<> 147:30b64687e01f 6280 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 6281 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 6282 #define CAN_F10R2_FB29_Pos (29U)
<> 147:30b64687e01f 6283 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6284 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 6285 #define CAN_F10R2_FB30_Pos (30U)
<> 147:30b64687e01f 6286 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 6287 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 6288 #define CAN_F10R2_FB31_Pos (31U)
<> 147:30b64687e01f 6289 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 6290 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 6291
<> 147:30b64687e01f 6292 /******************* Bit definition for CAN_F11R2 register ******************/
<> 147:30b64687e01f 6293 #define CAN_F11R2_FB0_Pos (0U)
<> 147:30b64687e01f 6294 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6295 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 6296 #define CAN_F11R2_FB1_Pos (1U)
<> 147:30b64687e01f 6297 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6298 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 6299 #define CAN_F11R2_FB2_Pos (2U)
<> 147:30b64687e01f 6300 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6301 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 6302 #define CAN_F11R2_FB3_Pos (3U)
<> 147:30b64687e01f 6303 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6304 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 6305 #define CAN_F11R2_FB4_Pos (4U)
<> 147:30b64687e01f 6306 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6307 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 6308 #define CAN_F11R2_FB5_Pos (5U)
<> 147:30b64687e01f 6309 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6310 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 6311 #define CAN_F11R2_FB6_Pos (6U)
<> 147:30b64687e01f 6312 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6313 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 6314 #define CAN_F11R2_FB7_Pos (7U)
<> 147:30b64687e01f 6315 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6316 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 6317 #define CAN_F11R2_FB8_Pos (8U)
<> 147:30b64687e01f 6318 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6319 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 6320 #define CAN_F11R2_FB9_Pos (9U)
<> 147:30b64687e01f 6321 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6322 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 6323 #define CAN_F11R2_FB10_Pos (10U)
<> 147:30b64687e01f 6324 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6325 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 6326 #define CAN_F11R2_FB11_Pos (11U)
<> 147:30b64687e01f 6327 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6328 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 6329 #define CAN_F11R2_FB12_Pos (12U)
<> 147:30b64687e01f 6330 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6331 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 6332 #define CAN_F11R2_FB13_Pos (13U)
<> 147:30b64687e01f 6333 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6334 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 6335 #define CAN_F11R2_FB14_Pos (14U)
<> 147:30b64687e01f 6336 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 6337 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 6338 #define CAN_F11R2_FB15_Pos (15U)
<> 147:30b64687e01f 6339 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 6340 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 6341 #define CAN_F11R2_FB16_Pos (16U)
<> 147:30b64687e01f 6342 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6343 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 6344 #define CAN_F11R2_FB17_Pos (17U)
<> 147:30b64687e01f 6345 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6346 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 6347 #define CAN_F11R2_FB18_Pos (18U)
<> 147:30b64687e01f 6348 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6349 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 6350 #define CAN_F11R2_FB19_Pos (19U)
<> 147:30b64687e01f 6351 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6352 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 6353 #define CAN_F11R2_FB20_Pos (20U)
<> 147:30b64687e01f 6354 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6355 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 6356 #define CAN_F11R2_FB21_Pos (21U)
<> 147:30b64687e01f 6357 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6358 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 6359 #define CAN_F11R2_FB22_Pos (22U)
<> 147:30b64687e01f 6360 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6361 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 6362 #define CAN_F11R2_FB23_Pos (23U)
<> 147:30b64687e01f 6363 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6364 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 6365 #define CAN_F11R2_FB24_Pos (24U)
<> 147:30b64687e01f 6366 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6367 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 6368 #define CAN_F11R2_FB25_Pos (25U)
<> 147:30b64687e01f 6369 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6370 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 6371 #define CAN_F11R2_FB26_Pos (26U)
<> 147:30b64687e01f 6372 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6373 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 6374 #define CAN_F11R2_FB27_Pos (27U)
<> 147:30b64687e01f 6375 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6376 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 6377 #define CAN_F11R2_FB28_Pos (28U)
<> 147:30b64687e01f 6378 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 6379 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 6380 #define CAN_F11R2_FB29_Pos (29U)
<> 147:30b64687e01f 6381 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6382 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 6383 #define CAN_F11R2_FB30_Pos (30U)
<> 147:30b64687e01f 6384 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 6385 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 6386 #define CAN_F11R2_FB31_Pos (31U)
<> 147:30b64687e01f 6387 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 6388 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 6389
<> 147:30b64687e01f 6390 /******************* Bit definition for CAN_F12R2 register ******************/
<> 147:30b64687e01f 6391 #define CAN_F12R2_FB0_Pos (0U)
<> 147:30b64687e01f 6392 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6393 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 6394 #define CAN_F12R2_FB1_Pos (1U)
<> 147:30b64687e01f 6395 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6396 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 6397 #define CAN_F12R2_FB2_Pos (2U)
<> 147:30b64687e01f 6398 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6399 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 6400 #define CAN_F12R2_FB3_Pos (3U)
<> 147:30b64687e01f 6401 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6402 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 6403 #define CAN_F12R2_FB4_Pos (4U)
<> 147:30b64687e01f 6404 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6405 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 6406 #define CAN_F12R2_FB5_Pos (5U)
<> 147:30b64687e01f 6407 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6408 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 6409 #define CAN_F12R2_FB6_Pos (6U)
<> 147:30b64687e01f 6410 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6411 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 6412 #define CAN_F12R2_FB7_Pos (7U)
<> 147:30b64687e01f 6413 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6414 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 6415 #define CAN_F12R2_FB8_Pos (8U)
<> 147:30b64687e01f 6416 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6417 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 6418 #define CAN_F12R2_FB9_Pos (9U)
<> 147:30b64687e01f 6419 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6420 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 6421 #define CAN_F12R2_FB10_Pos (10U)
<> 147:30b64687e01f 6422 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6423 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 6424 #define CAN_F12R2_FB11_Pos (11U)
<> 147:30b64687e01f 6425 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6426 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 6427 #define CAN_F12R2_FB12_Pos (12U)
<> 147:30b64687e01f 6428 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6429 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 6430 #define CAN_F12R2_FB13_Pos (13U)
<> 147:30b64687e01f 6431 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6432 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 6433 #define CAN_F12R2_FB14_Pos (14U)
<> 147:30b64687e01f 6434 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 6435 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 6436 #define CAN_F12R2_FB15_Pos (15U)
<> 147:30b64687e01f 6437 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 6438 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 6439 #define CAN_F12R2_FB16_Pos (16U)
<> 147:30b64687e01f 6440 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6441 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 6442 #define CAN_F12R2_FB17_Pos (17U)
<> 147:30b64687e01f 6443 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6444 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 6445 #define CAN_F12R2_FB18_Pos (18U)
<> 147:30b64687e01f 6446 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6447 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 6448 #define CAN_F12R2_FB19_Pos (19U)
<> 147:30b64687e01f 6449 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6450 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 6451 #define CAN_F12R2_FB20_Pos (20U)
<> 147:30b64687e01f 6452 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6453 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 6454 #define CAN_F12R2_FB21_Pos (21U)
<> 147:30b64687e01f 6455 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6456 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 6457 #define CAN_F12R2_FB22_Pos (22U)
<> 147:30b64687e01f 6458 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6459 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 6460 #define CAN_F12R2_FB23_Pos (23U)
<> 147:30b64687e01f 6461 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6462 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 6463 #define CAN_F12R2_FB24_Pos (24U)
<> 147:30b64687e01f 6464 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6465 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 6466 #define CAN_F12R2_FB25_Pos (25U)
<> 147:30b64687e01f 6467 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6468 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 6469 #define CAN_F12R2_FB26_Pos (26U)
<> 147:30b64687e01f 6470 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6471 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 6472 #define CAN_F12R2_FB27_Pos (27U)
<> 147:30b64687e01f 6473 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6474 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 6475 #define CAN_F12R2_FB28_Pos (28U)
<> 147:30b64687e01f 6476 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 6477 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 6478 #define CAN_F12R2_FB29_Pos (29U)
<> 147:30b64687e01f 6479 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6480 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 6481 #define CAN_F12R2_FB30_Pos (30U)
<> 147:30b64687e01f 6482 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 6483 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 6484 #define CAN_F12R2_FB31_Pos (31U)
<> 147:30b64687e01f 6485 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 6486 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 6487
<> 147:30b64687e01f 6488 /******************* Bit definition for CAN_F13R2 register ******************/
<> 147:30b64687e01f 6489 #define CAN_F13R2_FB0_Pos (0U)
<> 147:30b64687e01f 6490 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6491 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
<> 147:30b64687e01f 6492 #define CAN_F13R2_FB1_Pos (1U)
<> 147:30b64687e01f 6493 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6494 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
<> 147:30b64687e01f 6495 #define CAN_F13R2_FB2_Pos (2U)
<> 147:30b64687e01f 6496 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6497 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
<> 147:30b64687e01f 6498 #define CAN_F13R2_FB3_Pos (3U)
<> 147:30b64687e01f 6499 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6500 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
<> 147:30b64687e01f 6501 #define CAN_F13R2_FB4_Pos (4U)
<> 147:30b64687e01f 6502 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6503 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
<> 147:30b64687e01f 6504 #define CAN_F13R2_FB5_Pos (5U)
<> 147:30b64687e01f 6505 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6506 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
<> 147:30b64687e01f 6507 #define CAN_F13R2_FB6_Pos (6U)
<> 147:30b64687e01f 6508 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6509 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
<> 147:30b64687e01f 6510 #define CAN_F13R2_FB7_Pos (7U)
<> 147:30b64687e01f 6511 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6512 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
<> 147:30b64687e01f 6513 #define CAN_F13R2_FB8_Pos (8U)
<> 147:30b64687e01f 6514 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6515 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
<> 147:30b64687e01f 6516 #define CAN_F13R2_FB9_Pos (9U)
<> 147:30b64687e01f 6517 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6518 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
<> 147:30b64687e01f 6519 #define CAN_F13R2_FB10_Pos (10U)
<> 147:30b64687e01f 6520 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6521 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
<> 147:30b64687e01f 6522 #define CAN_F13R2_FB11_Pos (11U)
<> 147:30b64687e01f 6523 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6524 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
<> 147:30b64687e01f 6525 #define CAN_F13R2_FB12_Pos (12U)
<> 147:30b64687e01f 6526 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6527 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
<> 147:30b64687e01f 6528 #define CAN_F13R2_FB13_Pos (13U)
<> 147:30b64687e01f 6529 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6530 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
<> 147:30b64687e01f 6531 #define CAN_F13R2_FB14_Pos (14U)
<> 147:30b64687e01f 6532 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 6533 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
<> 147:30b64687e01f 6534 #define CAN_F13R2_FB15_Pos (15U)
<> 147:30b64687e01f 6535 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 6536 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
<> 147:30b64687e01f 6537 #define CAN_F13R2_FB16_Pos (16U)
<> 147:30b64687e01f 6538 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6539 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
<> 147:30b64687e01f 6540 #define CAN_F13R2_FB17_Pos (17U)
<> 147:30b64687e01f 6541 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6542 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
<> 147:30b64687e01f 6543 #define CAN_F13R2_FB18_Pos (18U)
<> 147:30b64687e01f 6544 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6545 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
<> 147:30b64687e01f 6546 #define CAN_F13R2_FB19_Pos (19U)
<> 147:30b64687e01f 6547 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6548 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
<> 147:30b64687e01f 6549 #define CAN_F13R2_FB20_Pos (20U)
<> 147:30b64687e01f 6550 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6551 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
<> 147:30b64687e01f 6552 #define CAN_F13R2_FB21_Pos (21U)
<> 147:30b64687e01f 6553 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6554 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
<> 147:30b64687e01f 6555 #define CAN_F13R2_FB22_Pos (22U)
<> 147:30b64687e01f 6556 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6557 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
<> 147:30b64687e01f 6558 #define CAN_F13R2_FB23_Pos (23U)
<> 147:30b64687e01f 6559 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6560 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
<> 147:30b64687e01f 6561 #define CAN_F13R2_FB24_Pos (24U)
<> 147:30b64687e01f 6562 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6563 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
<> 147:30b64687e01f 6564 #define CAN_F13R2_FB25_Pos (25U)
<> 147:30b64687e01f 6565 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6566 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
<> 147:30b64687e01f 6567 #define CAN_F13R2_FB26_Pos (26U)
<> 147:30b64687e01f 6568 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6569 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
<> 147:30b64687e01f 6570 #define CAN_F13R2_FB27_Pos (27U)
<> 147:30b64687e01f 6571 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6572 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
<> 147:30b64687e01f 6573 #define CAN_F13R2_FB28_Pos (28U)
<> 147:30b64687e01f 6574 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 6575 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
<> 147:30b64687e01f 6576 #define CAN_F13R2_FB29_Pos (29U)
<> 147:30b64687e01f 6577 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6578 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
<> 147:30b64687e01f 6579 #define CAN_F13R2_FB30_Pos (30U)
<> 147:30b64687e01f 6580 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 6581 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
<> 147:30b64687e01f 6582 #define CAN_F13R2_FB31_Pos (31U)
<> 147:30b64687e01f 6583 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 6584 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
<> 147:30b64687e01f 6585
<> 147:30b64687e01f 6586 /******************************************************************************/
<> 147:30b64687e01f 6587 /* */
<> 147:30b64687e01f 6588 /* CRC calculation unit (CRC) */
<> 147:30b64687e01f 6589 /* */
<> 147:30b64687e01f 6590 /******************************************************************************/
<> 147:30b64687e01f 6591 /******************* Bit definition for CRC_DR register *********************/
<> 147:30b64687e01f 6592 #define CRC_DR_DR_Pos (0U)
<> 147:30b64687e01f 6593 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 6594 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 147:30b64687e01f 6595
<> 147:30b64687e01f 6596 /******************* Bit definition for CRC_IDR register ********************/
<> 147:30b64687e01f 6597 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
<> 147:30b64687e01f 6598
<> 147:30b64687e01f 6599 /******************** Bit definition for CRC_CR register ********************/
<> 147:30b64687e01f 6600 #define CRC_CR_RESET_Pos (0U)
<> 147:30b64687e01f 6601 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6602 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
<> 147:30b64687e01f 6603 #define CRC_CR_POLYSIZE_Pos (3U)
<> 147:30b64687e01f 6604 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
<> 147:30b64687e01f 6605 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
<> 147:30b64687e01f 6606 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6607 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6608 #define CRC_CR_REV_IN_Pos (5U)
<> 147:30b64687e01f 6609 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
<> 147:30b64687e01f 6610 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
<> 147:30b64687e01f 6611 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6612 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6613 #define CRC_CR_REV_OUT_Pos (7U)
<> 147:30b64687e01f 6614 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6615 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
<> 147:30b64687e01f 6616
<> 147:30b64687e01f 6617 /******************* Bit definition for CRC_INIT register *******************/
<> 147:30b64687e01f 6618 #define CRC_INIT_INIT_Pos (0U)
<> 147:30b64687e01f 6619 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 6620 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
<> 147:30b64687e01f 6621
<> 147:30b64687e01f 6622 /******************* Bit definition for CRC_POL register ********************/
<> 147:30b64687e01f 6623 #define CRC_POL_POL_Pos (0U)
<> 147:30b64687e01f 6624 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 6625 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
<> 147:30b64687e01f 6626
<> 147:30b64687e01f 6627 /******************************************************************************/
<> 147:30b64687e01f 6628 /* */
<> 147:30b64687e01f 6629 /* Digital to Analog Converter (DAC) */
<> 147:30b64687e01f 6630 /* */
<> 147:30b64687e01f 6631 /******************************************************************************/
<> 147:30b64687e01f 6632
<> 147:30b64687e01f 6633 /*
<> 147:30b64687e01f 6634 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 147:30b64687e01f 6635 */
<> 147:30b64687e01f 6636 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */
<> 147:30b64687e01f 6637
<> 147:30b64687e01f 6638
<> 147:30b64687e01f 6639 /******************** Bit definition for DAC_CR register ********************/
<> 147:30b64687e01f 6640 #define DAC_CR_EN1_Pos (0U)
<> 147:30b64687e01f 6641 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6642 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
<> 147:30b64687e01f 6643 #define DAC_CR_BOFF1_Pos (1U)
<> 147:30b64687e01f 6644 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6645 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
<> 147:30b64687e01f 6646 #define DAC_CR_TEN1_Pos (2U)
<> 147:30b64687e01f 6647 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6648 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
<> 147:30b64687e01f 6649
<> 147:30b64687e01f 6650 #define DAC_CR_TSEL1_Pos (3U)
<> 147:30b64687e01f 6651 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
<> 147:30b64687e01f 6652 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 147:30b64687e01f 6653 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6654 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6655 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6656
<> 147:30b64687e01f 6657 #define DAC_CR_WAVE1_Pos (6U)
<> 147:30b64687e01f 6658 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
<> 147:30b64687e01f 6659 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 147:30b64687e01f 6660 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6661 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6662
<> 147:30b64687e01f 6663 #define DAC_CR_MAMP1_Pos (8U)
<> 147:30b64687e01f 6664 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 6665 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 147:30b64687e01f 6666 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6667 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6668 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6669 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6670
<> 147:30b64687e01f 6671 #define DAC_CR_DMAEN1_Pos (12U)
<> 147:30b64687e01f 6672 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6673 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
<> 147:30b64687e01f 6674 #define DAC_CR_DMAUDRIE1_Pos (13U)
<> 147:30b64687e01f 6675 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6676 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun IT enable */
<> 147:30b64687e01f 6677 #define DAC_CR_EN2_Pos (16U)
<> 147:30b64687e01f 6678 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6679 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
<> 147:30b64687e01f 6680 #define DAC_CR_BOFF2_Pos (17U)
<> 147:30b64687e01f 6681 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6682 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
<> 147:30b64687e01f 6683 #define DAC_CR_TEN2_Pos (18U)
<> 147:30b64687e01f 6684 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6685 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
<> 147:30b64687e01f 6686
<> 147:30b64687e01f 6687 #define DAC_CR_TSEL2_Pos (19U)
<> 147:30b64687e01f 6688 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
<> 147:30b64687e01f 6689 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 147:30b64687e01f 6690 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6691 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6692 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6693
<> 147:30b64687e01f 6694 #define DAC_CR_WAVE2_Pos (22U)
<> 147:30b64687e01f 6695 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
<> 147:30b64687e01f 6696 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 147:30b64687e01f 6697 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6698 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6699
<> 147:30b64687e01f 6700 #define DAC_CR_MAMP2_Pos (24U)
<> 147:30b64687e01f 6701 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 6702 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 147:30b64687e01f 6703 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6704 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6705 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6706 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6707
<> 147:30b64687e01f 6708 #define DAC_CR_DMAEN2_Pos (28U)
<> 147:30b64687e01f 6709 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 6710 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
<> 147:30b64687e01f 6711 #define DAC_CR_DMAUDRIE2_Pos (29U)
<> 147:30b64687e01f 6712 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6713 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun IT enable */
<> 147:30b64687e01f 6714
<> 147:30b64687e01f 6715 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 147:30b64687e01f 6716 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
<> 147:30b64687e01f 6717 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6718 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
<> 147:30b64687e01f 6719 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
<> 147:30b64687e01f 6720 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6721 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
<> 147:30b64687e01f 6722
<> 147:30b64687e01f 6723 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 147:30b64687e01f 6724 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
<> 147:30b64687e01f 6725 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 6726 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
<> 147:30b64687e01f 6727
<> 147:30b64687e01f 6728 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 147:30b64687e01f 6729 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
<> 147:30b64687e01f 6730 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 147:30b64687e01f 6731 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
<> 147:30b64687e01f 6732
<> 147:30b64687e01f 6733 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 147:30b64687e01f 6734 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
<> 147:30b64687e01f 6735 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 6736 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
<> 147:30b64687e01f 6737
<> 147:30b64687e01f 6738 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 147:30b64687e01f 6739 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
<> 147:30b64687e01f 6740 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 6741 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
<> 147:30b64687e01f 6742
<> 147:30b64687e01f 6743 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 147:30b64687e01f 6744 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
<> 147:30b64687e01f 6745 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
<> 147:30b64687e01f 6746 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
<> 147:30b64687e01f 6747
<> 147:30b64687e01f 6748 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 147:30b64687e01f 6749 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
<> 147:30b64687e01f 6750 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 6751 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
<> 147:30b64687e01f 6752
<> 147:30b64687e01f 6753 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 147:30b64687e01f 6754 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
<> 147:30b64687e01f 6755 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 6756 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
<> 147:30b64687e01f 6757 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
<> 147:30b64687e01f 6758 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
<> 147:30b64687e01f 6759 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
<> 147:30b64687e01f 6760
<> 147:30b64687e01f 6761 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 147:30b64687e01f 6762 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
<> 147:30b64687e01f 6763 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 147:30b64687e01f 6764 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
<> 147:30b64687e01f 6765 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
<> 147:30b64687e01f 6766 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
<> 147:30b64687e01f 6767 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
<> 147:30b64687e01f 6768
<> 147:30b64687e01f 6769 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 147:30b64687e01f 6770 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
<> 147:30b64687e01f 6771 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 6772 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
<> 147:30b64687e01f 6773 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
<> 147:30b64687e01f 6774 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 6775 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
<> 147:30b64687e01f 6776
<> 147:30b64687e01f 6777 /******************* Bit definition for DAC_DOR1 register *******************/
<> 147:30b64687e01f 6778 #define DAC_DOR1_DACC1DOR_Pos (0U)
<> 147:30b64687e01f 6779 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 6780 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
<> 147:30b64687e01f 6781
<> 147:30b64687e01f 6782 /******************* Bit definition for DAC_DOR2 register *******************/
<> 147:30b64687e01f 6783 #define DAC_DOR2_DACC2DOR_Pos (0U)
<> 147:30b64687e01f 6784 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 6785 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
<> 147:30b64687e01f 6786
<> 147:30b64687e01f 6787 /******************** Bit definition for DAC_SR register ********************/
<> 147:30b64687e01f 6788 #define DAC_SR_DMAUDR1_Pos (13U)
<> 147:30b64687e01f 6789 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6790 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
<> 147:30b64687e01f 6791 #define DAC_SR_DMAUDR2_Pos (29U)
<> 147:30b64687e01f 6792 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 6793 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
<> 147:30b64687e01f 6794
<> 147:30b64687e01f 6795 /******************************************************************************/
<> 147:30b64687e01f 6796 /* */
<> 147:30b64687e01f 6797 /* Debug MCU (DBGMCU) */
<> 147:30b64687e01f 6798 /* */
<> 147:30b64687e01f 6799 /******************************************************************************/
<> 147:30b64687e01f 6800 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 147:30b64687e01f 6801 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
<> 147:30b64687e01f 6802 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 6803 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
<> 147:30b64687e01f 6804 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
<> 147:30b64687e01f 6805 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
<> 147:30b64687e01f 6806 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
<> 147:30b64687e01f 6807
<> 147:30b64687e01f 6808 /******************** Bit definition for DBGMCU_CR register *****************/
<> 147:30b64687e01f 6809 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
<> 147:30b64687e01f 6810 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6811 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
<> 147:30b64687e01f 6812 #define DBGMCU_CR_DBG_STOP_Pos (1U)
<> 147:30b64687e01f 6813 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6814 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
<> 147:30b64687e01f 6815 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
<> 147:30b64687e01f 6816 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6817 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
<> 147:30b64687e01f 6818 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
<> 147:30b64687e01f 6819 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6820 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
<> 147:30b64687e01f 6821
<> 147:30b64687e01f 6822 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
<> 147:30b64687e01f 6823 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
<> 147:30b64687e01f 6824 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
<> 147:30b64687e01f 6825 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6826 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6827
<> 147:30b64687e01f 6828 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 147:30b64687e01f 6829 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
<> 147:30b64687e01f 6830 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6831 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
<> 147:30b64687e01f 6832 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
<> 147:30b64687e01f 6833 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6834 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
<> 147:30b64687e01f 6835 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
<> 147:30b64687e01f 6836 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6837 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
<> 147:30b64687e01f 6838 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
<> 147:30b64687e01f 6839 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6840 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
<> 147:30b64687e01f 6841 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
<> 147:30b64687e01f 6842 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6843 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
<> 147:30b64687e01f 6844 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
<> 147:30b64687e01f 6845 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6846 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
<> 147:30b64687e01f 6847 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
<> 147:30b64687e01f 6848 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6849 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
<> 147:30b64687e01f 6850 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
<> 147:30b64687e01f 6851 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6852 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
<> 147:30b64687e01f 6853 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
<> 147:30b64687e01f 6854 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6855 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
<> 147:30b64687e01f 6856 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
<> 147:30b64687e01f 6857 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6858 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
<> 147:30b64687e01f 6859 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (30U)
<> 147:30b64687e01f 6860 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 6861 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
<> 147:30b64687e01f 6862 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)
<> 147:30b64687e01f 6863 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6864 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk
<> 147:30b64687e01f 6865
<> 147:30b64687e01f 6866 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 147:30b64687e01f 6867 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
<> 147:30b64687e01f 6868 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6869 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
<> 147:30b64687e01f 6870 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
<> 147:30b64687e01f 6871 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6872 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
<> 147:30b64687e01f 6873 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)
<> 147:30b64687e01f 6874 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6875 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
<> 147:30b64687e01f 6876 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)
<> 147:30b64687e01f 6877 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6878 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
<> 147:30b64687e01f 6879 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)
<> 147:30b64687e01f 6880 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6881 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
<> 147:30b64687e01f 6882 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos (5U)
<> 147:30b64687e01f 6883 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6884 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk
<> 147:30b64687e01f 6885
<> 147:30b64687e01f 6886 /******************************************************************************/
<> 147:30b64687e01f 6887 /* */
<> 147:30b64687e01f 6888 /* DMA Controller (DMA) */
<> 147:30b64687e01f 6889 /* */
<> 147:30b64687e01f 6890 /******************************************************************************/
<> 147:30b64687e01f 6891 /******************* Bit definition for DMA_ISR register ********************/
<> 147:30b64687e01f 6892 #define DMA_ISR_GIF1_Pos (0U)
<> 147:30b64687e01f 6893 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6894 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
<> 147:30b64687e01f 6895 #define DMA_ISR_TCIF1_Pos (1U)
<> 147:30b64687e01f 6896 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6897 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
<> 147:30b64687e01f 6898 #define DMA_ISR_HTIF1_Pos (2U)
<> 147:30b64687e01f 6899 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6900 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
<> 147:30b64687e01f 6901 #define DMA_ISR_TEIF1_Pos (3U)
<> 147:30b64687e01f 6902 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6903 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
<> 147:30b64687e01f 6904 #define DMA_ISR_GIF2_Pos (4U)
<> 147:30b64687e01f 6905 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6906 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
<> 147:30b64687e01f 6907 #define DMA_ISR_TCIF2_Pos (5U)
<> 147:30b64687e01f 6908 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6909 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
<> 147:30b64687e01f 6910 #define DMA_ISR_HTIF2_Pos (6U)
<> 147:30b64687e01f 6911 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6912 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
<> 147:30b64687e01f 6913 #define DMA_ISR_TEIF2_Pos (7U)
<> 147:30b64687e01f 6914 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 6915 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
<> 147:30b64687e01f 6916 #define DMA_ISR_GIF3_Pos (8U)
<> 147:30b64687e01f 6917 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 6918 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
<> 147:30b64687e01f 6919 #define DMA_ISR_TCIF3_Pos (9U)
<> 147:30b64687e01f 6920 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 6921 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
<> 147:30b64687e01f 6922 #define DMA_ISR_HTIF3_Pos (10U)
<> 147:30b64687e01f 6923 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 6924 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
<> 147:30b64687e01f 6925 #define DMA_ISR_TEIF3_Pos (11U)
<> 147:30b64687e01f 6926 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 6927 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
<> 147:30b64687e01f 6928 #define DMA_ISR_GIF4_Pos (12U)
<> 147:30b64687e01f 6929 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 6930 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
<> 147:30b64687e01f 6931 #define DMA_ISR_TCIF4_Pos (13U)
<> 147:30b64687e01f 6932 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 6933 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
<> 147:30b64687e01f 6934 #define DMA_ISR_HTIF4_Pos (14U)
<> 147:30b64687e01f 6935 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 6936 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
<> 147:30b64687e01f 6937 #define DMA_ISR_TEIF4_Pos (15U)
<> 147:30b64687e01f 6938 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 6939 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
<> 147:30b64687e01f 6940 #define DMA_ISR_GIF5_Pos (16U)
<> 147:30b64687e01f 6941 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 6942 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
<> 147:30b64687e01f 6943 #define DMA_ISR_TCIF5_Pos (17U)
<> 147:30b64687e01f 6944 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 6945 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
<> 147:30b64687e01f 6946 #define DMA_ISR_HTIF5_Pos (18U)
<> 147:30b64687e01f 6947 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 6948 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
<> 147:30b64687e01f 6949 #define DMA_ISR_TEIF5_Pos (19U)
<> 147:30b64687e01f 6950 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 6951 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
<> 147:30b64687e01f 6952 #define DMA_ISR_GIF6_Pos (20U)
<> 147:30b64687e01f 6953 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 6954 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
<> 147:30b64687e01f 6955 #define DMA_ISR_TCIF6_Pos (21U)
<> 147:30b64687e01f 6956 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 6957 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
<> 147:30b64687e01f 6958 #define DMA_ISR_HTIF6_Pos (22U)
<> 147:30b64687e01f 6959 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 6960 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
<> 147:30b64687e01f 6961 #define DMA_ISR_TEIF6_Pos (23U)
<> 147:30b64687e01f 6962 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 6963 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
<> 147:30b64687e01f 6964 #define DMA_ISR_GIF7_Pos (24U)
<> 147:30b64687e01f 6965 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 6966 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
<> 147:30b64687e01f 6967 #define DMA_ISR_TCIF7_Pos (25U)
<> 147:30b64687e01f 6968 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 6969 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
<> 147:30b64687e01f 6970 #define DMA_ISR_HTIF7_Pos (26U)
<> 147:30b64687e01f 6971 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 6972 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
<> 147:30b64687e01f 6973 #define DMA_ISR_TEIF7_Pos (27U)
<> 147:30b64687e01f 6974 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 6975 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
<> 147:30b64687e01f 6976
<> 147:30b64687e01f 6977 /******************* Bit definition for DMA_IFCR register *******************/
<> 147:30b64687e01f 6978 #define DMA_IFCR_CGIF1_Pos (0U)
<> 147:30b64687e01f 6979 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 6980 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
<> 147:30b64687e01f 6981 #define DMA_IFCR_CTCIF1_Pos (1U)
<> 147:30b64687e01f 6982 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 6983 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
<> 147:30b64687e01f 6984 #define DMA_IFCR_CHTIF1_Pos (2U)
<> 147:30b64687e01f 6985 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 6986 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
<> 147:30b64687e01f 6987 #define DMA_IFCR_CTEIF1_Pos (3U)
<> 147:30b64687e01f 6988 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 6989 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
<> 147:30b64687e01f 6990 #define DMA_IFCR_CGIF2_Pos (4U)
<> 147:30b64687e01f 6991 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 6992 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
<> 147:30b64687e01f 6993 #define DMA_IFCR_CTCIF2_Pos (5U)
<> 147:30b64687e01f 6994 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 6995 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
<> 147:30b64687e01f 6996 #define DMA_IFCR_CHTIF2_Pos (6U)
<> 147:30b64687e01f 6997 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 6998 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
<> 147:30b64687e01f 6999 #define DMA_IFCR_CTEIF2_Pos (7U)
<> 147:30b64687e01f 7000 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7001 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
<> 147:30b64687e01f 7002 #define DMA_IFCR_CGIF3_Pos (8U)
<> 147:30b64687e01f 7003 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7004 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
<> 147:30b64687e01f 7005 #define DMA_IFCR_CTCIF3_Pos (9U)
<> 147:30b64687e01f 7006 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7007 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
<> 147:30b64687e01f 7008 #define DMA_IFCR_CHTIF3_Pos (10U)
<> 147:30b64687e01f 7009 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7010 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
<> 147:30b64687e01f 7011 #define DMA_IFCR_CTEIF3_Pos (11U)
<> 147:30b64687e01f 7012 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7013 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
<> 147:30b64687e01f 7014 #define DMA_IFCR_CGIF4_Pos (12U)
<> 147:30b64687e01f 7015 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7016 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
<> 147:30b64687e01f 7017 #define DMA_IFCR_CTCIF4_Pos (13U)
<> 147:30b64687e01f 7018 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7019 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
<> 147:30b64687e01f 7020 #define DMA_IFCR_CHTIF4_Pos (14U)
<> 147:30b64687e01f 7021 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7022 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
<> 147:30b64687e01f 7023 #define DMA_IFCR_CTEIF4_Pos (15U)
<> 147:30b64687e01f 7024 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 7025 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
<> 147:30b64687e01f 7026 #define DMA_IFCR_CGIF5_Pos (16U)
<> 147:30b64687e01f 7027 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 7028 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
<> 147:30b64687e01f 7029 #define DMA_IFCR_CTCIF5_Pos (17U)
<> 147:30b64687e01f 7030 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 7031 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
<> 147:30b64687e01f 7032 #define DMA_IFCR_CHTIF5_Pos (18U)
<> 147:30b64687e01f 7033 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 7034 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
<> 147:30b64687e01f 7035 #define DMA_IFCR_CTEIF5_Pos (19U)
<> 147:30b64687e01f 7036 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 7037 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
<> 147:30b64687e01f 7038 #define DMA_IFCR_CGIF6_Pos (20U)
<> 147:30b64687e01f 7039 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 7040 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
<> 147:30b64687e01f 7041 #define DMA_IFCR_CTCIF6_Pos (21U)
<> 147:30b64687e01f 7042 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 7043 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
<> 147:30b64687e01f 7044 #define DMA_IFCR_CHTIF6_Pos (22U)
<> 147:30b64687e01f 7045 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 7046 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
<> 147:30b64687e01f 7047 #define DMA_IFCR_CTEIF6_Pos (23U)
<> 147:30b64687e01f 7048 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 7049 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
<> 147:30b64687e01f 7050 #define DMA_IFCR_CGIF7_Pos (24U)
<> 147:30b64687e01f 7051 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 7052 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
<> 147:30b64687e01f 7053 #define DMA_IFCR_CTCIF7_Pos (25U)
<> 147:30b64687e01f 7054 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 7055 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
<> 147:30b64687e01f 7056 #define DMA_IFCR_CHTIF7_Pos (26U)
<> 147:30b64687e01f 7057 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 7058 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
<> 147:30b64687e01f 7059 #define DMA_IFCR_CTEIF7_Pos (27U)
<> 147:30b64687e01f 7060 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 7061 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
<> 147:30b64687e01f 7062
<> 147:30b64687e01f 7063 /******************* Bit definition for DMA_CCR register ********************/
<> 147:30b64687e01f 7064 #define DMA_CCR_EN_Pos (0U)
<> 147:30b64687e01f 7065 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7066 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
<> 147:30b64687e01f 7067 #define DMA_CCR_TCIE_Pos (1U)
<> 147:30b64687e01f 7068 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7069 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 147:30b64687e01f 7070 #define DMA_CCR_HTIE_Pos (2U)
<> 147:30b64687e01f 7071 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7072 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
<> 147:30b64687e01f 7073 #define DMA_CCR_TEIE_Pos (3U)
<> 147:30b64687e01f 7074 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7075 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
<> 147:30b64687e01f 7076 #define DMA_CCR_DIR_Pos (4U)
<> 147:30b64687e01f 7077 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7078 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
<> 147:30b64687e01f 7079 #define DMA_CCR_CIRC_Pos (5U)
<> 147:30b64687e01f 7080 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7081 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
<> 147:30b64687e01f 7082 #define DMA_CCR_PINC_Pos (6U)
<> 147:30b64687e01f 7083 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 7084 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
<> 147:30b64687e01f 7085 #define DMA_CCR_MINC_Pos (7U)
<> 147:30b64687e01f 7086 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7087 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
<> 147:30b64687e01f 7088
<> 147:30b64687e01f 7089 #define DMA_CCR_PSIZE_Pos (8U)
<> 147:30b64687e01f 7090 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 7091 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
<> 147:30b64687e01f 7092 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7093 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7094
<> 147:30b64687e01f 7095 #define DMA_CCR_MSIZE_Pos (10U)
<> 147:30b64687e01f 7096 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
<> 147:30b64687e01f 7097 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
<> 147:30b64687e01f 7098 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7099 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7100
<> 147:30b64687e01f 7101 #define DMA_CCR_PL_Pos (12U)
<> 147:30b64687e01f 7102 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 7103 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
<> 147:30b64687e01f 7104 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7105 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7106
<> 147:30b64687e01f 7107 #define DMA_CCR_MEM2MEM_Pos (14U)
<> 147:30b64687e01f 7108 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7109 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
<> 147:30b64687e01f 7110
<> 147:30b64687e01f 7111 /****************** Bit definition for DMA_CNDTR register *******************/
<> 147:30b64687e01f 7112 #define DMA_CNDTR_NDT_Pos (0U)
<> 147:30b64687e01f 7113 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 7114 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
<> 147:30b64687e01f 7115
<> 147:30b64687e01f 7116 /****************** Bit definition for DMA_CPAR register ********************/
<> 147:30b64687e01f 7117 #define DMA_CPAR_PA_Pos (0U)
<> 147:30b64687e01f 7118 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 7119 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
<> 147:30b64687e01f 7120
<> 147:30b64687e01f 7121 /****************** Bit definition for DMA_CMAR register ********************/
<> 147:30b64687e01f 7122 #define DMA_CMAR_MA_Pos (0U)
<> 147:30b64687e01f 7123 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 7124 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
<> 147:30b64687e01f 7125
<> 147:30b64687e01f 7126 /******************************************************************************/
<> 147:30b64687e01f 7127 /* */
<> 147:30b64687e01f 7128 /* External Interrupt/Event Controller (EXTI) */
<> 147:30b64687e01f 7129 /* */
<> 147:30b64687e01f 7130 /******************************************************************************/
<> 147:30b64687e01f 7131 /******************* Bit definition for EXTI_IMR register *******************/
<> 147:30b64687e01f 7132 #define EXTI_IMR_MR0_Pos (0U)
<> 147:30b64687e01f 7133 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7134 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
<> 147:30b64687e01f 7135 #define EXTI_IMR_MR1_Pos (1U)
<> 147:30b64687e01f 7136 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7137 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
<> 147:30b64687e01f 7138 #define EXTI_IMR_MR2_Pos (2U)
<> 147:30b64687e01f 7139 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7140 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
<> 147:30b64687e01f 7141 #define EXTI_IMR_MR3_Pos (3U)
<> 147:30b64687e01f 7142 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7143 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
<> 147:30b64687e01f 7144 #define EXTI_IMR_MR4_Pos (4U)
<> 147:30b64687e01f 7145 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7146 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
<> 147:30b64687e01f 7147 #define EXTI_IMR_MR5_Pos (5U)
<> 147:30b64687e01f 7148 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7149 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
<> 147:30b64687e01f 7150 #define EXTI_IMR_MR6_Pos (6U)
<> 147:30b64687e01f 7151 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 7152 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
<> 147:30b64687e01f 7153 #define EXTI_IMR_MR7_Pos (7U)
<> 147:30b64687e01f 7154 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7155 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
<> 147:30b64687e01f 7156 #define EXTI_IMR_MR8_Pos (8U)
<> 147:30b64687e01f 7157 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7158 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
<> 147:30b64687e01f 7159 #define EXTI_IMR_MR9_Pos (9U)
<> 147:30b64687e01f 7160 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7161 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
<> 147:30b64687e01f 7162 #define EXTI_IMR_MR10_Pos (10U)
<> 147:30b64687e01f 7163 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7164 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
<> 147:30b64687e01f 7165 #define EXTI_IMR_MR11_Pos (11U)
<> 147:30b64687e01f 7166 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7167 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
<> 147:30b64687e01f 7168 #define EXTI_IMR_MR12_Pos (12U)
<> 147:30b64687e01f 7169 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7170 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
<> 147:30b64687e01f 7171 #define EXTI_IMR_MR13_Pos (13U)
<> 147:30b64687e01f 7172 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7173 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
<> 147:30b64687e01f 7174 #define EXTI_IMR_MR14_Pos (14U)
<> 147:30b64687e01f 7175 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7176 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
<> 147:30b64687e01f 7177 #define EXTI_IMR_MR15_Pos (15U)
<> 147:30b64687e01f 7178 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 7179 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
<> 147:30b64687e01f 7180 #define EXTI_IMR_MR16_Pos (16U)
<> 147:30b64687e01f 7181 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 7182 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
<> 147:30b64687e01f 7183 #define EXTI_IMR_MR17_Pos (17U)
<> 147:30b64687e01f 7184 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 7185 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
<> 147:30b64687e01f 7186 #define EXTI_IMR_MR18_Pos (18U)
<> 147:30b64687e01f 7187 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 7188 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
<> 147:30b64687e01f 7189 #define EXTI_IMR_MR19_Pos (19U)
<> 147:30b64687e01f 7190 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 7191 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
<> 147:30b64687e01f 7192 #define EXTI_IMR_MR20_Pos (20U)
<> 147:30b64687e01f 7193 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 7194 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
<> 147:30b64687e01f 7195 #define EXTI_IMR_MR21_Pos (21U)
<> 147:30b64687e01f 7196 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 7197 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
<> 147:30b64687e01f 7198 #define EXTI_IMR_MR22_Pos (22U)
<> 147:30b64687e01f 7199 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 7200 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
<> 147:30b64687e01f 7201 #define EXTI_IMR_MR23_Pos (23U)
<> 147:30b64687e01f 7202 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 7203 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
<> 147:30b64687e01f 7204 #define EXTI_IMR_MR24_Pos (24U)
<> 147:30b64687e01f 7205 #define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 7206 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
<> 147:30b64687e01f 7207 #define EXTI_IMR_MR25_Pos (25U)
<> 147:30b64687e01f 7208 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 7209 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
<> 147:30b64687e01f 7210 #define EXTI_IMR_MR26_Pos (26U)
<> 147:30b64687e01f 7211 #define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 7212 #define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
<> 147:30b64687e01f 7213 #define EXTI_IMR_MR27_Pos (27U)
<> 147:30b64687e01f 7214 #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 7215 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
<> 147:30b64687e01f 7216 #define EXTI_IMR_MR28_Pos (28U)
<> 147:30b64687e01f 7217 #define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 7218 #define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
<> 147:30b64687e01f 7219 #define EXTI_IMR_MR29_Pos (29U)
<> 147:30b64687e01f 7220 #define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 7221 #define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
<> 147:30b64687e01f 7222 #define EXTI_IMR_MR30_Pos (30U)
<> 147:30b64687e01f 7223 #define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 7224 #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
<> 147:30b64687e01f 7225 #define EXTI_IMR_MR31_Pos (31U)
<> 147:30b64687e01f 7226 #define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 7227 #define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
<> 147:30b64687e01f 7228
<> 147:30b64687e01f 7229 /* References Defines */
<> 147:30b64687e01f 7230 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 147:30b64687e01f 7231 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 147:30b64687e01f 7232 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 147:30b64687e01f 7233 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 147:30b64687e01f 7234 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 147:30b64687e01f 7235 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 147:30b64687e01f 7236 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 147:30b64687e01f 7237 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 147:30b64687e01f 7238 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 147:30b64687e01f 7239 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 147:30b64687e01f 7240 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 147:30b64687e01f 7241 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 147:30b64687e01f 7242 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 147:30b64687e01f 7243 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 147:30b64687e01f 7244 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 147:30b64687e01f 7245 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 147:30b64687e01f 7246 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 147:30b64687e01f 7247 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 147:30b64687e01f 7248 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 147:30b64687e01f 7249 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 147:30b64687e01f 7250 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 147:30b64687e01f 7251 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 147:30b64687e01f 7252 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 147:30b64687e01f 7253 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 147:30b64687e01f 7254 #define EXTI_IMR_IM24 EXTI_IMR_MR24
<> 147:30b64687e01f 7255 #define EXTI_IMR_IM25 EXTI_IMR_MR25
<> 147:30b64687e01f 7256 #define EXTI_IMR_IM26 EXTI_IMR_MR26
<> 147:30b64687e01f 7257 #define EXTI_IMR_IM27 EXTI_IMR_MR27
<> 147:30b64687e01f 7258 #define EXTI_IMR_IM28 EXTI_IMR_MR28
<> 147:30b64687e01f 7259 #define EXTI_IMR_IM29 EXTI_IMR_MR29
<> 147:30b64687e01f 7260 #define EXTI_IMR_IM30 EXTI_IMR_MR30
<> 147:30b64687e01f 7261 #define EXTI_IMR_IM31 EXTI_IMR_MR31
<> 147:30b64687e01f 7262
<> 147:30b64687e01f 7263 #define EXTI_IMR_IM_Pos (0U)
<> 147:30b64687e01f 7264 #define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 7265 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
<> 147:30b64687e01f 7266
<> 147:30b64687e01f 7267 /******************* Bit definition for EXTI_EMR register *******************/
<> 147:30b64687e01f 7268 #define EXTI_EMR_MR0_Pos (0U)
<> 147:30b64687e01f 7269 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7270 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
<> 147:30b64687e01f 7271 #define EXTI_EMR_MR1_Pos (1U)
<> 147:30b64687e01f 7272 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7273 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
<> 147:30b64687e01f 7274 #define EXTI_EMR_MR2_Pos (2U)
<> 147:30b64687e01f 7275 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7276 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
<> 147:30b64687e01f 7277 #define EXTI_EMR_MR3_Pos (3U)
<> 147:30b64687e01f 7278 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7279 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
<> 147:30b64687e01f 7280 #define EXTI_EMR_MR4_Pos (4U)
<> 147:30b64687e01f 7281 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7282 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
<> 147:30b64687e01f 7283 #define EXTI_EMR_MR5_Pos (5U)
<> 147:30b64687e01f 7284 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7285 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
<> 147:30b64687e01f 7286 #define EXTI_EMR_MR6_Pos (6U)
<> 147:30b64687e01f 7287 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 7288 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
<> 147:30b64687e01f 7289 #define EXTI_EMR_MR7_Pos (7U)
<> 147:30b64687e01f 7290 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7291 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
<> 147:30b64687e01f 7292 #define EXTI_EMR_MR8_Pos (8U)
<> 147:30b64687e01f 7293 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7294 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
<> 147:30b64687e01f 7295 #define EXTI_EMR_MR9_Pos (9U)
<> 147:30b64687e01f 7296 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7297 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
<> 147:30b64687e01f 7298 #define EXTI_EMR_MR10_Pos (10U)
<> 147:30b64687e01f 7299 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7300 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
<> 147:30b64687e01f 7301 #define EXTI_EMR_MR11_Pos (11U)
<> 147:30b64687e01f 7302 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7303 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
<> 147:30b64687e01f 7304 #define EXTI_EMR_MR12_Pos (12U)
<> 147:30b64687e01f 7305 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7306 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
<> 147:30b64687e01f 7307 #define EXTI_EMR_MR13_Pos (13U)
<> 147:30b64687e01f 7308 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7309 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
<> 147:30b64687e01f 7310 #define EXTI_EMR_MR14_Pos (14U)
<> 147:30b64687e01f 7311 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7312 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
<> 147:30b64687e01f 7313 #define EXTI_EMR_MR15_Pos (15U)
<> 147:30b64687e01f 7314 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 7315 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
<> 147:30b64687e01f 7316 #define EXTI_EMR_MR16_Pos (16U)
<> 147:30b64687e01f 7317 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 7318 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
<> 147:30b64687e01f 7319 #define EXTI_EMR_MR17_Pos (17U)
<> 147:30b64687e01f 7320 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 7321 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
<> 147:30b64687e01f 7322 #define EXTI_EMR_MR18_Pos (18U)
<> 147:30b64687e01f 7323 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 7324 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
<> 147:30b64687e01f 7325 #define EXTI_EMR_MR19_Pos (19U)
<> 147:30b64687e01f 7326 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 7327 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
<> 147:30b64687e01f 7328 #define EXTI_EMR_MR20_Pos (20U)
<> 147:30b64687e01f 7329 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 7330 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
<> 147:30b64687e01f 7331 #define EXTI_EMR_MR21_Pos (21U)
<> 147:30b64687e01f 7332 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 7333 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
<> 147:30b64687e01f 7334 #define EXTI_EMR_MR22_Pos (22U)
<> 147:30b64687e01f 7335 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 7336 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
<> 147:30b64687e01f 7337 #define EXTI_EMR_MR23_Pos (23U)
<> 147:30b64687e01f 7338 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 7339 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
<> 147:30b64687e01f 7340 #define EXTI_EMR_MR24_Pos (24U)
<> 147:30b64687e01f 7341 #define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 7342 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
<> 147:30b64687e01f 7343 #define EXTI_EMR_MR25_Pos (25U)
<> 147:30b64687e01f 7344 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 7345 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
<> 147:30b64687e01f 7346 #define EXTI_EMR_MR26_Pos (26U)
<> 147:30b64687e01f 7347 #define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 7348 #define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
<> 147:30b64687e01f 7349 #define EXTI_EMR_MR27_Pos (27U)
<> 147:30b64687e01f 7350 #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 7351 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
<> 147:30b64687e01f 7352 #define EXTI_EMR_MR28_Pos (28U)
<> 147:30b64687e01f 7353 #define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 7354 #define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
<> 147:30b64687e01f 7355 #define EXTI_EMR_MR29_Pos (29U)
<> 147:30b64687e01f 7356 #define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 7357 #define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
<> 147:30b64687e01f 7358 #define EXTI_EMR_MR30_Pos (30U)
<> 147:30b64687e01f 7359 #define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 7360 #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
<> 147:30b64687e01f 7361 #define EXTI_EMR_MR31_Pos (31U)
<> 147:30b64687e01f 7362 #define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 7363 #define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
<> 147:30b64687e01f 7364
<> 147:30b64687e01f 7365 /* References Defines */
<> 147:30b64687e01f 7366 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 147:30b64687e01f 7367 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 147:30b64687e01f 7368 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 147:30b64687e01f 7369 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 147:30b64687e01f 7370 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 147:30b64687e01f 7371 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 147:30b64687e01f 7372 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 147:30b64687e01f 7373 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 147:30b64687e01f 7374 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 147:30b64687e01f 7375 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 147:30b64687e01f 7376 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 147:30b64687e01f 7377 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 147:30b64687e01f 7378 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 147:30b64687e01f 7379 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 147:30b64687e01f 7380 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 147:30b64687e01f 7381 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 147:30b64687e01f 7382 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 147:30b64687e01f 7383 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 147:30b64687e01f 7384 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 147:30b64687e01f 7385 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 147:30b64687e01f 7386 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 147:30b64687e01f 7387 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 147:30b64687e01f 7388 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 147:30b64687e01f 7389 #define EXTI_EMR_EM23 EXTI_EMR_MR23
<> 147:30b64687e01f 7390 #define EXTI_EMR_EM24 EXTI_EMR_MR24
<> 147:30b64687e01f 7391 #define EXTI_EMR_EM25 EXTI_EMR_MR25
<> 147:30b64687e01f 7392 #define EXTI_EMR_EM26 EXTI_EMR_MR26
<> 147:30b64687e01f 7393 #define EXTI_EMR_EM27 EXTI_EMR_MR27
<> 147:30b64687e01f 7394 #define EXTI_EMR_EM28 EXTI_EMR_MR28
<> 147:30b64687e01f 7395 #define EXTI_EMR_EM29 EXTI_EMR_MR29
<> 147:30b64687e01f 7396 #define EXTI_EMR_EM30 EXTI_EMR_MR30
<> 147:30b64687e01f 7397 #define EXTI_EMR_EM31 EXTI_EMR_MR31
<> 147:30b64687e01f 7398
<> 147:30b64687e01f 7399 /****************** Bit definition for EXTI_RTSR register *******************/
<> 147:30b64687e01f 7400 #define EXTI_RTSR_TR0_Pos (0U)
<> 147:30b64687e01f 7401 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7402 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
<> 147:30b64687e01f 7403 #define EXTI_RTSR_TR1_Pos (1U)
<> 147:30b64687e01f 7404 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7405 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
<> 147:30b64687e01f 7406 #define EXTI_RTSR_TR2_Pos (2U)
<> 147:30b64687e01f 7407 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7408 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
<> 147:30b64687e01f 7409 #define EXTI_RTSR_TR3_Pos (3U)
<> 147:30b64687e01f 7410 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7411 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
<> 147:30b64687e01f 7412 #define EXTI_RTSR_TR4_Pos (4U)
<> 147:30b64687e01f 7413 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7414 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
<> 147:30b64687e01f 7415 #define EXTI_RTSR_TR5_Pos (5U)
<> 147:30b64687e01f 7416 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7417 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
<> 147:30b64687e01f 7418 #define EXTI_RTSR_TR6_Pos (6U)
<> 147:30b64687e01f 7419 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 7420 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
<> 147:30b64687e01f 7421 #define EXTI_RTSR_TR7_Pos (7U)
<> 147:30b64687e01f 7422 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7423 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
<> 147:30b64687e01f 7424 #define EXTI_RTSR_TR8_Pos (8U)
<> 147:30b64687e01f 7425 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7426 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
<> 147:30b64687e01f 7427 #define EXTI_RTSR_TR9_Pos (9U)
<> 147:30b64687e01f 7428 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7429 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
<> 147:30b64687e01f 7430 #define EXTI_RTSR_TR10_Pos (10U)
<> 147:30b64687e01f 7431 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7432 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
<> 147:30b64687e01f 7433 #define EXTI_RTSR_TR11_Pos (11U)
<> 147:30b64687e01f 7434 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7435 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
<> 147:30b64687e01f 7436 #define EXTI_RTSR_TR12_Pos (12U)
<> 147:30b64687e01f 7437 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7438 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
<> 147:30b64687e01f 7439 #define EXTI_RTSR_TR13_Pos (13U)
<> 147:30b64687e01f 7440 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7441 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
<> 147:30b64687e01f 7442 #define EXTI_RTSR_TR14_Pos (14U)
<> 147:30b64687e01f 7443 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7444 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
<> 147:30b64687e01f 7445 #define EXTI_RTSR_TR15_Pos (15U)
<> 147:30b64687e01f 7446 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 7447 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
<> 147:30b64687e01f 7448 #define EXTI_RTSR_TR16_Pos (16U)
<> 147:30b64687e01f 7449 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 7450 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
<> 147:30b64687e01f 7451 #define EXTI_RTSR_TR17_Pos (17U)
<> 147:30b64687e01f 7452 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 7453 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
<> 147:30b64687e01f 7454 #define EXTI_RTSR_TR18_Pos (18U)
<> 147:30b64687e01f 7455 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 7456 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
<> 147:30b64687e01f 7457 #define EXTI_RTSR_TR19_Pos (19U)
<> 147:30b64687e01f 7458 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 7459 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
<> 147:30b64687e01f 7460 #define EXTI_RTSR_TR20_Pos (20U)
<> 147:30b64687e01f 7461 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 7462 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
<> 147:30b64687e01f 7463 #define EXTI_RTSR_TR21_Pos (21U)
<> 147:30b64687e01f 7464 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 7465 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
<> 147:30b64687e01f 7466 #define EXTI_RTSR_TR22_Pos (22U)
<> 147:30b64687e01f 7467 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 7468 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 147:30b64687e01f 7469 #define EXTI_RTSR_TR29_Pos (29U)
<> 147:30b64687e01f 7470 #define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 7471 #define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
<> 147:30b64687e01f 7472 #define EXTI_RTSR_TR30_Pos (30U)
<> 147:30b64687e01f 7473 #define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 7474 #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
<> 147:30b64687e01f 7475 #define EXTI_RTSR_TR31_Pos (31U)
<> 147:30b64687e01f 7476 #define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 7477 #define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
<> 147:30b64687e01f 7478
<> 147:30b64687e01f 7479 /* References Defines */
<> 147:30b64687e01f 7480 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
<> 147:30b64687e01f 7481 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
<> 147:30b64687e01f 7482 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
<> 147:30b64687e01f 7483 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
<> 147:30b64687e01f 7484 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
<> 147:30b64687e01f 7485 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
<> 147:30b64687e01f 7486 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
<> 147:30b64687e01f 7487 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
<> 147:30b64687e01f 7488 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
<> 147:30b64687e01f 7489 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
<> 147:30b64687e01f 7490 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
<> 147:30b64687e01f 7491 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
<> 147:30b64687e01f 7492 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
<> 147:30b64687e01f 7493 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
<> 147:30b64687e01f 7494 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
<> 147:30b64687e01f 7495 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
<> 147:30b64687e01f 7496 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
<> 147:30b64687e01f 7497 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
<> 147:30b64687e01f 7498 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
<> 147:30b64687e01f 7499 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
<> 147:30b64687e01f 7500 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
<> 147:30b64687e01f 7501 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
<> 147:30b64687e01f 7502 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
<> 147:30b64687e01f 7503 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29
<> 147:30b64687e01f 7504 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30
<> 147:30b64687e01f 7505 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
<> 147:30b64687e01f 7506
<> 147:30b64687e01f 7507 /****************** Bit definition for EXTI_FTSR register *******************/
<> 147:30b64687e01f 7508 #define EXTI_FTSR_TR0_Pos (0U)
<> 147:30b64687e01f 7509 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7510 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
<> 147:30b64687e01f 7511 #define EXTI_FTSR_TR1_Pos (1U)
<> 147:30b64687e01f 7512 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7513 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
<> 147:30b64687e01f 7514 #define EXTI_FTSR_TR2_Pos (2U)
<> 147:30b64687e01f 7515 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7516 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
<> 147:30b64687e01f 7517 #define EXTI_FTSR_TR3_Pos (3U)
<> 147:30b64687e01f 7518 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7519 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
<> 147:30b64687e01f 7520 #define EXTI_FTSR_TR4_Pos (4U)
<> 147:30b64687e01f 7521 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7522 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
<> 147:30b64687e01f 7523 #define EXTI_FTSR_TR5_Pos (5U)
<> 147:30b64687e01f 7524 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7525 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
<> 147:30b64687e01f 7526 #define EXTI_FTSR_TR6_Pos (6U)
<> 147:30b64687e01f 7527 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 7528 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
<> 147:30b64687e01f 7529 #define EXTI_FTSR_TR7_Pos (7U)
<> 147:30b64687e01f 7530 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7531 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
<> 147:30b64687e01f 7532 #define EXTI_FTSR_TR8_Pos (8U)
<> 147:30b64687e01f 7533 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7534 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
<> 147:30b64687e01f 7535 #define EXTI_FTSR_TR9_Pos (9U)
<> 147:30b64687e01f 7536 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7537 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
<> 147:30b64687e01f 7538 #define EXTI_FTSR_TR10_Pos (10U)
<> 147:30b64687e01f 7539 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7540 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
<> 147:30b64687e01f 7541 #define EXTI_FTSR_TR11_Pos (11U)
<> 147:30b64687e01f 7542 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7543 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
<> 147:30b64687e01f 7544 #define EXTI_FTSR_TR12_Pos (12U)
<> 147:30b64687e01f 7545 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7546 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
<> 147:30b64687e01f 7547 #define EXTI_FTSR_TR13_Pos (13U)
<> 147:30b64687e01f 7548 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7549 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
<> 147:30b64687e01f 7550 #define EXTI_FTSR_TR14_Pos (14U)
<> 147:30b64687e01f 7551 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7552 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
<> 147:30b64687e01f 7553 #define EXTI_FTSR_TR15_Pos (15U)
<> 147:30b64687e01f 7554 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 7555 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
<> 147:30b64687e01f 7556 #define EXTI_FTSR_TR16_Pos (16U)
<> 147:30b64687e01f 7557 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 7558 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
<> 147:30b64687e01f 7559 #define EXTI_FTSR_TR17_Pos (17U)
<> 147:30b64687e01f 7560 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 7561 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
<> 147:30b64687e01f 7562 #define EXTI_FTSR_TR18_Pos (18U)
<> 147:30b64687e01f 7563 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 7564 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
<> 147:30b64687e01f 7565 #define EXTI_FTSR_TR19_Pos (19U)
<> 147:30b64687e01f 7566 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 7567 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
<> 147:30b64687e01f 7568 #define EXTI_FTSR_TR20_Pos (20U)
<> 147:30b64687e01f 7569 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 7570 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
<> 147:30b64687e01f 7571 #define EXTI_FTSR_TR21_Pos (21U)
<> 147:30b64687e01f 7572 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 7573 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
<> 147:30b64687e01f 7574 #define EXTI_FTSR_TR22_Pos (22U)
<> 147:30b64687e01f 7575 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 7576 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 147:30b64687e01f 7577 #define EXTI_FTSR_TR29_Pos (29U)
<> 147:30b64687e01f 7578 #define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 7579 #define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
<> 147:30b64687e01f 7580 #define EXTI_FTSR_TR30_Pos (30U)
<> 147:30b64687e01f 7581 #define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 7582 #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
<> 147:30b64687e01f 7583 #define EXTI_FTSR_TR31_Pos (31U)
<> 147:30b64687e01f 7584 #define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 7585 #define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
<> 147:30b64687e01f 7586
<> 147:30b64687e01f 7587 /* References Defines */
<> 147:30b64687e01f 7588 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
<> 147:30b64687e01f 7589 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
<> 147:30b64687e01f 7590 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
<> 147:30b64687e01f 7591 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
<> 147:30b64687e01f 7592 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
<> 147:30b64687e01f 7593 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
<> 147:30b64687e01f 7594 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
<> 147:30b64687e01f 7595 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
<> 147:30b64687e01f 7596 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
<> 147:30b64687e01f 7597 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
<> 147:30b64687e01f 7598 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
<> 147:30b64687e01f 7599 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
<> 147:30b64687e01f 7600 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
<> 147:30b64687e01f 7601 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
<> 147:30b64687e01f 7602 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
<> 147:30b64687e01f 7603 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
<> 147:30b64687e01f 7604 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
<> 147:30b64687e01f 7605 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
<> 147:30b64687e01f 7606 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
<> 147:30b64687e01f 7607 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
<> 147:30b64687e01f 7608 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
<> 147:30b64687e01f 7609 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
<> 147:30b64687e01f 7610 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
<> 147:30b64687e01f 7611 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29
<> 147:30b64687e01f 7612 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30
<> 147:30b64687e01f 7613 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
<> 147:30b64687e01f 7614
<> 147:30b64687e01f 7615 /****************** Bit definition for EXTI_SWIER register ******************/
<> 147:30b64687e01f 7616 #define EXTI_SWIER_SWIER0_Pos (0U)
<> 147:30b64687e01f 7617 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7618 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
<> 147:30b64687e01f 7619 #define EXTI_SWIER_SWIER1_Pos (1U)
<> 147:30b64687e01f 7620 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7621 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
<> 147:30b64687e01f 7622 #define EXTI_SWIER_SWIER2_Pos (2U)
<> 147:30b64687e01f 7623 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7624 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
<> 147:30b64687e01f 7625 #define EXTI_SWIER_SWIER3_Pos (3U)
<> 147:30b64687e01f 7626 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7627 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
<> 147:30b64687e01f 7628 #define EXTI_SWIER_SWIER4_Pos (4U)
<> 147:30b64687e01f 7629 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7630 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
<> 147:30b64687e01f 7631 #define EXTI_SWIER_SWIER5_Pos (5U)
<> 147:30b64687e01f 7632 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7633 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
<> 147:30b64687e01f 7634 #define EXTI_SWIER_SWIER6_Pos (6U)
<> 147:30b64687e01f 7635 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 7636 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
<> 147:30b64687e01f 7637 #define EXTI_SWIER_SWIER7_Pos (7U)
<> 147:30b64687e01f 7638 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7639 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
<> 147:30b64687e01f 7640 #define EXTI_SWIER_SWIER8_Pos (8U)
<> 147:30b64687e01f 7641 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7642 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
<> 147:30b64687e01f 7643 #define EXTI_SWIER_SWIER9_Pos (9U)
<> 147:30b64687e01f 7644 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7645 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
<> 147:30b64687e01f 7646 #define EXTI_SWIER_SWIER10_Pos (10U)
<> 147:30b64687e01f 7647 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7648 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
<> 147:30b64687e01f 7649 #define EXTI_SWIER_SWIER11_Pos (11U)
<> 147:30b64687e01f 7650 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7651 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
<> 147:30b64687e01f 7652 #define EXTI_SWIER_SWIER12_Pos (12U)
<> 147:30b64687e01f 7653 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7654 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
<> 147:30b64687e01f 7655 #define EXTI_SWIER_SWIER13_Pos (13U)
<> 147:30b64687e01f 7656 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7657 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
<> 147:30b64687e01f 7658 #define EXTI_SWIER_SWIER14_Pos (14U)
<> 147:30b64687e01f 7659 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7660 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
<> 147:30b64687e01f 7661 #define EXTI_SWIER_SWIER15_Pos (15U)
<> 147:30b64687e01f 7662 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 7663 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
<> 147:30b64687e01f 7664 #define EXTI_SWIER_SWIER16_Pos (16U)
<> 147:30b64687e01f 7665 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 7666 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
<> 147:30b64687e01f 7667 #define EXTI_SWIER_SWIER17_Pos (17U)
<> 147:30b64687e01f 7668 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 7669 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
<> 147:30b64687e01f 7670 #define EXTI_SWIER_SWIER18_Pos (18U)
<> 147:30b64687e01f 7671 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 7672 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
<> 147:30b64687e01f 7673 #define EXTI_SWIER_SWIER19_Pos (19U)
<> 147:30b64687e01f 7674 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 7675 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
<> 147:30b64687e01f 7676 #define EXTI_SWIER_SWIER20_Pos (20U)
<> 147:30b64687e01f 7677 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 7678 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
<> 147:30b64687e01f 7679 #define EXTI_SWIER_SWIER21_Pos (21U)
<> 147:30b64687e01f 7680 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 7681 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
<> 147:30b64687e01f 7682 #define EXTI_SWIER_SWIER22_Pos (22U)
<> 147:30b64687e01f 7683 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 7684 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
<> 147:30b64687e01f 7685 #define EXTI_SWIER_SWIER29_Pos (29U)
<> 147:30b64687e01f 7686 #define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 7687 #define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
<> 147:30b64687e01f 7688 #define EXTI_SWIER_SWIER30_Pos (30U)
<> 147:30b64687e01f 7689 #define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 7690 #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
<> 147:30b64687e01f 7691 #define EXTI_SWIER_SWIER31_Pos (31U)
<> 147:30b64687e01f 7692 #define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 7693 #define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
<> 147:30b64687e01f 7694
<> 147:30b64687e01f 7695 /* References Defines */
<> 147:30b64687e01f 7696 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
<> 147:30b64687e01f 7697 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
<> 147:30b64687e01f 7698 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
<> 147:30b64687e01f 7699 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
<> 147:30b64687e01f 7700 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
<> 147:30b64687e01f 7701 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
<> 147:30b64687e01f 7702 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
<> 147:30b64687e01f 7703 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
<> 147:30b64687e01f 7704 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
<> 147:30b64687e01f 7705 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
<> 147:30b64687e01f 7706 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
<> 147:30b64687e01f 7707 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
<> 147:30b64687e01f 7708 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
<> 147:30b64687e01f 7709 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
<> 147:30b64687e01f 7710 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
<> 147:30b64687e01f 7711 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
<> 147:30b64687e01f 7712 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
<> 147:30b64687e01f 7713 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
<> 147:30b64687e01f 7714 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
<> 147:30b64687e01f 7715 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
<> 147:30b64687e01f 7716 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
<> 147:30b64687e01f 7717 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
<> 147:30b64687e01f 7718 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
<> 147:30b64687e01f 7719 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
<> 147:30b64687e01f 7720 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
<> 147:30b64687e01f 7721 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
<> 147:30b64687e01f 7722
<> 147:30b64687e01f 7723 /******************* Bit definition for EXTI_PR register ********************/
<> 147:30b64687e01f 7724 #define EXTI_PR_PR0_Pos (0U)
<> 147:30b64687e01f 7725 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7726 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
<> 147:30b64687e01f 7727 #define EXTI_PR_PR1_Pos (1U)
<> 147:30b64687e01f 7728 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7729 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
<> 147:30b64687e01f 7730 #define EXTI_PR_PR2_Pos (2U)
<> 147:30b64687e01f 7731 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7732 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
<> 147:30b64687e01f 7733 #define EXTI_PR_PR3_Pos (3U)
<> 147:30b64687e01f 7734 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7735 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
<> 147:30b64687e01f 7736 #define EXTI_PR_PR4_Pos (4U)
<> 147:30b64687e01f 7737 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7738 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
<> 147:30b64687e01f 7739 #define EXTI_PR_PR5_Pos (5U)
<> 147:30b64687e01f 7740 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7741 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
<> 147:30b64687e01f 7742 #define EXTI_PR_PR6_Pos (6U)
<> 147:30b64687e01f 7743 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 7744 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
<> 147:30b64687e01f 7745 #define EXTI_PR_PR7_Pos (7U)
<> 147:30b64687e01f 7746 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 7747 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
<> 147:30b64687e01f 7748 #define EXTI_PR_PR8_Pos (8U)
<> 147:30b64687e01f 7749 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 7750 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
<> 147:30b64687e01f 7751 #define EXTI_PR_PR9_Pos (9U)
<> 147:30b64687e01f 7752 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 7753 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
<> 147:30b64687e01f 7754 #define EXTI_PR_PR10_Pos (10U)
<> 147:30b64687e01f 7755 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 7756 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
<> 147:30b64687e01f 7757 #define EXTI_PR_PR11_Pos (11U)
<> 147:30b64687e01f 7758 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 7759 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
<> 147:30b64687e01f 7760 #define EXTI_PR_PR12_Pos (12U)
<> 147:30b64687e01f 7761 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 7762 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
<> 147:30b64687e01f 7763 #define EXTI_PR_PR13_Pos (13U)
<> 147:30b64687e01f 7764 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 7765 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
<> 147:30b64687e01f 7766 #define EXTI_PR_PR14_Pos (14U)
<> 147:30b64687e01f 7767 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 7768 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
<> 147:30b64687e01f 7769 #define EXTI_PR_PR15_Pos (15U)
<> 147:30b64687e01f 7770 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 7771 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
<> 147:30b64687e01f 7772 #define EXTI_PR_PR16_Pos (16U)
<> 147:30b64687e01f 7773 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 7774 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
<> 147:30b64687e01f 7775 #define EXTI_PR_PR17_Pos (17U)
<> 147:30b64687e01f 7776 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 7777 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
<> 147:30b64687e01f 7778 #define EXTI_PR_PR18_Pos (18U)
<> 147:30b64687e01f 7779 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 7780 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
<> 147:30b64687e01f 7781 #define EXTI_PR_PR19_Pos (19U)
<> 147:30b64687e01f 7782 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 7783 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
<> 147:30b64687e01f 7784 #define EXTI_PR_PR20_Pos (20U)
<> 147:30b64687e01f 7785 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 7786 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
<> 147:30b64687e01f 7787 #define EXTI_PR_PR21_Pos (21U)
<> 147:30b64687e01f 7788 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 7789 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
<> 147:30b64687e01f 7790 #define EXTI_PR_PR22_Pos (22U)
<> 147:30b64687e01f 7791 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 7792 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
<> 147:30b64687e01f 7793 #define EXTI_PR_PR29_Pos (29U)
<> 147:30b64687e01f 7794 #define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 7795 #define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
<> 147:30b64687e01f 7796 #define EXTI_PR_PR30_Pos (30U)
<> 147:30b64687e01f 7797 #define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 7798 #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
<> 147:30b64687e01f 7799 #define EXTI_PR_PR31_Pos (31U)
<> 147:30b64687e01f 7800 #define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 7801 #define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
<> 147:30b64687e01f 7802
<> 147:30b64687e01f 7803 /* References Defines */
<> 147:30b64687e01f 7804 #define EXTI_PR_PIF0 EXTI_PR_PR0
<> 147:30b64687e01f 7805 #define EXTI_PR_PIF1 EXTI_PR_PR1
<> 147:30b64687e01f 7806 #define EXTI_PR_PIF2 EXTI_PR_PR2
<> 147:30b64687e01f 7807 #define EXTI_PR_PIF3 EXTI_PR_PR3
<> 147:30b64687e01f 7808 #define EXTI_PR_PIF4 EXTI_PR_PR4
<> 147:30b64687e01f 7809 #define EXTI_PR_PIF5 EXTI_PR_PR5
<> 147:30b64687e01f 7810 #define EXTI_PR_PIF6 EXTI_PR_PR6
<> 147:30b64687e01f 7811 #define EXTI_PR_PIF7 EXTI_PR_PR7
<> 147:30b64687e01f 7812 #define EXTI_PR_PIF8 EXTI_PR_PR8
<> 147:30b64687e01f 7813 #define EXTI_PR_PIF9 EXTI_PR_PR9
<> 147:30b64687e01f 7814 #define EXTI_PR_PIF10 EXTI_PR_PR10
<> 147:30b64687e01f 7815 #define EXTI_PR_PIF11 EXTI_PR_PR11
<> 147:30b64687e01f 7816 #define EXTI_PR_PIF12 EXTI_PR_PR12
<> 147:30b64687e01f 7817 #define EXTI_PR_PIF13 EXTI_PR_PR13
<> 147:30b64687e01f 7818 #define EXTI_PR_PIF14 EXTI_PR_PR14
<> 147:30b64687e01f 7819 #define EXTI_PR_PIF15 EXTI_PR_PR15
<> 147:30b64687e01f 7820 #define EXTI_PR_PIF16 EXTI_PR_PR16
<> 147:30b64687e01f 7821 #define EXTI_PR_PIF17 EXTI_PR_PR17
<> 147:30b64687e01f 7822 #define EXTI_PR_PIF18 EXTI_PR_PR18
<> 147:30b64687e01f 7823 #define EXTI_PR_PIF19 EXTI_PR_PR19
<> 147:30b64687e01f 7824 #define EXTI_PR_PIF20 EXTI_PR_PR20
<> 147:30b64687e01f 7825 #define EXTI_PR_PIF21 EXTI_PR_PR21
<> 147:30b64687e01f 7826 #define EXTI_PR_PIF22 EXTI_PR_PR22
<> 147:30b64687e01f 7827 #define EXTI_PR_PIF29 EXTI_PR_PR29
<> 147:30b64687e01f 7828 #define EXTI_PR_PIF30 EXTI_PR_PR30
<> 147:30b64687e01f 7829 #define EXTI_PR_PIF31 EXTI_PR_PR31
<> 147:30b64687e01f 7830
<> 147:30b64687e01f 7831 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
<> 147:30b64687e01f 7832
<> 147:30b64687e01f 7833 /******************* Bit definition for EXTI_IMR2 register ******************/
<> 147:30b64687e01f 7834 #define EXTI_IMR2_MR32_Pos (0U)
<> 147:30b64687e01f 7835 #define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7836 #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
<> 147:30b64687e01f 7837 #define EXTI_IMR2_MR33_Pos (1U)
<> 147:30b64687e01f 7838 #define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7839 #define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
<> 147:30b64687e01f 7840 #define EXTI_IMR2_MR34_Pos (2U)
<> 147:30b64687e01f 7841 #define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7842 #define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
<> 147:30b64687e01f 7843 #define EXTI_IMR2_MR35_Pos (3U)
<> 147:30b64687e01f 7844 #define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7845 #define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
<> 147:30b64687e01f 7846
<> 147:30b64687e01f 7847 /* References Defines */
<> 147:30b64687e01f 7848 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32
<> 147:30b64687e01f 7849 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33
<> 147:30b64687e01f 7850 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
<> 147:30b64687e01f 7851 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
<> 147:30b64687e01f 7852
<> 147:30b64687e01f 7853 #define EXTI_IMR2_IM_Pos (0U)
<> 147:30b64687e01f 7854 #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 7855 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
<> 147:30b64687e01f 7856
<> 147:30b64687e01f 7857 /******************* Bit definition for EXTI_EMR2 ****************************/
<> 147:30b64687e01f 7858 #define EXTI_EMR2_MR32_Pos (0U)
<> 147:30b64687e01f 7859 #define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7860 #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
<> 147:30b64687e01f 7861 #define EXTI_EMR2_MR33_Pos (1U)
<> 147:30b64687e01f 7862 #define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7863 #define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
<> 147:30b64687e01f 7864 #define EXTI_EMR2_MR34_Pos (2U)
<> 147:30b64687e01f 7865 #define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7866 #define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
<> 147:30b64687e01f 7867 #define EXTI_EMR2_MR35_Pos (3U)
<> 147:30b64687e01f 7868 #define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7869 #define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
<> 147:30b64687e01f 7870
<> 147:30b64687e01f 7871 /* References Defines */
<> 147:30b64687e01f 7872 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32
<> 147:30b64687e01f 7873 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33
<> 147:30b64687e01f 7874 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
<> 147:30b64687e01f 7875 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
<> 147:30b64687e01f 7876
<> 147:30b64687e01f 7877 /****************** Bit definition for EXTI_RTSR2 register ********************/
<> 147:30b64687e01f 7878 #define EXTI_RTSR2_TR32_Pos (0U)
<> 147:30b64687e01f 7879 #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7880 #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
<> 147:30b64687e01f 7881 #define EXTI_RTSR2_TR33_Pos (1U)
<> 147:30b64687e01f 7882 #define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7883 #define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
<> 147:30b64687e01f 7884
<> 147:30b64687e01f 7885 /* References Defines */
<> 147:30b64687e01f 7886 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
<> 147:30b64687e01f 7887 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
<> 147:30b64687e01f 7888
<> 147:30b64687e01f 7889 /****************** Bit definition for EXTI_FTSR2 register ******************/
<> 147:30b64687e01f 7890 #define EXTI_FTSR2_TR32_Pos (0U)
<> 147:30b64687e01f 7891 #define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7892 #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
<> 147:30b64687e01f 7893 #define EXTI_FTSR2_TR33_Pos (1U)
<> 147:30b64687e01f 7894 #define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7895 #define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
<> 147:30b64687e01f 7896
<> 147:30b64687e01f 7897 /* References Defines */
<> 147:30b64687e01f 7898 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
<> 147:30b64687e01f 7899 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
<> 147:30b64687e01f 7900
<> 147:30b64687e01f 7901 /****************** Bit definition for EXTI_SWIER2 register *****************/
<> 147:30b64687e01f 7902 #define EXTI_SWIER2_SWIER32_Pos (0U)
<> 147:30b64687e01f 7903 #define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7904 #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
<> 147:30b64687e01f 7905 #define EXTI_SWIER2_SWIER33_Pos (1U)
<> 147:30b64687e01f 7906 #define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7907 #define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
<> 147:30b64687e01f 7908
<> 147:30b64687e01f 7909 /* References Defines */
<> 147:30b64687e01f 7910 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
<> 147:30b64687e01f 7911 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
<> 147:30b64687e01f 7912
<> 147:30b64687e01f 7913 /******************* Bit definition for EXTI_PR2 register *******************/
<> 147:30b64687e01f 7914 #define EXTI_PR2_PR32_Pos (0U)
<> 147:30b64687e01f 7915 #define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7916 #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
<> 147:30b64687e01f 7917 #define EXTI_PR2_PR33_Pos (1U)
<> 147:30b64687e01f 7918 #define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7919 #define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
<> 147:30b64687e01f 7920
<> 147:30b64687e01f 7921 /* References Defines */
<> 147:30b64687e01f 7922 #define EXTI_PR2_PIF32 EXTI_PR2_PR32
<> 147:30b64687e01f 7923 #define EXTI_PR2_PIF33 EXTI_PR2_PR33
<> 147:30b64687e01f 7924
<> 147:30b64687e01f 7925 /******************************************************************************/
<> 147:30b64687e01f 7926 /* */
<> 147:30b64687e01f 7927 /* FLASH */
<> 147:30b64687e01f 7928 /* */
<> 147:30b64687e01f 7929 /******************************************************************************/
<> 147:30b64687e01f 7930 /******************* Bit definition for FLASH_ACR register ******************/
<> 147:30b64687e01f 7931 #define FLASH_ACR_LATENCY_Pos (0U)
<> 147:30b64687e01f 7932 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
<> 147:30b64687e01f 7933 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
<> 147:30b64687e01f 7934 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7935 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7936 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7937
<> 147:30b64687e01f 7938 #define FLASH_ACR_HLFCYA_Pos (3U)
<> 147:30b64687e01f 7939 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 7940 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
<> 147:30b64687e01f 7941 #define FLASH_ACR_PRFTBE_Pos (4U)
<> 147:30b64687e01f 7942 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7943 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
<> 147:30b64687e01f 7944 #define FLASH_ACR_PRFTBS_Pos (5U)
<> 147:30b64687e01f 7945 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7946 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
<> 147:30b64687e01f 7947
<> 147:30b64687e01f 7948 /****************** Bit definition for FLASH_KEYR register ******************/
<> 147:30b64687e01f 7949 #define FLASH_KEYR_FKEYR_Pos (0U)
<> 147:30b64687e01f 7950 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 7951 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
<> 147:30b64687e01f 7952
<> 147:30b64687e01f 7953 #define RDP_KEY_Pos (0U)
<> 147:30b64687e01f 7954 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
<> 147:30b64687e01f 7955 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
<> 147:30b64687e01f 7956 #define FLASH_KEY1_Pos (0U)
<> 147:30b64687e01f 7957 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
<> 147:30b64687e01f 7958 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
<> 147:30b64687e01f 7959 #define FLASH_KEY2_Pos (0U)
<> 147:30b64687e01f 7960 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
<> 147:30b64687e01f 7961 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
<> 147:30b64687e01f 7962
<> 147:30b64687e01f 7963 /***************** Bit definition for FLASH_OPTKEYR register ****************/
<> 147:30b64687e01f 7964 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
<> 147:30b64687e01f 7965 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 7966 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
<> 147:30b64687e01f 7967
<> 147:30b64687e01f 7968 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
<> 147:30b64687e01f 7969 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
<> 147:30b64687e01f 7970
<> 147:30b64687e01f 7971 /****************** Bit definition for FLASH_SR register *******************/
<> 147:30b64687e01f 7972 #define FLASH_SR_BSY_Pos (0U)
<> 147:30b64687e01f 7973 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7974 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
<> 147:30b64687e01f 7975 #define FLASH_SR_PGERR_Pos (2U)
<> 147:30b64687e01f 7976 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7977 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
<> 147:30b64687e01f 7978 #define FLASH_SR_WRPERR_Pos (4U)
<> 147:30b64687e01f 7979 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7980 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write Protection Error */
<> 147:30b64687e01f 7981 #define FLASH_SR_EOP_Pos (5U)
<> 147:30b64687e01f 7982 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 7983 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
<> 147:30b64687e01f 7984
<> 147:30b64687e01f 7985 /******************* Bit definition for FLASH_CR register *******************/
<> 147:30b64687e01f 7986 #define FLASH_CR_PG_Pos (0U)
<> 147:30b64687e01f 7987 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 7988 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
<> 147:30b64687e01f 7989 #define FLASH_CR_PER_Pos (1U)
<> 147:30b64687e01f 7990 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 7991 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
<> 147:30b64687e01f 7992 #define FLASH_CR_MER_Pos (2U)
<> 147:30b64687e01f 7993 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 7994 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
<> 147:30b64687e01f 7995 #define FLASH_CR_OPTPG_Pos (4U)
<> 147:30b64687e01f 7996 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 7997 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
<> 147:30b64687e01f 7998 #define FLASH_CR_OPTER_Pos (5U)
<> 147:30b64687e01f 7999 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8000 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
<> 147:30b64687e01f 8001 #define FLASH_CR_STRT_Pos (6U)
<> 147:30b64687e01f 8002 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8003 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
<> 147:30b64687e01f 8004 #define FLASH_CR_LOCK_Pos (7U)
<> 147:30b64687e01f 8005 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8006 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
<> 147:30b64687e01f 8007 #define FLASH_CR_OPTWRE_Pos (9U)
<> 147:30b64687e01f 8008 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8009 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
<> 147:30b64687e01f 8010 #define FLASH_CR_ERRIE_Pos (10U)
<> 147:30b64687e01f 8011 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8012 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
<> 147:30b64687e01f 8013 #define FLASH_CR_EOPIE_Pos (12U)
<> 147:30b64687e01f 8014 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8015 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
<> 147:30b64687e01f 8016 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
<> 147:30b64687e01f 8017 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8018 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< OptionBytes Loader Launch */
<> 147:30b64687e01f 8019
<> 147:30b64687e01f 8020 /******************* Bit definition for FLASH_AR register *******************/
<> 147:30b64687e01f 8021 #define FLASH_AR_FAR_Pos (0U)
<> 147:30b64687e01f 8022 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 8023 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
<> 147:30b64687e01f 8024
<> 147:30b64687e01f 8025 /****************** Bit definition for FLASH_OBR register *******************/
<> 147:30b64687e01f 8026 #define FLASH_OBR_OPTERR_Pos (0U)
<> 147:30b64687e01f 8027 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8028 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
<> 147:30b64687e01f 8029 #define FLASH_OBR_RDPRT_Pos (1U)
<> 147:30b64687e01f 8030 #define FLASH_OBR_RDPRT_Msk (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
<> 147:30b64687e01f 8031 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
<> 147:30b64687e01f 8032 #define FLASH_OBR_RDPRT_1 (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8033 #define FLASH_OBR_RDPRT_2 (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
<> 147:30b64687e01f 8034
<> 147:30b64687e01f 8035 #define FLASH_OBR_USER_Pos (8U)
<> 147:30b64687e01f 8036 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
<> 147:30b64687e01f 8037 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
<> 147:30b64687e01f 8038 #define FLASH_OBR_IWDG_SW_Pos (8U)
<> 147:30b64687e01f 8039 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8040 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
<> 147:30b64687e01f 8041 #define FLASH_OBR_nRST_STOP_Pos (9U)
<> 147:30b64687e01f 8042 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8043 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
<> 147:30b64687e01f 8044 #define FLASH_OBR_nRST_STDBY_Pos (10U)
<> 147:30b64687e01f 8045 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8046 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
<> 147:30b64687e01f 8047 #define FLASH_OBR_nBOOT1_Pos (12U)
<> 147:30b64687e01f 8048 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8049 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
<> 147:30b64687e01f 8050 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
<> 147:30b64687e01f 8051 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8052 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA_MONITOR */
<> 147:30b64687e01f 8053 #define FLASH_OBR_SRAM_PE_Pos (14U)
<> 147:30b64687e01f 8054 #define FLASH_OBR_SRAM_PE_Msk (0x1U << FLASH_OBR_SRAM_PE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8055 #define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk /*!< SRAM_PE */
<> 147:30b64687e01f 8056 #define FLASH_OBR_DATA0_Pos (16U)
<> 147:30b64687e01f 8057 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 8058 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
<> 147:30b64687e01f 8059 #define FLASH_OBR_DATA1_Pos (24U)
<> 147:30b64687e01f 8060 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 8061 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
<> 147:30b64687e01f 8062
<> 147:30b64687e01f 8063 /* Legacy defines */
<> 147:30b64687e01f 8064 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
<> 147:30b64687e01f 8065
<> 147:30b64687e01f 8066 /****************** Bit definition for FLASH_WRPR register ******************/
<> 147:30b64687e01f 8067 #define FLASH_WRPR_WRP_Pos (0U)
<> 147:30b64687e01f 8068 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 8069 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
<> 147:30b64687e01f 8070
<> 147:30b64687e01f 8071 /*----------------------------------------------------------------------------*/
<> 147:30b64687e01f 8072
<> 147:30b64687e01f 8073 /****************** Bit definition for OB_RDP register **********************/
<> 147:30b64687e01f 8074 #define OB_RDP_RDP_Pos (0U)
<> 147:30b64687e01f 8075 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 8076 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
<> 147:30b64687e01f 8077 #define OB_RDP_nRDP_Pos (8U)
<> 147:30b64687e01f 8078 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8079 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
<> 147:30b64687e01f 8080
<> 147:30b64687e01f 8081 /****************** Bit definition for OB_USER register *********************/
<> 147:30b64687e01f 8082 #define OB_USER_USER_Pos (16U)
<> 147:30b64687e01f 8083 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 8084 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
<> 147:30b64687e01f 8085 #define OB_USER_nUSER_Pos (24U)
<> 147:30b64687e01f 8086 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 8087 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
<> 147:30b64687e01f 8088
<> 147:30b64687e01f 8089 /****************** Bit definition for FLASH_WRP0 register ******************/
<> 147:30b64687e01f 8090 #define OB_WRP0_WRP0_Pos (0U)
<> 147:30b64687e01f 8091 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 8092 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
<> 147:30b64687e01f 8093 #define OB_WRP0_nWRP0_Pos (8U)
<> 147:30b64687e01f 8094 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8095 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
<> 147:30b64687e01f 8096
<> 147:30b64687e01f 8097 /****************** Bit definition for FLASH_WRP1 register ******************/
<> 147:30b64687e01f 8098 #define OB_WRP1_WRP1_Pos (16U)
<> 147:30b64687e01f 8099 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 8100 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
<> 147:30b64687e01f 8101 #define OB_WRP1_nWRP1_Pos (24U)
<> 147:30b64687e01f 8102 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 8103 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
<> 147:30b64687e01f 8104
<> 147:30b64687e01f 8105 /****************** Bit definition for FLASH_WRP2 register ******************/
<> 147:30b64687e01f 8106 #define OB_WRP2_WRP2_Pos (0U)
<> 147:30b64687e01f 8107 #define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 8108 #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
<> 147:30b64687e01f 8109 #define OB_WRP2_nWRP2_Pos (8U)
<> 147:30b64687e01f 8110 #define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8111 #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
<> 147:30b64687e01f 8112
<> 147:30b64687e01f 8113 /****************** Bit definition for FLASH_WRP3 register ******************/
<> 147:30b64687e01f 8114 #define OB_WRP3_WRP3_Pos (16U)
<> 147:30b64687e01f 8115 #define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 8116 #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
<> 147:30b64687e01f 8117 #define OB_WRP3_nWRP3_Pos (24U)
<> 147:30b64687e01f 8118 #define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 8119 #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
<> 147:30b64687e01f 8120
<> 147:30b64687e01f 8121 /******************************************************************************/
<> 147:30b64687e01f 8122 /* */
<> 147:30b64687e01f 8123 /* Flexible Memory Controller */
<> 147:30b64687e01f 8124 /* */
<> 147:30b64687e01f 8125 /******************************************************************************/
<> 147:30b64687e01f 8126 /****************** Bit definition for FMC_BCRx register *******************/
<> 147:30b64687e01f 8127 #define FMC_BCRx_MBKEN_Pos (0U)
<> 147:30b64687e01f 8128 #define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8129 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
<> 147:30b64687e01f 8130 #define FMC_BCRx_MUXEN_Pos (1U)
<> 147:30b64687e01f 8131 #define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8132 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 8133
<> 147:30b64687e01f 8134 #define FMC_BCRx_MTYP_Pos (2U)
<> 147:30b64687e01f 8135 #define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 8136 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 8137 #define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8138 #define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8139
<> 147:30b64687e01f 8140 #define FMC_BCRx_MWID_Pos (4U)
<> 147:30b64687e01f 8141 #define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 8142 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 8143 #define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8144 #define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8145
<> 147:30b64687e01f 8146 #define FMC_BCRx_FACCEN_Pos (6U)
<> 147:30b64687e01f 8147 #define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8148 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
<> 147:30b64687e01f 8149 #define FMC_BCRx_BURSTEN_Pos (8U)
<> 147:30b64687e01f 8150 #define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8151 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
<> 147:30b64687e01f 8152 #define FMC_BCRx_WAITPOL_Pos (9U)
<> 147:30b64687e01f 8153 #define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8154 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 147:30b64687e01f 8155 #define FMC_BCRx_WRAPMOD_Pos (10U)
<> 147:30b64687e01f 8156 #define FMC_BCRx_WRAPMOD_Msk (0x1U << FMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8157 #define FMC_BCRx_WRAPMOD FMC_BCRx_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 147:30b64687e01f 8158 #define FMC_BCRx_WAITCFG_Pos (11U)
<> 147:30b64687e01f 8159 #define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8160 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
<> 147:30b64687e01f 8161 #define FMC_BCRx_WREN_Pos (12U)
<> 147:30b64687e01f 8162 #define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8163 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
<> 147:30b64687e01f 8164 #define FMC_BCRx_WAITEN_Pos (13U)
<> 147:30b64687e01f 8165 #define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8166 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
<> 147:30b64687e01f 8167 #define FMC_BCRx_EXTMOD_Pos (14U)
<> 147:30b64687e01f 8168 #define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8169 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
<> 147:30b64687e01f 8170 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
<> 147:30b64687e01f 8171 #define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8172 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 147:30b64687e01f 8173 #define FMC_BCRx_CBURSTRW_Pos (19U)
<> 147:30b64687e01f 8174 #define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8175 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
<> 147:30b64687e01f 8176
<> 147:30b64687e01f 8177 /****************** Bit definition for FMC_BCR1 register *******************/
<> 147:30b64687e01f 8178 #define FMC_BCR1_MBKEN_Pos (0U)
<> 147:30b64687e01f 8179 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8180 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
<> 147:30b64687e01f 8181 #define FMC_BCR1_MUXEN_Pos (1U)
<> 147:30b64687e01f 8182 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8183 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 8184
<> 147:30b64687e01f 8185 #define FMC_BCR1_MTYP_Pos (2U)
<> 147:30b64687e01f 8186 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 8187 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 8188 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8189 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8190
<> 147:30b64687e01f 8191 #define FMC_BCR1_MWID_Pos (4U)
<> 147:30b64687e01f 8192 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 8193 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 8194 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8195 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8196
<> 147:30b64687e01f 8197 #define FMC_BCR1_FACCEN_Pos (6U)
<> 147:30b64687e01f 8198 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8199 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
<> 147:30b64687e01f 8200 #define FMC_BCR1_BURSTEN_Pos (8U)
<> 147:30b64687e01f 8201 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8202 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
<> 147:30b64687e01f 8203 #define FMC_BCR1_WAITPOL_Pos (9U)
<> 147:30b64687e01f 8204 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8205 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 147:30b64687e01f 8206 #define FMC_BCR1_WRAPMOD_Pos (10U)
<> 147:30b64687e01f 8207 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8208 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 147:30b64687e01f 8209 #define FMC_BCR1_WAITCFG_Pos (11U)
<> 147:30b64687e01f 8210 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8211 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
<> 147:30b64687e01f 8212 #define FMC_BCR1_WREN_Pos (12U)
<> 147:30b64687e01f 8213 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8214 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
<> 147:30b64687e01f 8215 #define FMC_BCR1_WAITEN_Pos (13U)
<> 147:30b64687e01f 8216 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8217 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
<> 147:30b64687e01f 8218 #define FMC_BCR1_EXTMOD_Pos (14U)
<> 147:30b64687e01f 8219 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8220 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
<> 147:30b64687e01f 8221 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
<> 147:30b64687e01f 8222 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8223 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 147:30b64687e01f 8224 #define FMC_BCR1_CBURSTRW_Pos (19U)
<> 147:30b64687e01f 8225 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8226 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
<> 147:30b64687e01f 8227 #define FMC_BCR1_CCLKEN_Pos (20U)
<> 147:30b64687e01f 8228 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8229 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
<> 147:30b64687e01f 8230
<> 147:30b64687e01f 8231 /****************** Bit definition for FMC_BCR2 register *******************/
<> 147:30b64687e01f 8232 #define FMC_BCR2_MBKEN_Pos (0U)
<> 147:30b64687e01f 8233 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8234 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
<> 147:30b64687e01f 8235 #define FMC_BCR2_MUXEN_Pos (1U)
<> 147:30b64687e01f 8236 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8237 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 8238
<> 147:30b64687e01f 8239 #define FMC_BCR2_MTYP_Pos (2U)
<> 147:30b64687e01f 8240 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 8241 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 8242 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8243 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8244
<> 147:30b64687e01f 8245 #define FMC_BCR2_MWID_Pos (4U)
<> 147:30b64687e01f 8246 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 8247 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 8248 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8249 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8250
<> 147:30b64687e01f 8251 #define FMC_BCR2_FACCEN_Pos (6U)
<> 147:30b64687e01f 8252 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8253 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
<> 147:30b64687e01f 8254 #define FMC_BCR2_BURSTEN_Pos (8U)
<> 147:30b64687e01f 8255 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8256 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
<> 147:30b64687e01f 8257 #define FMC_BCR2_WAITPOL_Pos (9U)
<> 147:30b64687e01f 8258 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8259 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 147:30b64687e01f 8260 #define FMC_BCR2_WRAPMOD_Pos (10U)
<> 147:30b64687e01f 8261 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8262 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 147:30b64687e01f 8263 #define FMC_BCR2_WAITCFG_Pos (11U)
<> 147:30b64687e01f 8264 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8265 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
<> 147:30b64687e01f 8266 #define FMC_BCR2_WREN_Pos (12U)
<> 147:30b64687e01f 8267 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8268 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
<> 147:30b64687e01f 8269 #define FMC_BCR2_WAITEN_Pos (13U)
<> 147:30b64687e01f 8270 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8271 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
<> 147:30b64687e01f 8272 #define FMC_BCR2_EXTMOD_Pos (14U)
<> 147:30b64687e01f 8273 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8274 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
<> 147:30b64687e01f 8275 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
<> 147:30b64687e01f 8276 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8277 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 147:30b64687e01f 8278 #define FMC_BCR2_CBURSTRW_Pos (19U)
<> 147:30b64687e01f 8279 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8280 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
<> 147:30b64687e01f 8281
<> 147:30b64687e01f 8282 /****************** Bit definition for FMC_BCR3 register *******************/
<> 147:30b64687e01f 8283 #define FMC_BCR3_MBKEN_Pos (0U)
<> 147:30b64687e01f 8284 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8285 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
<> 147:30b64687e01f 8286 #define FMC_BCR3_MUXEN_Pos (1U)
<> 147:30b64687e01f 8287 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8288 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 8289
<> 147:30b64687e01f 8290 #define FMC_BCR3_MTYP_Pos (2U)
<> 147:30b64687e01f 8291 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 8292 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 8293 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8294 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8295
<> 147:30b64687e01f 8296 #define FMC_BCR3_MWID_Pos (4U)
<> 147:30b64687e01f 8297 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 8298 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 8299 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8300 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8301
<> 147:30b64687e01f 8302 #define FMC_BCR3_FACCEN_Pos (6U)
<> 147:30b64687e01f 8303 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8304 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
<> 147:30b64687e01f 8305 #define FMC_BCR3_BURSTEN_Pos (8U)
<> 147:30b64687e01f 8306 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8307 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
<> 147:30b64687e01f 8308 #define FMC_BCR3_WAITPOL_Pos (9U)
<> 147:30b64687e01f 8309 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8310 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 147:30b64687e01f 8311 #define FMC_BCR3_WRAPMOD_Pos (10U)
<> 147:30b64687e01f 8312 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8313 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 147:30b64687e01f 8314 #define FMC_BCR3_WAITCFG_Pos (11U)
<> 147:30b64687e01f 8315 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8316 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
<> 147:30b64687e01f 8317 #define FMC_BCR3_WREN_Pos (12U)
<> 147:30b64687e01f 8318 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8319 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
<> 147:30b64687e01f 8320 #define FMC_BCR3_WAITEN_Pos (13U)
<> 147:30b64687e01f 8321 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8322 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
<> 147:30b64687e01f 8323 #define FMC_BCR3_EXTMOD_Pos (14U)
<> 147:30b64687e01f 8324 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8325 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
<> 147:30b64687e01f 8326 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
<> 147:30b64687e01f 8327 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8328 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 147:30b64687e01f 8329 #define FMC_BCR3_CBURSTRW_Pos (19U)
<> 147:30b64687e01f 8330 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8331 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
<> 147:30b64687e01f 8332
<> 147:30b64687e01f 8333 /****************** Bit definition for FMC_BCR4 register *******************/
<> 147:30b64687e01f 8334 #define FMC_BCR4_MBKEN_Pos (0U)
<> 147:30b64687e01f 8335 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8336 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
<> 147:30b64687e01f 8337 #define FMC_BCR4_MUXEN_Pos (1U)
<> 147:30b64687e01f 8338 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8339 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 8340
<> 147:30b64687e01f 8341 #define FMC_BCR4_MTYP_Pos (2U)
<> 147:30b64687e01f 8342 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 8343 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 8344 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8345 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8346
<> 147:30b64687e01f 8347 #define FMC_BCR4_MWID_Pos (4U)
<> 147:30b64687e01f 8348 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 8349 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 8350 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8351 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8352
<> 147:30b64687e01f 8353 #define FMC_BCR4_FACCEN_Pos (6U)
<> 147:30b64687e01f 8354 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8355 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
<> 147:30b64687e01f 8356 #define FMC_BCR4_BURSTEN_Pos (8U)
<> 147:30b64687e01f 8357 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8358 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
<> 147:30b64687e01f 8359 #define FMC_BCR4_WAITPOL_Pos (9U)
<> 147:30b64687e01f 8360 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8361 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 147:30b64687e01f 8362 #define FMC_BCR4_WRAPMOD_Pos (10U)
<> 147:30b64687e01f 8363 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8364 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 147:30b64687e01f 8365 #define FMC_BCR4_WAITCFG_Pos (11U)
<> 147:30b64687e01f 8366 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8367 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
<> 147:30b64687e01f 8368 #define FMC_BCR4_WREN_Pos (12U)
<> 147:30b64687e01f 8369 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8370 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
<> 147:30b64687e01f 8371 #define FMC_BCR4_WAITEN_Pos (13U)
<> 147:30b64687e01f 8372 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8373 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
<> 147:30b64687e01f 8374 #define FMC_BCR4_EXTMOD_Pos (14U)
<> 147:30b64687e01f 8375 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8376 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
<> 147:30b64687e01f 8377 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
<> 147:30b64687e01f 8378 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8379 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 147:30b64687e01f 8380 #define FMC_BCR4_CBURSTRW_Pos (19U)
<> 147:30b64687e01f 8381 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8382 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
<> 147:30b64687e01f 8383
<> 147:30b64687e01f 8384 /****************** Bit definition for FMC_BTRx register ******************/
<> 147:30b64687e01f 8385 #define FMC_BTRx_ADDSET_Pos (0U)
<> 147:30b64687e01f 8386 #define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8387 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8388 #define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8389 #define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8390 #define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8391 #define FMC_BTR_ADDSET_3 (0x00000008U) /*!<Bit 3 */
<> 147:30b64687e01f 8392
<> 147:30b64687e01f 8393 #define FMC_BTRx_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8394 #define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8395 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8396 #define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8397 #define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8398 #define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8399 #define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8400
<> 147:30b64687e01f 8401 #define FMC_BTRx_DATAST_Pos (8U)
<> 147:30b64687e01f 8402 #define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8403 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8404 #define FMC_BTR_DATAST_0 (0x00000100U) /*!<Bit 0 */
<> 147:30b64687e01f 8405 #define FMC_BTRx_DATAST_1 (0x00000200U) /*!<Bit 1 */
<> 147:30b64687e01f 8406 #define FMC_BTRx_DATAST_2 (0x00000400U) /*!<Bit 2 */
<> 147:30b64687e01f 8407 #define FMC_BTRx_DATAST_3 (0x00000800U) /*!<Bit 3 */
<> 147:30b64687e01f 8408 #define FMC_BTRx_DATAST_4 (0x00001000U) /*!<Bit 4 */
<> 147:30b64687e01f 8409 #define FMC_BTRx_DATAST_5 (0x00002000U) /*!<Bit 5 */
<> 147:30b64687e01f 8410 #define FMC_BTRx_DATAST_6 (0x00004000U) /*!<Bit 6 */
<> 147:30b64687e01f 8411 #define FMC_BTRx_DATAST_7 (0x00008000U) /*!<Bit 7 */
<> 147:30b64687e01f 8412
<> 147:30b64687e01f 8413 #define FMC_BTRx_BUSTURN_Pos (16U)
<> 147:30b64687e01f 8414 #define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 8415 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 8416 #define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 8417 #define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 8418 #define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 8419 #define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8420
<> 147:30b64687e01f 8421 #define FMC_BTRx_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8422 #define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8423 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8424 #define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8425 #define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8426 #define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8427 #define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8428
<> 147:30b64687e01f 8429 #define FMC_BTRx_DATLAT_Pos (24U)
<> 147:30b64687e01f 8430 #define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8431 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8432 #define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8433 #define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8434 #define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8435 #define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8436
<> 147:30b64687e01f 8437 #define FMC_BTRx_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8438 #define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8439 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8440 #define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8441 #define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8442
<> 147:30b64687e01f 8443 /****************** Bit definition for FMC_BTR1 register ******************/
<> 147:30b64687e01f 8444 #define FMC_BTR1_ADDSET_Pos (0U)
<> 147:30b64687e01f 8445 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8446 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8447 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8448 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8449 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8450 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8451
<> 147:30b64687e01f 8452 #define FMC_BTR1_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8453 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8454 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8455 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8456 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8457 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8458 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8459
<> 147:30b64687e01f 8460 #define FMC_BTR1_DATAST_Pos (8U)
<> 147:30b64687e01f 8461 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8462 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8463 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8464 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8465 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8466 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8467 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8468 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8469 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8470 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8471
<> 147:30b64687e01f 8472 #define FMC_BTR1_BUSTURN_Pos (16U)
<> 147:30b64687e01f 8473 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 8474 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 8475 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 8476 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 8477 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 8478 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8479
<> 147:30b64687e01f 8480 #define FMC_BTR1_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8481 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8482 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8483 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8484 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8485 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8486 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8487
<> 147:30b64687e01f 8488 #define FMC_BTR1_DATLAT_Pos (24U)
<> 147:30b64687e01f 8489 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8490 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8491 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8492 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8493 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8494 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8495
<> 147:30b64687e01f 8496 #define FMC_BTR1_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8497 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8498 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8499 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8500 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8501
<> 147:30b64687e01f 8502 /****************** Bit definition for FMC_BTR2 register *******************/
<> 147:30b64687e01f 8503 #define FMC_BTR2_ADDSET_Pos (0U)
<> 147:30b64687e01f 8504 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8505 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8506 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8507 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8508 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8509 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8510
<> 147:30b64687e01f 8511 #define FMC_BTR2_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8512 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8513 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8514 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8515 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8516 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8517 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8518
<> 147:30b64687e01f 8519 #define FMC_BTR2_DATAST_Pos (8U)
<> 147:30b64687e01f 8520 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8521 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8522 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8523 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8524 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8525 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8526 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8527 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8528 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8529 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8530
<> 147:30b64687e01f 8531 #define FMC_BTR2_BUSTURN_Pos (16U)
<> 147:30b64687e01f 8532 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 8533 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 8534 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 8535 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 8536 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 8537 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8538
<> 147:30b64687e01f 8539 #define FMC_BTR2_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8540 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8541 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8542 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8543 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8544 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8545 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8546
<> 147:30b64687e01f 8547 #define FMC_BTR2_DATLAT_Pos (24U)
<> 147:30b64687e01f 8548 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8549 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8550 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8551 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8552 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8553 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8554
<> 147:30b64687e01f 8555 #define FMC_BTR2_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8556 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8557 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8558 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8559 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8560
<> 147:30b64687e01f 8561 /******************* Bit definition for FMC_BTR3 register *******************/
<> 147:30b64687e01f 8562 #define FMC_BTR3_ADDSET_Pos (0U)
<> 147:30b64687e01f 8563 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8564 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8565 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8566 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8567 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8568 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8569
<> 147:30b64687e01f 8570 #define FMC_BTR3_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8571 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8572 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8573 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8574 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8575 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8576 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8577
<> 147:30b64687e01f 8578 #define FMC_BTR3_DATAST_Pos (8U)
<> 147:30b64687e01f 8579 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8580 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8581 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8582 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8583 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8584 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8585 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8586 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8587 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8588 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8589
<> 147:30b64687e01f 8590 #define FMC_BTR3_BUSTURN_Pos (16U)
<> 147:30b64687e01f 8591 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 8592 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 8593 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 8594 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 8595 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 8596 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8597
<> 147:30b64687e01f 8598 #define FMC_BTR3_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8599 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8600 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8601 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8602 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8603 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8604 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8605
<> 147:30b64687e01f 8606 #define FMC_BTR3_DATLAT_Pos (24U)
<> 147:30b64687e01f 8607 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8608 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8609 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8610 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8611 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8612 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8613
<> 147:30b64687e01f 8614 #define FMC_BTR3_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8615 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8616 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8617 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8618 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8619
<> 147:30b64687e01f 8620 /****************** Bit definition for FMC_BTR4 register *******************/
<> 147:30b64687e01f 8621 #define FMC_BTR4_ADDSET_Pos (0U)
<> 147:30b64687e01f 8622 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8623 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8624 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8625 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8626 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8627 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8628
<> 147:30b64687e01f 8629 #define FMC_BTR4_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8630 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8631 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8632 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8633 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8634 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8635 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8636
<> 147:30b64687e01f 8637 #define FMC_BTR4_DATAST_Pos (8U)
<> 147:30b64687e01f 8638 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8639 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8640 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8641 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8642 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8643 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8644 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8645 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8646 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8647 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8648
<> 147:30b64687e01f 8649 #define FMC_BTR4_BUSTURN_Pos (16U)
<> 147:30b64687e01f 8650 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 8651 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 8652 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 8653 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 8654 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 8655 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8656
<> 147:30b64687e01f 8657 #define FMC_BTR4_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8658 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8659 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8660 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8661 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8662 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8663 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8664
<> 147:30b64687e01f 8665 #define FMC_BTR4_DATLAT_Pos (24U)
<> 147:30b64687e01f 8666 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8667 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8668 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8669 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8670 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8671 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8672
<> 147:30b64687e01f 8673 #define FMC_BTR4_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8674 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8675 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8676 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8677 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8678
<> 147:30b64687e01f 8679 /****************** Bit definition for FMC_BWTRx register ******************/
<> 147:30b64687e01f 8680 #define FMC_BWTRx_ADDSET_Pos (0U)
<> 147:30b64687e01f 8681 #define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8682 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8683 #define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8684 #define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8685 #define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8686 #define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8687
<> 147:30b64687e01f 8688 #define FMC_BWTRx_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8689 #define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8690 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8691 #define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8692 #define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8693 #define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8694 #define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8695
<> 147:30b64687e01f 8696 #define FMC_BWTRx_DATAST_Pos (8U)
<> 147:30b64687e01f 8697 #define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8698 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8699 #define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8700 #define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8701 #define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8702 #define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8703 #define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8704 #define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8705 #define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8706 #define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8707
<> 147:30b64687e01f 8708 #define FMC_BWTRx_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8709 #define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8710 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8711 #define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8712 #define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8713
<> 147:30b64687e01f 8714 /* Old Bit definition for FMC_BWTRx register maintained for legacy purpose */
<> 147:30b64687e01f 8715 #define FMC_BWTRx_ADDSETx FMC_BWTRx_ADDSET
<> 147:30b64687e01f 8716 #define FMC_BWTRx_ADDSETx_0 FMC_BWTRx_ADDSET_0
<> 147:30b64687e01f 8717 #define FMC_BWTRx_ADDSETx_1 FMC_BWTRx_ADDSET_1
<> 147:30b64687e01f 8718 #define FMC_BWTRx_ADDSETx_2 FMC_BWTRx_ADDSET_2
<> 147:30b64687e01f 8719 #define FMC_BWTRx_ADDSETx_3 FMC_BWTRx_ADDSET_3
<> 147:30b64687e01f 8720
<> 147:30b64687e01f 8721 #define FMC_BWTRx_ADDHLDx FMC_BWTRx_ADDHLD
<> 147:30b64687e01f 8722 #define FMC_BWTRx_ADDHLDx_0 FMC_BWTRx_ADDHLD_0
<> 147:30b64687e01f 8723 #define FMC_BWTRx_ADDHLDx_1 FMC_BWTRx_ADDHLD_1
<> 147:30b64687e01f 8724 #define FMC_BWTRx_ADDHLDx_2 FMC_BWTRx_ADDHLD_2
<> 147:30b64687e01f 8725 #define FMC_BWTRx_ADDHLDx_3 FMC_BWTRx_ADDHLD_3
<> 147:30b64687e01f 8726
<> 147:30b64687e01f 8727 #define FMC_BWTRx_DATASTx FMC_BWTRx_DATAST
<> 147:30b64687e01f 8728 #define FMC_BWTRx_DATASTx_0 FMC_BWTRx_DATAST_0
<> 147:30b64687e01f 8729 #define FMC_BWTRx_DATASTx_1 FMC_BWTRx_DATAST_1
<> 147:30b64687e01f 8730 #define FMC_BWTRx_DATASTx_2 FMC_BWTRx_DATAST_2
<> 147:30b64687e01f 8731 #define FMC_BWTRx_DATASTx_3 FMC_BWTRx_DATAST_3
<> 147:30b64687e01f 8732 #define FMC_BWTRx_DATASTx_4 FMC_BWTRx_DATAST_4
<> 147:30b64687e01f 8733 #define FMC_BWTRx_DATASTx_5 FMC_BWTRx_DATAST_5
<> 147:30b64687e01f 8734 #define FMC_BWTRx_DATASTx_6 FMC_BWTRx_DATAST_6
<> 147:30b64687e01f 8735 #define FMC_BWTRx_DATASTx_7 FMC_BWTRx_DATAST_7
<> 147:30b64687e01f 8736
<> 147:30b64687e01f 8737 #define FMC_BWTRx_ACCMODx FMC_BWTRx_ACCMOD
<> 147:30b64687e01f 8738 #define FMC_BWTRx_ACCMODx_0 FMC_BWTRx_ACCMOD_0
<> 147:30b64687e01f 8739 #define FMC_BWTRx_ACCMODx_1 FMC_BWTRx_ACCMOD_1
<> 147:30b64687e01f 8740
<> 147:30b64687e01f 8741 /****************** Bit definition for FMC_BWTR1 register ******************/
<> 147:30b64687e01f 8742 #define FMC_BWTR1_ADDSET_Pos (0U)
<> 147:30b64687e01f 8743 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8744 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8745 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8746 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8747 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8748 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8749
<> 147:30b64687e01f 8750 #define FMC_BWTR1_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8751 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8752 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8753 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8754 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8755 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8756 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8757
<> 147:30b64687e01f 8758 #define FMC_BWTR1_DATAST_Pos (8U)
<> 147:30b64687e01f 8759 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8760 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8761 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8762 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8763 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8764 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8765 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8766 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8767 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8768 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8769
<> 147:30b64687e01f 8770 #define FMC_BWTR1_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8771 #define FMC_BWTR1_CLKDIV_Msk (0xFU << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8772 #define FMC_BWTR1_CLKDIV FMC_BWTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8773 #define FMC_BWTR1_CLKDIV_0 (0x1U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8774 #define FMC_BWTR1_CLKDIV_1 (0x2U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8775 #define FMC_BWTR1_CLKDIV_2 (0x4U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8776 #define FMC_BWTR1_CLKDIV_3 (0x8U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8777
<> 147:30b64687e01f 8778 #define FMC_BWTR1_DATLAT_Pos (24U)
<> 147:30b64687e01f 8779 #define FMC_BWTR1_DATLAT_Msk (0xFU << FMC_BWTR1_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8780 #define FMC_BWTR1_DATLAT FMC_BWTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8781 #define FMC_BWTR1_DATLAT_0 (0x1U << FMC_BWTR1_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8782 #define FMC_BWTR1_DATLAT_1 (0x2U << FMC_BWTR1_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8783 #define FMC_BWTR1_DATLAT_2 (0x4U << FMC_BWTR1_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8784 #define FMC_BWTR1_DATLAT_3 (0x8U << FMC_BWTR1_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8785
<> 147:30b64687e01f 8786 #define FMC_BWTR1_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8787 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8788 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8789 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8790 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8791
<> 147:30b64687e01f 8792 /****************** Bit definition for FMC_BWTR2 register ******************/
<> 147:30b64687e01f 8793 #define FMC_BWTR2_ADDSET_Pos (0U)
<> 147:30b64687e01f 8794 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8795 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8796 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8797 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8798 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8799 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8800
<> 147:30b64687e01f 8801 #define FMC_BWTR2_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8802 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8803 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8804 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8805 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8806 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8807 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8808
<> 147:30b64687e01f 8809 #define FMC_BWTR2_DATAST_Pos (8U)
<> 147:30b64687e01f 8810 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8811 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8812 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8813 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8814 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8815 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8816 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8817 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8818 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8819 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8820
<> 147:30b64687e01f 8821 #define FMC_BWTR2_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8822 #define FMC_BWTR2_CLKDIV_Msk (0xFU << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8823 #define FMC_BWTR2_CLKDIV FMC_BWTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8824 #define FMC_BWTR2_CLKDIV_0 (0x1U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8825 #define FMC_BWTR2_CLKDIV_1 (0x2U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8826 #define FMC_BWTR2_CLKDIV_2 (0x4U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8827 #define FMC_BWTR2_CLKDIV_3 (0x8U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8828
<> 147:30b64687e01f 8829 #define FMC_BWTR2_DATLAT_Pos (24U)
<> 147:30b64687e01f 8830 #define FMC_BWTR2_DATLAT_Msk (0xFU << FMC_BWTR2_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8831 #define FMC_BWTR2_DATLAT FMC_BWTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8832 #define FMC_BWTR2_DATLAT_0 (0x1U << FMC_BWTR2_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8833 #define FMC_BWTR2_DATLAT_1 (0x2U << FMC_BWTR2_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8834 #define FMC_BWTR2_DATLAT_2 (0x4U << FMC_BWTR2_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8835 #define FMC_BWTR2_DATLAT_3 (0x8U << FMC_BWTR2_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8836
<> 147:30b64687e01f 8837 #define FMC_BWTR2_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8838 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8839 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8840 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8841 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8842
<> 147:30b64687e01f 8843 /****************** Bit definition for FMC_BWTR3 register ******************/
<> 147:30b64687e01f 8844 #define FMC_BWTR3_ADDSET_Pos (0U)
<> 147:30b64687e01f 8845 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8846 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8847 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8848 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8849 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8850 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8851
<> 147:30b64687e01f 8852 #define FMC_BWTR3_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8853 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8854 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8855 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8856 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8857 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8858 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8859
<> 147:30b64687e01f 8860 #define FMC_BWTR3_DATAST_Pos (8U)
<> 147:30b64687e01f 8861 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8862 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8863 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8864 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8865 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8866 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8867 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8868 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8869 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8870 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8871
<> 147:30b64687e01f 8872 #define FMC_BWTR3_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8873 #define FMC_BWTR3_CLKDIV_Msk (0xFU << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8874 #define FMC_BWTR3_CLKDIV FMC_BWTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8875 #define FMC_BWTR3_CLKDIV_0 (0x1U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8876 #define FMC_BWTR3_CLKDIV_1 (0x2U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8877 #define FMC_BWTR3_CLKDIV_2 (0x4U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8878 #define FMC_BWTR3_CLKDIV_3 (0x8U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8879
<> 147:30b64687e01f 8880 #define FMC_BWTR3_DATLAT_Pos (24U)
<> 147:30b64687e01f 8881 #define FMC_BWTR3_DATLAT_Msk (0xFU << FMC_BWTR3_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8882 #define FMC_BWTR3_DATLAT FMC_BWTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8883 #define FMC_BWTR3_DATLAT_0 (0x1U << FMC_BWTR3_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8884 #define FMC_BWTR3_DATLAT_1 (0x2U << FMC_BWTR3_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8885 #define FMC_BWTR3_DATLAT_2 (0x4U << FMC_BWTR3_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8886 #define FMC_BWTR3_DATLAT_3 (0x8U << FMC_BWTR3_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8887
<> 147:30b64687e01f 8888 #define FMC_BWTR3_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8889 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8890 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8891 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8892 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8893
<> 147:30b64687e01f 8894 /****************** Bit definition for FMC_BWTR4 register ******************/
<> 147:30b64687e01f 8895 #define FMC_BWTR4_ADDSET_Pos (0U)
<> 147:30b64687e01f 8896 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 8897 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 8898 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 8899 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8900 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8901 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8902
<> 147:30b64687e01f 8903 #define FMC_BWTR4_ADDHLD_Pos (4U)
<> 147:30b64687e01f 8904 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 8905 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 8906 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8907 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8908 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8909 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 8910
<> 147:30b64687e01f 8911 #define FMC_BWTR4_DATAST_Pos (8U)
<> 147:30b64687e01f 8912 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 8913 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 8914 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 8915 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8916 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8917 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8918 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8919 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8920 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8921 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8922
<> 147:30b64687e01f 8923 #define FMC_BWTR4_CLKDIV_Pos (20U)
<> 147:30b64687e01f 8924 #define FMC_BWTR4_CLKDIV_Msk (0xFU << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 8925 #define FMC_BWTR4_CLKDIV FMC_BWTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 8926 #define FMC_BWTR4_CLKDIV_0 (0x1U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 8927 #define FMC_BWTR4_CLKDIV_1 (0x2U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 8928 #define FMC_BWTR4_CLKDIV_2 (0x4U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 8929 #define FMC_BWTR4_CLKDIV_3 (0x8U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 8930
<> 147:30b64687e01f 8931 #define FMC_BWTR4_DATLAT_Pos (24U)
<> 147:30b64687e01f 8932 #define FMC_BWTR4_DATLAT_Msk (0xFU << FMC_BWTR4_DATLAT_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 8933 #define FMC_BWTR4_DATLAT FMC_BWTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 8934 #define FMC_BWTR4_DATLAT_0 (0x1U << FMC_BWTR4_DATLAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 8935 #define FMC_BWTR4_DATLAT_1 (0x2U << FMC_BWTR4_DATLAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 8936 #define FMC_BWTR4_DATLAT_2 (0x4U << FMC_BWTR4_DATLAT_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 8937 #define FMC_BWTR4_DATLAT_3 (0x8U << FMC_BWTR4_DATLAT_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 8938
<> 147:30b64687e01f 8939 #define FMC_BWTR4_ACCMOD_Pos (28U)
<> 147:30b64687e01f 8940 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 8941 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 8942 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 8943 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 8944
<> 147:30b64687e01f 8945 /****************** Bit definition for FMC_PCRx register *******************/
<> 147:30b64687e01f 8946 #define FMC_PCRx_PWAITEN_Pos (1U)
<> 147:30b64687e01f 8947 #define FMC_PCRx_PWAITEN_Msk (0x1U << FMC_PCRx_PWAITEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8948 #define FMC_PCRx_PWAITEN FMC_PCRx_PWAITEN_Msk /*!<Wait feature enable bit */
<> 147:30b64687e01f 8949 #define FMC_PCRx_PBKEN_Pos (2U)
<> 147:30b64687e01f 8950 #define FMC_PCRx_PBKEN_Msk (0x1U << FMC_PCRx_PBKEN_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8951 #define FMC_PCRx_PBKEN FMC_PCRx_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
<> 147:30b64687e01f 8952 #define FMC_PCRx_PTYP_Pos (3U)
<> 147:30b64687e01f 8953 #define FMC_PCRx_PTYP_Msk (0x1U << FMC_PCRx_PTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8954 #define FMC_PCRx_PTYP FMC_PCRx_PTYP_Msk /*!<Memory type */
<> 147:30b64687e01f 8955
<> 147:30b64687e01f 8956 #define FMC_PCRx_PWID_Pos (4U)
<> 147:30b64687e01f 8957 #define FMC_PCRx_PWID_Msk (0x3U << FMC_PCRx_PWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 8958 #define FMC_PCRx_PWID FMC_PCRx_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 147:30b64687e01f 8959 #define FMC_PCRx_PWID_0 (0x1U << FMC_PCRx_PWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 8960 #define FMC_PCRx_PWID_1 (0x2U << FMC_PCRx_PWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 8961
<> 147:30b64687e01f 8962 #define FMC_PCRx_ECCEN_Pos (6U)
<> 147:30b64687e01f 8963 #define FMC_PCRx_ECCEN_Msk (0x1U << FMC_PCRx_ECCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 8964 #define FMC_PCRx_ECCEN FMC_PCRx_ECCEN_Msk /*!<ECC computation logic enable bit */
<> 147:30b64687e01f 8965
<> 147:30b64687e01f 8966 #define FMC_PCRx_TCLR_Pos (9U)
<> 147:30b64687e01f 8967 #define FMC_PCRx_TCLR_Msk (0xFU << FMC_PCRx_TCLR_Pos) /*!< 0x00001E00 */
<> 147:30b64687e01f 8968 #define FMC_PCRx_TCLR FMC_PCRx_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 147:30b64687e01f 8969 #define FMC_PCRx_TCLR_0 (0x1U << FMC_PCRx_TCLR_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 8970 #define FMC_PCRx_TCLR_1 (0x2U << FMC_PCRx_TCLR_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 8971 #define FMC_PCRx_TCLR_2 (0x4U << FMC_PCRx_TCLR_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 8972 #define FMC_PCRx_TCLR_3 (0x8U << FMC_PCRx_TCLR_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 8973
<> 147:30b64687e01f 8974 #define FMC_PCRx_TAR_Pos (13U)
<> 147:30b64687e01f 8975 #define FMC_PCRx_TAR_Msk (0xFU << FMC_PCRx_TAR_Pos) /*!< 0x0001E000 */
<> 147:30b64687e01f 8976 #define FMC_PCRx_TAR FMC_PCRx_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
<> 147:30b64687e01f 8977 #define FMC_PCRx_TAR_0 (0x1U << FMC_PCRx_TAR_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 8978 #define FMC_PCRx_TAR_1 (0x2U << FMC_PCRx_TAR_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 8979 #define FMC_PCRx_TAR_2 (0x4U << FMC_PCRx_TAR_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 8980 #define FMC_PCRx_TAR_3 (0x8U << FMC_PCRx_TAR_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 8981
<> 147:30b64687e01f 8982 #define FMC_PCRx_ECCPS_Pos (17U)
<> 147:30b64687e01f 8983 #define FMC_PCRx_ECCPS_Msk (0x7U << FMC_PCRx_ECCPS_Pos) /*!< 0x000E0000 */
<> 147:30b64687e01f 8984 #define FMC_PCRx_ECCPS FMC_PCRx_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
<> 147:30b64687e01f 8985 #define FMC_PCRx_ECCPS_0 (0x1U << FMC_PCRx_ECCPS_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 8986 #define FMC_PCRx_ECCPS_1 (0x2U << FMC_PCRx_ECCPS_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 8987 #define FMC_PCRx_ECCPS_2 (0x4U << FMC_PCRx_ECCPS_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 8988
<> 147:30b64687e01f 8989 /****************** Bit definition for FMC_PCR2 register *******************/
<> 147:30b64687e01f 8990 #define FMC_PCR2_PWAITEN_Pos (1U)
<> 147:30b64687e01f 8991 #define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 8992 #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
<> 147:30b64687e01f 8993 #define FMC_PCR2_PBKEN_Pos (2U)
<> 147:30b64687e01f 8994 #define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 8995 #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
<> 147:30b64687e01f 8996 #define FMC_PCR2_PTYP_Pos (3U)
<> 147:30b64687e01f 8997 #define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 8998 #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
<> 147:30b64687e01f 8999
<> 147:30b64687e01f 9000 #define FMC_PCR2_PWID_Pos (4U)
<> 147:30b64687e01f 9001 #define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 9002 #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 147:30b64687e01f 9003 #define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9004 #define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9005
<> 147:30b64687e01f 9006 #define FMC_PCR2_ECCEN_Pos (6U)
<> 147:30b64687e01f 9007 #define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9008 #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
<> 147:30b64687e01f 9009
<> 147:30b64687e01f 9010 #define FMC_PCR2_TCLR_Pos (9U)
<> 147:30b64687e01f 9011 #define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
<> 147:30b64687e01f 9012 #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 147:30b64687e01f 9013 #define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9014 #define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9015 #define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9016 #define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9017
<> 147:30b64687e01f 9018 #define FMC_PCR2_TAR_Pos (13U)
<> 147:30b64687e01f 9019 #define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
<> 147:30b64687e01f 9020 #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
<> 147:30b64687e01f 9021 #define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9022 #define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9023 #define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9024 #define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9025
<> 147:30b64687e01f 9026 #define FMC_PCR2_ECCPS_Pos (17U)
<> 147:30b64687e01f 9027 #define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
<> 147:30b64687e01f 9028 #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
<> 147:30b64687e01f 9029 #define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9030 #define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9031 #define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9032
<> 147:30b64687e01f 9033 /****************** Bit definition for FMC_PCR3 register *******************/
<> 147:30b64687e01f 9034 #define FMC_PCR3_PWAITEN_Pos (1U)
<> 147:30b64687e01f 9035 #define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9036 #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
<> 147:30b64687e01f 9037 #define FMC_PCR3_PBKEN_Pos (2U)
<> 147:30b64687e01f 9038 #define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9039 #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
<> 147:30b64687e01f 9040 #define FMC_PCR3_PTYP_Pos (3U)
<> 147:30b64687e01f 9041 #define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9042 #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
<> 147:30b64687e01f 9043
<> 147:30b64687e01f 9044 #define FMC_PCR3_PWID_Pos (4U)
<> 147:30b64687e01f 9045 #define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 9046 #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 147:30b64687e01f 9047 #define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9048 #define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9049
<> 147:30b64687e01f 9050 #define FMC_PCR3_ECCEN_Pos (6U)
<> 147:30b64687e01f 9051 #define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9052 #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
<> 147:30b64687e01f 9053
<> 147:30b64687e01f 9054 #define FMC_PCR3_TCLR_Pos (9U)
<> 147:30b64687e01f 9055 #define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
<> 147:30b64687e01f 9056 #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 147:30b64687e01f 9057 #define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9058 #define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9059 #define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9060 #define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9061
<> 147:30b64687e01f 9062 #define FMC_PCR3_TAR_Pos (13U)
<> 147:30b64687e01f 9063 #define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
<> 147:30b64687e01f 9064 #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
<> 147:30b64687e01f 9065 #define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9066 #define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9067 #define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9068 #define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9069
<> 147:30b64687e01f 9070 #define FMC_PCR3_ECCPS_Pos (17U)
<> 147:30b64687e01f 9071 #define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
<> 147:30b64687e01f 9072 #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
<> 147:30b64687e01f 9073 #define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9074 #define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9075 #define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9076
<> 147:30b64687e01f 9077 /****************** Bit definition for FMC_PCR4 register *******************/
<> 147:30b64687e01f 9078 #define FMC_PCR4_PWAITEN_Pos (1U)
<> 147:30b64687e01f 9079 #define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9080 #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
<> 147:30b64687e01f 9081 #define FMC_PCR4_PBKEN_Pos (2U)
<> 147:30b64687e01f 9082 #define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9083 #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
<> 147:30b64687e01f 9084 #define FMC_PCR4_PTYP_Pos (3U)
<> 147:30b64687e01f 9085 #define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9086 #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
<> 147:30b64687e01f 9087
<> 147:30b64687e01f 9088 #define FMC_PCR4_PWID_Pos (4U)
<> 147:30b64687e01f 9089 #define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 9090 #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 147:30b64687e01f 9091 #define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9092 #define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9093
<> 147:30b64687e01f 9094 #define FMC_PCR4_ECCEN_Pos (6U)
<> 147:30b64687e01f 9095 #define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9096 #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
<> 147:30b64687e01f 9097
<> 147:30b64687e01f 9098 #define FMC_PCR4_TCLR_Pos (9U)
<> 147:30b64687e01f 9099 #define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
<> 147:30b64687e01f 9100 #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 147:30b64687e01f 9101 #define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9102 #define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9103 #define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9104 #define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9105
<> 147:30b64687e01f 9106 #define FMC_PCR4_TAR_Pos (13U)
<> 147:30b64687e01f 9107 #define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
<> 147:30b64687e01f 9108 #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
<> 147:30b64687e01f 9109 #define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9110 #define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9111 #define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9112 #define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9113
<> 147:30b64687e01f 9114 #define FMC_PCR4_ECCPS_Pos (17U)
<> 147:30b64687e01f 9115 #define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
<> 147:30b64687e01f 9116 #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
<> 147:30b64687e01f 9117 #define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9118 #define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9119 #define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9120
<> 147:30b64687e01f 9121 /******************* Bit definition for FMC_SRx register *******************/
<> 147:30b64687e01f 9122 #define FMC_SRx_IRS_Pos (0U)
<> 147:30b64687e01f 9123 #define FMC_SRx_IRS_Msk (0x1U << FMC_SRx_IRS_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9124 #define FMC_SRx_IRS FMC_SRx_IRS_Msk /*!<Interrupt Rising Edge status */
<> 147:30b64687e01f 9125 #define FMC_SRx_ILS_Pos (1U)
<> 147:30b64687e01f 9126 #define FMC_SRx_ILS_Msk (0x1U << FMC_SRx_ILS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9127 #define FMC_SRx_ILS FMC_SRx_ILS_Msk /*!<Interrupt Level status */
<> 147:30b64687e01f 9128 #define FMC_SRx_IFS_Pos (2U)
<> 147:30b64687e01f 9129 #define FMC_SRx_IFS_Msk (0x1U << FMC_SRx_IFS_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9130 #define FMC_SRx_IFS FMC_SRx_IFS_Msk /*!<Interrupt Falling Edge status */
<> 147:30b64687e01f 9131 #define FMC_SRx_IREN_Pos (3U)
<> 147:30b64687e01f 9132 #define FMC_SRx_IREN_Msk (0x1U << FMC_SRx_IREN_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9133 #define FMC_SRx_IREN FMC_SRx_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
<> 147:30b64687e01f 9134 #define FMC_SRx_ILEN_Pos (4U)
<> 147:30b64687e01f 9135 #define FMC_SRx_ILEN_Msk (0x1U << FMC_SRx_ILEN_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9136 #define FMC_SRx_ILEN FMC_SRx_ILEN_Msk /*!<Interrupt Level detection Enable bit */
<> 147:30b64687e01f 9137 #define FMC_SRx_IFEN_Pos (5U)
<> 147:30b64687e01f 9138 #define FMC_SRx_IFEN_Msk (0x1U << FMC_SRx_IFEN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9139 #define FMC_SRx_IFEN FMC_SRx_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
<> 147:30b64687e01f 9140 #define FMC_SRx_FEMPT_Pos (6U)
<> 147:30b64687e01f 9141 #define FMC_SRx_FEMPT_Msk (0x1U << FMC_SRx_FEMPT_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9142 #define FMC_SRx_FEMPT FMC_SRx_FEMPT_Msk /*!<FIFO empty */
<> 147:30b64687e01f 9143
<> 147:30b64687e01f 9144 /******************* Bit definition for FMC_SR2 register *******************/
<> 147:30b64687e01f 9145 #define FMC_SR2_IRS_Pos (0U)
<> 147:30b64687e01f 9146 #define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9147 #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
<> 147:30b64687e01f 9148 #define FMC_SR2_ILS_Pos (1U)
<> 147:30b64687e01f 9149 #define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9150 #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
<> 147:30b64687e01f 9151 #define FMC_SR2_IFS_Pos (2U)
<> 147:30b64687e01f 9152 #define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9153 #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
<> 147:30b64687e01f 9154 #define FMC_SR2_IREN_Pos (3U)
<> 147:30b64687e01f 9155 #define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9156 #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
<> 147:30b64687e01f 9157 #define FMC_SR2_ILEN_Pos (4U)
<> 147:30b64687e01f 9158 #define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9159 #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
<> 147:30b64687e01f 9160 #define FMC_SR2_IFEN_Pos (5U)
<> 147:30b64687e01f 9161 #define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9162 #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
<> 147:30b64687e01f 9163 #define FMC_SR2_FEMPT_Pos (6U)
<> 147:30b64687e01f 9164 #define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9165 #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
<> 147:30b64687e01f 9166
<> 147:30b64687e01f 9167 /******************* Bit definition for FMC_SR3 register *******************/
<> 147:30b64687e01f 9168 #define FMC_SR3_IRS_Pos (0U)
<> 147:30b64687e01f 9169 #define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9170 #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
<> 147:30b64687e01f 9171 #define FMC_SR3_ILS_Pos (1U)
<> 147:30b64687e01f 9172 #define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9173 #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
<> 147:30b64687e01f 9174 #define FMC_SR3_IFS_Pos (2U)
<> 147:30b64687e01f 9175 #define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9176 #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
<> 147:30b64687e01f 9177 #define FMC_SR3_IREN_Pos (3U)
<> 147:30b64687e01f 9178 #define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9179 #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
<> 147:30b64687e01f 9180 #define FMC_SR3_ILEN_Pos (4U)
<> 147:30b64687e01f 9181 #define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9182 #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
<> 147:30b64687e01f 9183 #define FMC_SR3_IFEN_Pos (5U)
<> 147:30b64687e01f 9184 #define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9185 #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
<> 147:30b64687e01f 9186 #define FMC_SR3_FEMPT_Pos (6U)
<> 147:30b64687e01f 9187 #define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9188 #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
<> 147:30b64687e01f 9189
<> 147:30b64687e01f 9190 /******************* Bit definition for FMC_SR4 register *******************/
<> 147:30b64687e01f 9191 #define FMC_SR4_IRS_Pos (0U)
<> 147:30b64687e01f 9192 #define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9193 #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
<> 147:30b64687e01f 9194 #define FMC_SR4_ILS_Pos (1U)
<> 147:30b64687e01f 9195 #define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9196 #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
<> 147:30b64687e01f 9197 #define FMC_SR4_IFS_Pos (2U)
<> 147:30b64687e01f 9198 #define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9199 #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
<> 147:30b64687e01f 9200 #define FMC_SR4_IREN_Pos (3U)
<> 147:30b64687e01f 9201 #define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9202 #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
<> 147:30b64687e01f 9203 #define FMC_SR4_ILEN_Pos (4U)
<> 147:30b64687e01f 9204 #define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9205 #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
<> 147:30b64687e01f 9206 #define FMC_SR4_IFEN_Pos (5U)
<> 147:30b64687e01f 9207 #define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9208 #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
<> 147:30b64687e01f 9209 #define FMC_SR4_FEMPT_Pos (6U)
<> 147:30b64687e01f 9210 #define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9211 #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
<> 147:30b64687e01f 9212
<> 147:30b64687e01f 9213 /****************** Bit definition for FMC_PMEMx register ******************/
<> 147:30b64687e01f 9214 #define FMC_PMEMx_MEMSETx_Pos (0U)
<> 147:30b64687e01f 9215 #define FMC_PMEMx_MEMSETx_Msk (0xFFU << FMC_PMEMx_MEMSETx_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9216 #define FMC_PMEMx_MEMSETx FMC_PMEMx_MEMSETx_Msk /*!<MEMSETx[7:0] bits (Common memory x setup time) */
<> 147:30b64687e01f 9217 #define FMC_PMEMx_MEMSETx_0 (0x01U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9218 #define FMC_PMEMx_MEMSETx_1 (0x02U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9219 #define FMC_PMEMx_MEMSETx_2 (0x04U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9220 #define FMC_PMEMx_MEMSETx_3 (0x08U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9221 #define FMC_PMEMx_MEMSETx_4 (0x10U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9222 #define FMC_PMEMx_MEMSETx_5 (0x20U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9223 #define FMC_PMEMx_MEMSETx_6 (0x40U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9224 #define FMC_PMEMx_MEMSETx_7 (0x80U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9225
<> 147:30b64687e01f 9226 #define FMC_PMEMx_MEMWAITx_Pos (8U)
<> 147:30b64687e01f 9227 #define FMC_PMEMx_MEMWAITx_Msk (0xFFU << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9228 #define FMC_PMEMx_MEMWAITx FMC_PMEMx_MEMWAITx_Msk /*!<MEMWAITx[7:0] bits (Common memory x wait time) */
<> 147:30b64687e01f 9229 #define FMC_PMEMx_MEMWAITx_0 (0x01U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9230 #define FMC_PMEMx_MEMWAITx_1 (0x02U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9231 #define FMC_PMEMx_MEMWAITx_2 (0x04U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9232 #define FMC_PMEMx_MEMWAITx_3 (0x08U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9233 #define FMC_PMEMx_MEMWAITx_4 (0x10U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9234 #define FMC_PMEMx_MEMWAITx_5 (0x20U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9235 #define FMC_PMEMx_MEMWAITx_6 (0x40U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9236 #define FMC_PMEMx_MEMWAITx_7 (0x80U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9237
<> 147:30b64687e01f 9238 #define FMC_PMEMx_MEMHOLDx_Pos (16U)
<> 147:30b64687e01f 9239 #define FMC_PMEMx_MEMHOLDx_Msk (0xFFU << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9240 #define FMC_PMEMx_MEMHOLDx FMC_PMEMx_MEMHOLDx_Msk /*!<MEMHOLDx[7:0] bits (Common memory x hold time) */
<> 147:30b64687e01f 9241 #define FMC_PMEMx_MEMHOLDx_0 (0x01U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9242 #define FMC_PMEMx_MEMHOLDx_1 (0x02U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9243 #define FMC_PMEMx_MEMHOLDx_2 (0x04U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9244 #define FMC_PMEMx_MEMHOLDx_3 (0x08U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9245 #define FMC_PMEMx_MEMHOLDx_4 (0x10U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9246 #define FMC_PMEMx_MEMHOLDx_5 (0x20U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9247 #define FMC_PMEMx_MEMHOLDx_6 (0x40U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9248 #define FMC_PMEMx_MEMHOLDx_7 (0x80U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9249
<> 147:30b64687e01f 9250 #define FMC_PMEMx_MEMHIZx_Pos (24U)
<> 147:30b64687e01f 9251 #define FMC_PMEMx_MEMHIZx_Msk (0xFFU << FMC_PMEMx_MEMHIZx_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9252 #define FMC_PMEMx_MEMHIZx FMC_PMEMx_MEMHIZx_Msk /*!<MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
<> 147:30b64687e01f 9253 #define FMC_PMEMx_MEMHIZx_0 (0x01U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9254 #define FMC_PMEMx_MEMHIZx_1 (0x02U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9255 #define FMC_PMEMx_MEMHIZx_2 (0x04U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9256 #define FMC_PMEMx_MEMHIZx_3 (0x08U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9257 #define FMC_PMEMx_MEMHIZx_4 (0x10U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9258 #define FMC_PMEMx_MEMHIZx_5 (0x20U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9259 #define FMC_PMEMx_MEMHIZx_6 (0x40U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9260 #define FMC_PMEMx_MEMHIZx_7 (0x80U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9261
<> 147:30b64687e01f 9262 /****************** Bit definition for FMC_PMEM2 register ******************/
<> 147:30b64687e01f 9263 #define FMC_PMEM2_MEMSET2_Pos (0U)
<> 147:30b64687e01f 9264 #define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9265 #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
<> 147:30b64687e01f 9266 #define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9267 #define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9268 #define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9269 #define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9270 #define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9271 #define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9272 #define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9273 #define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9274
<> 147:30b64687e01f 9275 #define FMC_PMEM2_MEMWAIT2_Pos (8U)
<> 147:30b64687e01f 9276 #define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9277 #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
<> 147:30b64687e01f 9278 #define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9279 #define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9280 #define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9281 #define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9282 #define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9283 #define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9284 #define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9285 #define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9286
<> 147:30b64687e01f 9287 #define FMC_PMEM2_MEMHOLD2_Pos (16U)
<> 147:30b64687e01f 9288 #define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9289 #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
<> 147:30b64687e01f 9290 #define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9291 #define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9292 #define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9293 #define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9294 #define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9295 #define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9296 #define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9297 #define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9298
<> 147:30b64687e01f 9299 #define FMC_PMEM2_MEMHIZ2_Pos (24U)
<> 147:30b64687e01f 9300 #define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9301 #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
<> 147:30b64687e01f 9302 #define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9303 #define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9304 #define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9305 #define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9306 #define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9307 #define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9308 #define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9309 #define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9310
<> 147:30b64687e01f 9311 /****************** Bit definition for FMC_PMEM3 register ******************/
<> 147:30b64687e01f 9312 #define FMC_PMEM3_MEMSET3_Pos (0U)
<> 147:30b64687e01f 9313 #define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9314 #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
<> 147:30b64687e01f 9315 #define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9316 #define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9317 #define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9318 #define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9319 #define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9320 #define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9321 #define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9322 #define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9323
<> 147:30b64687e01f 9324 #define FMC_PMEM3_MEMWAIT3_Pos (8U)
<> 147:30b64687e01f 9325 #define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9326 #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
<> 147:30b64687e01f 9327 #define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9328 #define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9329 #define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9330 #define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9331 #define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9332 #define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9333 #define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9334 #define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9335
<> 147:30b64687e01f 9336 #define FMC_PMEM3_MEMHOLD3_Pos (16U)
<> 147:30b64687e01f 9337 #define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9338 #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
<> 147:30b64687e01f 9339 #define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9340 #define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9341 #define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9342 #define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9343 #define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9344 #define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9345 #define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9346 #define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9347
<> 147:30b64687e01f 9348 #define FMC_PMEM3_MEMHIZ3_Pos (24U)
<> 147:30b64687e01f 9349 #define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9350 #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
<> 147:30b64687e01f 9351 #define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9352 #define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9353 #define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9354 #define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9355 #define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9356 #define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9357 #define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9358 #define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9359
<> 147:30b64687e01f 9360 /****************** Bit definition for FMC_PMEM4 register ******************/
<> 147:30b64687e01f 9361 #define FMC_PMEM4_MEMSET4_Pos (0U)
<> 147:30b64687e01f 9362 #define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9363 #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
<> 147:30b64687e01f 9364 #define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9365 #define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9366 #define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9367 #define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9368 #define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9369 #define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9370 #define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9371 #define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9372
<> 147:30b64687e01f 9373 #define FMC_PMEM4_MEMWAIT4_Pos (8U)
<> 147:30b64687e01f 9374 #define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9375 #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
<> 147:30b64687e01f 9376 #define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9377 #define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9378 #define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9379 #define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9380 #define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9381 #define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9382 #define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9383 #define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9384
<> 147:30b64687e01f 9385 #define FMC_PMEM4_MEMHOLD4_Pos (16U)
<> 147:30b64687e01f 9386 #define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9387 #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
<> 147:30b64687e01f 9388 #define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9389 #define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9390 #define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9391 #define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9392 #define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9393 #define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9394 #define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9395 #define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9396
<> 147:30b64687e01f 9397 #define FMC_PMEM4_MEMHIZ4_Pos (24U)
<> 147:30b64687e01f 9398 #define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9399 #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
<> 147:30b64687e01f 9400 #define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9401 #define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9402 #define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9403 #define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9404 #define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9405 #define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9406 #define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9407 #define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9408
<> 147:30b64687e01f 9409 /****************** Bit definition for FMC_PATTx register ******************/
<> 147:30b64687e01f 9410 #define FMC_PATTx_ATTSETx_Pos (0U)
<> 147:30b64687e01f 9411 #define FMC_PATTx_ATTSETx_Msk (0xFFU << FMC_PATTx_ATTSETx_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9412 #define FMC_PATTx_ATTSETx FMC_PATTx_ATTSETx_Msk /*!<ATTSETx[7:0] bits (Attribute memory x setup time) */
<> 147:30b64687e01f 9413 #define FMC_PATTx_ATTSETx_0 (0x01U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9414 #define FMC_PATTx_ATTSETx_1 (0x02U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9415 #define FMC_PATTx_ATTSETx_2 (0x04U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9416 #define FMC_PATTx_ATTSETx_3 (0x08U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9417 #define FMC_PATTx_ATTSETx_4 (0x10U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9418 #define FMC_PATTx_ATTSETx_5 (0x20U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9419 #define FMC_PATTx_ATTSETx_6 (0x40U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9420 #define FMC_PATTx_ATTSETx_7 (0x80U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9421
<> 147:30b64687e01f 9422 #define FMC_PATTx_ATTWAITx_Pos (8U)
<> 147:30b64687e01f 9423 #define FMC_PATTx_ATTWAITx_Msk (0xFFU << FMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9424 #define FMC_PATTx_ATTWAITx FMC_PATTx_ATTWAITx_Msk /*!<ATTWAITx[7:0] bits (Attribute memory x wait time) */
<> 147:30b64687e01f 9425 #define FMC_PATTx_ATTWAITx_0 (0x01U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9426 #define FMC_PATTx_ATTWAITx_1 (0x02U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9427 #define FMC_PATTx_ATTWAITx_2 (0x04U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9428 #define FMC_PATTx_ATTWAITx_3 (0x08U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9429 #define FMC_PATTx_ATTWAITx_4 (0x10U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9430 #define FMC_PATTx_ATTWAITx_5 (0x20U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9431 #define FMC_PATTx_ATTWAITx_6 (0x40U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9432 #define FMC_PATTx_ATTWAITx_7 (0x80U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9433
<> 147:30b64687e01f 9434 #define FMC_PATTx_ATTHOLDx_Pos (16U)
<> 147:30b64687e01f 9435 #define FMC_PATTx_ATTHOLDx_Msk (0xFFU << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9436 #define FMC_PATTx_ATTHOLDx FMC_PATTx_ATTHOLDx_Msk /*!<ATTHOLDx[7:0] bits (Attribute memory x hold time) */
<> 147:30b64687e01f 9437 #define FMC_PATTx_ATTHOLDx_0 (0x01U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9438 #define FMC_PATTx_ATTHOLDx_1 (0x02U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9439 #define FMC_PATTx_ATTHOLDx_2 (0x04U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9440 #define FMC_PATTx_ATTHOLDx_3 (0x08U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9441 #define FMC_PATTx_ATTHOLDx_4 (0x10U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9442 #define FMC_PATTx_ATTHOLDx_5 (0x20U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9443 #define FMC_PATTx_ATTHOLDx_6 (0x40U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9444 #define FMC_PATTx_ATTHOLDx_7 (0x80U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9445
<> 147:30b64687e01f 9446 #define FMC_PATTx_ATTHIZx_Pos (24U)
<> 147:30b64687e01f 9447 #define FMC_PATTx_ATTHIZx_Msk (0xFFU << FMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9448 #define FMC_PATTx_ATTHIZx FMC_PATTx_ATTHIZx_Msk /*!<ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
<> 147:30b64687e01f 9449 #define FMC_PATTx_ATTHIZx_0 (0x01U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9450 #define FMC_PATTx_ATTHIZx_1 (0x02U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9451 #define FMC_PATTx_ATTHIZx_2 (0x04U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9452 #define FMC_PATTx_ATTHIZx_3 (0x08U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9453 #define FMC_PATTx_ATTHIZx_4 (0x10U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9454 #define FMC_PATTx_ATTHIZx_5 (0x20U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9455 #define FMC_PATTx_ATTHIZx_6 (0x40U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9456 #define FMC_PATTx_ATTHIZx_7 (0x80U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9457
<> 147:30b64687e01f 9458 /****************** Bit definition for FMC_PATT2 register ******************/
<> 147:30b64687e01f 9459 #define FMC_PATT2_ATTSET2_Pos (0U)
<> 147:30b64687e01f 9460 #define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9461 #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
<> 147:30b64687e01f 9462 #define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9463 #define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9464 #define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9465 #define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9466 #define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9467 #define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9468 #define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9469 #define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9470
<> 147:30b64687e01f 9471 #define FMC_PATT2_ATTWAIT2_Pos (8U)
<> 147:30b64687e01f 9472 #define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9473 #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
<> 147:30b64687e01f 9474 #define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9475 #define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9476 #define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9477 #define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9478 #define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9479 #define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9480 #define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9481 #define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9482
<> 147:30b64687e01f 9483 #define FMC_PATT2_ATTHOLD2_Pos (16U)
<> 147:30b64687e01f 9484 #define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9485 #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
<> 147:30b64687e01f 9486 #define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9487 #define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9488 #define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9489 #define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9490 #define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9491 #define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9492 #define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9493 #define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9494
<> 147:30b64687e01f 9495 #define FMC_PATT2_ATTHIZ2_Pos (24U)
<> 147:30b64687e01f 9496 #define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9497 #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
<> 147:30b64687e01f 9498 #define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9499 #define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9500 #define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9501 #define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9502 #define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9503 #define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9504 #define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9505 #define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9506
<> 147:30b64687e01f 9507 /****************** Bit definition for FMC_PATT3 register ******************/
<> 147:30b64687e01f 9508 #define FMC_PATT3_ATTSET3_Pos (0U)
<> 147:30b64687e01f 9509 #define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9510 #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
<> 147:30b64687e01f 9511 #define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9512 #define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9513 #define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9514 #define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9515 #define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9516 #define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9517 #define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9518 #define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9519
<> 147:30b64687e01f 9520 #define FMC_PATT3_ATTWAIT3_Pos (8U)
<> 147:30b64687e01f 9521 #define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9522 #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
<> 147:30b64687e01f 9523 #define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9524 #define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9525 #define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9526 #define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9527 #define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9528 #define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9529 #define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9530 #define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9531
<> 147:30b64687e01f 9532 #define FMC_PATT3_ATTHOLD3_Pos (16U)
<> 147:30b64687e01f 9533 #define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9534 #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
<> 147:30b64687e01f 9535 #define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9536 #define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9537 #define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9538 #define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9539 #define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9540 #define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9541 #define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9542 #define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9543
<> 147:30b64687e01f 9544 #define FMC_PATT3_ATTHIZ3_Pos (24U)
<> 147:30b64687e01f 9545 #define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9546 #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
<> 147:30b64687e01f 9547 #define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9548 #define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9549 #define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9550 #define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9551 #define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9552 #define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9553 #define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9554 #define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9555
<> 147:30b64687e01f 9556 /****************** Bit definition for FMC_PATT4 register ******************/
<> 147:30b64687e01f 9557 #define FMC_PATT4_ATTSET4_Pos (0U)
<> 147:30b64687e01f 9558 #define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9559 #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
<> 147:30b64687e01f 9560 #define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9561 #define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9562 #define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9563 #define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9564 #define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9565 #define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9566 #define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9567 #define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9568
<> 147:30b64687e01f 9569 #define FMC_PATT4_ATTWAIT4_Pos (8U)
<> 147:30b64687e01f 9570 #define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9571 #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
<> 147:30b64687e01f 9572 #define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9573 #define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9574 #define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9575 #define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9576 #define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9577 #define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9578 #define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9579 #define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9580
<> 147:30b64687e01f 9581 #define FMC_PATT4_ATTHOLD4_Pos (16U)
<> 147:30b64687e01f 9582 #define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9583 #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
<> 147:30b64687e01f 9584 #define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9585 #define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9586 #define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9587 #define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9588 #define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9589 #define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9590 #define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9591 #define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9592
<> 147:30b64687e01f 9593 #define FMC_PATT4_ATTHIZ4_Pos (24U)
<> 147:30b64687e01f 9594 #define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9595 #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
<> 147:30b64687e01f 9596 #define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9597 #define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9598 #define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9599 #define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9600 #define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9601 #define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9602 #define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9603 #define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9604
<> 147:30b64687e01f 9605 /****************** Bit definition for FMC_PIO4 register *******************/
<> 147:30b64687e01f 9606 #define FMC_PIO4_IOSET4_Pos (0U)
<> 147:30b64687e01f 9607 #define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 9608 #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
<> 147:30b64687e01f 9609 #define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9610 #define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9611 #define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9612 #define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9613 #define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9614 #define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9615 #define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9616 #define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9617
<> 147:30b64687e01f 9618 #define FMC_PIO4_IOWAIT4_Pos (8U)
<> 147:30b64687e01f 9619 #define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 9620 #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
<> 147:30b64687e01f 9621 #define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9622 #define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9623 #define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9624 #define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9625 #define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9626 #define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9627 #define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9628 #define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9629
<> 147:30b64687e01f 9630 #define FMC_PIO4_IOHOLD4_Pos (16U)
<> 147:30b64687e01f 9631 #define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 9632 #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
<> 147:30b64687e01f 9633 #define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9634 #define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9635 #define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9636 #define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9637 #define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9638 #define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9639 #define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9640 #define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9641
<> 147:30b64687e01f 9642 #define FMC_PIO4_IOHIZ4_Pos (24U)
<> 147:30b64687e01f 9643 #define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 9644 #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
<> 147:30b64687e01f 9645 #define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9646 #define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9647 #define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9648 #define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9649 #define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9650 #define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9651 #define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9652 #define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9653
<> 147:30b64687e01f 9654 /****************** Bit definition for FMC_ECCR2 register ******************/
<> 147:30b64687e01f 9655 #define FMC_ECCR2_ECC2_Pos (0U)
<> 147:30b64687e01f 9656 #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 9657 #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
<> 147:30b64687e01f 9658
<> 147:30b64687e01f 9659 /****************** Bit definition for FMC_ECCR3 register ******************/
<> 147:30b64687e01f 9660 #define FMC_ECCR3_ECC3_Pos (0U)
<> 147:30b64687e01f 9661 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 9662 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
<> 147:30b64687e01f 9663
<> 147:30b64687e01f 9664 /******************************************************************************/
<> 147:30b64687e01f 9665 /* */
<> 147:30b64687e01f 9666 /* General Purpose I/O (GPIO) */
<> 147:30b64687e01f 9667 /* */
<> 147:30b64687e01f 9668 /******************************************************************************/
<> 147:30b64687e01f 9669 /******************* Bit definition for GPIO_MODER register *****************/
<> 147:30b64687e01f 9670 #define GPIO_MODER_MODER0_Pos (0U)
<> 147:30b64687e01f 9671 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 9672 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
<> 147:30b64687e01f 9673 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9674 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9675 #define GPIO_MODER_MODER1_Pos (2U)
<> 147:30b64687e01f 9676 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 9677 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
<> 147:30b64687e01f 9678 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9679 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9680 #define GPIO_MODER_MODER2_Pos (4U)
<> 147:30b64687e01f 9681 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 9682 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
<> 147:30b64687e01f 9683 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9684 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9685 #define GPIO_MODER_MODER3_Pos (6U)
<> 147:30b64687e01f 9686 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
<> 147:30b64687e01f 9687 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
<> 147:30b64687e01f 9688 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9689 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9690 #define GPIO_MODER_MODER4_Pos (8U)
<> 147:30b64687e01f 9691 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 9692 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
<> 147:30b64687e01f 9693 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9694 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9695 #define GPIO_MODER_MODER5_Pos (10U)
<> 147:30b64687e01f 9696 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
<> 147:30b64687e01f 9697 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
<> 147:30b64687e01f 9698 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9699 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9700 #define GPIO_MODER_MODER6_Pos (12U)
<> 147:30b64687e01f 9701 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 9702 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
<> 147:30b64687e01f 9703 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9704 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9705 #define GPIO_MODER_MODER7_Pos (14U)
<> 147:30b64687e01f 9706 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
<> 147:30b64687e01f 9707 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
<> 147:30b64687e01f 9708 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9709 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9710 #define GPIO_MODER_MODER8_Pos (16U)
<> 147:30b64687e01f 9711 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
<> 147:30b64687e01f 9712 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
<> 147:30b64687e01f 9713 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9714 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9715 #define GPIO_MODER_MODER9_Pos (18U)
<> 147:30b64687e01f 9716 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 9717 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
<> 147:30b64687e01f 9718 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9719 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9720 #define GPIO_MODER_MODER10_Pos (20U)
<> 147:30b64687e01f 9721 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 9722 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
<> 147:30b64687e01f 9723 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9724 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9725 #define GPIO_MODER_MODER11_Pos (22U)
<> 147:30b64687e01f 9726 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
<> 147:30b64687e01f 9727 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
<> 147:30b64687e01f 9728 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9729 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9730 #define GPIO_MODER_MODER12_Pos (24U)
<> 147:30b64687e01f 9731 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
<> 147:30b64687e01f 9732 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
<> 147:30b64687e01f 9733 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9734 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9735 #define GPIO_MODER_MODER13_Pos (26U)
<> 147:30b64687e01f 9736 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
<> 147:30b64687e01f 9737 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
<> 147:30b64687e01f 9738 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9739 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9740 #define GPIO_MODER_MODER14_Pos (28U)
<> 147:30b64687e01f 9741 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 9742 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
<> 147:30b64687e01f 9743 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9744 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9745 #define GPIO_MODER_MODER15_Pos (30U)
<> 147:30b64687e01f 9746 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
<> 147:30b64687e01f 9747 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
<> 147:30b64687e01f 9748 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9749 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9750
<> 147:30b64687e01f 9751 /****************** Bit definition for GPIO_OTYPER register *****************/
<> 147:30b64687e01f 9752 #define GPIO_OTYPER_OT_0 (0x00000001U)
<> 147:30b64687e01f 9753 #define GPIO_OTYPER_OT_1 (0x00000002U)
<> 147:30b64687e01f 9754 #define GPIO_OTYPER_OT_2 (0x00000004U)
<> 147:30b64687e01f 9755 #define GPIO_OTYPER_OT_3 (0x00000008U)
<> 147:30b64687e01f 9756 #define GPIO_OTYPER_OT_4 (0x00000010U)
<> 147:30b64687e01f 9757 #define GPIO_OTYPER_OT_5 (0x00000020U)
<> 147:30b64687e01f 9758 #define GPIO_OTYPER_OT_6 (0x00000040U)
<> 147:30b64687e01f 9759 #define GPIO_OTYPER_OT_7 (0x00000080U)
<> 147:30b64687e01f 9760 #define GPIO_OTYPER_OT_8 (0x00000100U)
<> 147:30b64687e01f 9761 #define GPIO_OTYPER_OT_9 (0x00000200U)
<> 147:30b64687e01f 9762 #define GPIO_OTYPER_OT_10 (0x00000400U)
<> 147:30b64687e01f 9763 #define GPIO_OTYPER_OT_11 (0x00000800U)
<> 147:30b64687e01f 9764 #define GPIO_OTYPER_OT_12 (0x00001000U)
<> 147:30b64687e01f 9765 #define GPIO_OTYPER_OT_13 (0x00002000U)
<> 147:30b64687e01f 9766 #define GPIO_OTYPER_OT_14 (0x00004000U)
<> 147:30b64687e01f 9767 #define GPIO_OTYPER_OT_15 (0x00008000U)
<> 147:30b64687e01f 9768
<> 147:30b64687e01f 9769 /**************** Bit definition for GPIO_OSPEEDR register ******************/
<> 147:30b64687e01f 9770 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
<> 147:30b64687e01f 9771 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 9772 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
<> 147:30b64687e01f 9773 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9774 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9775 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
<> 147:30b64687e01f 9776 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 9777 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
<> 147:30b64687e01f 9778 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9779 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9780 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
<> 147:30b64687e01f 9781 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 9782 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
<> 147:30b64687e01f 9783 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9784 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9785 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
<> 147:30b64687e01f 9786 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
<> 147:30b64687e01f 9787 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
<> 147:30b64687e01f 9788 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9789 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9790 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
<> 147:30b64687e01f 9791 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 9792 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
<> 147:30b64687e01f 9793 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9794 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9795 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
<> 147:30b64687e01f 9796 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
<> 147:30b64687e01f 9797 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
<> 147:30b64687e01f 9798 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9799 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9800 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
<> 147:30b64687e01f 9801 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 9802 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
<> 147:30b64687e01f 9803 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9804 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9805 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
<> 147:30b64687e01f 9806 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
<> 147:30b64687e01f 9807 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
<> 147:30b64687e01f 9808 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9809 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9810 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
<> 147:30b64687e01f 9811 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
<> 147:30b64687e01f 9812 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
<> 147:30b64687e01f 9813 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9814 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9815 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
<> 147:30b64687e01f 9816 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 9817 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
<> 147:30b64687e01f 9818 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9819 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9820 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
<> 147:30b64687e01f 9821 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 9822 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
<> 147:30b64687e01f 9823 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9824 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9825 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
<> 147:30b64687e01f 9826 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
<> 147:30b64687e01f 9827 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
<> 147:30b64687e01f 9828 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9829 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9830 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
<> 147:30b64687e01f 9831 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
<> 147:30b64687e01f 9832 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
<> 147:30b64687e01f 9833 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9834 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9835 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
<> 147:30b64687e01f 9836 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
<> 147:30b64687e01f 9837 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
<> 147:30b64687e01f 9838 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9839 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9840 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
<> 147:30b64687e01f 9841 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 9842 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
<> 147:30b64687e01f 9843 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9844 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9845 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
<> 147:30b64687e01f 9846 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
<> 147:30b64687e01f 9847 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
<> 147:30b64687e01f 9848 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9849 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9850
<> 147:30b64687e01f 9851 /******************* Bit definition for GPIO_PUPDR register ******************/
<> 147:30b64687e01f 9852 #define GPIO_PUPDR_PUPDR0_Pos (0U)
<> 147:30b64687e01f 9853 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 9854 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
<> 147:30b64687e01f 9855 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 9856 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 9857 #define GPIO_PUPDR_PUPDR1_Pos (2U)
<> 147:30b64687e01f 9858 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 9859 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
<> 147:30b64687e01f 9860 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 9861 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 9862 #define GPIO_PUPDR_PUPDR2_Pos (4U)
<> 147:30b64687e01f 9863 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 9864 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
<> 147:30b64687e01f 9865 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 9866 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 9867 #define GPIO_PUPDR_PUPDR3_Pos (6U)
<> 147:30b64687e01f 9868 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
<> 147:30b64687e01f 9869 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
<> 147:30b64687e01f 9870 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 9871 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 9872 #define GPIO_PUPDR_PUPDR4_Pos (8U)
<> 147:30b64687e01f 9873 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 9874 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
<> 147:30b64687e01f 9875 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 9876 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 9877 #define GPIO_PUPDR_PUPDR5_Pos (10U)
<> 147:30b64687e01f 9878 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
<> 147:30b64687e01f 9879 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
<> 147:30b64687e01f 9880 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 9881 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 9882 #define GPIO_PUPDR_PUPDR6_Pos (12U)
<> 147:30b64687e01f 9883 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 9884 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
<> 147:30b64687e01f 9885 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 9886 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 9887 #define GPIO_PUPDR_PUPDR7_Pos (14U)
<> 147:30b64687e01f 9888 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
<> 147:30b64687e01f 9889 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
<> 147:30b64687e01f 9890 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 9891 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 9892 #define GPIO_PUPDR_PUPDR8_Pos (16U)
<> 147:30b64687e01f 9893 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
<> 147:30b64687e01f 9894 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
<> 147:30b64687e01f 9895 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 9896 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 9897 #define GPIO_PUPDR_PUPDR9_Pos (18U)
<> 147:30b64687e01f 9898 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 9899 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
<> 147:30b64687e01f 9900 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 9901 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 9902 #define GPIO_PUPDR_PUPDR10_Pos (20U)
<> 147:30b64687e01f 9903 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 9904 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
<> 147:30b64687e01f 9905 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 9906 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 9907 #define GPIO_PUPDR_PUPDR11_Pos (22U)
<> 147:30b64687e01f 9908 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
<> 147:30b64687e01f 9909 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
<> 147:30b64687e01f 9910 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 9911 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 9912 #define GPIO_PUPDR_PUPDR12_Pos (24U)
<> 147:30b64687e01f 9913 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
<> 147:30b64687e01f 9914 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
<> 147:30b64687e01f 9915 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 9916 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 9917 #define GPIO_PUPDR_PUPDR13_Pos (26U)
<> 147:30b64687e01f 9918 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
<> 147:30b64687e01f 9919 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
<> 147:30b64687e01f 9920 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 9921 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 9922 #define GPIO_PUPDR_PUPDR14_Pos (28U)
<> 147:30b64687e01f 9923 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 9924 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
<> 147:30b64687e01f 9925 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 9926 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 9927 #define GPIO_PUPDR_PUPDR15_Pos (30U)
<> 147:30b64687e01f 9928 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
<> 147:30b64687e01f 9929 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
<> 147:30b64687e01f 9930 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 9931 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 9932
<> 147:30b64687e01f 9933 /******************* Bit definition for GPIO_IDR register *******************/
<> 147:30b64687e01f 9934 #define GPIO_IDR_0 (0x00000001U)
<> 147:30b64687e01f 9935 #define GPIO_IDR_1 (0x00000002U)
<> 147:30b64687e01f 9936 #define GPIO_IDR_2 (0x00000004U)
<> 147:30b64687e01f 9937 #define GPIO_IDR_3 (0x00000008U)
<> 147:30b64687e01f 9938 #define GPIO_IDR_4 (0x00000010U)
<> 147:30b64687e01f 9939 #define GPIO_IDR_5 (0x00000020U)
<> 147:30b64687e01f 9940 #define GPIO_IDR_6 (0x00000040U)
<> 147:30b64687e01f 9941 #define GPIO_IDR_7 (0x00000080U)
<> 147:30b64687e01f 9942 #define GPIO_IDR_8 (0x00000100U)
<> 147:30b64687e01f 9943 #define GPIO_IDR_9 (0x00000200U)
<> 147:30b64687e01f 9944 #define GPIO_IDR_10 (0x00000400U)
<> 147:30b64687e01f 9945 #define GPIO_IDR_11 (0x00000800U)
<> 147:30b64687e01f 9946 #define GPIO_IDR_12 (0x00001000U)
<> 147:30b64687e01f 9947 #define GPIO_IDR_13 (0x00002000U)
<> 147:30b64687e01f 9948 #define GPIO_IDR_14 (0x00004000U)
<> 147:30b64687e01f 9949 #define GPIO_IDR_15 (0x00008000U)
<> 147:30b64687e01f 9950
<> 147:30b64687e01f 9951 /****************** Bit definition for GPIO_ODR register ********************/
<> 147:30b64687e01f 9952 #define GPIO_ODR_0 (0x00000001U)
<> 147:30b64687e01f 9953 #define GPIO_ODR_1 (0x00000002U)
<> 147:30b64687e01f 9954 #define GPIO_ODR_2 (0x00000004U)
<> 147:30b64687e01f 9955 #define GPIO_ODR_3 (0x00000008U)
<> 147:30b64687e01f 9956 #define GPIO_ODR_4 (0x00000010U)
<> 147:30b64687e01f 9957 #define GPIO_ODR_5 (0x00000020U)
<> 147:30b64687e01f 9958 #define GPIO_ODR_6 (0x00000040U)
<> 147:30b64687e01f 9959 #define GPIO_ODR_7 (0x00000080U)
<> 147:30b64687e01f 9960 #define GPIO_ODR_8 (0x00000100U)
<> 147:30b64687e01f 9961 #define GPIO_ODR_9 (0x00000200U)
<> 147:30b64687e01f 9962 #define GPIO_ODR_10 (0x00000400U)
<> 147:30b64687e01f 9963 #define GPIO_ODR_11 (0x00000800U)
<> 147:30b64687e01f 9964 #define GPIO_ODR_12 (0x00001000U)
<> 147:30b64687e01f 9965 #define GPIO_ODR_13 (0x00002000U)
<> 147:30b64687e01f 9966 #define GPIO_ODR_14 (0x00004000U)
<> 147:30b64687e01f 9967 #define GPIO_ODR_15 (0x00008000U)
<> 147:30b64687e01f 9968
<> 147:30b64687e01f 9969 /****************** Bit definition for GPIO_BSRR register ********************/
<> 147:30b64687e01f 9970 #define GPIO_BSRR_BS_0 (0x00000001U)
<> 147:30b64687e01f 9971 #define GPIO_BSRR_BS_1 (0x00000002U)
<> 147:30b64687e01f 9972 #define GPIO_BSRR_BS_2 (0x00000004U)
<> 147:30b64687e01f 9973 #define GPIO_BSRR_BS_3 (0x00000008U)
<> 147:30b64687e01f 9974 #define GPIO_BSRR_BS_4 (0x00000010U)
<> 147:30b64687e01f 9975 #define GPIO_BSRR_BS_5 (0x00000020U)
<> 147:30b64687e01f 9976 #define GPIO_BSRR_BS_6 (0x00000040U)
<> 147:30b64687e01f 9977 #define GPIO_BSRR_BS_7 (0x00000080U)
<> 147:30b64687e01f 9978 #define GPIO_BSRR_BS_8 (0x00000100U)
<> 147:30b64687e01f 9979 #define GPIO_BSRR_BS_9 (0x00000200U)
<> 147:30b64687e01f 9980 #define GPIO_BSRR_BS_10 (0x00000400U)
<> 147:30b64687e01f 9981 #define GPIO_BSRR_BS_11 (0x00000800U)
<> 147:30b64687e01f 9982 #define GPIO_BSRR_BS_12 (0x00001000U)
<> 147:30b64687e01f 9983 #define GPIO_BSRR_BS_13 (0x00002000U)
<> 147:30b64687e01f 9984 #define GPIO_BSRR_BS_14 (0x00004000U)
<> 147:30b64687e01f 9985 #define GPIO_BSRR_BS_15 (0x00008000U)
<> 147:30b64687e01f 9986 #define GPIO_BSRR_BR_0 (0x00010000U)
<> 147:30b64687e01f 9987 #define GPIO_BSRR_BR_1 (0x00020000U)
<> 147:30b64687e01f 9988 #define GPIO_BSRR_BR_2 (0x00040000U)
<> 147:30b64687e01f 9989 #define GPIO_BSRR_BR_3 (0x00080000U)
<> 147:30b64687e01f 9990 #define GPIO_BSRR_BR_4 (0x00100000U)
<> 147:30b64687e01f 9991 #define GPIO_BSRR_BR_5 (0x00200000U)
<> 147:30b64687e01f 9992 #define GPIO_BSRR_BR_6 (0x00400000U)
<> 147:30b64687e01f 9993 #define GPIO_BSRR_BR_7 (0x00800000U)
<> 147:30b64687e01f 9994 #define GPIO_BSRR_BR_8 (0x01000000U)
<> 147:30b64687e01f 9995 #define GPIO_BSRR_BR_9 (0x02000000U)
<> 147:30b64687e01f 9996 #define GPIO_BSRR_BR_10 (0x04000000U)
<> 147:30b64687e01f 9997 #define GPIO_BSRR_BR_11 (0x08000000U)
<> 147:30b64687e01f 9998 #define GPIO_BSRR_BR_12 (0x10000000U)
<> 147:30b64687e01f 9999 #define GPIO_BSRR_BR_13 (0x20000000U)
<> 147:30b64687e01f 10000 #define GPIO_BSRR_BR_14 (0x40000000U)
<> 147:30b64687e01f 10001 #define GPIO_BSRR_BR_15 (0x80000000U)
<> 147:30b64687e01f 10002
<> 147:30b64687e01f 10003 /****************** Bit definition for GPIO_LCKR register ********************/
<> 147:30b64687e01f 10004 #define GPIO_LCKR_LCK0_Pos (0U)
<> 147:30b64687e01f 10005 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10006 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
<> 147:30b64687e01f 10007 #define GPIO_LCKR_LCK1_Pos (1U)
<> 147:30b64687e01f 10008 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10009 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
<> 147:30b64687e01f 10010 #define GPIO_LCKR_LCK2_Pos (2U)
<> 147:30b64687e01f 10011 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10012 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
<> 147:30b64687e01f 10013 #define GPIO_LCKR_LCK3_Pos (3U)
<> 147:30b64687e01f 10014 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10015 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
<> 147:30b64687e01f 10016 #define GPIO_LCKR_LCK4_Pos (4U)
<> 147:30b64687e01f 10017 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10018 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
<> 147:30b64687e01f 10019 #define GPIO_LCKR_LCK5_Pos (5U)
<> 147:30b64687e01f 10020 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10021 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
<> 147:30b64687e01f 10022 #define GPIO_LCKR_LCK6_Pos (6U)
<> 147:30b64687e01f 10023 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 10024 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
<> 147:30b64687e01f 10025 #define GPIO_LCKR_LCK7_Pos (7U)
<> 147:30b64687e01f 10026 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 10027 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
<> 147:30b64687e01f 10028 #define GPIO_LCKR_LCK8_Pos (8U)
<> 147:30b64687e01f 10029 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10030 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
<> 147:30b64687e01f 10031 #define GPIO_LCKR_LCK9_Pos (9U)
<> 147:30b64687e01f 10032 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10033 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
<> 147:30b64687e01f 10034 #define GPIO_LCKR_LCK10_Pos (10U)
<> 147:30b64687e01f 10035 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10036 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
<> 147:30b64687e01f 10037 #define GPIO_LCKR_LCK11_Pos (11U)
<> 147:30b64687e01f 10038 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10039 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
<> 147:30b64687e01f 10040 #define GPIO_LCKR_LCK12_Pos (12U)
<> 147:30b64687e01f 10041 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10042 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
<> 147:30b64687e01f 10043 #define GPIO_LCKR_LCK13_Pos (13U)
<> 147:30b64687e01f 10044 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10045 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
<> 147:30b64687e01f 10046 #define GPIO_LCKR_LCK14_Pos (14U)
<> 147:30b64687e01f 10047 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10048 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
<> 147:30b64687e01f 10049 #define GPIO_LCKR_LCK15_Pos (15U)
<> 147:30b64687e01f 10050 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10051 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
<> 147:30b64687e01f 10052 #define GPIO_LCKR_LCKK_Pos (16U)
<> 147:30b64687e01f 10053 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10054 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
<> 147:30b64687e01f 10055
<> 147:30b64687e01f 10056 /****************** Bit definition for GPIO_AFRL register ********************/
<> 147:30b64687e01f 10057 #define GPIO_AFRL_AFRL0_Pos (0U)
<> 147:30b64687e01f 10058 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 10059 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
<> 147:30b64687e01f 10060 #define GPIO_AFRL_AFRL1_Pos (4U)
<> 147:30b64687e01f 10061 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 10062 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
<> 147:30b64687e01f 10063 #define GPIO_AFRL_AFRL2_Pos (8U)
<> 147:30b64687e01f 10064 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 10065 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
<> 147:30b64687e01f 10066 #define GPIO_AFRL_AFRL3_Pos (12U)
<> 147:30b64687e01f 10067 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 10068 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
<> 147:30b64687e01f 10069 #define GPIO_AFRL_AFRL4_Pos (16U)
<> 147:30b64687e01f 10070 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 10071 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
<> 147:30b64687e01f 10072 #define GPIO_AFRL_AFRL5_Pos (20U)
<> 147:30b64687e01f 10073 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 10074 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
<> 147:30b64687e01f 10075 #define GPIO_AFRL_AFRL6_Pos (24U)
<> 147:30b64687e01f 10076 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 10077 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
<> 147:30b64687e01f 10078 #define GPIO_AFRL_AFRL7_Pos (28U)
<> 147:30b64687e01f 10079 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
<> 147:30b64687e01f 10080 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
<> 147:30b64687e01f 10081
<> 147:30b64687e01f 10082 /****************** Bit definition for GPIO_AFRH register ********************/
<> 147:30b64687e01f 10083 #define GPIO_AFRH_AFRH0_Pos (0U)
<> 147:30b64687e01f 10084 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 10085 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
<> 147:30b64687e01f 10086 #define GPIO_AFRH_AFRH1_Pos (4U)
<> 147:30b64687e01f 10087 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 10088 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
<> 147:30b64687e01f 10089 #define GPIO_AFRH_AFRH2_Pos (8U)
<> 147:30b64687e01f 10090 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 10091 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
<> 147:30b64687e01f 10092 #define GPIO_AFRH_AFRH3_Pos (12U)
<> 147:30b64687e01f 10093 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 10094 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
<> 147:30b64687e01f 10095 #define GPIO_AFRH_AFRH4_Pos (16U)
<> 147:30b64687e01f 10096 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 10097 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
<> 147:30b64687e01f 10098 #define GPIO_AFRH_AFRH5_Pos (20U)
<> 147:30b64687e01f 10099 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 10100 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
<> 147:30b64687e01f 10101 #define GPIO_AFRH_AFRH6_Pos (24U)
<> 147:30b64687e01f 10102 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 10103 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
<> 147:30b64687e01f 10104 #define GPIO_AFRH_AFRH7_Pos (28U)
<> 147:30b64687e01f 10105 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
<> 147:30b64687e01f 10106 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
<> 147:30b64687e01f 10107
<> 147:30b64687e01f 10108 /****************** Bit definition for GPIO_BRR register *********************/
<> 147:30b64687e01f 10109 #define GPIO_BRR_BR_0 (0x00000001U)
<> 147:30b64687e01f 10110 #define GPIO_BRR_BR_1 (0x00000002U)
<> 147:30b64687e01f 10111 #define GPIO_BRR_BR_2 (0x00000004U)
<> 147:30b64687e01f 10112 #define GPIO_BRR_BR_3 (0x00000008U)
<> 147:30b64687e01f 10113 #define GPIO_BRR_BR_4 (0x00000010U)
<> 147:30b64687e01f 10114 #define GPIO_BRR_BR_5 (0x00000020U)
<> 147:30b64687e01f 10115 #define GPIO_BRR_BR_6 (0x00000040U)
<> 147:30b64687e01f 10116 #define GPIO_BRR_BR_7 (0x00000080U)
<> 147:30b64687e01f 10117 #define GPIO_BRR_BR_8 (0x00000100U)
<> 147:30b64687e01f 10118 #define GPIO_BRR_BR_9 (0x00000200U)
<> 147:30b64687e01f 10119 #define GPIO_BRR_BR_10 (0x00000400U)
<> 147:30b64687e01f 10120 #define GPIO_BRR_BR_11 (0x00000800U)
<> 147:30b64687e01f 10121 #define GPIO_BRR_BR_12 (0x00001000U)
<> 147:30b64687e01f 10122 #define GPIO_BRR_BR_13 (0x00002000U)
<> 147:30b64687e01f 10123 #define GPIO_BRR_BR_14 (0x00004000U)
<> 147:30b64687e01f 10124 #define GPIO_BRR_BR_15 (0x00008000U)
<> 147:30b64687e01f 10125
<> 147:30b64687e01f 10126 /******************************************************************************/
<> 147:30b64687e01f 10127 /* */
<> 147:30b64687e01f 10128 /* Inter-integrated Circuit Interface (I2C) */
<> 147:30b64687e01f 10129 /* */
<> 147:30b64687e01f 10130 /******************************************************************************/
<> 147:30b64687e01f 10131 /******************* Bit definition for I2C_CR1 register *******************/
<> 147:30b64687e01f 10132 #define I2C_CR1_PE_Pos (0U)
<> 147:30b64687e01f 10133 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10134 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
<> 147:30b64687e01f 10135 #define I2C_CR1_TXIE_Pos (1U)
<> 147:30b64687e01f 10136 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10137 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
<> 147:30b64687e01f 10138 #define I2C_CR1_RXIE_Pos (2U)
<> 147:30b64687e01f 10139 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10140 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
<> 147:30b64687e01f 10141 #define I2C_CR1_ADDRIE_Pos (3U)
<> 147:30b64687e01f 10142 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10143 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
<> 147:30b64687e01f 10144 #define I2C_CR1_NACKIE_Pos (4U)
<> 147:30b64687e01f 10145 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10146 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
<> 147:30b64687e01f 10147 #define I2C_CR1_STOPIE_Pos (5U)
<> 147:30b64687e01f 10148 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10149 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
<> 147:30b64687e01f 10150 #define I2C_CR1_TCIE_Pos (6U)
<> 147:30b64687e01f 10151 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 10152 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 147:30b64687e01f 10153 #define I2C_CR1_ERRIE_Pos (7U)
<> 147:30b64687e01f 10154 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 10155 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
<> 147:30b64687e01f 10156 #define I2C_CR1_DNF_Pos (8U)
<> 147:30b64687e01f 10157 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 10158 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
<> 147:30b64687e01f 10159 #define I2C_CR1_ANFOFF_Pos (12U)
<> 147:30b64687e01f 10160 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10161 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
<> 147:30b64687e01f 10162 #define I2C_CR1_SWRST_Pos (13U)
<> 147:30b64687e01f 10163 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10164 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
<> 147:30b64687e01f 10165 #define I2C_CR1_TXDMAEN_Pos (14U)
<> 147:30b64687e01f 10166 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10167 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
<> 147:30b64687e01f 10168 #define I2C_CR1_RXDMAEN_Pos (15U)
<> 147:30b64687e01f 10169 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10170 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
<> 147:30b64687e01f 10171 #define I2C_CR1_SBC_Pos (16U)
<> 147:30b64687e01f 10172 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10173 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
<> 147:30b64687e01f 10174 #define I2C_CR1_NOSTRETCH_Pos (17U)
<> 147:30b64687e01f 10175 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10176 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
<> 147:30b64687e01f 10177 #define I2C_CR1_WUPEN_Pos (18U)
<> 147:30b64687e01f 10178 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10179 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
<> 147:30b64687e01f 10180 #define I2C_CR1_GCEN_Pos (19U)
<> 147:30b64687e01f 10181 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 10182 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
<> 147:30b64687e01f 10183 #define I2C_CR1_SMBHEN_Pos (20U)
<> 147:30b64687e01f 10184 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 10185 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
<> 147:30b64687e01f 10186 #define I2C_CR1_SMBDEN_Pos (21U)
<> 147:30b64687e01f 10187 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 10188 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
<> 147:30b64687e01f 10189 #define I2C_CR1_ALERTEN_Pos (22U)
<> 147:30b64687e01f 10190 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 10191 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
<> 147:30b64687e01f 10192 #define I2C_CR1_PECEN_Pos (23U)
<> 147:30b64687e01f 10193 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 10194 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
<> 147:30b64687e01f 10195
<> 147:30b64687e01f 10196 /* Legacy defines */
<> 147:30b64687e01f 10197 #define I2C_CR1_DFN I2C_CR1_DNF
<> 147:30b64687e01f 10198
<> 147:30b64687e01f 10199 /****************** Bit definition for I2C_CR2 register ********************/
<> 147:30b64687e01f 10200 #define I2C_CR2_SADD_Pos (0U)
<> 147:30b64687e01f 10201 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
<> 147:30b64687e01f 10202 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
<> 147:30b64687e01f 10203 #define I2C_CR2_RD_WRN_Pos (10U)
<> 147:30b64687e01f 10204 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10205 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
<> 147:30b64687e01f 10206 #define I2C_CR2_ADD10_Pos (11U)
<> 147:30b64687e01f 10207 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10208 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
<> 147:30b64687e01f 10209 #define I2C_CR2_HEAD10R_Pos (12U)
<> 147:30b64687e01f 10210 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10211 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
<> 147:30b64687e01f 10212 #define I2C_CR2_START_Pos (13U)
<> 147:30b64687e01f 10213 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10214 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
<> 147:30b64687e01f 10215 #define I2C_CR2_STOP_Pos (14U)
<> 147:30b64687e01f 10216 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10217 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
<> 147:30b64687e01f 10218 #define I2C_CR2_NACK_Pos (15U)
<> 147:30b64687e01f 10219 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10220 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
<> 147:30b64687e01f 10221 #define I2C_CR2_NBYTES_Pos (16U)
<> 147:30b64687e01f 10222 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
<> 147:30b64687e01f 10223 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
<> 147:30b64687e01f 10224 #define I2C_CR2_RELOAD_Pos (24U)
<> 147:30b64687e01f 10225 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 10226 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
<> 147:30b64687e01f 10227 #define I2C_CR2_AUTOEND_Pos (25U)
<> 147:30b64687e01f 10228 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 10229 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
<> 147:30b64687e01f 10230 #define I2C_CR2_PECBYTE_Pos (26U)
<> 147:30b64687e01f 10231 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 10232 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
<> 147:30b64687e01f 10233
<> 147:30b64687e01f 10234 /******************* Bit definition for I2C_OAR1 register ******************/
<> 147:30b64687e01f 10235 #define I2C_OAR1_OA1_Pos (0U)
<> 147:30b64687e01f 10236 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
<> 147:30b64687e01f 10237 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
<> 147:30b64687e01f 10238 #define I2C_OAR1_OA1MODE_Pos (10U)
<> 147:30b64687e01f 10239 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10240 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
<> 147:30b64687e01f 10241 #define I2C_OAR1_OA1EN_Pos (15U)
<> 147:30b64687e01f 10242 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10243 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
<> 147:30b64687e01f 10244
<> 147:30b64687e01f 10245 /******************* Bit definition for I2C_OAR2 register *******************/
<> 147:30b64687e01f 10246 #define I2C_OAR2_OA2_Pos (1U)
<> 147:30b64687e01f 10247 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
<> 147:30b64687e01f 10248 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
<> 147:30b64687e01f 10249 #define I2C_OAR2_OA2MSK_Pos (8U)
<> 147:30b64687e01f 10250 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
<> 147:30b64687e01f 10251 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
<> 147:30b64687e01f 10252 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
<> 147:30b64687e01f 10253 #define I2C_OAR2_OA2MASK01_Pos (8U)
<> 147:30b64687e01f 10254 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10255 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
<> 147:30b64687e01f 10256 #define I2C_OAR2_OA2MASK02_Pos (9U)
<> 147:30b64687e01f 10257 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10258 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
<> 147:30b64687e01f 10259 #define I2C_OAR2_OA2MASK03_Pos (8U)
<> 147:30b64687e01f 10260 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 10261 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
<> 147:30b64687e01f 10262 #define I2C_OAR2_OA2MASK04_Pos (10U)
<> 147:30b64687e01f 10263 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10264 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
<> 147:30b64687e01f 10265 #define I2C_OAR2_OA2MASK05_Pos (8U)
<> 147:30b64687e01f 10266 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
<> 147:30b64687e01f 10267 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
<> 147:30b64687e01f 10268 #define I2C_OAR2_OA2MASK06_Pos (9U)
<> 147:30b64687e01f 10269 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
<> 147:30b64687e01f 10270 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
<> 147:30b64687e01f 10271 #define I2C_OAR2_OA2MASK07_Pos (8U)
<> 147:30b64687e01f 10272 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
<> 147:30b64687e01f 10273 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
<> 147:30b64687e01f 10274 #define I2C_OAR2_OA2EN_Pos (15U)
<> 147:30b64687e01f 10275 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10276 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
<> 147:30b64687e01f 10277
<> 147:30b64687e01f 10278 /******************* Bit definition for I2C_TIMINGR register *****************/
<> 147:30b64687e01f 10279 #define I2C_TIMINGR_SCLL_Pos (0U)
<> 147:30b64687e01f 10280 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 10281 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
<> 147:30b64687e01f 10282 #define I2C_TIMINGR_SCLH_Pos (8U)
<> 147:30b64687e01f 10283 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 10284 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
<> 147:30b64687e01f 10285 #define I2C_TIMINGR_SDADEL_Pos (16U)
<> 147:30b64687e01f 10286 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 10287 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
<> 147:30b64687e01f 10288 #define I2C_TIMINGR_SCLDEL_Pos (20U)
<> 147:30b64687e01f 10289 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 10290 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
<> 147:30b64687e01f 10291 #define I2C_TIMINGR_PRESC_Pos (28U)
<> 147:30b64687e01f 10292 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
<> 147:30b64687e01f 10293 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
<> 147:30b64687e01f 10294
<> 147:30b64687e01f 10295 /******************* Bit definition for I2C_TIMEOUTR register *****************/
<> 147:30b64687e01f 10296 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
<> 147:30b64687e01f 10297 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 10298 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
<> 147:30b64687e01f 10299 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
<> 147:30b64687e01f 10300 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10301 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
<> 147:30b64687e01f 10302 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
<> 147:30b64687e01f 10303 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10304 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
<> 147:30b64687e01f 10305 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
<> 147:30b64687e01f 10306 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
<> 147:30b64687e01f 10307 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
<> 147:30b64687e01f 10308 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
<> 147:30b64687e01f 10309 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 10310 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
<> 147:30b64687e01f 10311
<> 147:30b64687e01f 10312 /****************** Bit definition for I2C_ISR register *********************/
<> 147:30b64687e01f 10313 #define I2C_ISR_TXE_Pos (0U)
<> 147:30b64687e01f 10314 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10315 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
<> 147:30b64687e01f 10316 #define I2C_ISR_TXIS_Pos (1U)
<> 147:30b64687e01f 10317 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10318 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
<> 147:30b64687e01f 10319 #define I2C_ISR_RXNE_Pos (2U)
<> 147:30b64687e01f 10320 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10321 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
<> 147:30b64687e01f 10322 #define I2C_ISR_ADDR_Pos (3U)
<> 147:30b64687e01f 10323 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10324 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
<> 147:30b64687e01f 10325 #define I2C_ISR_NACKF_Pos (4U)
<> 147:30b64687e01f 10326 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10327 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
<> 147:30b64687e01f 10328 #define I2C_ISR_STOPF_Pos (5U)
<> 147:30b64687e01f 10329 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10330 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
<> 147:30b64687e01f 10331 #define I2C_ISR_TC_Pos (6U)
<> 147:30b64687e01f 10332 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 10333 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
<> 147:30b64687e01f 10334 #define I2C_ISR_TCR_Pos (7U)
<> 147:30b64687e01f 10335 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 10336 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
<> 147:30b64687e01f 10337 #define I2C_ISR_BERR_Pos (8U)
<> 147:30b64687e01f 10338 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10339 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
<> 147:30b64687e01f 10340 #define I2C_ISR_ARLO_Pos (9U)
<> 147:30b64687e01f 10341 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10342 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
<> 147:30b64687e01f 10343 #define I2C_ISR_OVR_Pos (10U)
<> 147:30b64687e01f 10344 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10345 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
<> 147:30b64687e01f 10346 #define I2C_ISR_PECERR_Pos (11U)
<> 147:30b64687e01f 10347 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10348 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
<> 147:30b64687e01f 10349 #define I2C_ISR_TIMEOUT_Pos (12U)
<> 147:30b64687e01f 10350 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10351 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
<> 147:30b64687e01f 10352 #define I2C_ISR_ALERT_Pos (13U)
<> 147:30b64687e01f 10353 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10354 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
<> 147:30b64687e01f 10355 #define I2C_ISR_BUSY_Pos (15U)
<> 147:30b64687e01f 10356 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10357 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
<> 147:30b64687e01f 10358 #define I2C_ISR_DIR_Pos (16U)
<> 147:30b64687e01f 10359 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10360 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
<> 147:30b64687e01f 10361 #define I2C_ISR_ADDCODE_Pos (17U)
<> 147:30b64687e01f 10362 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
<> 147:30b64687e01f 10363 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
<> 147:30b64687e01f 10364
<> 147:30b64687e01f 10365 /****************** Bit definition for I2C_ICR register *********************/
<> 147:30b64687e01f 10366 #define I2C_ICR_ADDRCF_Pos (3U)
<> 147:30b64687e01f 10367 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10368 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
<> 147:30b64687e01f 10369 #define I2C_ICR_NACKCF_Pos (4U)
<> 147:30b64687e01f 10370 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10371 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
<> 147:30b64687e01f 10372 #define I2C_ICR_STOPCF_Pos (5U)
<> 147:30b64687e01f 10373 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10374 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
<> 147:30b64687e01f 10375 #define I2C_ICR_BERRCF_Pos (8U)
<> 147:30b64687e01f 10376 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10377 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
<> 147:30b64687e01f 10378 #define I2C_ICR_ARLOCF_Pos (9U)
<> 147:30b64687e01f 10379 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10380 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
<> 147:30b64687e01f 10381 #define I2C_ICR_OVRCF_Pos (10U)
<> 147:30b64687e01f 10382 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10383 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
<> 147:30b64687e01f 10384 #define I2C_ICR_PECCF_Pos (11U)
<> 147:30b64687e01f 10385 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10386 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
<> 147:30b64687e01f 10387 #define I2C_ICR_TIMOUTCF_Pos (12U)
<> 147:30b64687e01f 10388 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10389 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
<> 147:30b64687e01f 10390 #define I2C_ICR_ALERTCF_Pos (13U)
<> 147:30b64687e01f 10391 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10392 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
<> 147:30b64687e01f 10393
<> 147:30b64687e01f 10394 /****************** Bit definition for I2C_PECR register ********************/
<> 147:30b64687e01f 10395 #define I2C_PECR_PEC_Pos (0U)
<> 147:30b64687e01f 10396 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 10397 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
<> 147:30b64687e01f 10398
<> 147:30b64687e01f 10399 /****************** Bit definition for I2C_RXDR register *********************/
<> 147:30b64687e01f 10400 #define I2C_RXDR_RXDATA_Pos (0U)
<> 147:30b64687e01f 10401 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 10402 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
<> 147:30b64687e01f 10403
<> 147:30b64687e01f 10404 /****************** Bit definition for I2C_TXDR register *********************/
<> 147:30b64687e01f 10405 #define I2C_TXDR_TXDATA_Pos (0U)
<> 147:30b64687e01f 10406 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 10407 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
<> 147:30b64687e01f 10408
<> 147:30b64687e01f 10409
<> 147:30b64687e01f 10410 /******************************************************************************/
<> 147:30b64687e01f 10411 /* */
<> 147:30b64687e01f 10412 /* Independent WATCHDOG (IWDG) */
<> 147:30b64687e01f 10413 /* */
<> 147:30b64687e01f 10414 /******************************************************************************/
<> 147:30b64687e01f 10415 /******************* Bit definition for IWDG_KR register ********************/
<> 147:30b64687e01f 10416 #define IWDG_KR_KEY_Pos (0U)
<> 147:30b64687e01f 10417 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 10418 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
<> 147:30b64687e01f 10419
<> 147:30b64687e01f 10420 /******************* Bit definition for IWDG_PR register ********************/
<> 147:30b64687e01f 10421 #define IWDG_PR_PR_Pos (0U)
<> 147:30b64687e01f 10422 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
<> 147:30b64687e01f 10423 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
<> 147:30b64687e01f 10424 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10425 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10426 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10427
<> 147:30b64687e01f 10428 /******************* Bit definition for IWDG_RLR register *******************/
<> 147:30b64687e01f 10429 #define IWDG_RLR_RL_Pos (0U)
<> 147:30b64687e01f 10430 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 10431 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
<> 147:30b64687e01f 10432
<> 147:30b64687e01f 10433 /******************* Bit definition for IWDG_SR register ********************/
<> 147:30b64687e01f 10434 #define IWDG_SR_PVU_Pos (0U)
<> 147:30b64687e01f 10435 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10436 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
<> 147:30b64687e01f 10437 #define IWDG_SR_RVU_Pos (1U)
<> 147:30b64687e01f 10438 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10439 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
<> 147:30b64687e01f 10440 #define IWDG_SR_WVU_Pos (2U)
<> 147:30b64687e01f 10441 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10442 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
<> 147:30b64687e01f 10443
<> 147:30b64687e01f 10444 /******************* Bit definition for IWDG_KR register ********************/
<> 147:30b64687e01f 10445 #define IWDG_WINR_WIN_Pos (0U)
<> 147:30b64687e01f 10446 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
<> 147:30b64687e01f 10447 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
<> 147:30b64687e01f 10448
<> 147:30b64687e01f 10449 /******************************************************************************/
<> 147:30b64687e01f 10450 /* */
<> 147:30b64687e01f 10451 /* Power Control */
<> 147:30b64687e01f 10452 /* */
<> 147:30b64687e01f 10453 /******************************************************************************/
<> 147:30b64687e01f 10454 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
<> 147:30b64687e01f 10455 /******************** Bit definition for PWR_CR register ********************/
<> 147:30b64687e01f 10456 #define PWR_CR_LPDS_Pos (0U)
<> 147:30b64687e01f 10457 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10458 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
<> 147:30b64687e01f 10459 #define PWR_CR_PDDS_Pos (1U)
<> 147:30b64687e01f 10460 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10461 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
<> 147:30b64687e01f 10462 #define PWR_CR_CWUF_Pos (2U)
<> 147:30b64687e01f 10463 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10464 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
<> 147:30b64687e01f 10465 #define PWR_CR_CSBF_Pos (3U)
<> 147:30b64687e01f 10466 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10467 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
<> 147:30b64687e01f 10468 #define PWR_CR_PVDE_Pos (4U)
<> 147:30b64687e01f 10469 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10470 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
<> 147:30b64687e01f 10471
<> 147:30b64687e01f 10472 #define PWR_CR_PLS_Pos (5U)
<> 147:30b64687e01f 10473 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
<> 147:30b64687e01f 10474 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
<> 147:30b64687e01f 10475 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10476 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 10477 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 10478
<> 147:30b64687e01f 10479 /*!< PVD level configuration */
<> 147:30b64687e01f 10480 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
<> 147:30b64687e01f 10481 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
<> 147:30b64687e01f 10482 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
<> 147:30b64687e01f 10483 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
<> 147:30b64687e01f 10484 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
<> 147:30b64687e01f 10485 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
<> 147:30b64687e01f 10486 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
<> 147:30b64687e01f 10487 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
<> 147:30b64687e01f 10488
<> 147:30b64687e01f 10489 #define PWR_CR_DBP_Pos (8U)
<> 147:30b64687e01f 10490 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10491 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
<> 147:30b64687e01f 10492
<> 147:30b64687e01f 10493 /******************* Bit definition for PWR_CSR register ********************/
<> 147:30b64687e01f 10494 #define PWR_CSR_WUF_Pos (0U)
<> 147:30b64687e01f 10495 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10496 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
<> 147:30b64687e01f 10497 #define PWR_CSR_SBF_Pos (1U)
<> 147:30b64687e01f 10498 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10499 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
<> 147:30b64687e01f 10500 #define PWR_CSR_PVDO_Pos (2U)
<> 147:30b64687e01f 10501 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10502 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
<> 147:30b64687e01f 10503 #define PWR_CSR_VREFINTRDYF_Pos (3U)
<> 147:30b64687e01f 10504 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10505 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
<> 147:30b64687e01f 10506
<> 147:30b64687e01f 10507 #define PWR_CSR_EWUP1_Pos (8U)
<> 147:30b64687e01f 10508 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10509 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
<> 147:30b64687e01f 10510 #define PWR_CSR_EWUP2_Pos (9U)
<> 147:30b64687e01f 10511 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10512 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
<> 147:30b64687e01f 10513 #define PWR_CSR_EWUP3_Pos (10U)
<> 147:30b64687e01f 10514 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10515 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
<> 147:30b64687e01f 10516
<> 147:30b64687e01f 10517 /******************************************************************************/
<> 147:30b64687e01f 10518 /* */
<> 147:30b64687e01f 10519 /* Reset and Clock Control */
<> 147:30b64687e01f 10520 /* */
<> 147:30b64687e01f 10521 /******************************************************************************/
<> 147:30b64687e01f 10522 /*
<> 147:30b64687e01f 10523 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 147:30b64687e01f 10524 */
<> 147:30b64687e01f 10525 #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */
<> 147:30b64687e01f 10526
<> 147:30b64687e01f 10527 /******************** Bit definition for RCC_CR register ********************/
<> 147:30b64687e01f 10528 #define RCC_CR_HSION_Pos (0U)
<> 147:30b64687e01f 10529 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10530 #define RCC_CR_HSION RCC_CR_HSION_Msk
<> 147:30b64687e01f 10531 #define RCC_CR_HSIRDY_Pos (1U)
<> 147:30b64687e01f 10532 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10533 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
<> 147:30b64687e01f 10534
<> 147:30b64687e01f 10535 #define RCC_CR_HSITRIM_Pos (3U)
<> 147:30b64687e01f 10536 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
<> 147:30b64687e01f 10537 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
<> 147:30b64687e01f 10538 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10539 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10540 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10541 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 10542 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 10543
<> 147:30b64687e01f 10544 #define RCC_CR_HSICAL_Pos (8U)
<> 147:30b64687e01f 10545 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 10546 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
<> 147:30b64687e01f 10547 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10548 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10549 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10550 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10551 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10552 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10553 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10554 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10555
<> 147:30b64687e01f 10556 #define RCC_CR_HSEON_Pos (16U)
<> 147:30b64687e01f 10557 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10558 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
<> 147:30b64687e01f 10559 #define RCC_CR_HSERDY_Pos (17U)
<> 147:30b64687e01f 10560 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10561 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
<> 147:30b64687e01f 10562 #define RCC_CR_HSEBYP_Pos (18U)
<> 147:30b64687e01f 10563 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10564 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
<> 147:30b64687e01f 10565 #define RCC_CR_CSSON_Pos (19U)
<> 147:30b64687e01f 10566 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 10567 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
<> 147:30b64687e01f 10568 #define RCC_CR_PLLON_Pos (24U)
<> 147:30b64687e01f 10569 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 10570 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
<> 147:30b64687e01f 10571 #define RCC_CR_PLLRDY_Pos (25U)
<> 147:30b64687e01f 10572 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 10573 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
<> 147:30b64687e01f 10574
<> 147:30b64687e01f 10575 /******************** Bit definition for RCC_CFGR register ******************/
<> 147:30b64687e01f 10576 /*!< SW configuration */
<> 147:30b64687e01f 10577 #define RCC_CFGR_SW_Pos (0U)
<> 147:30b64687e01f 10578 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 10579 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
<> 147:30b64687e01f 10580 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10581 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10582
<> 147:30b64687e01f 10583 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
<> 147:30b64687e01f 10584 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
<> 147:30b64687e01f 10585 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
<> 147:30b64687e01f 10586
<> 147:30b64687e01f 10587 /*!< SWS configuration */
<> 147:30b64687e01f 10588 #define RCC_CFGR_SWS_Pos (2U)
<> 147:30b64687e01f 10589 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 10590 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 147:30b64687e01f 10591 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10592 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10593
<> 147:30b64687e01f 10594 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
<> 147:30b64687e01f 10595 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
<> 147:30b64687e01f 10596 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
<> 147:30b64687e01f 10597
<> 147:30b64687e01f 10598 /*!< HPRE configuration */
<> 147:30b64687e01f 10599 #define RCC_CFGR_HPRE_Pos (4U)
<> 147:30b64687e01f 10600 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 10601 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
<> 147:30b64687e01f 10602 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10603 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10604 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 10605 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 10606
<> 147:30b64687e01f 10607 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
<> 147:30b64687e01f 10608 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
<> 147:30b64687e01f 10609 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
<> 147:30b64687e01f 10610 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
<> 147:30b64687e01f 10611 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
<> 147:30b64687e01f 10612 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
<> 147:30b64687e01f 10613 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
<> 147:30b64687e01f 10614 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
<> 147:30b64687e01f 10615 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
<> 147:30b64687e01f 10616
<> 147:30b64687e01f 10617 /*!< PPRE1 configuration */
<> 147:30b64687e01f 10618 #define RCC_CFGR_PPRE1_Pos (8U)
<> 147:30b64687e01f 10619 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
<> 147:30b64687e01f 10620 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 147:30b64687e01f 10621 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10622 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10623 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10624
<> 147:30b64687e01f 10625 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 147:30b64687e01f 10626 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
<> 147:30b64687e01f 10627 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
<> 147:30b64687e01f 10628 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
<> 147:30b64687e01f 10629 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
<> 147:30b64687e01f 10630
<> 147:30b64687e01f 10631 /*!< PPRE2 configuration */
<> 147:30b64687e01f 10632 #define RCC_CFGR_PPRE2_Pos (11U)
<> 147:30b64687e01f 10633 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
<> 147:30b64687e01f 10634 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 147:30b64687e01f 10635 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10636 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10637 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10638
<> 147:30b64687e01f 10639 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 147:30b64687e01f 10640 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
<> 147:30b64687e01f 10641 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
<> 147:30b64687e01f 10642 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
<> 147:30b64687e01f 10643 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
<> 147:30b64687e01f 10644
<> 147:30b64687e01f 10645 #define RCC_CFGR_PLLSRC_Pos (15U)
<> 147:30b64687e01f 10646 #define RCC_CFGR_PLLSRC_Msk (0x3U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
<> 147:30b64687e01f 10647 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
<> 147:30b64687e01f 10648 #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock as PLL entry clock source */
<> 147:30b64687e01f 10649 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
<> 147:30b64687e01f 10650
<> 147:30b64687e01f 10651 #define RCC_CFGR_PLLXTPRE_Pos (17U)
<> 147:30b64687e01f 10652 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10653 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
<> 147:30b64687e01f 10654 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
<> 147:30b64687e01f 10655 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
<> 147:30b64687e01f 10656
<> 147:30b64687e01f 10657 /*!< PLLMUL configuration */
<> 147:30b64687e01f 10658 #define RCC_CFGR_PLLMUL_Pos (18U)
<> 147:30b64687e01f 10659 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
<> 147:30b64687e01f 10660 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
<> 147:30b64687e01f 10661 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10662 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 10663 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 10664 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 10665
<> 147:30b64687e01f 10666 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
<> 147:30b64687e01f 10667 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
<> 147:30b64687e01f 10668 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
<> 147:30b64687e01f 10669 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
<> 147:30b64687e01f 10670 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
<> 147:30b64687e01f 10671 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
<> 147:30b64687e01f 10672 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
<> 147:30b64687e01f 10673 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
<> 147:30b64687e01f 10674 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
<> 147:30b64687e01f 10675 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
<> 147:30b64687e01f 10676 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
<> 147:30b64687e01f 10677 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
<> 147:30b64687e01f 10678 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
<> 147:30b64687e01f 10679 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
<> 147:30b64687e01f 10680 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
<> 147:30b64687e01f 10681
<> 147:30b64687e01f 10682 /*!< USB configuration */
<> 147:30b64687e01f 10683 #define RCC_CFGR_USBPRE_Pos (22U)
<> 147:30b64687e01f 10684 #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 10685 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB prescaler */
<> 147:30b64687e01f 10686
<> 147:30b64687e01f 10687 #define RCC_CFGR_USBPRE_DIV1_5 (0x00000000U) /*!< USB prescaler is PLL clock divided by 1.5 */
<> 147:30b64687e01f 10688 #define RCC_CFGR_USBPRE_DIV1 (0x00400000U) /*!< USB prescaler is PLL clock divided by 1 */
<> 147:30b64687e01f 10689
<> 147:30b64687e01f 10690 /*!< I2S configuration */
<> 147:30b64687e01f 10691 #define RCC_CFGR_I2SSRC_Pos (23U)
<> 147:30b64687e01f 10692 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 10693 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk /*!< I2S external clock source selection */
<> 147:30b64687e01f 10694
<> 147:30b64687e01f 10695 #define RCC_CFGR_I2SSRC_SYSCLK (0x00000000U) /*!< System clock selected as I2S clock source */
<> 147:30b64687e01f 10696 #define RCC_CFGR_I2SSRC_EXT (0x00800000U) /*!< External clock selected as I2S clock source */
<> 147:30b64687e01f 10697
<> 147:30b64687e01f 10698 /*!< MCO configuration */
<> 147:30b64687e01f 10699 #define RCC_CFGR_MCO_Pos (24U)
<> 147:30b64687e01f 10700 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
<> 147:30b64687e01f 10701 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
<> 147:30b64687e01f 10702 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 10703 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 10704 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 10705
<> 147:30b64687e01f 10706 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
<> 147:30b64687e01f 10707 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
<> 147:30b64687e01f 10708 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
<> 147:30b64687e01f 10709 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
<> 147:30b64687e01f 10710 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
<> 147:30b64687e01f 10711 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
<> 147:30b64687e01f 10712 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
<> 147:30b64687e01f 10713
<> 147:30b64687e01f 10714 #define RCC_CFGR_MCOPRE_Pos (28U)
<> 147:30b64687e01f 10715 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
<> 147:30b64687e01f 10716 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
<> 147:30b64687e01f 10717 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 10718 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 10719 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 10720
<> 147:30b64687e01f 10721 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
<> 147:30b64687e01f 10722 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
<> 147:30b64687e01f 10723 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
<> 147:30b64687e01f 10724 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
<> 147:30b64687e01f 10725 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
<> 147:30b64687e01f 10726 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
<> 147:30b64687e01f 10727 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
<> 147:30b64687e01f 10728 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
<> 147:30b64687e01f 10729
<> 147:30b64687e01f 10730 #define RCC_CFGR_PLLNODIV_Pos (31U)
<> 147:30b64687e01f 10731 #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 10732 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< Do not divide PLL to MCO */
<> 147:30b64687e01f 10733
<> 147:30b64687e01f 10734 /* Reference defines */
<> 147:30b64687e01f 10735 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
<> 147:30b64687e01f 10736 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
<> 147:30b64687e01f 10737 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
<> 147:30b64687e01f 10738 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
<> 147:30b64687e01f 10739 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
<> 147:30b64687e01f 10740 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
<> 147:30b64687e01f 10741 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
<> 147:30b64687e01f 10742 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
<> 147:30b64687e01f 10743 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
<> 147:30b64687e01f 10744 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
<> 147:30b64687e01f 10745 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
<> 147:30b64687e01f 10746
<> 147:30b64687e01f 10747 /********************* Bit definition for RCC_CIR register ********************/
<> 147:30b64687e01f 10748 #define RCC_CIR_LSIRDYF_Pos (0U)
<> 147:30b64687e01f 10749 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10750 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
<> 147:30b64687e01f 10751 #define RCC_CIR_LSERDYF_Pos (1U)
<> 147:30b64687e01f 10752 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10753 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
<> 147:30b64687e01f 10754 #define RCC_CIR_HSIRDYF_Pos (2U)
<> 147:30b64687e01f 10755 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10756 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
<> 147:30b64687e01f 10757 #define RCC_CIR_HSERDYF_Pos (3U)
<> 147:30b64687e01f 10758 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 10759 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
<> 147:30b64687e01f 10760 #define RCC_CIR_PLLRDYF_Pos (4U)
<> 147:30b64687e01f 10761 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10762 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
<> 147:30b64687e01f 10763 #define RCC_CIR_CSSF_Pos (7U)
<> 147:30b64687e01f 10764 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 10765 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
<> 147:30b64687e01f 10766 #define RCC_CIR_LSIRDYIE_Pos (8U)
<> 147:30b64687e01f 10767 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 10768 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
<> 147:30b64687e01f 10769 #define RCC_CIR_LSERDYIE_Pos (9U)
<> 147:30b64687e01f 10770 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 10771 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
<> 147:30b64687e01f 10772 #define RCC_CIR_HSIRDYIE_Pos (10U)
<> 147:30b64687e01f 10773 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 10774 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
<> 147:30b64687e01f 10775 #define RCC_CIR_HSERDYIE_Pos (11U)
<> 147:30b64687e01f 10776 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10777 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
<> 147:30b64687e01f 10778 #define RCC_CIR_PLLRDYIE_Pos (12U)
<> 147:30b64687e01f 10779 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10780 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
<> 147:30b64687e01f 10781 #define RCC_CIR_LSIRDYC_Pos (16U)
<> 147:30b64687e01f 10782 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10783 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
<> 147:30b64687e01f 10784 #define RCC_CIR_LSERDYC_Pos (17U)
<> 147:30b64687e01f 10785 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10786 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
<> 147:30b64687e01f 10787 #define RCC_CIR_HSIRDYC_Pos (18U)
<> 147:30b64687e01f 10788 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10789 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
<> 147:30b64687e01f 10790 #define RCC_CIR_HSERDYC_Pos (19U)
<> 147:30b64687e01f 10791 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 10792 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
<> 147:30b64687e01f 10793 #define RCC_CIR_PLLRDYC_Pos (20U)
<> 147:30b64687e01f 10794 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 10795 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
<> 147:30b64687e01f 10796 #define RCC_CIR_CSSC_Pos (23U)
<> 147:30b64687e01f 10797 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 10798 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
<> 147:30b64687e01f 10799
<> 147:30b64687e01f 10800 /****************** Bit definition for RCC_APB2RSTR register *****************/
<> 147:30b64687e01f 10801 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
<> 147:30b64687e01f 10802 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10803 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
<> 147:30b64687e01f 10804 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
<> 147:30b64687e01f 10805 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10806 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
<> 147:30b64687e01f 10807 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
<> 147:30b64687e01f 10808 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10809 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
<> 147:30b64687e01f 10810 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
<> 147:30b64687e01f 10811 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10812 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */
<> 147:30b64687e01f 10813 #define RCC_APB2RSTR_USART1RST_Pos (14U)
<> 147:30b64687e01f 10814 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10815 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
<> 147:30b64687e01f 10816 #define RCC_APB2RSTR_SPI4RST_Pos (15U)
<> 147:30b64687e01f 10817 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10818 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */
<> 147:30b64687e01f 10819 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
<> 147:30b64687e01f 10820 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10821 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
<> 147:30b64687e01f 10822 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
<> 147:30b64687e01f 10823 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10824 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
<> 147:30b64687e01f 10825 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
<> 147:30b64687e01f 10826 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10827 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
<> 147:30b64687e01f 10828 #define RCC_APB2RSTR_TIM20RST_Pos (20U)
<> 147:30b64687e01f 10829 #define RCC_APB2RSTR_TIM20RST_Msk (0x1U << RCC_APB2RSTR_TIM20RST_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 10830 #define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk /*!< TIM20 reset */
<> 147:30b64687e01f 10831
<> 147:30b64687e01f 10832 /****************** Bit definition for RCC_APB1RSTR register ******************/
<> 147:30b64687e01f 10833 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
<> 147:30b64687e01f 10834 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10835 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
<> 147:30b64687e01f 10836 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
<> 147:30b64687e01f 10837 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10838 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
<> 147:30b64687e01f 10839 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
<> 147:30b64687e01f 10840 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10841 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
<> 147:30b64687e01f 10842 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
<> 147:30b64687e01f 10843 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10844 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
<> 147:30b64687e01f 10845 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
<> 147:30b64687e01f 10846 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10847 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
<> 147:30b64687e01f 10848 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
<> 147:30b64687e01f 10849 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10850 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
<> 147:30b64687e01f 10851 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
<> 147:30b64687e01f 10852 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10853 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
<> 147:30b64687e01f 10854 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
<> 147:30b64687e01f 10855 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10856 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI3 reset */
<> 147:30b64687e01f 10857 #define RCC_APB1RSTR_USART2RST_Pos (17U)
<> 147:30b64687e01f 10858 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10859 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
<> 147:30b64687e01f 10860 #define RCC_APB1RSTR_USART3RST_Pos (18U)
<> 147:30b64687e01f 10861 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10862 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
<> 147:30b64687e01f 10863 #define RCC_APB1RSTR_UART4RST_Pos (19U)
<> 147:30b64687e01f 10864 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 10865 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
<> 147:30b64687e01f 10866 #define RCC_APB1RSTR_UART5RST_Pos (20U)
<> 147:30b64687e01f 10867 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 10868 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
<> 147:30b64687e01f 10869 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
<> 147:30b64687e01f 10870 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 10871 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
<> 147:30b64687e01f 10872 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
<> 147:30b64687e01f 10873 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 10874 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
<> 147:30b64687e01f 10875 #define RCC_APB1RSTR_USBRST_Pos (23U)
<> 147:30b64687e01f 10876 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 10877 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
<> 147:30b64687e01f 10878 #define RCC_APB1RSTR_CANRST_Pos (25U)
<> 147:30b64687e01f 10879 #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 10880 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */
<> 147:30b64687e01f 10881 #define RCC_APB1RSTR_PWRRST_Pos (28U)
<> 147:30b64687e01f 10882 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 10883 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
<> 147:30b64687e01f 10884 #define RCC_APB1RSTR_DAC1RST_Pos (29U)
<> 147:30b64687e01f 10885 #define RCC_APB1RSTR_DAC1RST_Msk (0x1U << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 10886 #define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk /*!< DAC 1 reset */
<> 147:30b64687e01f 10887 #define RCC_APB1RSTR_I2C3RST_Pos (30U)
<> 147:30b64687e01f 10888 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 10889 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 reset */
<> 147:30b64687e01f 10890
<> 147:30b64687e01f 10891 /****************** Bit definition for RCC_AHBENR register ******************/
<> 147:30b64687e01f 10892 #define RCC_AHBENR_DMA1EN_Pos (0U)
<> 147:30b64687e01f 10893 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10894 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
<> 147:30b64687e01f 10895 #define RCC_AHBENR_DMA2EN_Pos (1U)
<> 147:30b64687e01f 10896 #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10897 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
<> 147:30b64687e01f 10898 #define RCC_AHBENR_SRAMEN_Pos (2U)
<> 147:30b64687e01f 10899 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10900 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
<> 147:30b64687e01f 10901 #define RCC_AHBENR_FLITFEN_Pos (4U)
<> 147:30b64687e01f 10902 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10903 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
<> 147:30b64687e01f 10904 #define RCC_AHBENR_FMCEN_Pos (5U)
<> 147:30b64687e01f 10905 #define RCC_AHBENR_FMCEN_Msk (0x1U << RCC_AHBENR_FMCEN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10906 #define RCC_AHBENR_FMCEN RCC_AHBENR_FMCEN_Msk /*!< FMC clock enable */
<> 147:30b64687e01f 10907 #define RCC_AHBENR_CRCEN_Pos (6U)
<> 147:30b64687e01f 10908 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 10909 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
<> 147:30b64687e01f 10910 #define RCC_AHBENR_GPIOHEN_Pos (16U)
<> 147:30b64687e01f 10911 #define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10912 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIOH clock enable */
<> 147:30b64687e01f 10913 #define RCC_AHBENR_GPIOAEN_Pos (17U)
<> 147:30b64687e01f 10914 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10915 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
<> 147:30b64687e01f 10916 #define RCC_AHBENR_GPIOBEN_Pos (18U)
<> 147:30b64687e01f 10917 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10918 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
<> 147:30b64687e01f 10919 #define RCC_AHBENR_GPIOCEN_Pos (19U)
<> 147:30b64687e01f 10920 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 10921 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
<> 147:30b64687e01f 10922 #define RCC_AHBENR_GPIODEN_Pos (20U)
<> 147:30b64687e01f 10923 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 10924 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
<> 147:30b64687e01f 10925 #define RCC_AHBENR_GPIOEEN_Pos (21U)
<> 147:30b64687e01f 10926 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 10927 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIOE clock enable */
<> 147:30b64687e01f 10928 #define RCC_AHBENR_GPIOFEN_Pos (22U)
<> 147:30b64687e01f 10929 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 10930 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
<> 147:30b64687e01f 10931 #define RCC_AHBENR_GPIOGEN_Pos (23U)
<> 147:30b64687e01f 10932 #define RCC_AHBENR_GPIOGEN_Msk (0x1U << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 10933 #define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIOG clock enable */
<> 147:30b64687e01f 10934 #define RCC_AHBENR_TSCEN_Pos (24U)
<> 147:30b64687e01f 10935 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 10936 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS clock enable */
<> 147:30b64687e01f 10937 #define RCC_AHBENR_ADC12EN_Pos (28U)
<> 147:30b64687e01f 10938 #define RCC_AHBENR_ADC12EN_Msk (0x1U << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 10939 #define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk /*!< ADC1/ ADC2 clock enable */
<> 147:30b64687e01f 10940 #define RCC_AHBENR_ADC34EN_Pos (29U)
<> 147:30b64687e01f 10941 #define RCC_AHBENR_ADC34EN_Msk (0x1U << RCC_AHBENR_ADC34EN_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 10942 #define RCC_AHBENR_ADC34EN RCC_AHBENR_ADC34EN_Msk /*!< ADC3/ ADC4 clock enable */
<> 147:30b64687e01f 10943
<> 147:30b64687e01f 10944 /***************** Bit definition for RCC_APB2ENR register ******************/
<> 147:30b64687e01f 10945 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
<> 147:30b64687e01f 10946 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10947 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
<> 147:30b64687e01f 10948 #define RCC_APB2ENR_TIM1EN_Pos (11U)
<> 147:30b64687e01f 10949 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10950 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
<> 147:30b64687e01f 10951 #define RCC_APB2ENR_SPI1EN_Pos (12U)
<> 147:30b64687e01f 10952 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 10953 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
<> 147:30b64687e01f 10954 #define RCC_APB2ENR_TIM8EN_Pos (13U)
<> 147:30b64687e01f 10955 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 10956 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */
<> 147:30b64687e01f 10957 #define RCC_APB2ENR_USART1EN_Pos (14U)
<> 147:30b64687e01f 10958 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10959 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
<> 147:30b64687e01f 10960 #define RCC_APB2ENR_SPI4EN_Pos (15U)
<> 147:30b64687e01f 10961 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 10962 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 clock enable */
<> 147:30b64687e01f 10963 #define RCC_APB2ENR_TIM15EN_Pos (16U)
<> 147:30b64687e01f 10964 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 10965 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
<> 147:30b64687e01f 10966 #define RCC_APB2ENR_TIM16EN_Pos (17U)
<> 147:30b64687e01f 10967 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 10968 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
<> 147:30b64687e01f 10969 #define RCC_APB2ENR_TIM17EN_Pos (18U)
<> 147:30b64687e01f 10970 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 10971 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
<> 147:30b64687e01f 10972 #define RCC_APB2ENR_TIM20EN_Pos (20U)
<> 147:30b64687e01f 10973 #define RCC_APB2ENR_TIM20EN_Msk (0x1U << RCC_APB2ENR_TIM20EN_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 10974 #define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk /*!< TIM20 clock enable */
<> 147:30b64687e01f 10975
<> 147:30b64687e01f 10976 /****************** Bit definition for RCC_APB1ENR register ******************/
<> 147:30b64687e01f 10977 #define RCC_APB1ENR_TIM2EN_Pos (0U)
<> 147:30b64687e01f 10978 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 10979 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
<> 147:30b64687e01f 10980 #define RCC_APB1ENR_TIM3EN_Pos (1U)
<> 147:30b64687e01f 10981 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 10982 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
<> 147:30b64687e01f 10983 #define RCC_APB1ENR_TIM4EN_Pos (2U)
<> 147:30b64687e01f 10984 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 10985 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
<> 147:30b64687e01f 10986 #define RCC_APB1ENR_TIM6EN_Pos (4U)
<> 147:30b64687e01f 10987 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 10988 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
<> 147:30b64687e01f 10989 #define RCC_APB1ENR_TIM7EN_Pos (5U)
<> 147:30b64687e01f 10990 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 10991 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
<> 147:30b64687e01f 10992 #define RCC_APB1ENR_WWDGEN_Pos (11U)
<> 147:30b64687e01f 10993 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 10994 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
<> 147:30b64687e01f 10995 #define RCC_APB1ENR_SPI2EN_Pos (14U)
<> 147:30b64687e01f 10996 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 10997 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
<> 147:30b64687e01f 10998 #define RCC_APB1ENR_SPI3EN_Pos (15U)
<> 147:30b64687e01f 10999 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11000 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI3 clock enable */
<> 147:30b64687e01f 11001 #define RCC_APB1ENR_USART2EN_Pos (17U)
<> 147:30b64687e01f 11002 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11003 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
<> 147:30b64687e01f 11004 #define RCC_APB1ENR_USART3EN_Pos (18U)
<> 147:30b64687e01f 11005 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11006 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
<> 147:30b64687e01f 11007 #define RCC_APB1ENR_UART4EN_Pos (19U)
<> 147:30b64687e01f 11008 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11009 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
<> 147:30b64687e01f 11010 #define RCC_APB1ENR_UART5EN_Pos (20U)
<> 147:30b64687e01f 11011 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11012 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
<> 147:30b64687e01f 11013 #define RCC_APB1ENR_I2C1EN_Pos (21U)
<> 147:30b64687e01f 11014 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11015 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
<> 147:30b64687e01f 11016 #define RCC_APB1ENR_I2C2EN_Pos (22U)
<> 147:30b64687e01f 11017 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11018 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
<> 147:30b64687e01f 11019 #define RCC_APB1ENR_USBEN_Pos (23U)
<> 147:30b64687e01f 11020 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11021 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
<> 147:30b64687e01f 11022 #define RCC_APB1ENR_CANEN_Pos (25U)
<> 147:30b64687e01f 11023 #define RCC_APB1ENR_CANEN_Msk (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11024 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */
<> 147:30b64687e01f 11025 #define RCC_APB1ENR_PWREN_Pos (28U)
<> 147:30b64687e01f 11026 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 11027 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
<> 147:30b64687e01f 11028 #define RCC_APB1ENR_DAC1EN_Pos (29U)
<> 147:30b64687e01f 11029 #define RCC_APB1ENR_DAC1EN_Msk (0x1U << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 11030 #define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk /*!< DAC 1 clock enable */
<> 147:30b64687e01f 11031 #define RCC_APB1ENR_I2C3EN_Pos (30U)
<> 147:30b64687e01f 11032 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 11033 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C 3 clock enable */
<> 147:30b64687e01f 11034
<> 147:30b64687e01f 11035 /******************** Bit definition for RCC_BDCR register ******************/
<> 147:30b64687e01f 11036 #define RCC_BDCR_LSE_Pos (0U)
<> 147:30b64687e01f 11037 #define RCC_BDCR_LSE_Msk (0x7U << RCC_BDCR_LSE_Pos) /*!< 0x00000007 */
<> 147:30b64687e01f 11038 #define RCC_BDCR_LSE RCC_BDCR_LSE_Msk /*!< External Low Speed oscillator [2:0] bits */
<> 147:30b64687e01f 11039 #define RCC_BDCR_LSEON_Pos (0U)
<> 147:30b64687e01f 11040 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11041 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
<> 147:30b64687e01f 11042 #define RCC_BDCR_LSERDY_Pos (1U)
<> 147:30b64687e01f 11043 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11044 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
<> 147:30b64687e01f 11045 #define RCC_BDCR_LSEBYP_Pos (2U)
<> 147:30b64687e01f 11046 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11047 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
<> 147:30b64687e01f 11048
<> 147:30b64687e01f 11049 #define RCC_BDCR_LSEDRV_Pos (3U)
<> 147:30b64687e01f 11050 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
<> 147:30b64687e01f 11051 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
<> 147:30b64687e01f 11052 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11053 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11054
<> 147:30b64687e01f 11055 #define RCC_BDCR_RTCSEL_Pos (8U)
<> 147:30b64687e01f 11056 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 11057 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
<> 147:30b64687e01f 11058 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11059 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11060
<> 147:30b64687e01f 11061 /*!< RTC configuration */
<> 147:30b64687e01f 11062 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 147:30b64687e01f 11063 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
<> 147:30b64687e01f 11064 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
<> 147:30b64687e01f 11065 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 32 used as RTC clock */
<> 147:30b64687e01f 11066
<> 147:30b64687e01f 11067 #define RCC_BDCR_RTCEN_Pos (15U)
<> 147:30b64687e01f 11068 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11069 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
<> 147:30b64687e01f 11070 #define RCC_BDCR_BDRST_Pos (16U)
<> 147:30b64687e01f 11071 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11072 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
<> 147:30b64687e01f 11073
<> 147:30b64687e01f 11074 /******************** Bit definition for RCC_CSR register *******************/
<> 147:30b64687e01f 11075 #define RCC_CSR_LSION_Pos (0U)
<> 147:30b64687e01f 11076 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11077 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
<> 147:30b64687e01f 11078 #define RCC_CSR_LSIRDY_Pos (1U)
<> 147:30b64687e01f 11079 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11080 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
<> 147:30b64687e01f 11081 #define RCC_CSR_V18PWRRSTF_Pos (23U)
<> 147:30b64687e01f 11082 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11083 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
<> 147:30b64687e01f 11084 #define RCC_CSR_RMVF_Pos (24U)
<> 147:30b64687e01f 11085 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11086 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
<> 147:30b64687e01f 11087 #define RCC_CSR_OBLRSTF_Pos (25U)
<> 147:30b64687e01f 11088 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11089 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
<> 147:30b64687e01f 11090 #define RCC_CSR_PINRSTF_Pos (26U)
<> 147:30b64687e01f 11091 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 11092 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
<> 147:30b64687e01f 11093 #define RCC_CSR_PORRSTF_Pos (27U)
<> 147:30b64687e01f 11094 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 11095 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
<> 147:30b64687e01f 11096 #define RCC_CSR_SFTRSTF_Pos (28U)
<> 147:30b64687e01f 11097 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 11098 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
<> 147:30b64687e01f 11099 #define RCC_CSR_IWDGRSTF_Pos (29U)
<> 147:30b64687e01f 11100 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 11101 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
<> 147:30b64687e01f 11102 #define RCC_CSR_WWDGRSTF_Pos (30U)
<> 147:30b64687e01f 11103 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 11104 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
<> 147:30b64687e01f 11105 #define RCC_CSR_LPWRRSTF_Pos (31U)
<> 147:30b64687e01f 11106 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 11107 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
<> 147:30b64687e01f 11108
<> 147:30b64687e01f 11109 /* Legacy defines */
<> 147:30b64687e01f 11110 #define RCC_CSR_VREGRSTF RCC_CSR_V18PWRRSTF
<> 147:30b64687e01f 11111
<> 147:30b64687e01f 11112 /******************* Bit definition for RCC_AHBRSTR register ****************/
<> 147:30b64687e01f 11113 #define RCC_AHBRSTR_FMCRST_Pos (5U)
<> 147:30b64687e01f 11114 #define RCC_AHBRSTR_FMCRST_Msk (0x1U << RCC_AHBRSTR_FMCRST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11115 #define RCC_AHBRSTR_FMCRST RCC_AHBRSTR_FMCRST_Msk /*!< FMC reset */
<> 147:30b64687e01f 11116 #define RCC_AHBRSTR_GPIOHRST_Pos (16U)
<> 147:30b64687e01f 11117 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11118 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIOH reset */
<> 147:30b64687e01f 11119 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
<> 147:30b64687e01f 11120 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11121 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
<> 147:30b64687e01f 11122 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
<> 147:30b64687e01f 11123 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11124 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
<> 147:30b64687e01f 11125 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
<> 147:30b64687e01f 11126 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11127 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
<> 147:30b64687e01f 11128 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
<> 147:30b64687e01f 11129 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11130 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
<> 147:30b64687e01f 11131 #define RCC_AHBRSTR_GPIOERST_Pos (21U)
<> 147:30b64687e01f 11132 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11133 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */
<> 147:30b64687e01f 11134 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
<> 147:30b64687e01f 11135 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11136 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
<> 147:30b64687e01f 11137 #define RCC_AHBRSTR_GPIOGRST_Pos (23U)
<> 147:30b64687e01f 11138 #define RCC_AHBRSTR_GPIOGRST_Msk (0x1U << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11139 #define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIOG reset */
<> 147:30b64687e01f 11140 #define RCC_AHBRSTR_TSCRST_Pos (24U)
<> 147:30b64687e01f 11141 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11142 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
<> 147:30b64687e01f 11143 #define RCC_AHBRSTR_ADC12RST_Pos (28U)
<> 147:30b64687e01f 11144 #define RCC_AHBRSTR_ADC12RST_Msk (0x1U << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 11145 #define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk /*!< ADC1 & ADC2 reset */
<> 147:30b64687e01f 11146 #define RCC_AHBRSTR_ADC34RST_Pos (29U)
<> 147:30b64687e01f 11147 #define RCC_AHBRSTR_ADC34RST_Msk (0x1U << RCC_AHBRSTR_ADC34RST_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 11148 #define RCC_AHBRSTR_ADC34RST RCC_AHBRSTR_ADC34RST_Msk /*!< ADC3 & ADC4 reset */
<> 147:30b64687e01f 11149
<> 147:30b64687e01f 11150 /******************* Bit definition for RCC_CFGR2 register ******************/
<> 147:30b64687e01f 11151 /*!< PREDIV configuration */
<> 147:30b64687e01f 11152 #define RCC_CFGR2_PREDIV_Pos (0U)
<> 147:30b64687e01f 11153 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 11154 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
<> 147:30b64687e01f 11155 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11156 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11157 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11158 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11159
<> 147:30b64687e01f 11160 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
<> 147:30b64687e01f 11161 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
<> 147:30b64687e01f 11162 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
<> 147:30b64687e01f 11163 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
<> 147:30b64687e01f 11164 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
<> 147:30b64687e01f 11165 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
<> 147:30b64687e01f 11166 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
<> 147:30b64687e01f 11167 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
<> 147:30b64687e01f 11168 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
<> 147:30b64687e01f 11169 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
<> 147:30b64687e01f 11170 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
<> 147:30b64687e01f 11171 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
<> 147:30b64687e01f 11172 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
<> 147:30b64687e01f 11173 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
<> 147:30b64687e01f 11174 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
<> 147:30b64687e01f 11175 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
<> 147:30b64687e01f 11176
<> 147:30b64687e01f 11177 /*!< ADCPRE12 configuration */
<> 147:30b64687e01f 11178 #define RCC_CFGR2_ADCPRE12_Pos (4U)
<> 147:30b64687e01f 11179 #define RCC_CFGR2_ADCPRE12_Msk (0x1FU << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */
<> 147:30b64687e01f 11180 #define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk /*!< ADCPRE12[8:4] bits */
<> 147:30b64687e01f 11181 #define RCC_CFGR2_ADCPRE12_0 (0x01U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11182 #define RCC_CFGR2_ADCPRE12_1 (0x02U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11183 #define RCC_CFGR2_ADCPRE12_2 (0x04U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11184 #define RCC_CFGR2_ADCPRE12_3 (0x08U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 11185 #define RCC_CFGR2_ADCPRE12_4 (0x10U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11186
<> 147:30b64687e01f 11187 #define RCC_CFGR2_ADCPRE12_NO (0x00000000U) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
<> 147:30b64687e01f 11188 #define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U) /*!< ADC12 PLL clock divided by 1 */
<> 147:30b64687e01f 11189 #define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U) /*!< ADC12 PLL clock divided by 2 */
<> 147:30b64687e01f 11190 #define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U) /*!< ADC12 PLL clock divided by 4 */
<> 147:30b64687e01f 11191 #define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U) /*!< ADC12 PLL clock divided by 6 */
<> 147:30b64687e01f 11192 #define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U) /*!< ADC12 PLL clock divided by 8 */
<> 147:30b64687e01f 11193 #define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U) /*!< ADC12 PLL clock divided by 10 */
<> 147:30b64687e01f 11194 #define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U) /*!< ADC12 PLL clock divided by 12 */
<> 147:30b64687e01f 11195 #define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U) /*!< ADC12 PLL clock divided by 16 */
<> 147:30b64687e01f 11196 #define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U) /*!< ADC12 PLL clock divided by 32 */
<> 147:30b64687e01f 11197 #define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U) /*!< ADC12 PLL clock divided by 64 */
<> 147:30b64687e01f 11198 #define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U) /*!< ADC12 PLL clock divided by 128 */
<> 147:30b64687e01f 11199 #define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U) /*!< ADC12 PLL clock divided by 256 */
<> 147:30b64687e01f 11200
<> 147:30b64687e01f 11201 /*!< ADCPRE34 configuration */
<> 147:30b64687e01f 11202 #define RCC_CFGR2_ADCPRE34_Pos (9U)
<> 147:30b64687e01f 11203 #define RCC_CFGR2_ADCPRE34_Msk (0x1FU << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00003E00 */
<> 147:30b64687e01f 11204 #define RCC_CFGR2_ADCPRE34 RCC_CFGR2_ADCPRE34_Msk /*!< ADCPRE34[13:5] bits */
<> 147:30b64687e01f 11205 #define RCC_CFGR2_ADCPRE34_0 (0x01U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11206 #define RCC_CFGR2_ADCPRE34_1 (0x02U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11207 #define RCC_CFGR2_ADCPRE34_2 (0x04U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11208 #define RCC_CFGR2_ADCPRE34_3 (0x08U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11209 #define RCC_CFGR2_ADCPRE34_4 (0x10U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11210
<> 147:30b64687e01f 11211 #define RCC_CFGR2_ADCPRE34_NO (0x00000000U) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
<> 147:30b64687e01f 11212 #define RCC_CFGR2_ADCPRE34_DIV1 (0x00002000U) /*!< ADC34 PLL clock divided by 1 */
<> 147:30b64687e01f 11213 #define RCC_CFGR2_ADCPRE34_DIV2 (0x00002200U) /*!< ADC34 PLL clock divided by 2 */
<> 147:30b64687e01f 11214 #define RCC_CFGR2_ADCPRE34_DIV4 (0x00002400U) /*!< ADC34 PLL clock divided by 4 */
<> 147:30b64687e01f 11215 #define RCC_CFGR2_ADCPRE34_DIV6 (0x00002600U) /*!< ADC34 PLL clock divided by 6 */
<> 147:30b64687e01f 11216 #define RCC_CFGR2_ADCPRE34_DIV8 (0x00002800U) /*!< ADC34 PLL clock divided by 8 */
<> 147:30b64687e01f 11217 #define RCC_CFGR2_ADCPRE34_DIV10 (0x00002A00U) /*!< ADC34 PLL clock divided by 10 */
<> 147:30b64687e01f 11218 #define RCC_CFGR2_ADCPRE34_DIV12 (0x00002C00U) /*!< ADC34 PLL clock divided by 12 */
<> 147:30b64687e01f 11219 #define RCC_CFGR2_ADCPRE34_DIV16 (0x00002E00U) /*!< ADC34 PLL clock divided by 16 */
<> 147:30b64687e01f 11220 #define RCC_CFGR2_ADCPRE34_DIV32 (0x00003000U) /*!< ADC34 PLL clock divided by 32 */
<> 147:30b64687e01f 11221 #define RCC_CFGR2_ADCPRE34_DIV64 (0x00003200U) /*!< ADC34 PLL clock divided by 64 */
<> 147:30b64687e01f 11222 #define RCC_CFGR2_ADCPRE34_DIV128 (0x00003400U) /*!< ADC34 PLL clock divided by 128 */
<> 147:30b64687e01f 11223 #define RCC_CFGR2_ADCPRE34_DIV256 (0x00003600U) /*!< ADC34 PLL clock divided by 256 */
<> 147:30b64687e01f 11224
<> 147:30b64687e01f 11225 /******************* Bit definition for RCC_CFGR3 register ******************/
<> 147:30b64687e01f 11226 #define RCC_CFGR3_USART1SW_Pos (0U)
<> 147:30b64687e01f 11227 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 11228 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
<> 147:30b64687e01f 11229 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11230 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11231
<> 147:30b64687e01f 11232 #define RCC_CFGR3_USART1SW_PCLK2 (0x00000000U) /*!< PCLK2 clock used as USART1 clock source */
<> 147:30b64687e01f 11233 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
<> 147:30b64687e01f 11234 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
<> 147:30b64687e01f 11235 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
<> 147:30b64687e01f 11236 /* Legacy defines */
<> 147:30b64687e01f 11237 #define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
<> 147:30b64687e01f 11238
<> 147:30b64687e01f 11239 #define RCC_CFGR3_I2CSW_Pos (4U)
<> 147:30b64687e01f 11240 #define RCC_CFGR3_I2CSW_Msk (0x7U << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 11241 #define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk /*!< I2CSW bits */
<> 147:30b64687e01f 11242 #define RCC_CFGR3_I2C1SW_Pos (4U)
<> 147:30b64687e01f 11243 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11244 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
<> 147:30b64687e01f 11245 #define RCC_CFGR3_I2C2SW_Pos (5U)
<> 147:30b64687e01f 11246 #define RCC_CFGR3_I2C2SW_Msk (0x1U << RCC_CFGR3_I2C2SW_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11247 #define RCC_CFGR3_I2C2SW RCC_CFGR3_I2C2SW_Msk /*!< I2C2SW bits */
<> 147:30b64687e01f 11248 #define RCC_CFGR3_I2C3SW_Pos (6U)
<> 147:30b64687e01f 11249 #define RCC_CFGR3_I2C3SW_Msk (0x1U << RCC_CFGR3_I2C3SW_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11250 #define RCC_CFGR3_I2C3SW RCC_CFGR3_I2C3SW_Msk /*!< I2C3SW bits */
<> 147:30b64687e01f 11251
<> 147:30b64687e01f 11252 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
<> 147:30b64687e01f 11253 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
<> 147:30b64687e01f 11254 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11255 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
<> 147:30b64687e01f 11256 #define RCC_CFGR3_I2C2SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C2 clock source */
<> 147:30b64687e01f 11257 #define RCC_CFGR3_I2C2SW_SYSCLK_Pos (5U)
<> 147:30b64687e01f 11258 #define RCC_CFGR3_I2C2SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C2SW_SYSCLK_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11259 #define RCC_CFGR3_I2C2SW_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK_Msk /*!< System clock selected as I2C2 clock source */
<> 147:30b64687e01f 11260 #define RCC_CFGR3_I2C3SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C3 clock source */
<> 147:30b64687e01f 11261 #define RCC_CFGR3_I2C3SW_SYSCLK_Pos (6U)
<> 147:30b64687e01f 11262 #define RCC_CFGR3_I2C3SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C3SW_SYSCLK_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11263 #define RCC_CFGR3_I2C3SW_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK_Msk /*!< System clock selected as I2C3 clock source */
<> 147:30b64687e01f 11264
<> 147:30b64687e01f 11265 #define RCC_CFGR3_TIMSW_Pos (8U)
<> 147:30b64687e01f 11266 #define RCC_CFGR3_TIMSW_Msk (0xAFU << RCC_CFGR3_TIMSW_Pos) /*!< 0x0000AF00 */
<> 147:30b64687e01f 11267 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
<> 147:30b64687e01f 11268 #define RCC_CFGR3_TIM1SW_Pos (8U)
<> 147:30b64687e01f 11269 #define RCC_CFGR3_TIM1SW_Msk (0x1U << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11270 #define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk /*!< TIM1SW bits */
<> 147:30b64687e01f 11271 #define RCC_CFGR3_TIM8SW_Pos (9U)
<> 147:30b64687e01f 11272 #define RCC_CFGR3_TIM8SW_Msk (0x1U << RCC_CFGR3_TIM8SW_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11273 #define RCC_CFGR3_TIM8SW RCC_CFGR3_TIM8SW_Msk /*!< TIM8SW bits */
<> 147:30b64687e01f 11274 #define RCC_CFGR3_TIM15SW_Pos (10U)
<> 147:30b64687e01f 11275 #define RCC_CFGR3_TIM15SW_Msk (0x1U << RCC_CFGR3_TIM15SW_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11276 #define RCC_CFGR3_TIM15SW RCC_CFGR3_TIM15SW_Msk /*!< TIM15SW bits */
<> 147:30b64687e01f 11277 #define RCC_CFGR3_TIM16SW_Pos (11U)
<> 147:30b64687e01f 11278 #define RCC_CFGR3_TIM16SW_Msk (0x1U << RCC_CFGR3_TIM16SW_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11279 #define RCC_CFGR3_TIM16SW RCC_CFGR3_TIM16SW_Msk /*!< TIM16SW bits */
<> 147:30b64687e01f 11280 #define RCC_CFGR3_TIM17SW_Pos (13U)
<> 147:30b64687e01f 11281 #define RCC_CFGR3_TIM17SW_Msk (0x1U << RCC_CFGR3_TIM17SW_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11282 #define RCC_CFGR3_TIM17SW RCC_CFGR3_TIM17SW_Msk /*!< TIM17SW bits */
<> 147:30b64687e01f 11283 #define RCC_CFGR3_TIM20SW_Pos (15U)
<> 147:30b64687e01f 11284 #define RCC_CFGR3_TIM20SW_Msk (0x1U << RCC_CFGR3_TIM20SW_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11285 #define RCC_CFGR3_TIM20SW RCC_CFGR3_TIM20SW_Msk /*!< TIM20SW bits */
<> 147:30b64687e01f 11286 #define RCC_CFGR3_TIM2SW_Pos (24U)
<> 147:30b64687e01f 11287 #define RCC_CFGR3_TIM2SW_Msk (0x1U << RCC_CFGR3_TIM2SW_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11288 #define RCC_CFGR3_TIM2SW RCC_CFGR3_TIM2SW_Msk /*!< TIM2SW bits */
<> 147:30b64687e01f 11289 #define RCC_CFGR3_TIM34SW_Pos (25U)
<> 147:30b64687e01f 11290 #define RCC_CFGR3_TIM34SW_Msk (0x1U << RCC_CFGR3_TIM34SW_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11291 #define RCC_CFGR3_TIM34SW RCC_CFGR3_TIM34SW_Msk /*!< TIM34SW bits */
<> 147:30b64687e01f 11292 #define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM1 clock source */
<> 147:30b64687e01f 11293 #define RCC_CFGR3_TIM1SW_PLL_Pos (8U)
<> 147:30b64687e01f 11294 #define RCC_CFGR3_TIM1SW_PLL_Msk (0x1U << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11295 #define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk /*!< PLL clock used as TIM1 clock source */
<> 147:30b64687e01f 11296 #define RCC_CFGR3_TIM8SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM8 clock source */
<> 147:30b64687e01f 11297 #define RCC_CFGR3_TIM8SW_PLL_Pos (9U)
<> 147:30b64687e01f 11298 #define RCC_CFGR3_TIM8SW_PLL_Msk (0x1U << RCC_CFGR3_TIM8SW_PLL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11299 #define RCC_CFGR3_TIM8SW_PLL RCC_CFGR3_TIM8SW_PLL_Msk /*!< PLL clock used as TIM8 clock source */
<> 147:30b64687e01f 11300 #define RCC_CFGR3_TIM15SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM15 clock source */
<> 147:30b64687e01f 11301 #define RCC_CFGR3_TIM15SW_PLL_Pos (10U)
<> 147:30b64687e01f 11302 #define RCC_CFGR3_TIM15SW_PLL_Msk (0x1U << RCC_CFGR3_TIM15SW_PLL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11303 #define RCC_CFGR3_TIM15SW_PLL RCC_CFGR3_TIM15SW_PLL_Msk /*!< PLL clock used as TIM15 clock source */
<> 147:30b64687e01f 11304 #define RCC_CFGR3_TIM16SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM16 clock source */
<> 147:30b64687e01f 11305 #define RCC_CFGR3_TIM16SW_PLL_Pos (11U)
<> 147:30b64687e01f 11306 #define RCC_CFGR3_TIM16SW_PLL_Msk (0x1U << RCC_CFGR3_TIM16SW_PLL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11307 #define RCC_CFGR3_TIM16SW_PLL RCC_CFGR3_TIM16SW_PLL_Msk /*!< PLL clock used as TIM16 clock source */
<> 147:30b64687e01f 11308 #define RCC_CFGR3_TIM17SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM17 clock source */
<> 147:30b64687e01f 11309 #define RCC_CFGR3_TIM17SW_PLL_Pos (13U)
<> 147:30b64687e01f 11310 #define RCC_CFGR3_TIM17SW_PLL_Msk (0x1U << RCC_CFGR3_TIM17SW_PLL_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11311 #define RCC_CFGR3_TIM17SW_PLL RCC_CFGR3_TIM17SW_PLL_Msk /*!< PLL clock used as TIM17 clock source */
<> 147:30b64687e01f 11312 #define RCC_CFGR3_TIM20SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM20 clock source */
<> 147:30b64687e01f 11313 #define RCC_CFGR3_TIM20SW_PLL_Pos (15U)
<> 147:30b64687e01f 11314 #define RCC_CFGR3_TIM20SW_PLL_Msk (0x1U << RCC_CFGR3_TIM20SW_PLL_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11315 #define RCC_CFGR3_TIM20SW_PLL RCC_CFGR3_TIM20SW_PLL_Msk /*!< PLL clock used as TIM20 clock source */
<> 147:30b64687e01f 11316
<> 147:30b64687e01f 11317 #define RCC_CFGR3_USART2SW_Pos (16U)
<> 147:30b64687e01f 11318 #define RCC_CFGR3_USART2SW_Msk (0x3U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
<> 147:30b64687e01f 11319 #define RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk /*!< USART2SW[1:0] bits */
<> 147:30b64687e01f 11320 #define RCC_CFGR3_USART2SW_0 (0x1U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11321 #define RCC_CFGR3_USART2SW_1 (0x2U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11322
<> 147:30b64687e01f 11323 #define RCC_CFGR3_USART2SW_PCLK (0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
<> 147:30b64687e01f 11324 #define RCC_CFGR3_USART2SW_SYSCLK (0x00010000U) /*!< System clock selected as USART2 clock source */
<> 147:30b64687e01f 11325 #define RCC_CFGR3_USART2SW_LSE (0x00020000U) /*!< LSE oscillator clock used as USART2 clock source */
<> 147:30b64687e01f 11326 #define RCC_CFGR3_USART2SW_HSI (0x00030000U) /*!< HSI oscillator clock used as USART2 clock source */
<> 147:30b64687e01f 11327
<> 147:30b64687e01f 11328 #define RCC_CFGR3_USART3SW_Pos (18U)
<> 147:30b64687e01f 11329 #define RCC_CFGR3_USART3SW_Msk (0x3U << RCC_CFGR3_USART3SW_Pos) /*!< 0x000C0000 */
<> 147:30b64687e01f 11330 #define RCC_CFGR3_USART3SW RCC_CFGR3_USART3SW_Msk /*!< USART3SW[1:0] bits */
<> 147:30b64687e01f 11331 #define RCC_CFGR3_USART3SW_0 (0x1U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11332 #define RCC_CFGR3_USART3SW_1 (0x2U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11333
<> 147:30b64687e01f 11334 #define RCC_CFGR3_USART3SW_PCLK (0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
<> 147:30b64687e01f 11335 #define RCC_CFGR3_USART3SW_SYSCLK (0x00040000U) /*!< System clock selected as USART3 clock source */
<> 147:30b64687e01f 11336 #define RCC_CFGR3_USART3SW_LSE (0x00080000U) /*!< LSE oscillator clock used as USART3 clock source */
<> 147:30b64687e01f 11337 #define RCC_CFGR3_USART3SW_HSI (0x000C0000U) /*!< HSI oscillator clock used as USART3 clock source */
<> 147:30b64687e01f 11338
<> 147:30b64687e01f 11339 #define RCC_CFGR3_UART4SW_Pos (20U)
<> 147:30b64687e01f 11340 #define RCC_CFGR3_UART4SW_Msk (0x3U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 11341 #define RCC_CFGR3_UART4SW RCC_CFGR3_UART4SW_Msk /*!< UART4SW[1:0] bits */
<> 147:30b64687e01f 11342 #define RCC_CFGR3_UART4SW_0 (0x1U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11343 #define RCC_CFGR3_UART4SW_1 (0x2U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11344
<> 147:30b64687e01f 11345 #define RCC_CFGR3_UART4SW_PCLK (0x00000000U) /*!< PCLK1 clock used as UART4 clock source */
<> 147:30b64687e01f 11346 #define RCC_CFGR3_UART4SW_SYSCLK (0x00100000U) /*!< System clock selected as UART4 clock source */
<> 147:30b64687e01f 11347 #define RCC_CFGR3_UART4SW_LSE (0x00200000U) /*!< LSE oscillator clock used as UART4 clock source */
<> 147:30b64687e01f 11348 #define RCC_CFGR3_UART4SW_HSI (0x00300000U) /*!< HSI oscillator clock used as UART4 clock source */
<> 147:30b64687e01f 11349
<> 147:30b64687e01f 11350 #define RCC_CFGR3_UART5SW_Pos (22U)
<> 147:30b64687e01f 11351 #define RCC_CFGR3_UART5SW_Msk (0x3U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00C00000 */
<> 147:30b64687e01f 11352 #define RCC_CFGR3_UART5SW RCC_CFGR3_UART5SW_Msk /*!< UART5SW[1:0] bits */
<> 147:30b64687e01f 11353 #define RCC_CFGR3_UART5SW_0 (0x1U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11354 #define RCC_CFGR3_UART5SW_1 (0x2U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11355
<> 147:30b64687e01f 11356 #define RCC_CFGR3_UART5SW_PCLK (0x00000000U) /*!< PCLK1 clock used as UART5 clock source */
<> 147:30b64687e01f 11357 #define RCC_CFGR3_UART5SW_SYSCLK (0x00400000U) /*!< System clock selected as UART5 clock source */
<> 147:30b64687e01f 11358 #define RCC_CFGR3_UART5SW_LSE (0x00800000U) /*!< LSE oscillator clock used as UART5 clock source */
<> 147:30b64687e01f 11359 #define RCC_CFGR3_UART5SW_HSI (0x00C00000U) /*!< HSI oscillator clock used as UART5 clock source */
<> 147:30b64687e01f 11360
<> 147:30b64687e01f 11361 #define RCC_CFGR3_TIM2SW_PCLK1 (0x00000000U) /*!< PCLK1 used as TIM2 clock source */
<> 147:30b64687e01f 11362 #define RCC_CFGR3_TIM2SW_PLL_Pos (24U)
<> 147:30b64687e01f 11363 #define RCC_CFGR3_TIM2SW_PLL_Msk (0x1U << RCC_CFGR3_TIM2SW_PLL_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11364 #define RCC_CFGR3_TIM2SW_PLL RCC_CFGR3_TIM2SW_PLL_Msk /*!< PLL clock used as TIM2 clock source */
<> 147:30b64687e01f 11365
<> 147:30b64687e01f 11366 #define RCC_CFGR3_TIM34SW_PCLK1 (0x00000000U) /*!< PCLK1 used as TIM3/TIM4 clock source */
<> 147:30b64687e01f 11367 #define RCC_CFGR3_TIM34SW_PLL_Pos (25U)
<> 147:30b64687e01f 11368 #define RCC_CFGR3_TIM34SW_PLL_Msk (0x1U << RCC_CFGR3_TIM34SW_PLL_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11369 #define RCC_CFGR3_TIM34SW_PLL RCC_CFGR3_TIM34SW_PLL_Msk /*!< PLL clock used as TIM3/TIM4 clock source */
<> 147:30b64687e01f 11370
<> 147:30b64687e01f 11371 /* Legacy defines */
<> 147:30b64687e01f 11372 #define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2
<> 147:30b64687e01f 11373 #define RCC_CFGR3_TIM8SW_HCLK RCC_CFGR3_TIM8SW_PCLK2
<> 147:30b64687e01f 11374 #define RCC_CFGR3_TIM15SW_HCLK RCC_CFGR3_TIM15SW_PCLK2
<> 147:30b64687e01f 11375 #define RCC_CFGR3_TIM16SW_HCLK RCC_CFGR3_TIM16SW_PCLK2
<> 147:30b64687e01f 11376 #define RCC_CFGR3_TIM17SW_HCLK RCC_CFGR3_TIM17SW_PCLK2
<> 147:30b64687e01f 11377 #define RCC_CFGR3_TIM20SW_HCLK RCC_CFGR3_TIM20SW_PCLK2
<> 147:30b64687e01f 11378 #define RCC_CFGR3_TIM2SW_HCLK RCC_CFGR3_TIM2SW_PCLK1
<> 147:30b64687e01f 11379 #define RCC_CFGR3_TIM34SW_HCLK RCC_CFGR3_TIM34SW_PCLK1
<> 147:30b64687e01f 11380
<> 147:30b64687e01f 11381 /******************************************************************************/
<> 147:30b64687e01f 11382 /* */
<> 147:30b64687e01f 11383 /* Real-Time Clock (RTC) */
<> 147:30b64687e01f 11384 /* */
<> 147:30b64687e01f 11385 /******************************************************************************/
<> 147:30b64687e01f 11386 /*
<> 147:30b64687e01f 11387 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 147:30b64687e01f 11388 */
<> 147:30b64687e01f 11389 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
<> 147:30b64687e01f 11390 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
<> 147:30b64687e01f 11391 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
<> 147:30b64687e01f 11392 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
<> 147:30b64687e01f 11393 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
<> 147:30b64687e01f 11394
<> 147:30b64687e01f 11395 /******************** Bits definition for RTC_TR register *******************/
<> 147:30b64687e01f 11396 #define RTC_TR_PM_Pos (22U)
<> 147:30b64687e01f 11397 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11398 #define RTC_TR_PM RTC_TR_PM_Msk
<> 147:30b64687e01f 11399 #define RTC_TR_HT_Pos (20U)
<> 147:30b64687e01f 11400 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 11401 #define RTC_TR_HT RTC_TR_HT_Msk
<> 147:30b64687e01f 11402 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11403 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11404 #define RTC_TR_HU_Pos (16U)
<> 147:30b64687e01f 11405 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 11406 #define RTC_TR_HU RTC_TR_HU_Msk
<> 147:30b64687e01f 11407 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11408 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11409 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11410 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11411 #define RTC_TR_MNT_Pos (12U)
<> 147:30b64687e01f 11412 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
<> 147:30b64687e01f 11413 #define RTC_TR_MNT RTC_TR_MNT_Msk
<> 147:30b64687e01f 11414 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11415 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11416 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11417 #define RTC_TR_MNU_Pos (8U)
<> 147:30b64687e01f 11418 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 11419 #define RTC_TR_MNU RTC_TR_MNU_Msk
<> 147:30b64687e01f 11420 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11421 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11422 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11423 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11424 #define RTC_TR_ST_Pos (4U)
<> 147:30b64687e01f 11425 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 11426 #define RTC_TR_ST RTC_TR_ST_Msk
<> 147:30b64687e01f 11427 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11428 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11429 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11430 #define RTC_TR_SU_Pos (0U)
<> 147:30b64687e01f 11431 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 11432 #define RTC_TR_SU RTC_TR_SU_Msk
<> 147:30b64687e01f 11433 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11434 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11435 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11436 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11437
<> 147:30b64687e01f 11438 /******************** Bits definition for RTC_DR register *******************/
<> 147:30b64687e01f 11439 #define RTC_DR_YT_Pos (20U)
<> 147:30b64687e01f 11440 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 11441 #define RTC_DR_YT RTC_DR_YT_Msk
<> 147:30b64687e01f 11442 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11443 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11444 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11445 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11446 #define RTC_DR_YU_Pos (16U)
<> 147:30b64687e01f 11447 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 11448 #define RTC_DR_YU RTC_DR_YU_Msk
<> 147:30b64687e01f 11449 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11450 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11451 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11452 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11453 #define RTC_DR_WDU_Pos (13U)
<> 147:30b64687e01f 11454 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
<> 147:30b64687e01f 11455 #define RTC_DR_WDU RTC_DR_WDU_Msk
<> 147:30b64687e01f 11456 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11457 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11458 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11459 #define RTC_DR_MT_Pos (12U)
<> 147:30b64687e01f 11460 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11461 #define RTC_DR_MT RTC_DR_MT_Msk
<> 147:30b64687e01f 11462 #define RTC_DR_MU_Pos (8U)
<> 147:30b64687e01f 11463 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 11464 #define RTC_DR_MU RTC_DR_MU_Msk
<> 147:30b64687e01f 11465 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11466 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11467 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11468 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11469 #define RTC_DR_DT_Pos (4U)
<> 147:30b64687e01f 11470 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 11471 #define RTC_DR_DT RTC_DR_DT_Msk
<> 147:30b64687e01f 11472 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11473 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11474 #define RTC_DR_DU_Pos (0U)
<> 147:30b64687e01f 11475 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 11476 #define RTC_DR_DU RTC_DR_DU_Msk
<> 147:30b64687e01f 11477 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11478 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11479 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11480 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11481
<> 147:30b64687e01f 11482 /******************** Bits definition for RTC_CR register *******************/
<> 147:30b64687e01f 11483 #define RTC_CR_COE_Pos (23U)
<> 147:30b64687e01f 11484 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11485 #define RTC_CR_COE RTC_CR_COE_Msk
<> 147:30b64687e01f 11486 #define RTC_CR_OSEL_Pos (21U)
<> 147:30b64687e01f 11487 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
<> 147:30b64687e01f 11488 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
<> 147:30b64687e01f 11489 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11490 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11491 #define RTC_CR_POL_Pos (20U)
<> 147:30b64687e01f 11492 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11493 #define RTC_CR_POL RTC_CR_POL_Msk
<> 147:30b64687e01f 11494 #define RTC_CR_COSEL_Pos (19U)
<> 147:30b64687e01f 11495 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11496 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
<> 147:30b64687e01f 11497 #define RTC_CR_BCK_Pos (18U)
<> 147:30b64687e01f 11498 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11499 #define RTC_CR_BCK RTC_CR_BCK_Msk
<> 147:30b64687e01f 11500 #define RTC_CR_SUB1H_Pos (17U)
<> 147:30b64687e01f 11501 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11502 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
<> 147:30b64687e01f 11503 #define RTC_CR_ADD1H_Pos (16U)
<> 147:30b64687e01f 11504 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11505 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
<> 147:30b64687e01f 11506 #define RTC_CR_TSIE_Pos (15U)
<> 147:30b64687e01f 11507 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11508 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
<> 147:30b64687e01f 11509 #define RTC_CR_WUTIE_Pos (14U)
<> 147:30b64687e01f 11510 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11511 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
<> 147:30b64687e01f 11512 #define RTC_CR_ALRBIE_Pos (13U)
<> 147:30b64687e01f 11513 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11514 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
<> 147:30b64687e01f 11515 #define RTC_CR_ALRAIE_Pos (12U)
<> 147:30b64687e01f 11516 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11517 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
<> 147:30b64687e01f 11518 #define RTC_CR_TSE_Pos (11U)
<> 147:30b64687e01f 11519 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11520 #define RTC_CR_TSE RTC_CR_TSE_Msk
<> 147:30b64687e01f 11521 #define RTC_CR_WUTE_Pos (10U)
<> 147:30b64687e01f 11522 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11523 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
<> 147:30b64687e01f 11524 #define RTC_CR_ALRBE_Pos (9U)
<> 147:30b64687e01f 11525 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11526 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
<> 147:30b64687e01f 11527 #define RTC_CR_ALRAE_Pos (8U)
<> 147:30b64687e01f 11528 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11529 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
<> 147:30b64687e01f 11530 #define RTC_CR_FMT_Pos (6U)
<> 147:30b64687e01f 11531 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11532 #define RTC_CR_FMT RTC_CR_FMT_Msk
<> 147:30b64687e01f 11533 #define RTC_CR_BYPSHAD_Pos (5U)
<> 147:30b64687e01f 11534 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11535 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
<> 147:30b64687e01f 11536 #define RTC_CR_REFCKON_Pos (4U)
<> 147:30b64687e01f 11537 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11538 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
<> 147:30b64687e01f 11539 #define RTC_CR_TSEDGE_Pos (3U)
<> 147:30b64687e01f 11540 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11541 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
<> 147:30b64687e01f 11542 #define RTC_CR_WUCKSEL_Pos (0U)
<> 147:30b64687e01f 11543 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
<> 147:30b64687e01f 11544 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
<> 147:30b64687e01f 11545 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11546 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11547 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11548
<> 147:30b64687e01f 11549 /******************** Bits definition for RTC_ISR register ******************/
<> 147:30b64687e01f 11550 #define RTC_ISR_RECALPF_Pos (16U)
<> 147:30b64687e01f 11551 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11552 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
<> 147:30b64687e01f 11553 #define RTC_ISR_TAMP3F_Pos (15U)
<> 147:30b64687e01f 11554 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11555 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
<> 147:30b64687e01f 11556 #define RTC_ISR_TAMP2F_Pos (14U)
<> 147:30b64687e01f 11557 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11558 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
<> 147:30b64687e01f 11559 #define RTC_ISR_TAMP1F_Pos (13U)
<> 147:30b64687e01f 11560 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11561 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
<> 147:30b64687e01f 11562 #define RTC_ISR_TSOVF_Pos (12U)
<> 147:30b64687e01f 11563 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11564 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
<> 147:30b64687e01f 11565 #define RTC_ISR_TSF_Pos (11U)
<> 147:30b64687e01f 11566 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11567 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
<> 147:30b64687e01f 11568 #define RTC_ISR_WUTF_Pos (10U)
<> 147:30b64687e01f 11569 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11570 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
<> 147:30b64687e01f 11571 #define RTC_ISR_ALRBF_Pos (9U)
<> 147:30b64687e01f 11572 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11573 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
<> 147:30b64687e01f 11574 #define RTC_ISR_ALRAF_Pos (8U)
<> 147:30b64687e01f 11575 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11576 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
<> 147:30b64687e01f 11577 #define RTC_ISR_INIT_Pos (7U)
<> 147:30b64687e01f 11578 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 11579 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
<> 147:30b64687e01f 11580 #define RTC_ISR_INITF_Pos (6U)
<> 147:30b64687e01f 11581 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11582 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
<> 147:30b64687e01f 11583 #define RTC_ISR_RSF_Pos (5U)
<> 147:30b64687e01f 11584 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11585 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
<> 147:30b64687e01f 11586 #define RTC_ISR_INITS_Pos (4U)
<> 147:30b64687e01f 11587 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11588 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
<> 147:30b64687e01f 11589 #define RTC_ISR_SHPF_Pos (3U)
<> 147:30b64687e01f 11590 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11591 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
<> 147:30b64687e01f 11592 #define RTC_ISR_WUTWF_Pos (2U)
<> 147:30b64687e01f 11593 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11594 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
<> 147:30b64687e01f 11595 #define RTC_ISR_ALRBWF_Pos (1U)
<> 147:30b64687e01f 11596 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11597 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
<> 147:30b64687e01f 11598 #define RTC_ISR_ALRAWF_Pos (0U)
<> 147:30b64687e01f 11599 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11600 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 147:30b64687e01f 11601
<> 147:30b64687e01f 11602 /******************** Bits definition for RTC_PRER register *****************/
<> 147:30b64687e01f 11603 #define RTC_PRER_PREDIV_A_Pos (16U)
<> 147:30b64687e01f 11604 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
<> 147:30b64687e01f 11605 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
<> 147:30b64687e01f 11606 #define RTC_PRER_PREDIV_S_Pos (0U)
<> 147:30b64687e01f 11607 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
<> 147:30b64687e01f 11608 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 147:30b64687e01f 11609
<> 147:30b64687e01f 11610 /******************** Bits definition for RTC_WUTR register *****************/
<> 147:30b64687e01f 11611 #define RTC_WUTR_WUT_Pos (0U)
<> 147:30b64687e01f 11612 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 11613 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 147:30b64687e01f 11614
<> 147:30b64687e01f 11615 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 147:30b64687e01f 11616 #define RTC_ALRMAR_MSK4_Pos (31U)
<> 147:30b64687e01f 11617 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 11618 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
<> 147:30b64687e01f 11619 #define RTC_ALRMAR_WDSEL_Pos (30U)
<> 147:30b64687e01f 11620 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 11621 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
<> 147:30b64687e01f 11622 #define RTC_ALRMAR_DT_Pos (28U)
<> 147:30b64687e01f 11623 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 11624 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
<> 147:30b64687e01f 11625 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 11626 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 11627 #define RTC_ALRMAR_DU_Pos (24U)
<> 147:30b64687e01f 11628 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 11629 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
<> 147:30b64687e01f 11630 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11631 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11632 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 11633 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 11634 #define RTC_ALRMAR_MSK3_Pos (23U)
<> 147:30b64687e01f 11635 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11636 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
<> 147:30b64687e01f 11637 #define RTC_ALRMAR_PM_Pos (22U)
<> 147:30b64687e01f 11638 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11639 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
<> 147:30b64687e01f 11640 #define RTC_ALRMAR_HT_Pos (20U)
<> 147:30b64687e01f 11641 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 11642 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
<> 147:30b64687e01f 11643 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11644 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11645 #define RTC_ALRMAR_HU_Pos (16U)
<> 147:30b64687e01f 11646 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 11647 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
<> 147:30b64687e01f 11648 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11649 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11650 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11651 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11652 #define RTC_ALRMAR_MSK2_Pos (15U)
<> 147:30b64687e01f 11653 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11654 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
<> 147:30b64687e01f 11655 #define RTC_ALRMAR_MNT_Pos (12U)
<> 147:30b64687e01f 11656 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
<> 147:30b64687e01f 11657 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
<> 147:30b64687e01f 11658 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11659 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11660 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11661 #define RTC_ALRMAR_MNU_Pos (8U)
<> 147:30b64687e01f 11662 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 11663 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
<> 147:30b64687e01f 11664 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11665 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11666 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11667 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11668 #define RTC_ALRMAR_MSK1_Pos (7U)
<> 147:30b64687e01f 11669 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 11670 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
<> 147:30b64687e01f 11671 #define RTC_ALRMAR_ST_Pos (4U)
<> 147:30b64687e01f 11672 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 11673 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
<> 147:30b64687e01f 11674 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11675 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11676 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11677 #define RTC_ALRMAR_SU_Pos (0U)
<> 147:30b64687e01f 11678 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 11679 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
<> 147:30b64687e01f 11680 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11681 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11682 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11683 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11684
<> 147:30b64687e01f 11685 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 147:30b64687e01f 11686 #define RTC_ALRMBR_MSK4_Pos (31U)
<> 147:30b64687e01f 11687 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 11688 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
<> 147:30b64687e01f 11689 #define RTC_ALRMBR_WDSEL_Pos (30U)
<> 147:30b64687e01f 11690 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 11691 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
<> 147:30b64687e01f 11692 #define RTC_ALRMBR_DT_Pos (28U)
<> 147:30b64687e01f 11693 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
<> 147:30b64687e01f 11694 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
<> 147:30b64687e01f 11695 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 11696 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 11697 #define RTC_ALRMBR_DU_Pos (24U)
<> 147:30b64687e01f 11698 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 11699 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
<> 147:30b64687e01f 11700 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11701 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11702 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 11703 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 11704 #define RTC_ALRMBR_MSK3_Pos (23U)
<> 147:30b64687e01f 11705 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11706 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
<> 147:30b64687e01f 11707 #define RTC_ALRMBR_PM_Pos (22U)
<> 147:30b64687e01f 11708 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11709 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
<> 147:30b64687e01f 11710 #define RTC_ALRMBR_HT_Pos (20U)
<> 147:30b64687e01f 11711 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 11712 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
<> 147:30b64687e01f 11713 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11714 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11715 #define RTC_ALRMBR_HU_Pos (16U)
<> 147:30b64687e01f 11716 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 11717 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
<> 147:30b64687e01f 11718 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11719 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11720 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11721 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11722 #define RTC_ALRMBR_MSK2_Pos (15U)
<> 147:30b64687e01f 11723 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11724 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
<> 147:30b64687e01f 11725 #define RTC_ALRMBR_MNT_Pos (12U)
<> 147:30b64687e01f 11726 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
<> 147:30b64687e01f 11727 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
<> 147:30b64687e01f 11728 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11729 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11730 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11731 #define RTC_ALRMBR_MNU_Pos (8U)
<> 147:30b64687e01f 11732 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 11733 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
<> 147:30b64687e01f 11734 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11735 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11736 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11737 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11738 #define RTC_ALRMBR_MSK1_Pos (7U)
<> 147:30b64687e01f 11739 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 11740 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
<> 147:30b64687e01f 11741 #define RTC_ALRMBR_ST_Pos (4U)
<> 147:30b64687e01f 11742 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 11743 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
<> 147:30b64687e01f 11744 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11745 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11746 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11747 #define RTC_ALRMBR_SU_Pos (0U)
<> 147:30b64687e01f 11748 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 11749 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
<> 147:30b64687e01f 11750 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11751 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11752 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11753 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11754
<> 147:30b64687e01f 11755 /******************** Bits definition for RTC_WPR register ******************/
<> 147:30b64687e01f 11756 #define RTC_WPR_KEY_Pos (0U)
<> 147:30b64687e01f 11757 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 11758 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 147:30b64687e01f 11759
<> 147:30b64687e01f 11760 /******************** Bits definition for RTC_SSR register ******************/
<> 147:30b64687e01f 11761 #define RTC_SSR_SS_Pos (0U)
<> 147:30b64687e01f 11762 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 11763 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 147:30b64687e01f 11764
<> 147:30b64687e01f 11765 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 147:30b64687e01f 11766 #define RTC_SHIFTR_SUBFS_Pos (0U)
<> 147:30b64687e01f 11767 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
<> 147:30b64687e01f 11768 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
<> 147:30b64687e01f 11769 #define RTC_SHIFTR_ADD1S_Pos (31U)
<> 147:30b64687e01f 11770 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 11771 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 147:30b64687e01f 11772
<> 147:30b64687e01f 11773 /******************** Bits definition for RTC_TSTR register *****************/
<> 147:30b64687e01f 11774 #define RTC_TSTR_PM_Pos (22U)
<> 147:30b64687e01f 11775 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11776 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
<> 147:30b64687e01f 11777 #define RTC_TSTR_HT_Pos (20U)
<> 147:30b64687e01f 11778 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 11779 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
<> 147:30b64687e01f 11780 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11781 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11782 #define RTC_TSTR_HU_Pos (16U)
<> 147:30b64687e01f 11783 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 11784 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
<> 147:30b64687e01f 11785 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 11786 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 11787 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11788 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11789 #define RTC_TSTR_MNT_Pos (12U)
<> 147:30b64687e01f 11790 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
<> 147:30b64687e01f 11791 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
<> 147:30b64687e01f 11792 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11793 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11794 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11795 #define RTC_TSTR_MNU_Pos (8U)
<> 147:30b64687e01f 11796 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 11797 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
<> 147:30b64687e01f 11798 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11799 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11800 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11801 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11802 #define RTC_TSTR_ST_Pos (4U)
<> 147:30b64687e01f 11803 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 11804 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
<> 147:30b64687e01f 11805 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11806 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11807 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11808 #define RTC_TSTR_SU_Pos (0U)
<> 147:30b64687e01f 11809 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 11810 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
<> 147:30b64687e01f 11811 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11812 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11813 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11814 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11815
<> 147:30b64687e01f 11816 /******************** Bits definition for RTC_TSDR register *****************/
<> 147:30b64687e01f 11817 #define RTC_TSDR_WDU_Pos (13U)
<> 147:30b64687e01f 11818 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
<> 147:30b64687e01f 11819 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
<> 147:30b64687e01f 11820 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11821 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11822 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11823 #define RTC_TSDR_MT_Pos (12U)
<> 147:30b64687e01f 11824 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11825 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
<> 147:30b64687e01f 11826 #define RTC_TSDR_MU_Pos (8U)
<> 147:30b64687e01f 11827 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 11828 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
<> 147:30b64687e01f 11829 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11830 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11831 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11832 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11833 #define RTC_TSDR_DT_Pos (4U)
<> 147:30b64687e01f 11834 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 11835 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
<> 147:30b64687e01f 11836 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11837 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11838 #define RTC_TSDR_DU_Pos (0U)
<> 147:30b64687e01f 11839 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 11840 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
<> 147:30b64687e01f 11841 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11842 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11843 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11844 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11845
<> 147:30b64687e01f 11846 /******************** Bits definition for RTC_TSSSR register ****************/
<> 147:30b64687e01f 11847 #define RTC_TSSSR_SS_Pos (0U)
<> 147:30b64687e01f 11848 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 11849 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 147:30b64687e01f 11850
<> 147:30b64687e01f 11851 /******************** Bits definition for RTC_CAL register *****************/
<> 147:30b64687e01f 11852 #define RTC_CALR_CALP_Pos (15U)
<> 147:30b64687e01f 11853 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11854 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
<> 147:30b64687e01f 11855 #define RTC_CALR_CALW8_Pos (14U)
<> 147:30b64687e01f 11856 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11857 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
<> 147:30b64687e01f 11858 #define RTC_CALR_CALW16_Pos (13U)
<> 147:30b64687e01f 11859 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11860 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
<> 147:30b64687e01f 11861 #define RTC_CALR_CALM_Pos (0U)
<> 147:30b64687e01f 11862 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
<> 147:30b64687e01f 11863 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
<> 147:30b64687e01f 11864 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11865 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11866 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11867 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11868 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11869 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11870 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11871 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 11872 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11873
<> 147:30b64687e01f 11874 /******************** Bits definition for RTC_TAFCR register ****************/
<> 147:30b64687e01f 11875 #define RTC_TAFCR_PC15MODE_Pos (23U)
<> 147:30b64687e01f 11876 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 11877 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
<> 147:30b64687e01f 11878 #define RTC_TAFCR_PC15VALUE_Pos (22U)
<> 147:30b64687e01f 11879 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 11880 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
<> 147:30b64687e01f 11881 #define RTC_TAFCR_PC14MODE_Pos (21U)
<> 147:30b64687e01f 11882 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 11883 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
<> 147:30b64687e01f 11884 #define RTC_TAFCR_PC14VALUE_Pos (20U)
<> 147:30b64687e01f 11885 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 11886 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
<> 147:30b64687e01f 11887 #define RTC_TAFCR_PC13MODE_Pos (19U)
<> 147:30b64687e01f 11888 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 11889 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
<> 147:30b64687e01f 11890 #define RTC_TAFCR_PC13VALUE_Pos (18U)
<> 147:30b64687e01f 11891 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 11892 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
<> 147:30b64687e01f 11893 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
<> 147:30b64687e01f 11894 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 11895 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
<> 147:30b64687e01f 11896 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
<> 147:30b64687e01f 11897 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
<> 147:30b64687e01f 11898 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
<> 147:30b64687e01f 11899 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 11900 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 11901 #define RTC_TAFCR_TAMPFLT_Pos (11U)
<> 147:30b64687e01f 11902 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
<> 147:30b64687e01f 11903 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
<> 147:30b64687e01f 11904 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 11905 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 11906 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
<> 147:30b64687e01f 11907 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
<> 147:30b64687e01f 11908 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
<> 147:30b64687e01f 11909 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 11910 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 11911 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 11912 #define RTC_TAFCR_TAMPTS_Pos (7U)
<> 147:30b64687e01f 11913 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 11914 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
<> 147:30b64687e01f 11915 #define RTC_TAFCR_TAMP3TRG_Pos (6U)
<> 147:30b64687e01f 11916 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 11917 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
<> 147:30b64687e01f 11918 #define RTC_TAFCR_TAMP3E_Pos (5U)
<> 147:30b64687e01f 11919 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 11920 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
<> 147:30b64687e01f 11921 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
<> 147:30b64687e01f 11922 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 11923 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
<> 147:30b64687e01f 11924 #define RTC_TAFCR_TAMP2E_Pos (3U)
<> 147:30b64687e01f 11925 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 11926 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
<> 147:30b64687e01f 11927 #define RTC_TAFCR_TAMPIE_Pos (2U)
<> 147:30b64687e01f 11928 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 11929 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
<> 147:30b64687e01f 11930 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
<> 147:30b64687e01f 11931 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 11932 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
<> 147:30b64687e01f 11933 #define RTC_TAFCR_TAMP1E_Pos (0U)
<> 147:30b64687e01f 11934 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 11935 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
<> 147:30b64687e01f 11936
<> 147:30b64687e01f 11937 /* Reference defines */
<> 147:30b64687e01f 11938 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
<> 147:30b64687e01f 11939
<> 147:30b64687e01f 11940 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 147:30b64687e01f 11941 #define RTC_ALRMASSR_MASKSS_Pos (24U)
<> 147:30b64687e01f 11942 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 11943 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
<> 147:30b64687e01f 11944 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11945 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11946 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 11947 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 11948 #define RTC_ALRMASSR_SS_Pos (0U)
<> 147:30b64687e01f 11949 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
<> 147:30b64687e01f 11950 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 147:30b64687e01f 11951
<> 147:30b64687e01f 11952 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 147:30b64687e01f 11953 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
<> 147:30b64687e01f 11954 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 11955 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
<> 147:30b64687e01f 11956 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 11957 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 11958 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 11959 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 11960 #define RTC_ALRMBSSR_SS_Pos (0U)
<> 147:30b64687e01f 11961 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
<> 147:30b64687e01f 11962 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
<> 147:30b64687e01f 11963
<> 147:30b64687e01f 11964 /******************** Bits definition for RTC_BKP0R register ****************/
<> 147:30b64687e01f 11965 #define RTC_BKP0R_Pos (0U)
<> 147:30b64687e01f 11966 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 11967 #define RTC_BKP0R RTC_BKP0R_Msk
<> 147:30b64687e01f 11968
<> 147:30b64687e01f 11969 /******************** Bits definition for RTC_BKP1R register ****************/
<> 147:30b64687e01f 11970 #define RTC_BKP1R_Pos (0U)
<> 147:30b64687e01f 11971 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 11972 #define RTC_BKP1R RTC_BKP1R_Msk
<> 147:30b64687e01f 11973
<> 147:30b64687e01f 11974 /******************** Bits definition for RTC_BKP2R register ****************/
<> 147:30b64687e01f 11975 #define RTC_BKP2R_Pos (0U)
<> 147:30b64687e01f 11976 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 11977 #define RTC_BKP2R RTC_BKP2R_Msk
<> 147:30b64687e01f 11978
<> 147:30b64687e01f 11979 /******************** Bits definition for RTC_BKP3R register ****************/
<> 147:30b64687e01f 11980 #define RTC_BKP3R_Pos (0U)
<> 147:30b64687e01f 11981 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 11982 #define RTC_BKP3R RTC_BKP3R_Msk
<> 147:30b64687e01f 11983
<> 147:30b64687e01f 11984 /******************** Bits definition for RTC_BKP4R register ****************/
<> 147:30b64687e01f 11985 #define RTC_BKP4R_Pos (0U)
<> 147:30b64687e01f 11986 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 11987 #define RTC_BKP4R RTC_BKP4R_Msk
<> 147:30b64687e01f 11988
<> 147:30b64687e01f 11989 /******************** Bits definition for RTC_BKP5R register ****************/
<> 147:30b64687e01f 11990 #define RTC_BKP5R_Pos (0U)
<> 147:30b64687e01f 11991 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 11992 #define RTC_BKP5R RTC_BKP5R_Msk
<> 147:30b64687e01f 11993
<> 147:30b64687e01f 11994 /******************** Bits definition for RTC_BKP6R register ****************/
<> 147:30b64687e01f 11995 #define RTC_BKP6R_Pos (0U)
<> 147:30b64687e01f 11996 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 11997 #define RTC_BKP6R RTC_BKP6R_Msk
<> 147:30b64687e01f 11998
<> 147:30b64687e01f 11999 /******************** Bits definition for RTC_BKP7R register ****************/
<> 147:30b64687e01f 12000 #define RTC_BKP7R_Pos (0U)
<> 147:30b64687e01f 12001 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12002 #define RTC_BKP7R RTC_BKP7R_Msk
<> 147:30b64687e01f 12003
<> 147:30b64687e01f 12004 /******************** Bits definition for RTC_BKP8R register ****************/
<> 147:30b64687e01f 12005 #define RTC_BKP8R_Pos (0U)
<> 147:30b64687e01f 12006 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12007 #define RTC_BKP8R RTC_BKP8R_Msk
<> 147:30b64687e01f 12008
<> 147:30b64687e01f 12009 /******************** Bits definition for RTC_BKP9R register ****************/
<> 147:30b64687e01f 12010 #define RTC_BKP9R_Pos (0U)
<> 147:30b64687e01f 12011 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12012 #define RTC_BKP9R RTC_BKP9R_Msk
<> 147:30b64687e01f 12013
<> 147:30b64687e01f 12014 /******************** Bits definition for RTC_BKP10R register ***************/
<> 147:30b64687e01f 12015 #define RTC_BKP10R_Pos (0U)
<> 147:30b64687e01f 12016 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12017 #define RTC_BKP10R RTC_BKP10R_Msk
<> 147:30b64687e01f 12018
<> 147:30b64687e01f 12019 /******************** Bits definition for RTC_BKP11R register ***************/
<> 147:30b64687e01f 12020 #define RTC_BKP11R_Pos (0U)
<> 147:30b64687e01f 12021 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12022 #define RTC_BKP11R RTC_BKP11R_Msk
<> 147:30b64687e01f 12023
<> 147:30b64687e01f 12024 /******************** Bits definition for RTC_BKP12R register ***************/
<> 147:30b64687e01f 12025 #define RTC_BKP12R_Pos (0U)
<> 147:30b64687e01f 12026 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12027 #define RTC_BKP12R RTC_BKP12R_Msk
<> 147:30b64687e01f 12028
<> 147:30b64687e01f 12029 /******************** Bits definition for RTC_BKP13R register ***************/
<> 147:30b64687e01f 12030 #define RTC_BKP13R_Pos (0U)
<> 147:30b64687e01f 12031 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12032 #define RTC_BKP13R RTC_BKP13R_Msk
<> 147:30b64687e01f 12033
<> 147:30b64687e01f 12034 /******************** Bits definition for RTC_BKP14R register ***************/
<> 147:30b64687e01f 12035 #define RTC_BKP14R_Pos (0U)
<> 147:30b64687e01f 12036 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12037 #define RTC_BKP14R RTC_BKP14R_Msk
<> 147:30b64687e01f 12038
<> 147:30b64687e01f 12039 /******************** Bits definition for RTC_BKP15R register ***************/
<> 147:30b64687e01f 12040 #define RTC_BKP15R_Pos (0U)
<> 147:30b64687e01f 12041 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 12042 #define RTC_BKP15R RTC_BKP15R_Msk
<> 147:30b64687e01f 12043
<> 147:30b64687e01f 12044 /******************** Number of backup registers ******************************/
<> 147:30b64687e01f 12045 #define RTC_BKP_NUMBER 16
<> 147:30b64687e01f 12046
<> 147:30b64687e01f 12047 /******************************************************************************/
<> 147:30b64687e01f 12048 /* */
<> 147:30b64687e01f 12049 /* Serial Peripheral Interface (SPI) */
<> 147:30b64687e01f 12050 /* */
<> 147:30b64687e01f 12051 /******************************************************************************/
<> 147:30b64687e01f 12052
<> 147:30b64687e01f 12053 /*
<> 147:30b64687e01f 12054 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 147:30b64687e01f 12055 */
<> 147:30b64687e01f 12056 #define SPI_I2S_SUPPORT /*!< I2S support */
<> 147:30b64687e01f 12057 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
<> 147:30b64687e01f 12058
<> 147:30b64687e01f 12059 /******************* Bit definition for SPI_CR1 register ********************/
<> 147:30b64687e01f 12060 #define SPI_CR1_CPHA_Pos (0U)
<> 147:30b64687e01f 12061 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12062 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
<> 147:30b64687e01f 12063 #define SPI_CR1_CPOL_Pos (1U)
<> 147:30b64687e01f 12064 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12065 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
<> 147:30b64687e01f 12066 #define SPI_CR1_MSTR_Pos (2U)
<> 147:30b64687e01f 12067 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12068 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
<> 147:30b64687e01f 12069 #define SPI_CR1_BR_Pos (3U)
<> 147:30b64687e01f 12070 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
<> 147:30b64687e01f 12071 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
<> 147:30b64687e01f 12072 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12073 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12074 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12075 #define SPI_CR1_SPE_Pos (6U)
<> 147:30b64687e01f 12076 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12077 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
<> 147:30b64687e01f 12078 #define SPI_CR1_LSBFIRST_Pos (7U)
<> 147:30b64687e01f 12079 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12080 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
<> 147:30b64687e01f 12081 #define SPI_CR1_SSI_Pos (8U)
<> 147:30b64687e01f 12082 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12083 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
<> 147:30b64687e01f 12084 #define SPI_CR1_SSM_Pos (9U)
<> 147:30b64687e01f 12085 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12086 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
<> 147:30b64687e01f 12087 #define SPI_CR1_RXONLY_Pos (10U)
<> 147:30b64687e01f 12088 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12089 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
<> 147:30b64687e01f 12090 #define SPI_CR1_CRCL_Pos (11U)
<> 147:30b64687e01f 12091 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12092 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
<> 147:30b64687e01f 12093 #define SPI_CR1_CRCNEXT_Pos (12U)
<> 147:30b64687e01f 12094 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12095 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
<> 147:30b64687e01f 12096 #define SPI_CR1_CRCEN_Pos (13U)
<> 147:30b64687e01f 12097 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12098 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
<> 147:30b64687e01f 12099 #define SPI_CR1_BIDIOE_Pos (14U)
<> 147:30b64687e01f 12100 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 12101 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
<> 147:30b64687e01f 12102 #define SPI_CR1_BIDIMODE_Pos (15U)
<> 147:30b64687e01f 12103 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 12104 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
<> 147:30b64687e01f 12105
<> 147:30b64687e01f 12106 /******************* Bit definition for SPI_CR2 register ********************/
<> 147:30b64687e01f 12107 #define SPI_CR2_RXDMAEN_Pos (0U)
<> 147:30b64687e01f 12108 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12109 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
<> 147:30b64687e01f 12110 #define SPI_CR2_TXDMAEN_Pos (1U)
<> 147:30b64687e01f 12111 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12112 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
<> 147:30b64687e01f 12113 #define SPI_CR2_SSOE_Pos (2U)
<> 147:30b64687e01f 12114 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12115 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
<> 147:30b64687e01f 12116 #define SPI_CR2_NSSP_Pos (3U)
<> 147:30b64687e01f 12117 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12118 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
<> 147:30b64687e01f 12119 #define SPI_CR2_FRF_Pos (4U)
<> 147:30b64687e01f 12120 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12121 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
<> 147:30b64687e01f 12122 #define SPI_CR2_ERRIE_Pos (5U)
<> 147:30b64687e01f 12123 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12124 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
<> 147:30b64687e01f 12125 #define SPI_CR2_RXNEIE_Pos (6U)
<> 147:30b64687e01f 12126 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12127 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
<> 147:30b64687e01f 12128 #define SPI_CR2_TXEIE_Pos (7U)
<> 147:30b64687e01f 12129 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12130 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
<> 147:30b64687e01f 12131 #define SPI_CR2_DS_Pos (8U)
<> 147:30b64687e01f 12132 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 12133 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
<> 147:30b64687e01f 12134 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12135 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12136 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12137 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12138 #define SPI_CR2_FRXTH_Pos (12U)
<> 147:30b64687e01f 12139 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12140 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
<> 147:30b64687e01f 12141 #define SPI_CR2_LDMARX_Pos (13U)
<> 147:30b64687e01f 12142 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12143 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
<> 147:30b64687e01f 12144 #define SPI_CR2_LDMATX_Pos (14U)
<> 147:30b64687e01f 12145 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 12146 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
<> 147:30b64687e01f 12147
<> 147:30b64687e01f 12148 /******************** Bit definition for SPI_SR register ********************/
<> 147:30b64687e01f 12149 #define SPI_SR_RXNE_Pos (0U)
<> 147:30b64687e01f 12150 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12151 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
<> 147:30b64687e01f 12152 #define SPI_SR_TXE_Pos (1U)
<> 147:30b64687e01f 12153 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12154 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
<> 147:30b64687e01f 12155 #define SPI_SR_CHSIDE_Pos (2U)
<> 147:30b64687e01f 12156 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12157 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
<> 147:30b64687e01f 12158 #define SPI_SR_UDR_Pos (3U)
<> 147:30b64687e01f 12159 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12160 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
<> 147:30b64687e01f 12161 #define SPI_SR_CRCERR_Pos (4U)
<> 147:30b64687e01f 12162 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12163 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
<> 147:30b64687e01f 12164 #define SPI_SR_MODF_Pos (5U)
<> 147:30b64687e01f 12165 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12166 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
<> 147:30b64687e01f 12167 #define SPI_SR_OVR_Pos (6U)
<> 147:30b64687e01f 12168 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12169 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
<> 147:30b64687e01f 12170 #define SPI_SR_BSY_Pos (7U)
<> 147:30b64687e01f 12171 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12172 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
<> 147:30b64687e01f 12173 #define SPI_SR_FRE_Pos (8U)
<> 147:30b64687e01f 12174 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12175 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
<> 147:30b64687e01f 12176 #define SPI_SR_FRLVL_Pos (9U)
<> 147:30b64687e01f 12177 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
<> 147:30b64687e01f 12178 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
<> 147:30b64687e01f 12179 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12180 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12181 #define SPI_SR_FTLVL_Pos (11U)
<> 147:30b64687e01f 12182 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
<> 147:30b64687e01f 12183 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
<> 147:30b64687e01f 12184 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12185 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12186
<> 147:30b64687e01f 12187 /******************** Bit definition for SPI_DR register ********************/
<> 147:30b64687e01f 12188 #define SPI_DR_DR_Pos (0U)
<> 147:30b64687e01f 12189 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 12190 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
<> 147:30b64687e01f 12191
<> 147:30b64687e01f 12192 /******************* Bit definition for SPI_CRCPR register ******************/
<> 147:30b64687e01f 12193 #define SPI_CRCPR_CRCPOLY_Pos (0U)
<> 147:30b64687e01f 12194 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 12195 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
<> 147:30b64687e01f 12196
<> 147:30b64687e01f 12197 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 147:30b64687e01f 12198 #define SPI_RXCRCR_RXCRC_Pos (0U)
<> 147:30b64687e01f 12199 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 12200 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
<> 147:30b64687e01f 12201
<> 147:30b64687e01f 12202 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 147:30b64687e01f 12203 #define SPI_TXCRCR_TXCRC_Pos (0U)
<> 147:30b64687e01f 12204 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 12205 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
<> 147:30b64687e01f 12206
<> 147:30b64687e01f 12207 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 147:30b64687e01f 12208 #define SPI_I2SCFGR_CHLEN_Pos (0U)
<> 147:30b64687e01f 12209 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12210 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
<> 147:30b64687e01f 12211 #define SPI_I2SCFGR_DATLEN_Pos (1U)
<> 147:30b64687e01f 12212 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
<> 147:30b64687e01f 12213 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 147:30b64687e01f 12214 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12215 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12216 #define SPI_I2SCFGR_CKPOL_Pos (3U)
<> 147:30b64687e01f 12217 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12218 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
<> 147:30b64687e01f 12219 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
<> 147:30b64687e01f 12220 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
<> 147:30b64687e01f 12221 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 147:30b64687e01f 12222 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12223 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12224 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
<> 147:30b64687e01f 12225 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12226 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
<> 147:30b64687e01f 12227 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
<> 147:30b64687e01f 12228 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 12229 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 147:30b64687e01f 12230 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12231 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12232 #define SPI_I2SCFGR_I2SE_Pos (10U)
<> 147:30b64687e01f 12233 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12234 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
<> 147:30b64687e01f 12235 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
<> 147:30b64687e01f 12236 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12237 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
<> 147:30b64687e01f 12238
<> 147:30b64687e01f 12239 /****************** Bit definition for SPI_I2SPR register *******************/
<> 147:30b64687e01f 12240 #define SPI_I2SPR_I2SDIV_Pos (0U)
<> 147:30b64687e01f 12241 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 12242 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
<> 147:30b64687e01f 12243 #define SPI_I2SPR_ODD_Pos (8U)
<> 147:30b64687e01f 12244 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12245 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
<> 147:30b64687e01f 12246 #define SPI_I2SPR_MCKOE_Pos (9U)
<> 147:30b64687e01f 12247 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12248 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
<> 147:30b64687e01f 12249
<> 147:30b64687e01f 12250 /******************************************************************************/
<> 147:30b64687e01f 12251 /* */
<> 147:30b64687e01f 12252 /* System Configuration(SYSCFG) */
<> 147:30b64687e01f 12253 /* */
<> 147:30b64687e01f 12254 /******************************************************************************/
<> 147:30b64687e01f 12255 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
<> 147:30b64687e01f 12256 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
<> 147:30b64687e01f 12257 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x7U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000007 */
<> 147:30b64687e01f 12258 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
<> 147:30b64687e01f 12259 #define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U) /*!< Bit 0 */
<> 147:30b64687e01f 12260 #define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U) /*!< Bit 1 */
<> 147:30b64687e01f 12261 #define SYSCFG_CFGR1_MEM_MODE_2 (0x00000004U) /*!< Bit 2 */
<> 147:30b64687e01f 12262 #define SYSCFG_CFGR1_USB_IT_RMP_Pos (5U)
<> 147:30b64687e01f 12263 #define SYSCFG_CFGR1_USB_IT_RMP_Msk (0x1U << SYSCFG_CFGR1_USB_IT_RMP_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12264 #define SYSCFG_CFGR1_USB_IT_RMP SYSCFG_CFGR1_USB_IT_RMP_Msk /*!< USB interrupt remap */
<> 147:30b64687e01f 12265 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)
<> 147:30b64687e01f 12266 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12267 #define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */
<> 147:30b64687e01f 12268 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)
<> 147:30b64687e01f 12269 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1U << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12270 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */
<> 147:30b64687e01f 12271 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
<> 147:30b64687e01f 12272 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x79U << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00007900 */
<> 147:30b64687e01f 12273 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
<> 147:30b64687e01f 12274 #define SYSCFG_CFGR1_ADC24_DMA_RMP_Pos (8U)
<> 147:30b64687e01f 12275 #define SYSCFG_CFGR1_ADC24_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12276 #define SYSCFG_CFGR1_ADC24_DMA_RMP SYSCFG_CFGR1_ADC24_DMA_RMP_Msk /*!< ADC2 and ADC4 DMA remap */
<> 147:30b64687e01f 12277 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
<> 147:30b64687e01f 12278 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12279 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
<> 147:30b64687e01f 12280 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
<> 147:30b64687e01f 12281 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12282 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
<> 147:30b64687e01f 12283 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)
<> 147:30b64687e01f 12284 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12285 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */
<> 147:30b64687e01f 12286 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)
<> 147:30b64687e01f 12287 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 12288 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */
<> 147:30b64687e01f 12289 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
<> 147:30b64687e01f 12290 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 12291 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
<> 147:30b64687e01f 12292 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
<> 147:30b64687e01f 12293 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 12294 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
<> 147:30b64687e01f 12295 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
<> 147:30b64687e01f 12296 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 12297 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
<> 147:30b64687e01f 12298 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
<> 147:30b64687e01f 12299 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 12300 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
<> 147:30b64687e01f 12301 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
<> 147:30b64687e01f 12302 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 12303 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
<> 147:30b64687e01f 12304 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
<> 147:30b64687e01f 12305 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 12306 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
<> 147:30b64687e01f 12307 #define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)
<> 147:30b64687e01f 12308 #define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */
<> 147:30b64687e01f 12309 #define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */
<> 147:30b64687e01f 12310 #define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 12311 #define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 12312 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)
<> 147:30b64687e01f 12313 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 12314 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
<> 147:30b64687e01f 12315 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)
<> 147:30b64687e01f 12316 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 12317 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
<> 147:30b64687e01f 12318 #define SYSCFG_CFGR1_I2C3_FMP_Pos (24U)
<> 147:30b64687e01f 12319 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 12320 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
<> 147:30b64687e01f 12321 #define SYSCFG_CFGR1_FPU_IE_Pos (26U)
<> 147:30b64687e01f 12322 #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FU << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */
<> 147:30b64687e01f 12323 #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Floating Point Unit Interrupt Enable */
<> 147:30b64687e01f 12324 #define SYSCFG_CFGR1_FPU_IE_0 (0x01U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 12325 #define SYSCFG_CFGR1_FPU_IE_1 (0x02U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 12326 #define SYSCFG_CFGR1_FPU_IE_2 (0x04U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 12327 #define SYSCFG_CFGR1_FPU_IE_3 (0x08U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 12328 #define SYSCFG_CFGR1_FPU_IE_4 (0x10U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 12329 #define SYSCFG_CFGR1_FPU_IE_5 (0x20U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 12330
<> 147:30b64687e01f 12331 /***************** Bit definition for SYSCFG_RCR register *******************/
<> 147:30b64687e01f 12332 #define SYSCFG_RCR_PAGE0_Pos (0U)
<> 147:30b64687e01f 12333 #define SYSCFG_RCR_PAGE0_Msk (0x1U << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12334 #define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk /*!< ICODE SRAM Write protection page 0 */
<> 147:30b64687e01f 12335 #define SYSCFG_RCR_PAGE1_Pos (1U)
<> 147:30b64687e01f 12336 #define SYSCFG_RCR_PAGE1_Msk (0x1U << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12337 #define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk /*!< ICODE SRAM Write protection page 1 */
<> 147:30b64687e01f 12338 #define SYSCFG_RCR_PAGE2_Pos (2U)
<> 147:30b64687e01f 12339 #define SYSCFG_RCR_PAGE2_Msk (0x1U << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12340 #define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk /*!< ICODE SRAM Write protection page 2 */
<> 147:30b64687e01f 12341 #define SYSCFG_RCR_PAGE3_Pos (3U)
<> 147:30b64687e01f 12342 #define SYSCFG_RCR_PAGE3_Msk (0x1U << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12343 #define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk /*!< ICODE SRAM Write protection page 3 */
<> 147:30b64687e01f 12344 #define SYSCFG_RCR_PAGE4_Pos (4U)
<> 147:30b64687e01f 12345 #define SYSCFG_RCR_PAGE4_Msk (0x1U << SYSCFG_RCR_PAGE4_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12346 #define SYSCFG_RCR_PAGE4 SYSCFG_RCR_PAGE4_Msk /*!< ICODE SRAM Write protection page 4 */
<> 147:30b64687e01f 12347 #define SYSCFG_RCR_PAGE5_Pos (5U)
<> 147:30b64687e01f 12348 #define SYSCFG_RCR_PAGE5_Msk (0x1U << SYSCFG_RCR_PAGE5_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12349 #define SYSCFG_RCR_PAGE5 SYSCFG_RCR_PAGE5_Msk /*!< ICODE SRAM Write protection page 5 */
<> 147:30b64687e01f 12350 #define SYSCFG_RCR_PAGE6_Pos (6U)
<> 147:30b64687e01f 12351 #define SYSCFG_RCR_PAGE6_Msk (0x1U << SYSCFG_RCR_PAGE6_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12352 #define SYSCFG_RCR_PAGE6 SYSCFG_RCR_PAGE6_Msk /*!< ICODE SRAM Write protection page 6 */
<> 147:30b64687e01f 12353 #define SYSCFG_RCR_PAGE7_Pos (7U)
<> 147:30b64687e01f 12354 #define SYSCFG_RCR_PAGE7_Msk (0x1U << SYSCFG_RCR_PAGE7_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12355 #define SYSCFG_RCR_PAGE7 SYSCFG_RCR_PAGE7_Msk /*!< ICODE SRAM Write protection page 7 */
<> 147:30b64687e01f 12356 #define SYSCFG_RCR_PAGE8_Pos (8U)
<> 147:30b64687e01f 12357 #define SYSCFG_RCR_PAGE8_Msk (0x1U << SYSCFG_RCR_PAGE8_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12358 #define SYSCFG_RCR_PAGE8 SYSCFG_RCR_PAGE8_Msk /*!< ICODE SRAM Write protection page 8 */
<> 147:30b64687e01f 12359 #define SYSCFG_RCR_PAGE9_Pos (9U)
<> 147:30b64687e01f 12360 #define SYSCFG_RCR_PAGE9_Msk (0x1U << SYSCFG_RCR_PAGE9_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12361 #define SYSCFG_RCR_PAGE9 SYSCFG_RCR_PAGE9_Msk /*!< ICODE SRAM Write protection page 9 */
<> 147:30b64687e01f 12362 #define SYSCFG_RCR_PAGE10_Pos (10U)
<> 147:30b64687e01f 12363 #define SYSCFG_RCR_PAGE10_Msk (0x1U << SYSCFG_RCR_PAGE10_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12364 #define SYSCFG_RCR_PAGE10 SYSCFG_RCR_PAGE10_Msk /*!< ICODE SRAM Write protection page 10 */
<> 147:30b64687e01f 12365 #define SYSCFG_RCR_PAGE11_Pos (11U)
<> 147:30b64687e01f 12366 #define SYSCFG_RCR_PAGE11_Msk (0x1U << SYSCFG_RCR_PAGE11_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12367 #define SYSCFG_RCR_PAGE11 SYSCFG_RCR_PAGE11_Msk /*!< ICODE SRAM Write protection page 11 */
<> 147:30b64687e01f 12368 #define SYSCFG_RCR_PAGE12_Pos (12U)
<> 147:30b64687e01f 12369 #define SYSCFG_RCR_PAGE12_Msk (0x1U << SYSCFG_RCR_PAGE12_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12370 #define SYSCFG_RCR_PAGE12 SYSCFG_RCR_PAGE12_Msk /*!< ICODE SRAM Write protection page 12 */
<> 147:30b64687e01f 12371 #define SYSCFG_RCR_PAGE13_Pos (13U)
<> 147:30b64687e01f 12372 #define SYSCFG_RCR_PAGE13_Msk (0x1U << SYSCFG_RCR_PAGE13_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12373 #define SYSCFG_RCR_PAGE13 SYSCFG_RCR_PAGE13_Msk /*!< ICODE SRAM Write protection page 13 */
<> 147:30b64687e01f 12374 #define SYSCFG_RCR_PAGE14_Pos (14U)
<> 147:30b64687e01f 12375 #define SYSCFG_RCR_PAGE14_Msk (0x1U << SYSCFG_RCR_PAGE14_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 12376 #define SYSCFG_RCR_PAGE14 SYSCFG_RCR_PAGE14_Msk /*!< ICODE SRAM Write protection page 14 */
<> 147:30b64687e01f 12377 #define SYSCFG_RCR_PAGE15_Pos (15U)
<> 147:30b64687e01f 12378 #define SYSCFG_RCR_PAGE15_Msk (0x1U << SYSCFG_RCR_PAGE15_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 12379 #define SYSCFG_RCR_PAGE15 SYSCFG_RCR_PAGE15_Msk /*!< ICODE SRAM Write protection page 15 */
<> 147:30b64687e01f 12380
<> 147:30b64687e01f 12381 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 147:30b64687e01f 12382 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
<> 147:30b64687e01f 12383 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 12384 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
<> 147:30b64687e01f 12385 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
<> 147:30b64687e01f 12386 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 12387 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
<> 147:30b64687e01f 12388 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
<> 147:30b64687e01f 12389 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 12390 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
<> 147:30b64687e01f 12391 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
<> 147:30b64687e01f 12392 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 12393 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
<> 147:30b64687e01f 12394
<> 147:30b64687e01f 12395 /*!<*
<> 147:30b64687e01f 12396 * @brief EXTI0 configuration
<> 147:30b64687e01f 12397 */
<> 147:30b64687e01f 12398 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
<> 147:30b64687e01f 12399 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
<> 147:30b64687e01f 12400 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
<> 147:30b64687e01f 12401 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
<> 147:30b64687e01f 12402 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
<> 147:30b64687e01f 12403 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
<> 147:30b64687e01f 12404 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!< PG[0] pin */
<> 147:30b64687e01f 12405 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!< PH[0] pin */
<> 147:30b64687e01f 12406
<> 147:30b64687e01f 12407 /*!<*
<> 147:30b64687e01f 12408 * @brief EXTI1 configuration
<> 147:30b64687e01f 12409 */
<> 147:30b64687e01f 12410 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
<> 147:30b64687e01f 12411 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
<> 147:30b64687e01f 12412 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
<> 147:30b64687e01f 12413 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
<> 147:30b64687e01f 12414 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
<> 147:30b64687e01f 12415 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
<> 147:30b64687e01f 12416 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!< PG[1] pin */
<> 147:30b64687e01f 12417 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!< PH[1] pin */
<> 147:30b64687e01f 12418
<> 147:30b64687e01f 12419 /*!<*
<> 147:30b64687e01f 12420 * @brief EXTI2 configuration
<> 147:30b64687e01f 12421 */
<> 147:30b64687e01f 12422 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
<> 147:30b64687e01f 12423 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
<> 147:30b64687e01f 12424 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
<> 147:30b64687e01f 12425 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
<> 147:30b64687e01f 12426 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
<> 147:30b64687e01f 12427 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
<> 147:30b64687e01f 12428 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!< PG[2] pin */
<> 147:30b64687e01f 12429
<> 147:30b64687e01f 12430 /*!<*
<> 147:30b64687e01f 12431 * @brief EXTI3 configuration
<> 147:30b64687e01f 12432 */
<> 147:30b64687e01f 12433 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
<> 147:30b64687e01f 12434 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
<> 147:30b64687e01f 12435 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
<> 147:30b64687e01f 12436 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
<> 147:30b64687e01f 12437 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
<> 147:30b64687e01f 12438 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PE[3] pin */
<> 147:30b64687e01f 12439 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!< PG[3] pin */
<> 147:30b64687e01f 12440
<> 147:30b64687e01f 12441 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 147:30b64687e01f 12442 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
<> 147:30b64687e01f 12443 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 12444 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
<> 147:30b64687e01f 12445 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
<> 147:30b64687e01f 12446 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 12447 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
<> 147:30b64687e01f 12448 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
<> 147:30b64687e01f 12449 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 12450 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
<> 147:30b64687e01f 12451 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
<> 147:30b64687e01f 12452 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 12453 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
<> 147:30b64687e01f 12454
<> 147:30b64687e01f 12455 /*!<*
<> 147:30b64687e01f 12456 * @brief EXTI4 configuration
<> 147:30b64687e01f 12457 */
<> 147:30b64687e01f 12458 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
<> 147:30b64687e01f 12459 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
<> 147:30b64687e01f 12460 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
<> 147:30b64687e01f 12461 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
<> 147:30b64687e01f 12462 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
<> 147:30b64687e01f 12463 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
<> 147:30b64687e01f 12464 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!< PG[4] pin */
<> 147:30b64687e01f 12465 #define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!< PH[4] pin */
<> 147:30b64687e01f 12466
<> 147:30b64687e01f 12467 /*!<*
<> 147:30b64687e01f 12468 * @brief EXTI5 configuration
<> 147:30b64687e01f 12469 */
<> 147:30b64687e01f 12470 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
<> 147:30b64687e01f 12471 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
<> 147:30b64687e01f 12472 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
<> 147:30b64687e01f 12473 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
<> 147:30b64687e01f 12474 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
<> 147:30b64687e01f 12475 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
<> 147:30b64687e01f 12476 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!< PG[5] pin */
<> 147:30b64687e01f 12477
<> 147:30b64687e01f 12478 /*!<*
<> 147:30b64687e01f 12479 * @brief EXTI6 configuration
<> 147:30b64687e01f 12480 */
<> 147:30b64687e01f 12481 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
<> 147:30b64687e01f 12482 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
<> 147:30b64687e01f 12483 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
<> 147:30b64687e01f 12484 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
<> 147:30b64687e01f 12485 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
<> 147:30b64687e01f 12486 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
<> 147:30b64687e01f 12487 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!< PG[6] pin */
<> 147:30b64687e01f 12488
<> 147:30b64687e01f 12489 /*!<*
<> 147:30b64687e01f 12490 * @brief EXTI7 configuration
<> 147:30b64687e01f 12491 */
<> 147:30b64687e01f 12492 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
<> 147:30b64687e01f 12493 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
<> 147:30b64687e01f 12494 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
<> 147:30b64687e01f 12495 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
<> 147:30b64687e01f 12496 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
<> 147:30b64687e01f 12497 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
<> 147:30b64687e01f 12498 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!< PG[7] pin */
<> 147:30b64687e01f 12499
<> 147:30b64687e01f 12500 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 147:30b64687e01f 12501 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
<> 147:30b64687e01f 12502 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 12503 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
<> 147:30b64687e01f 12504 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
<> 147:30b64687e01f 12505 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 12506 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
<> 147:30b64687e01f 12507 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
<> 147:30b64687e01f 12508 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 12509 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
<> 147:30b64687e01f 12510 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
<> 147:30b64687e01f 12511 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 12512 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
<> 147:30b64687e01f 12513
<> 147:30b64687e01f 12514 /*!<*
<> 147:30b64687e01f 12515 * @brief EXTI8 configuration
<> 147:30b64687e01f 12516 */
<> 147:30b64687e01f 12517 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
<> 147:30b64687e01f 12518 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
<> 147:30b64687e01f 12519 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
<> 147:30b64687e01f 12520 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
<> 147:30b64687e01f 12521 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
<> 147:30b64687e01f 12522 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */
<> 147:30b64687e01f 12523 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!< PG[8] pin */
<> 147:30b64687e01f 12524
<> 147:30b64687e01f 12525 /*!<*
<> 147:30b64687e01f 12526 * @brief EXTI9 configuration
<> 147:30b64687e01f 12527 */
<> 147:30b64687e01f 12528 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
<> 147:30b64687e01f 12529 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
<> 147:30b64687e01f 12530 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
<> 147:30b64687e01f 12531 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
<> 147:30b64687e01f 12532 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
<> 147:30b64687e01f 12533 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
<> 147:30b64687e01f 12534 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!< PG[9] pin */
<> 147:30b64687e01f 12535
<> 147:30b64687e01f 12536 /*!<*
<> 147:30b64687e01f 12537 * @brief EXTI10 configuration
<> 147:30b64687e01f 12538 */
<> 147:30b64687e01f 12539 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
<> 147:30b64687e01f 12540 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
<> 147:30b64687e01f 12541 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
<> 147:30b64687e01f 12542 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
<> 147:30b64687e01f 12543 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
<> 147:30b64687e01f 12544 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
<> 147:30b64687e01f 12545 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!< PG[10] pin */
<> 147:30b64687e01f 12546
<> 147:30b64687e01f 12547 /*!<*
<> 147:30b64687e01f 12548 * @brief EXTI11 configuration
<> 147:30b64687e01f 12549 */
<> 147:30b64687e01f 12550 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
<> 147:30b64687e01f 12551 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
<> 147:30b64687e01f 12552 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
<> 147:30b64687e01f 12553 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
<> 147:30b64687e01f 12554 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
<> 147:30b64687e01f 12555 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */
<> 147:30b64687e01f 12556 #define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!< PG[11] pin */
<> 147:30b64687e01f 12557
<> 147:30b64687e01f 12558 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
<> 147:30b64687e01f 12559 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
<> 147:30b64687e01f 12560 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 12561 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
<> 147:30b64687e01f 12562 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
<> 147:30b64687e01f 12563 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 12564 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
<> 147:30b64687e01f 12565 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
<> 147:30b64687e01f 12566 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 12567 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
<> 147:30b64687e01f 12568 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
<> 147:30b64687e01f 12569 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 12570 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
<> 147:30b64687e01f 12571
<> 147:30b64687e01f 12572 /*!<*
<> 147:30b64687e01f 12573 * @brief EXTI12 configuration
<> 147:30b64687e01f 12574 */
<> 147:30b64687e01f 12575 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
<> 147:30b64687e01f 12576 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
<> 147:30b64687e01f 12577 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
<> 147:30b64687e01f 12578 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
<> 147:30b64687e01f 12579 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
<> 147:30b64687e01f 12580 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */
<> 147:30b64687e01f 12581 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!< PG[12] pin */
<> 147:30b64687e01f 12582
<> 147:30b64687e01f 12583 /*!<*
<> 147:30b64687e01f 12584 * @brief EXTI13 configuration
<> 147:30b64687e01f 12585 */
<> 147:30b64687e01f 12586 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
<> 147:30b64687e01f 12587 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
<> 147:30b64687e01f 12588 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
<> 147:30b64687e01f 12589 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
<> 147:30b64687e01f 12590 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
<> 147:30b64687e01f 12591 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */
<> 147:30b64687e01f 12592 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!< PG[13] pin */
<> 147:30b64687e01f 12593
<> 147:30b64687e01f 12594 /*!<*
<> 147:30b64687e01f 12595 * @brief EXTI14 configuration
<> 147:30b64687e01f 12596 */
<> 147:30b64687e01f 12597 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
<> 147:30b64687e01f 12598 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
<> 147:30b64687e01f 12599 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
<> 147:30b64687e01f 12600 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
<> 147:30b64687e01f 12601 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
<> 147:30b64687e01f 12602 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */
<> 147:30b64687e01f 12603 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!< PG[14] pin */
<> 147:30b64687e01f 12604
<> 147:30b64687e01f 12605 /*!<*
<> 147:30b64687e01f 12606 * @brief EXTI15 configuration
<> 147:30b64687e01f 12607 */
<> 147:30b64687e01f 12608 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
<> 147:30b64687e01f 12609 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
<> 147:30b64687e01f 12610 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
<> 147:30b64687e01f 12611 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
<> 147:30b64687e01f 12612 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
<> 147:30b64687e01f 12613 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */
<> 147:30b64687e01f 12614 #define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!< PG[15] pin */
<> 147:30b64687e01f 12615
<> 147:30b64687e01f 12616 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
<> 147:30b64687e01f 12617 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
<> 147:30b64687e01f 12618 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12619 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
<> 147:30b64687e01f 12620 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
<> 147:30b64687e01f 12621 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12622 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
<> 147:30b64687e01f 12623 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
<> 147:30b64687e01f 12624 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12625 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
<> 147:30b64687e01f 12626 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)
<> 147:30b64687e01f 12627 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1U << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12628 #define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the adddress parity check on RAM */
<> 147:30b64687e01f 12629 #define SYSCFG_CFGR2_SRAM_PE_Pos (8U)
<> 147:30b64687e01f 12630 #define SYSCFG_CFGR2_SRAM_PE_Msk (0x1U << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12631 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk /*!< SRAM Parity error flag */
<> 147:30b64687e01f 12632 /***************** Bit definition for SYSCFG_CFGR4 register *****************/
<> 147:30b64687e01f 12633 #define SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos (0U)
<> 147:30b64687e01f 12634 #define SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12635 #define SYSCFG_CFGR4_ADC12_EXT2_RMP SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk /*!< ADC12 regular channel EXT2 remap */
<> 147:30b64687e01f 12636 #define SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos (1U)
<> 147:30b64687e01f 12637 #define SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12638 #define SYSCFG_CFGR4_ADC12_EXT3_RMP SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk /*!< ADC12 regular channel EXT3 remap */
<> 147:30b64687e01f 12639 #define SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos (2U)
<> 147:30b64687e01f 12640 #define SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12641 #define SYSCFG_CFGR4_ADC12_EXT5_RMP SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk /*!< ADC12 regular channel EXT5 remap */
<> 147:30b64687e01f 12642 #define SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos (3U)
<> 147:30b64687e01f 12643 #define SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12644 #define SYSCFG_CFGR4_ADC12_EXT13_RMP SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk /*!< ADC12 regular channel EXT13 remap */
<> 147:30b64687e01f 12645 #define SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos (4U)
<> 147:30b64687e01f 12646 #define SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12647 #define SYSCFG_CFGR4_ADC12_EXT15_RMP SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk /*!< ADC12 regular channel EXT15 remap */
<> 147:30b64687e01f 12648 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos (5U)
<> 147:30b64687e01f 12649 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12650 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk /*!< ADC12 injected channel JEXT3 remap */
<> 147:30b64687e01f 12651 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos (6U)
<> 147:30b64687e01f 12652 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12653 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk /*!< ADC12 injected channel JEXT6 remap */
<> 147:30b64687e01f 12654 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos (7U)
<> 147:30b64687e01f 12655 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12656 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk /*!< ADC12 injected channel JEXT13 remap */
<> 147:30b64687e01f 12657 #define SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos (8U)
<> 147:30b64687e01f 12658 #define SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12659 #define SYSCFG_CFGR4_ADC34_EXT5_RMP SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk /*!< ADC34 regular channel EXT5 remap */
<> 147:30b64687e01f 12660 #define SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos (9U)
<> 147:30b64687e01f 12661 #define SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12662 #define SYSCFG_CFGR4_ADC34_EXT6_RMP SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk /*!< ADC34 regular channel EXT6 remap */
<> 147:30b64687e01f 12663 #define SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos (10U)
<> 147:30b64687e01f 12664 #define SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12665 #define SYSCFG_CFGR4_ADC34_EXT15_RMP SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk /*!< ADC34 regular channel EXT15 remap */
<> 147:30b64687e01f 12666 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos (11U)
<> 147:30b64687e01f 12667 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12668 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk /*!< ADC34 injected channel JEXT5 remap */
<> 147:30b64687e01f 12669 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos (12U)
<> 147:30b64687e01f 12670 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12671 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk /*!< ADC34 injected channel JEXT11 remap */
<> 147:30b64687e01f 12672 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos (13U)
<> 147:30b64687e01f 12673 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12674 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk /*!< ADC34 injected channel JEXT14 remap */
<> 147:30b64687e01f 12675
<> 147:30b64687e01f 12676 /******************************************************************************/
<> 147:30b64687e01f 12677 /* */
<> 147:30b64687e01f 12678 /* TIM */
<> 147:30b64687e01f 12679 /* */
<> 147:30b64687e01f 12680 /******************************************************************************/
<> 147:30b64687e01f 12681 /******************* Bit definition for TIM_CR1 register ********************/
<> 147:30b64687e01f 12682 #define TIM_CR1_CEN_Pos (0U)
<> 147:30b64687e01f 12683 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12684 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
<> 147:30b64687e01f 12685 #define TIM_CR1_UDIS_Pos (1U)
<> 147:30b64687e01f 12686 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12687 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
<> 147:30b64687e01f 12688 #define TIM_CR1_URS_Pos (2U)
<> 147:30b64687e01f 12689 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12690 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
<> 147:30b64687e01f 12691 #define TIM_CR1_OPM_Pos (3U)
<> 147:30b64687e01f 12692 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12693 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
<> 147:30b64687e01f 12694 #define TIM_CR1_DIR_Pos (4U)
<> 147:30b64687e01f 12695 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12696 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
<> 147:30b64687e01f 12697
<> 147:30b64687e01f 12698 #define TIM_CR1_CMS_Pos (5U)
<> 147:30b64687e01f 12699 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
<> 147:30b64687e01f 12700 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 147:30b64687e01f 12701 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12702 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12703
<> 147:30b64687e01f 12704 #define TIM_CR1_ARPE_Pos (7U)
<> 147:30b64687e01f 12705 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12706 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
<> 147:30b64687e01f 12707
<> 147:30b64687e01f 12708 #define TIM_CR1_CKD_Pos (8U)
<> 147:30b64687e01f 12709 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 12710 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
<> 147:30b64687e01f 12711 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12712 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12713
<> 147:30b64687e01f 12714 #define TIM_CR1_UIFREMAP_Pos (11U)
<> 147:30b64687e01f 12715 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12716 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
<> 147:30b64687e01f 12717
<> 147:30b64687e01f 12718 /******************* Bit definition for TIM_CR2 register ********************/
<> 147:30b64687e01f 12719 #define TIM_CR2_CCPC_Pos (0U)
<> 147:30b64687e01f 12720 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12721 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
<> 147:30b64687e01f 12722 #define TIM_CR2_CCUS_Pos (2U)
<> 147:30b64687e01f 12723 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12724 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
<> 147:30b64687e01f 12725 #define TIM_CR2_CCDS_Pos (3U)
<> 147:30b64687e01f 12726 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12727 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
<> 147:30b64687e01f 12728
<> 147:30b64687e01f 12729 #define TIM_CR2_MMS_Pos (4U)
<> 147:30b64687e01f 12730 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 12731 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 147:30b64687e01f 12732 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12733 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12734 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12735
<> 147:30b64687e01f 12736 #define TIM_CR2_TI1S_Pos (7U)
<> 147:30b64687e01f 12737 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12738 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
<> 147:30b64687e01f 12739 #define TIM_CR2_OIS1_Pos (8U)
<> 147:30b64687e01f 12740 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12741 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
<> 147:30b64687e01f 12742 #define TIM_CR2_OIS1N_Pos (9U)
<> 147:30b64687e01f 12743 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12744 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
<> 147:30b64687e01f 12745 #define TIM_CR2_OIS2_Pos (10U)
<> 147:30b64687e01f 12746 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12747 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
<> 147:30b64687e01f 12748 #define TIM_CR2_OIS2N_Pos (11U)
<> 147:30b64687e01f 12749 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12750 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
<> 147:30b64687e01f 12751 #define TIM_CR2_OIS3_Pos (12U)
<> 147:30b64687e01f 12752 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12753 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
<> 147:30b64687e01f 12754 #define TIM_CR2_OIS3N_Pos (13U)
<> 147:30b64687e01f 12755 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12756 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
<> 147:30b64687e01f 12757 #define TIM_CR2_OIS4_Pos (14U)
<> 147:30b64687e01f 12758 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 12759 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
<> 147:30b64687e01f 12760 #define TIM_CR2_OIS5_Pos (16U)
<> 147:30b64687e01f 12761 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 12762 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
<> 147:30b64687e01f 12763 #define TIM_CR2_OIS6_Pos (18U)
<> 147:30b64687e01f 12764 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 12765 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
<> 147:30b64687e01f 12766
<> 147:30b64687e01f 12767 #define TIM_CR2_MMS2_Pos (20U)
<> 147:30b64687e01f 12768 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 12769 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 147:30b64687e01f 12770 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 12771 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 12772 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 12773 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 12774
<> 147:30b64687e01f 12775 /******************* Bit definition for TIM_SMCR register *******************/
<> 147:30b64687e01f 12776 #define TIM_SMCR_SMS_Pos (0U)
<> 147:30b64687e01f 12777 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
<> 147:30b64687e01f 12778 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
<> 147:30b64687e01f 12779 #define TIM_SMCR_SMS_0 (0x00000001U) /*!<Bit 0 */
<> 147:30b64687e01f 12780 #define TIM_SMCR_SMS_1 (0x00000002U) /*!<Bit 1 */
<> 147:30b64687e01f 12781 #define TIM_SMCR_SMS_2 (0x00000004U) /*!<Bit 2 */
<> 147:30b64687e01f 12782 #define TIM_SMCR_SMS_3 (0x00010000U) /*!<Bit 3 */
<> 147:30b64687e01f 12783
<> 147:30b64687e01f 12784 #define TIM_SMCR_OCCS_Pos (3U)
<> 147:30b64687e01f 12785 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12786 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
<> 147:30b64687e01f 12787
<> 147:30b64687e01f 12788 #define TIM_SMCR_TS_Pos (4U)
<> 147:30b64687e01f 12789 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
<> 147:30b64687e01f 12790 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
<> 147:30b64687e01f 12791 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12792 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12793 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12794
<> 147:30b64687e01f 12795 #define TIM_SMCR_MSM_Pos (7U)
<> 147:30b64687e01f 12796 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12797 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
<> 147:30b64687e01f 12798
<> 147:30b64687e01f 12799 #define TIM_SMCR_ETF_Pos (8U)
<> 147:30b64687e01f 12800 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
<> 147:30b64687e01f 12801 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
<> 147:30b64687e01f 12802 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12803 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12804 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12805 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12806
<> 147:30b64687e01f 12807 #define TIM_SMCR_ETPS_Pos (12U)
<> 147:30b64687e01f 12808 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 12809 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 147:30b64687e01f 12810 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12811 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12812
<> 147:30b64687e01f 12813 #define TIM_SMCR_ECE_Pos (14U)
<> 147:30b64687e01f 12814 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 12815 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
<> 147:30b64687e01f 12816 #define TIM_SMCR_ETP_Pos (15U)
<> 147:30b64687e01f 12817 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 12818 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 147:30b64687e01f 12819
<> 147:30b64687e01f 12820 /******************* Bit definition for TIM_DIER register *******************/
<> 147:30b64687e01f 12821 #define TIM_DIER_UIE_Pos (0U)
<> 147:30b64687e01f 12822 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12823 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
<> 147:30b64687e01f 12824 #define TIM_DIER_CC1IE_Pos (1U)
<> 147:30b64687e01f 12825 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12826 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
<> 147:30b64687e01f 12827 #define TIM_DIER_CC2IE_Pos (2U)
<> 147:30b64687e01f 12828 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12829 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
<> 147:30b64687e01f 12830 #define TIM_DIER_CC3IE_Pos (3U)
<> 147:30b64687e01f 12831 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12832 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
<> 147:30b64687e01f 12833 #define TIM_DIER_CC4IE_Pos (4U)
<> 147:30b64687e01f 12834 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12835 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
<> 147:30b64687e01f 12836 #define TIM_DIER_COMIE_Pos (5U)
<> 147:30b64687e01f 12837 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12838 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
<> 147:30b64687e01f 12839 #define TIM_DIER_TIE_Pos (6U)
<> 147:30b64687e01f 12840 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12841 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
<> 147:30b64687e01f 12842 #define TIM_DIER_BIE_Pos (7U)
<> 147:30b64687e01f 12843 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12844 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
<> 147:30b64687e01f 12845 #define TIM_DIER_UDE_Pos (8U)
<> 147:30b64687e01f 12846 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12847 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
<> 147:30b64687e01f 12848 #define TIM_DIER_CC1DE_Pos (9U)
<> 147:30b64687e01f 12849 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12850 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
<> 147:30b64687e01f 12851 #define TIM_DIER_CC2DE_Pos (10U)
<> 147:30b64687e01f 12852 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12853 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
<> 147:30b64687e01f 12854 #define TIM_DIER_CC3DE_Pos (11U)
<> 147:30b64687e01f 12855 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12856 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
<> 147:30b64687e01f 12857 #define TIM_DIER_CC4DE_Pos (12U)
<> 147:30b64687e01f 12858 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12859 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
<> 147:30b64687e01f 12860 #define TIM_DIER_COMDE_Pos (13U)
<> 147:30b64687e01f 12861 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 12862 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
<> 147:30b64687e01f 12863 #define TIM_DIER_TDE_Pos (14U)
<> 147:30b64687e01f 12864 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 12865 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 147:30b64687e01f 12866
<> 147:30b64687e01f 12867 /******************** Bit definition for TIM_SR register ********************/
<> 147:30b64687e01f 12868 #define TIM_SR_UIF_Pos (0U)
<> 147:30b64687e01f 12869 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12870 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
<> 147:30b64687e01f 12871 #define TIM_SR_CC1IF_Pos (1U)
<> 147:30b64687e01f 12872 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12873 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
<> 147:30b64687e01f 12874 #define TIM_SR_CC2IF_Pos (2U)
<> 147:30b64687e01f 12875 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12876 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
<> 147:30b64687e01f 12877 #define TIM_SR_CC3IF_Pos (3U)
<> 147:30b64687e01f 12878 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12879 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
<> 147:30b64687e01f 12880 #define TIM_SR_CC4IF_Pos (4U)
<> 147:30b64687e01f 12881 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12882 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
<> 147:30b64687e01f 12883 #define TIM_SR_COMIF_Pos (5U)
<> 147:30b64687e01f 12884 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12885 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
<> 147:30b64687e01f 12886 #define TIM_SR_TIF_Pos (6U)
<> 147:30b64687e01f 12887 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12888 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
<> 147:30b64687e01f 12889 #define TIM_SR_BIF_Pos (7U)
<> 147:30b64687e01f 12890 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12891 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
<> 147:30b64687e01f 12892 #define TIM_SR_B2IF_Pos (8U)
<> 147:30b64687e01f 12893 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12894 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
<> 147:30b64687e01f 12895 #define TIM_SR_CC1OF_Pos (9U)
<> 147:30b64687e01f 12896 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12897 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
<> 147:30b64687e01f 12898 #define TIM_SR_CC2OF_Pos (10U)
<> 147:30b64687e01f 12899 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12900 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
<> 147:30b64687e01f 12901 #define TIM_SR_CC3OF_Pos (11U)
<> 147:30b64687e01f 12902 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12903 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
<> 147:30b64687e01f 12904 #define TIM_SR_CC4OF_Pos (12U)
<> 147:30b64687e01f 12905 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 12906 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 147:30b64687e01f 12907 #define TIM_SR_CC5IF_Pos (16U)
<> 147:30b64687e01f 12908 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 12909 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
<> 147:30b64687e01f 12910 #define TIM_SR_CC6IF_Pos (17U)
<> 147:30b64687e01f 12911 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 12912 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
<> 147:30b64687e01f 12913
<> 147:30b64687e01f 12914 /******************* Bit definition for TIM_EGR register ********************/
<> 147:30b64687e01f 12915 #define TIM_EGR_UG_Pos (0U)
<> 147:30b64687e01f 12916 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12917 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
<> 147:30b64687e01f 12918 #define TIM_EGR_CC1G_Pos (1U)
<> 147:30b64687e01f 12919 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12920 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
<> 147:30b64687e01f 12921 #define TIM_EGR_CC2G_Pos (2U)
<> 147:30b64687e01f 12922 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12923 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
<> 147:30b64687e01f 12924 #define TIM_EGR_CC3G_Pos (3U)
<> 147:30b64687e01f 12925 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12926 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
<> 147:30b64687e01f 12927 #define TIM_EGR_CC4G_Pos (4U)
<> 147:30b64687e01f 12928 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 12929 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
<> 147:30b64687e01f 12930 #define TIM_EGR_COMG_Pos (5U)
<> 147:30b64687e01f 12931 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 12932 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
<> 147:30b64687e01f 12933 #define TIM_EGR_TG_Pos (6U)
<> 147:30b64687e01f 12934 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 12935 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
<> 147:30b64687e01f 12936 #define TIM_EGR_BG_Pos (7U)
<> 147:30b64687e01f 12937 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12938 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
<> 147:30b64687e01f 12939 #define TIM_EGR_B2G_Pos (8U)
<> 147:30b64687e01f 12940 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12941 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
<> 147:30b64687e01f 12942
<> 147:30b64687e01f 12943 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 147:30b64687e01f 12944 #define TIM_CCMR1_CC1S_Pos (0U)
<> 147:30b64687e01f 12945 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 12946 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 147:30b64687e01f 12947 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 12948 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 12949
<> 147:30b64687e01f 12950 #define TIM_CCMR1_OC1FE_Pos (2U)
<> 147:30b64687e01f 12951 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 12952 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
<> 147:30b64687e01f 12953 #define TIM_CCMR1_OC1PE_Pos (3U)
<> 147:30b64687e01f 12954 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 12955 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
<> 147:30b64687e01f 12956
<> 147:30b64687e01f 12957 #define TIM_CCMR1_OC1M_Pos (4U)
<> 147:30b64687e01f 12958 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
<> 147:30b64687e01f 12959 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 147:30b64687e01f 12960 #define TIM_CCMR1_OC1M_0 (0x00000010U) /*!<Bit 0 */
<> 147:30b64687e01f 12961 #define TIM_CCMR1_OC1M_1 (0x00000020U) /*!<Bit 1 */
<> 147:30b64687e01f 12962 #define TIM_CCMR1_OC1M_2 (0x00000040U) /*!<Bit 2 */
<> 147:30b64687e01f 12963 #define TIM_CCMR1_OC1M_3 (0x00010000U) /*!<Bit 3 */
<> 147:30b64687e01f 12964
<> 147:30b64687e01f 12965 #define TIM_CCMR1_OC1CE_Pos (7U)
<> 147:30b64687e01f 12966 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 12967 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
<> 147:30b64687e01f 12968
<> 147:30b64687e01f 12969 #define TIM_CCMR1_CC2S_Pos (8U)
<> 147:30b64687e01f 12970 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 12971 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 147:30b64687e01f 12972 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 12973 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 12974
<> 147:30b64687e01f 12975 #define TIM_CCMR1_OC2FE_Pos (10U)
<> 147:30b64687e01f 12976 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 12977 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
<> 147:30b64687e01f 12978 #define TIM_CCMR1_OC2PE_Pos (11U)
<> 147:30b64687e01f 12979 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 12980 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
<> 147:30b64687e01f 12981
<> 147:30b64687e01f 12982 #define TIM_CCMR1_OC2M_Pos (12U)
<> 147:30b64687e01f 12983 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
<> 147:30b64687e01f 12984 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 147:30b64687e01f 12985 #define TIM_CCMR1_OC2M_0 (0x00001000U) /*!<Bit 0 */
<> 147:30b64687e01f 12986 #define TIM_CCMR1_OC2M_1 (0x00002000U) /*!<Bit 1 */
<> 147:30b64687e01f 12987 #define TIM_CCMR1_OC2M_2 (0x00004000U) /*!<Bit 2 */
<> 147:30b64687e01f 12988 #define TIM_CCMR1_OC2M_3 (0x01000000U) /*!<Bit 3 */
<> 147:30b64687e01f 12989
<> 147:30b64687e01f 12990 #define TIM_CCMR1_OC2CE_Pos (15U)
<> 147:30b64687e01f 12991 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 12992 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 147:30b64687e01f 12993
<> 147:30b64687e01f 12994 /*----------------------------------------------------------------------------*/
<> 147:30b64687e01f 12995
<> 147:30b64687e01f 12996 #define TIM_CCMR1_IC1PSC_Pos (2U)
<> 147:30b64687e01f 12997 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 12998 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 147:30b64687e01f 12999 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13000 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13001
<> 147:30b64687e01f 13002 #define TIM_CCMR1_IC1F_Pos (4U)
<> 147:30b64687e01f 13003 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 13004 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 147:30b64687e01f 13005 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13006 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13007 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13008 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13009
<> 147:30b64687e01f 13010 #define TIM_CCMR1_IC2PSC_Pos (10U)
<> 147:30b64687e01f 13011 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
<> 147:30b64687e01f 13012 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 147:30b64687e01f 13013 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13014 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13015
<> 147:30b64687e01f 13016 #define TIM_CCMR1_IC2F_Pos (12U)
<> 147:30b64687e01f 13017 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 13018 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 147:30b64687e01f 13019 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13020 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13021 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13022 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13023
<> 147:30b64687e01f 13024 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 147:30b64687e01f 13025 #define TIM_CCMR2_CC3S_Pos (0U)
<> 147:30b64687e01f 13026 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 13027 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 147:30b64687e01f 13028 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13029 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13030
<> 147:30b64687e01f 13031 #define TIM_CCMR2_OC3FE_Pos (2U)
<> 147:30b64687e01f 13032 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13033 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
<> 147:30b64687e01f 13034 #define TIM_CCMR2_OC3PE_Pos (3U)
<> 147:30b64687e01f 13035 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13036 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
<> 147:30b64687e01f 13037
<> 147:30b64687e01f 13038 #define TIM_CCMR2_OC3M_Pos (4U)
<> 147:30b64687e01f 13039 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
<> 147:30b64687e01f 13040 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 147:30b64687e01f 13041 #define TIM_CCMR2_OC3M_0 (0x00000010U) /*!<Bit 0 */
<> 147:30b64687e01f 13042 #define TIM_CCMR2_OC3M_1 (0x00000020U) /*!<Bit 1 */
<> 147:30b64687e01f 13043 #define TIM_CCMR2_OC3M_2 (0x00000040U) /*!<Bit 2 */
<> 147:30b64687e01f 13044 #define TIM_CCMR2_OC3M_3 (0x00010000U) /*!<Bit 3 */
<> 147:30b64687e01f 13045
<> 147:30b64687e01f 13046 #define TIM_CCMR2_OC3CE_Pos (7U)
<> 147:30b64687e01f 13047 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13048 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
<> 147:30b64687e01f 13049
<> 147:30b64687e01f 13050 #define TIM_CCMR2_CC4S_Pos (8U)
<> 147:30b64687e01f 13051 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 13052 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 147:30b64687e01f 13053 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13054 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13055
<> 147:30b64687e01f 13056 #define TIM_CCMR2_OC4FE_Pos (10U)
<> 147:30b64687e01f 13057 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13058 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
<> 147:30b64687e01f 13059 #define TIM_CCMR2_OC4PE_Pos (11U)
<> 147:30b64687e01f 13060 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13061 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
<> 147:30b64687e01f 13062
<> 147:30b64687e01f 13063 #define TIM_CCMR2_OC4M_Pos (12U)
<> 147:30b64687e01f 13064 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
<> 147:30b64687e01f 13065 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 147:30b64687e01f 13066 #define TIM_CCMR2_OC4M_0 (0x00001000U) /*!<Bit 0 */
<> 147:30b64687e01f 13067 #define TIM_CCMR2_OC4M_1 (0x00002000U) /*!<Bit 1 */
<> 147:30b64687e01f 13068 #define TIM_CCMR2_OC4M_2 (0x00004000U) /*!<Bit 2 */
<> 147:30b64687e01f 13069 #define TIM_CCMR2_OC4M_3 (0x01000000U) /*!<Bit 3 */
<> 147:30b64687e01f 13070
<> 147:30b64687e01f 13071 #define TIM_CCMR2_OC4CE_Pos (15U)
<> 147:30b64687e01f 13072 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13073 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 147:30b64687e01f 13074
<> 147:30b64687e01f 13075 /*----------------------------------------------------------------------------*/
<> 147:30b64687e01f 13076
<> 147:30b64687e01f 13077 #define TIM_CCMR2_IC3PSC_Pos (2U)
<> 147:30b64687e01f 13078 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
<> 147:30b64687e01f 13079 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 147:30b64687e01f 13080 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13081 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13082
<> 147:30b64687e01f 13083 #define TIM_CCMR2_IC3F_Pos (4U)
<> 147:30b64687e01f 13084 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
<> 147:30b64687e01f 13085 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 147:30b64687e01f 13086 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13087 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13088 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13089 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13090
<> 147:30b64687e01f 13091 #define TIM_CCMR2_IC4PSC_Pos (10U)
<> 147:30b64687e01f 13092 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
<> 147:30b64687e01f 13093 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 147:30b64687e01f 13094 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13095 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13096
<> 147:30b64687e01f 13097 #define TIM_CCMR2_IC4F_Pos (12U)
<> 147:30b64687e01f 13098 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
<> 147:30b64687e01f 13099 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 147:30b64687e01f 13100 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13101 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13102 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13103 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13104
<> 147:30b64687e01f 13105 /******************* Bit definition for TIM_CCER register *******************/
<> 147:30b64687e01f 13106 #define TIM_CCER_CC1E_Pos (0U)
<> 147:30b64687e01f 13107 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13108 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
<> 147:30b64687e01f 13109 #define TIM_CCER_CC1P_Pos (1U)
<> 147:30b64687e01f 13110 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13111 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
<> 147:30b64687e01f 13112 #define TIM_CCER_CC1NE_Pos (2U)
<> 147:30b64687e01f 13113 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13114 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
<> 147:30b64687e01f 13115 #define TIM_CCER_CC1NP_Pos (3U)
<> 147:30b64687e01f 13116 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13117 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
<> 147:30b64687e01f 13118 #define TIM_CCER_CC2E_Pos (4U)
<> 147:30b64687e01f 13119 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13120 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
<> 147:30b64687e01f 13121 #define TIM_CCER_CC2P_Pos (5U)
<> 147:30b64687e01f 13122 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13123 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
<> 147:30b64687e01f 13124 #define TIM_CCER_CC2NE_Pos (6U)
<> 147:30b64687e01f 13125 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13126 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
<> 147:30b64687e01f 13127 #define TIM_CCER_CC2NP_Pos (7U)
<> 147:30b64687e01f 13128 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13129 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
<> 147:30b64687e01f 13130 #define TIM_CCER_CC3E_Pos (8U)
<> 147:30b64687e01f 13131 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13132 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
<> 147:30b64687e01f 13133 #define TIM_CCER_CC3P_Pos (9U)
<> 147:30b64687e01f 13134 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13135 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
<> 147:30b64687e01f 13136 #define TIM_CCER_CC3NE_Pos (10U)
<> 147:30b64687e01f 13137 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13138 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
<> 147:30b64687e01f 13139 #define TIM_CCER_CC3NP_Pos (11U)
<> 147:30b64687e01f 13140 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13141 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
<> 147:30b64687e01f 13142 #define TIM_CCER_CC4E_Pos (12U)
<> 147:30b64687e01f 13143 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13144 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
<> 147:30b64687e01f 13145 #define TIM_CCER_CC4P_Pos (13U)
<> 147:30b64687e01f 13146 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13147 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
<> 147:30b64687e01f 13148 #define TIM_CCER_CC4NP_Pos (15U)
<> 147:30b64687e01f 13149 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13150 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 147:30b64687e01f 13151 #define TIM_CCER_CC5E_Pos (16U)
<> 147:30b64687e01f 13152 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13153 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
<> 147:30b64687e01f 13154 #define TIM_CCER_CC5P_Pos (17U)
<> 147:30b64687e01f 13155 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13156 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
<> 147:30b64687e01f 13157 #define TIM_CCER_CC6E_Pos (20U)
<> 147:30b64687e01f 13158 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13159 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
<> 147:30b64687e01f 13160 #define TIM_CCER_CC6P_Pos (21U)
<> 147:30b64687e01f 13161 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13162 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
<> 147:30b64687e01f 13163
<> 147:30b64687e01f 13164 /******************* Bit definition for TIM_CNT register ********************/
<> 147:30b64687e01f 13165 #define TIM_CNT_CNT_Pos (0U)
<> 147:30b64687e01f 13166 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 13167 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 147:30b64687e01f 13168 #define TIM_CNT_UIFCPY_Pos (31U)
<> 147:30b64687e01f 13169 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 13170 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
<> 147:30b64687e01f 13171
<> 147:30b64687e01f 13172 /******************* Bit definition for TIM_PSC register ********************/
<> 147:30b64687e01f 13173 #define TIM_PSC_PSC_Pos (0U)
<> 147:30b64687e01f 13174 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13175 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 147:30b64687e01f 13176
<> 147:30b64687e01f 13177 /******************* Bit definition for TIM_ARR register ********************/
<> 147:30b64687e01f 13178 #define TIM_ARR_ARR_Pos (0U)
<> 147:30b64687e01f 13179 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 13180 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
<> 147:30b64687e01f 13181
<> 147:30b64687e01f 13182 /******************* Bit definition for TIM_RCR register ********************/
<> 147:30b64687e01f 13183 #define TIM_RCR_REP_Pos (0U)
<> 147:30b64687e01f 13184 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13185 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
<> 147:30b64687e01f 13186
<> 147:30b64687e01f 13187 /******************* Bit definition for TIM_CCR1 register *******************/
<> 147:30b64687e01f 13188 #define TIM_CCR1_CCR1_Pos (0U)
<> 147:30b64687e01f 13189 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13190 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 147:30b64687e01f 13191
<> 147:30b64687e01f 13192 /******************* Bit definition for TIM_CCR2 register *******************/
<> 147:30b64687e01f 13193 #define TIM_CCR2_CCR2_Pos (0U)
<> 147:30b64687e01f 13194 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13195 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 147:30b64687e01f 13196
<> 147:30b64687e01f 13197 /******************* Bit definition for TIM_CCR3 register *******************/
<> 147:30b64687e01f 13198 #define TIM_CCR3_CCR3_Pos (0U)
<> 147:30b64687e01f 13199 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13200 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 147:30b64687e01f 13201
<> 147:30b64687e01f 13202 /******************* Bit definition for TIM_CCR4 register *******************/
<> 147:30b64687e01f 13203 #define TIM_CCR4_CCR4_Pos (0U)
<> 147:30b64687e01f 13204 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13205 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 147:30b64687e01f 13206
<> 147:30b64687e01f 13207 /******************* Bit definition for TIM_CCR5 register *******************/
<> 147:30b64687e01f 13208 #define TIM_CCR5_CCR5_Pos (0U)
<> 147:30b64687e01f 13209 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
<> 147:30b64687e01f 13210 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
<> 147:30b64687e01f 13211 #define TIM_CCR5_GC5C1_Pos (29U)
<> 147:30b64687e01f 13212 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 13213 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
<> 147:30b64687e01f 13214 #define TIM_CCR5_GC5C2_Pos (30U)
<> 147:30b64687e01f 13215 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 13216 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
<> 147:30b64687e01f 13217 #define TIM_CCR5_GC5C3_Pos (31U)
<> 147:30b64687e01f 13218 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 13219 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
<> 147:30b64687e01f 13220
<> 147:30b64687e01f 13221 /******************* Bit definition for TIM_CCR6 register *******************/
<> 147:30b64687e01f 13222 #define TIM_CCR6_CCR6_Pos (0U)
<> 147:30b64687e01f 13223 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13224 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
<> 147:30b64687e01f 13225
<> 147:30b64687e01f 13226 /******************* Bit definition for TIM_BDTR register *******************/
<> 147:30b64687e01f 13227 #define TIM_BDTR_DTG_Pos (0U)
<> 147:30b64687e01f 13228 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 13229 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 147:30b64687e01f 13230 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13231 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13232 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13233 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13234 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13235 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13236 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13237 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13238
<> 147:30b64687e01f 13239 #define TIM_BDTR_LOCK_Pos (8U)
<> 147:30b64687e01f 13240 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
<> 147:30b64687e01f 13241 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
<> 147:30b64687e01f 13242 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13243 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13244
<> 147:30b64687e01f 13245 #define TIM_BDTR_OSSI_Pos (10U)
<> 147:30b64687e01f 13246 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13247 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
<> 147:30b64687e01f 13248 #define TIM_BDTR_OSSR_Pos (11U)
<> 147:30b64687e01f 13249 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13250 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
<> 147:30b64687e01f 13251 #define TIM_BDTR_BKE_Pos (12U)
<> 147:30b64687e01f 13252 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13253 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
<> 147:30b64687e01f 13254 #define TIM_BDTR_BKP_Pos (13U)
<> 147:30b64687e01f 13255 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13256 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
<> 147:30b64687e01f 13257 #define TIM_BDTR_AOE_Pos (14U)
<> 147:30b64687e01f 13258 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13259 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
<> 147:30b64687e01f 13260 #define TIM_BDTR_MOE_Pos (15U)
<> 147:30b64687e01f 13261 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13262 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
<> 147:30b64687e01f 13263
<> 147:30b64687e01f 13264 #define TIM_BDTR_BKF_Pos (16U)
<> 147:30b64687e01f 13265 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
<> 147:30b64687e01f 13266 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
<> 147:30b64687e01f 13267 #define TIM_BDTR_BK2F_Pos (20U)
<> 147:30b64687e01f 13268 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
<> 147:30b64687e01f 13269 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
<> 147:30b64687e01f 13270
<> 147:30b64687e01f 13271 #define TIM_BDTR_BK2E_Pos (24U)
<> 147:30b64687e01f 13272 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13273 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
<> 147:30b64687e01f 13274 #define TIM_BDTR_BK2P_Pos (25U)
<> 147:30b64687e01f 13275 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 13276 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
<> 147:30b64687e01f 13277
<> 147:30b64687e01f 13278 /******************* Bit definition for TIM_DCR register ********************/
<> 147:30b64687e01f 13279 #define TIM_DCR_DBA_Pos (0U)
<> 147:30b64687e01f 13280 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
<> 147:30b64687e01f 13281 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
<> 147:30b64687e01f 13282 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13283 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13284 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13285 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13286 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13287
<> 147:30b64687e01f 13288 #define TIM_DCR_DBL_Pos (8U)
<> 147:30b64687e01f 13289 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
<> 147:30b64687e01f 13290 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
<> 147:30b64687e01f 13291 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13292 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13293 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13294 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13295 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13296
<> 147:30b64687e01f 13297 /******************* Bit definition for TIM_DMAR register *******************/
<> 147:30b64687e01f 13298 #define TIM_DMAR_DMAB_Pos (0U)
<> 147:30b64687e01f 13299 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
<> 147:30b64687e01f 13300 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 147:30b64687e01f 13301
<> 147:30b64687e01f 13302 /******************* Bit definition for TIM16_OR register *********************/
<> 147:30b64687e01f 13303 #define TIM16_OR_TI1_RMP_Pos (0U)
<> 147:30b64687e01f 13304 #define TIM16_OR_TI1_RMP_Msk (0x3U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */
<> 147:30b64687e01f 13305 #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
<> 147:30b64687e01f 13306 #define TIM16_OR_TI1_RMP_0 (0x1U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13307 #define TIM16_OR_TI1_RMP_1 (0x2U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13308
<> 147:30b64687e01f 13309 /******************* Bit definition for TIM1_OR register *********************/
<> 147:30b64687e01f 13310 #define TIM1_OR_ETR_RMP_Pos (0U)
<> 147:30b64687e01f 13311 #define TIM1_OR_ETR_RMP_Msk (0xFU << TIM1_OR_ETR_RMP_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 13312 #define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
<> 147:30b64687e01f 13313 #define TIM1_OR_ETR_RMP_0 (0x1U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13314 #define TIM1_OR_ETR_RMP_1 (0x2U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13315 #define TIM1_OR_ETR_RMP_2 (0x4U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13316 #define TIM1_OR_ETR_RMP_3 (0x8U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13317
<> 147:30b64687e01f 13318 /******************* Bit definition for TIM8_OR register *********************/
<> 147:30b64687e01f 13319 #define TIM8_OR_ETR_RMP_Pos (0U)
<> 147:30b64687e01f 13320 #define TIM8_OR_ETR_RMP_Msk (0xFU << TIM8_OR_ETR_RMP_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 13321 #define TIM8_OR_ETR_RMP TIM8_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
<> 147:30b64687e01f 13322 #define TIM8_OR_ETR_RMP_0 (0x1U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13323 #define TIM8_OR_ETR_RMP_1 (0x2U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13324 #define TIM8_OR_ETR_RMP_2 (0x4U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13325 #define TIM8_OR_ETR_RMP_3 (0x8U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13326
<> 147:30b64687e01f 13327 /******************* Bit definition for TIM20_OR register *******************/
<> 147:30b64687e01f 13328 #define TIM20_OR_ETR_RMP_Pos (0U)
<> 147:30b64687e01f 13329 #define TIM20_OR_ETR_RMP_Msk (0xFU << TIM20_OR_ETR_RMP_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 13330 #define TIM20_OR_ETR_RMP TIM20_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
<> 147:30b64687e01f 13331 #define TIM20_OR_ETR_RMP_0 (0x1U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13332 #define TIM20_OR_ETR_RMP_1 (0x2U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13333 #define TIM20_OR_ETR_RMP_2 (0x4U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13334 #define TIM20_OR_ETR_RMP_3 (0x8U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13335
<> 147:30b64687e01f 13336 /****************** Bit definition for TIM_CCMR3 register *******************/
<> 147:30b64687e01f 13337 #define TIM_CCMR3_OC5FE_Pos (2U)
<> 147:30b64687e01f 13338 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13339 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
<> 147:30b64687e01f 13340 #define TIM_CCMR3_OC5PE_Pos (3U)
<> 147:30b64687e01f 13341 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13342 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
<> 147:30b64687e01f 13343
<> 147:30b64687e01f 13344 #define TIM_CCMR3_OC5M_Pos (4U)
<> 147:30b64687e01f 13345 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
<> 147:30b64687e01f 13346 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
<> 147:30b64687e01f 13347 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13348 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13349 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13350 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13351
<> 147:30b64687e01f 13352 #define TIM_CCMR3_OC5CE_Pos (7U)
<> 147:30b64687e01f 13353 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13354 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
<> 147:30b64687e01f 13355
<> 147:30b64687e01f 13356 #define TIM_CCMR3_OC6FE_Pos (10U)
<> 147:30b64687e01f 13357 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13358 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
<> 147:30b64687e01f 13359 #define TIM_CCMR3_OC6PE_Pos (11U)
<> 147:30b64687e01f 13360 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13361 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
<> 147:30b64687e01f 13362
<> 147:30b64687e01f 13363 #define TIM_CCMR3_OC6M_Pos (12U)
<> 147:30b64687e01f 13364 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
<> 147:30b64687e01f 13365 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
<> 147:30b64687e01f 13366 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13367 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13368 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13369 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13370
<> 147:30b64687e01f 13371 #define TIM_CCMR3_OC6CE_Pos (15U)
<> 147:30b64687e01f 13372 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13373 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
<> 147:30b64687e01f 13374
<> 147:30b64687e01f 13375 /******************************************************************************/
<> 147:30b64687e01f 13376 /* */
<> 147:30b64687e01f 13377 /* Touch Sensing Controller (TSC) */
<> 147:30b64687e01f 13378 /* */
<> 147:30b64687e01f 13379 /******************************************************************************/
<> 147:30b64687e01f 13380 /******************* Bit definition for TSC_CR register *********************/
<> 147:30b64687e01f 13381 #define TSC_CR_TSCE_Pos (0U)
<> 147:30b64687e01f 13382 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13383 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
<> 147:30b64687e01f 13384 #define TSC_CR_START_Pos (1U)
<> 147:30b64687e01f 13385 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13386 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
<> 147:30b64687e01f 13387 #define TSC_CR_AM_Pos (2U)
<> 147:30b64687e01f 13388 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13389 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
<> 147:30b64687e01f 13390 #define TSC_CR_SYNCPOL_Pos (3U)
<> 147:30b64687e01f 13391 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13392 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
<> 147:30b64687e01f 13393 #define TSC_CR_IODEF_Pos (4U)
<> 147:30b64687e01f 13394 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13395 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
<> 147:30b64687e01f 13396
<> 147:30b64687e01f 13397 #define TSC_CR_MCV_Pos (5U)
<> 147:30b64687e01f 13398 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
<> 147:30b64687e01f 13399 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
<> 147:30b64687e01f 13400 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13401 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13402 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13403
<> 147:30b64687e01f 13404 #define TSC_CR_PGPSC_Pos (12U)
<> 147:30b64687e01f 13405 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
<> 147:30b64687e01f 13406 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
<> 147:30b64687e01f 13407 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13408 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13409 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13410
<> 147:30b64687e01f 13411 #define TSC_CR_SSPSC_Pos (15U)
<> 147:30b64687e01f 13412 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13413 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
<> 147:30b64687e01f 13414 #define TSC_CR_SSE_Pos (16U)
<> 147:30b64687e01f 13415 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13416 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
<> 147:30b64687e01f 13417
<> 147:30b64687e01f 13418 #define TSC_CR_SSD_Pos (17U)
<> 147:30b64687e01f 13419 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
<> 147:30b64687e01f 13420 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
<> 147:30b64687e01f 13421 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13422 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 13423 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 13424 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13425 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13426 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 13427 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 13428
<> 147:30b64687e01f 13429 #define TSC_CR_CTPL_Pos (24U)
<> 147:30b64687e01f 13430 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
<> 147:30b64687e01f 13431 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
<> 147:30b64687e01f 13432 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13433 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 13434 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 13435 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 13436
<> 147:30b64687e01f 13437 #define TSC_CR_CTPH_Pos (28U)
<> 147:30b64687e01f 13438 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
<> 147:30b64687e01f 13439 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
<> 147:30b64687e01f 13440 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 13441 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 13442 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 13443 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 13444
<> 147:30b64687e01f 13445 /******************* Bit definition for TSC_IER register ********************/
<> 147:30b64687e01f 13446 #define TSC_IER_EOAIE_Pos (0U)
<> 147:30b64687e01f 13447 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13448 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
<> 147:30b64687e01f 13449 #define TSC_IER_MCEIE_Pos (1U)
<> 147:30b64687e01f 13450 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13451 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
<> 147:30b64687e01f 13452
<> 147:30b64687e01f 13453 /******************* Bit definition for TSC_ICR register ********************/
<> 147:30b64687e01f 13454 #define TSC_ICR_EOAIC_Pos (0U)
<> 147:30b64687e01f 13455 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13456 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
<> 147:30b64687e01f 13457 #define TSC_ICR_MCEIC_Pos (1U)
<> 147:30b64687e01f 13458 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13459 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
<> 147:30b64687e01f 13460
<> 147:30b64687e01f 13461 /******************* Bit definition for TSC_ISR register ********************/
<> 147:30b64687e01f 13462 #define TSC_ISR_EOAF_Pos (0U)
<> 147:30b64687e01f 13463 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13464 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
<> 147:30b64687e01f 13465 #define TSC_ISR_MCEF_Pos (1U)
<> 147:30b64687e01f 13466 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13467 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
<> 147:30b64687e01f 13468
<> 147:30b64687e01f 13469 /******************* Bit definition for TSC_IOHCR register ******************/
<> 147:30b64687e01f 13470 #define TSC_IOHCR_G1_IO1_Pos (0U)
<> 147:30b64687e01f 13471 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13472 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13473 #define TSC_IOHCR_G1_IO2_Pos (1U)
<> 147:30b64687e01f 13474 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13475 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13476 #define TSC_IOHCR_G1_IO3_Pos (2U)
<> 147:30b64687e01f 13477 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13478 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13479 #define TSC_IOHCR_G1_IO4_Pos (3U)
<> 147:30b64687e01f 13480 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13481 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13482 #define TSC_IOHCR_G2_IO1_Pos (4U)
<> 147:30b64687e01f 13483 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13484 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13485 #define TSC_IOHCR_G2_IO2_Pos (5U)
<> 147:30b64687e01f 13486 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13487 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13488 #define TSC_IOHCR_G2_IO3_Pos (6U)
<> 147:30b64687e01f 13489 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13490 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13491 #define TSC_IOHCR_G2_IO4_Pos (7U)
<> 147:30b64687e01f 13492 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13493 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13494 #define TSC_IOHCR_G3_IO1_Pos (8U)
<> 147:30b64687e01f 13495 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13496 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13497 #define TSC_IOHCR_G3_IO2_Pos (9U)
<> 147:30b64687e01f 13498 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13499 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13500 #define TSC_IOHCR_G3_IO3_Pos (10U)
<> 147:30b64687e01f 13501 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13502 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13503 #define TSC_IOHCR_G3_IO4_Pos (11U)
<> 147:30b64687e01f 13504 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13505 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13506 #define TSC_IOHCR_G4_IO1_Pos (12U)
<> 147:30b64687e01f 13507 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13508 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13509 #define TSC_IOHCR_G4_IO2_Pos (13U)
<> 147:30b64687e01f 13510 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13511 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13512 #define TSC_IOHCR_G4_IO3_Pos (14U)
<> 147:30b64687e01f 13513 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13514 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13515 #define TSC_IOHCR_G4_IO4_Pos (15U)
<> 147:30b64687e01f 13516 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13517 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13518 #define TSC_IOHCR_G5_IO1_Pos (16U)
<> 147:30b64687e01f 13519 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13520 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13521 #define TSC_IOHCR_G5_IO2_Pos (17U)
<> 147:30b64687e01f 13522 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13523 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13524 #define TSC_IOHCR_G5_IO3_Pos (18U)
<> 147:30b64687e01f 13525 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 13526 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13527 #define TSC_IOHCR_G5_IO4_Pos (19U)
<> 147:30b64687e01f 13528 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 13529 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13530 #define TSC_IOHCR_G6_IO1_Pos (20U)
<> 147:30b64687e01f 13531 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13532 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13533 #define TSC_IOHCR_G6_IO2_Pos (21U)
<> 147:30b64687e01f 13534 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13535 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13536 #define TSC_IOHCR_G6_IO3_Pos (22U)
<> 147:30b64687e01f 13537 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 13538 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13539 #define TSC_IOHCR_G6_IO4_Pos (23U)
<> 147:30b64687e01f 13540 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 13541 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13542 #define TSC_IOHCR_G7_IO1_Pos (24U)
<> 147:30b64687e01f 13543 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13544 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13545 #define TSC_IOHCR_G7_IO2_Pos (25U)
<> 147:30b64687e01f 13546 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 13547 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13548 #define TSC_IOHCR_G7_IO3_Pos (26U)
<> 147:30b64687e01f 13549 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 13550 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13551 #define TSC_IOHCR_G7_IO4_Pos (27U)
<> 147:30b64687e01f 13552 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 13553 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13554 #define TSC_IOHCR_G8_IO1_Pos (28U)
<> 147:30b64687e01f 13555 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 13556 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13557 #define TSC_IOHCR_G8_IO2_Pos (29U)
<> 147:30b64687e01f 13558 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 13559 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13560 #define TSC_IOHCR_G8_IO3_Pos (30U)
<> 147:30b64687e01f 13561 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 13562 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13563 #define TSC_IOHCR_G8_IO4_Pos (31U)
<> 147:30b64687e01f 13564 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 13565 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
<> 147:30b64687e01f 13566
<> 147:30b64687e01f 13567 /******************* Bit definition for TSC_IOASCR register *****************/
<> 147:30b64687e01f 13568 #define TSC_IOASCR_G1_IO1_Pos (0U)
<> 147:30b64687e01f 13569 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13570 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
<> 147:30b64687e01f 13571 #define TSC_IOASCR_G1_IO2_Pos (1U)
<> 147:30b64687e01f 13572 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13573 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
<> 147:30b64687e01f 13574 #define TSC_IOASCR_G1_IO3_Pos (2U)
<> 147:30b64687e01f 13575 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13576 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
<> 147:30b64687e01f 13577 #define TSC_IOASCR_G1_IO4_Pos (3U)
<> 147:30b64687e01f 13578 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13579 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
<> 147:30b64687e01f 13580 #define TSC_IOASCR_G2_IO1_Pos (4U)
<> 147:30b64687e01f 13581 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13582 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
<> 147:30b64687e01f 13583 #define TSC_IOASCR_G2_IO2_Pos (5U)
<> 147:30b64687e01f 13584 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13585 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
<> 147:30b64687e01f 13586 #define TSC_IOASCR_G2_IO3_Pos (6U)
<> 147:30b64687e01f 13587 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13588 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
<> 147:30b64687e01f 13589 #define TSC_IOASCR_G2_IO4_Pos (7U)
<> 147:30b64687e01f 13590 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13591 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
<> 147:30b64687e01f 13592 #define TSC_IOASCR_G3_IO1_Pos (8U)
<> 147:30b64687e01f 13593 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13594 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
<> 147:30b64687e01f 13595 #define TSC_IOASCR_G3_IO2_Pos (9U)
<> 147:30b64687e01f 13596 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13597 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
<> 147:30b64687e01f 13598 #define TSC_IOASCR_G3_IO3_Pos (10U)
<> 147:30b64687e01f 13599 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13600 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
<> 147:30b64687e01f 13601 #define TSC_IOASCR_G3_IO4_Pos (11U)
<> 147:30b64687e01f 13602 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13603 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
<> 147:30b64687e01f 13604 #define TSC_IOASCR_G4_IO1_Pos (12U)
<> 147:30b64687e01f 13605 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13606 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
<> 147:30b64687e01f 13607 #define TSC_IOASCR_G4_IO2_Pos (13U)
<> 147:30b64687e01f 13608 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13609 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
<> 147:30b64687e01f 13610 #define TSC_IOASCR_G4_IO3_Pos (14U)
<> 147:30b64687e01f 13611 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13612 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
<> 147:30b64687e01f 13613 #define TSC_IOASCR_G4_IO4_Pos (15U)
<> 147:30b64687e01f 13614 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13615 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
<> 147:30b64687e01f 13616 #define TSC_IOASCR_G5_IO1_Pos (16U)
<> 147:30b64687e01f 13617 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13618 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
<> 147:30b64687e01f 13619 #define TSC_IOASCR_G5_IO2_Pos (17U)
<> 147:30b64687e01f 13620 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13621 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
<> 147:30b64687e01f 13622 #define TSC_IOASCR_G5_IO3_Pos (18U)
<> 147:30b64687e01f 13623 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 13624 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
<> 147:30b64687e01f 13625 #define TSC_IOASCR_G5_IO4_Pos (19U)
<> 147:30b64687e01f 13626 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 13627 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
<> 147:30b64687e01f 13628 #define TSC_IOASCR_G6_IO1_Pos (20U)
<> 147:30b64687e01f 13629 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13630 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
<> 147:30b64687e01f 13631 #define TSC_IOASCR_G6_IO2_Pos (21U)
<> 147:30b64687e01f 13632 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13633 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
<> 147:30b64687e01f 13634 #define TSC_IOASCR_G6_IO3_Pos (22U)
<> 147:30b64687e01f 13635 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 13636 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
<> 147:30b64687e01f 13637 #define TSC_IOASCR_G6_IO4_Pos (23U)
<> 147:30b64687e01f 13638 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 13639 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
<> 147:30b64687e01f 13640 #define TSC_IOASCR_G7_IO1_Pos (24U)
<> 147:30b64687e01f 13641 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13642 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
<> 147:30b64687e01f 13643 #define TSC_IOASCR_G7_IO2_Pos (25U)
<> 147:30b64687e01f 13644 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 13645 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
<> 147:30b64687e01f 13646 #define TSC_IOASCR_G7_IO3_Pos (26U)
<> 147:30b64687e01f 13647 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 13648 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
<> 147:30b64687e01f 13649 #define TSC_IOASCR_G7_IO4_Pos (27U)
<> 147:30b64687e01f 13650 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 13651 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
<> 147:30b64687e01f 13652 #define TSC_IOASCR_G8_IO1_Pos (28U)
<> 147:30b64687e01f 13653 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 13654 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
<> 147:30b64687e01f 13655 #define TSC_IOASCR_G8_IO2_Pos (29U)
<> 147:30b64687e01f 13656 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 13657 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
<> 147:30b64687e01f 13658 #define TSC_IOASCR_G8_IO3_Pos (30U)
<> 147:30b64687e01f 13659 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 13660 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
<> 147:30b64687e01f 13661 #define TSC_IOASCR_G8_IO4_Pos (31U)
<> 147:30b64687e01f 13662 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 13663 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
<> 147:30b64687e01f 13664
<> 147:30b64687e01f 13665 /******************* Bit definition for TSC_IOSCR register ******************/
<> 147:30b64687e01f 13666 #define TSC_IOSCR_G1_IO1_Pos (0U)
<> 147:30b64687e01f 13667 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13668 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
<> 147:30b64687e01f 13669 #define TSC_IOSCR_G1_IO2_Pos (1U)
<> 147:30b64687e01f 13670 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13671 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
<> 147:30b64687e01f 13672 #define TSC_IOSCR_G1_IO3_Pos (2U)
<> 147:30b64687e01f 13673 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13674 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
<> 147:30b64687e01f 13675 #define TSC_IOSCR_G1_IO4_Pos (3U)
<> 147:30b64687e01f 13676 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13677 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
<> 147:30b64687e01f 13678 #define TSC_IOSCR_G2_IO1_Pos (4U)
<> 147:30b64687e01f 13679 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13680 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
<> 147:30b64687e01f 13681 #define TSC_IOSCR_G2_IO2_Pos (5U)
<> 147:30b64687e01f 13682 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13683 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
<> 147:30b64687e01f 13684 #define TSC_IOSCR_G2_IO3_Pos (6U)
<> 147:30b64687e01f 13685 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13686 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
<> 147:30b64687e01f 13687 #define TSC_IOSCR_G2_IO4_Pos (7U)
<> 147:30b64687e01f 13688 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13689 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
<> 147:30b64687e01f 13690 #define TSC_IOSCR_G3_IO1_Pos (8U)
<> 147:30b64687e01f 13691 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13692 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
<> 147:30b64687e01f 13693 #define TSC_IOSCR_G3_IO2_Pos (9U)
<> 147:30b64687e01f 13694 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13695 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
<> 147:30b64687e01f 13696 #define TSC_IOSCR_G3_IO3_Pos (10U)
<> 147:30b64687e01f 13697 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13698 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
<> 147:30b64687e01f 13699 #define TSC_IOSCR_G3_IO4_Pos (11U)
<> 147:30b64687e01f 13700 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13701 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
<> 147:30b64687e01f 13702 #define TSC_IOSCR_G4_IO1_Pos (12U)
<> 147:30b64687e01f 13703 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13704 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
<> 147:30b64687e01f 13705 #define TSC_IOSCR_G4_IO2_Pos (13U)
<> 147:30b64687e01f 13706 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13707 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
<> 147:30b64687e01f 13708 #define TSC_IOSCR_G4_IO3_Pos (14U)
<> 147:30b64687e01f 13709 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13710 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
<> 147:30b64687e01f 13711 #define TSC_IOSCR_G4_IO4_Pos (15U)
<> 147:30b64687e01f 13712 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13713 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
<> 147:30b64687e01f 13714 #define TSC_IOSCR_G5_IO1_Pos (16U)
<> 147:30b64687e01f 13715 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13716 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
<> 147:30b64687e01f 13717 #define TSC_IOSCR_G5_IO2_Pos (17U)
<> 147:30b64687e01f 13718 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13719 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
<> 147:30b64687e01f 13720 #define TSC_IOSCR_G5_IO3_Pos (18U)
<> 147:30b64687e01f 13721 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 13722 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
<> 147:30b64687e01f 13723 #define TSC_IOSCR_G5_IO4_Pos (19U)
<> 147:30b64687e01f 13724 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 13725 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
<> 147:30b64687e01f 13726 #define TSC_IOSCR_G6_IO1_Pos (20U)
<> 147:30b64687e01f 13727 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13728 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
<> 147:30b64687e01f 13729 #define TSC_IOSCR_G6_IO2_Pos (21U)
<> 147:30b64687e01f 13730 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13731 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
<> 147:30b64687e01f 13732 #define TSC_IOSCR_G6_IO3_Pos (22U)
<> 147:30b64687e01f 13733 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 13734 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
<> 147:30b64687e01f 13735 #define TSC_IOSCR_G6_IO4_Pos (23U)
<> 147:30b64687e01f 13736 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 13737 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
<> 147:30b64687e01f 13738 #define TSC_IOSCR_G7_IO1_Pos (24U)
<> 147:30b64687e01f 13739 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13740 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
<> 147:30b64687e01f 13741 #define TSC_IOSCR_G7_IO2_Pos (25U)
<> 147:30b64687e01f 13742 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 13743 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
<> 147:30b64687e01f 13744 #define TSC_IOSCR_G7_IO3_Pos (26U)
<> 147:30b64687e01f 13745 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 13746 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
<> 147:30b64687e01f 13747 #define TSC_IOSCR_G7_IO4_Pos (27U)
<> 147:30b64687e01f 13748 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 13749 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
<> 147:30b64687e01f 13750 #define TSC_IOSCR_G8_IO1_Pos (28U)
<> 147:30b64687e01f 13751 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 13752 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
<> 147:30b64687e01f 13753 #define TSC_IOSCR_G8_IO2_Pos (29U)
<> 147:30b64687e01f 13754 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 13755 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
<> 147:30b64687e01f 13756 #define TSC_IOSCR_G8_IO3_Pos (30U)
<> 147:30b64687e01f 13757 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 13758 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
<> 147:30b64687e01f 13759 #define TSC_IOSCR_G8_IO4_Pos (31U)
<> 147:30b64687e01f 13760 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 13761 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
<> 147:30b64687e01f 13762
<> 147:30b64687e01f 13763 /******************* Bit definition for TSC_IOCCR register ******************/
<> 147:30b64687e01f 13764 #define TSC_IOCCR_G1_IO1_Pos (0U)
<> 147:30b64687e01f 13765 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13766 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
<> 147:30b64687e01f 13767 #define TSC_IOCCR_G1_IO2_Pos (1U)
<> 147:30b64687e01f 13768 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13769 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
<> 147:30b64687e01f 13770 #define TSC_IOCCR_G1_IO3_Pos (2U)
<> 147:30b64687e01f 13771 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13772 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
<> 147:30b64687e01f 13773 #define TSC_IOCCR_G1_IO4_Pos (3U)
<> 147:30b64687e01f 13774 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13775 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
<> 147:30b64687e01f 13776 #define TSC_IOCCR_G2_IO1_Pos (4U)
<> 147:30b64687e01f 13777 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13778 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
<> 147:30b64687e01f 13779 #define TSC_IOCCR_G2_IO2_Pos (5U)
<> 147:30b64687e01f 13780 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13781 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
<> 147:30b64687e01f 13782 #define TSC_IOCCR_G2_IO3_Pos (6U)
<> 147:30b64687e01f 13783 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13784 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
<> 147:30b64687e01f 13785 #define TSC_IOCCR_G2_IO4_Pos (7U)
<> 147:30b64687e01f 13786 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13787 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
<> 147:30b64687e01f 13788 #define TSC_IOCCR_G3_IO1_Pos (8U)
<> 147:30b64687e01f 13789 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13790 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
<> 147:30b64687e01f 13791 #define TSC_IOCCR_G3_IO2_Pos (9U)
<> 147:30b64687e01f 13792 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13793 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
<> 147:30b64687e01f 13794 #define TSC_IOCCR_G3_IO3_Pos (10U)
<> 147:30b64687e01f 13795 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13796 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
<> 147:30b64687e01f 13797 #define TSC_IOCCR_G3_IO4_Pos (11U)
<> 147:30b64687e01f 13798 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13799 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
<> 147:30b64687e01f 13800 #define TSC_IOCCR_G4_IO1_Pos (12U)
<> 147:30b64687e01f 13801 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13802 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
<> 147:30b64687e01f 13803 #define TSC_IOCCR_G4_IO2_Pos (13U)
<> 147:30b64687e01f 13804 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13805 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
<> 147:30b64687e01f 13806 #define TSC_IOCCR_G4_IO3_Pos (14U)
<> 147:30b64687e01f 13807 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13808 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
<> 147:30b64687e01f 13809 #define TSC_IOCCR_G4_IO4_Pos (15U)
<> 147:30b64687e01f 13810 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13811 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
<> 147:30b64687e01f 13812 #define TSC_IOCCR_G5_IO1_Pos (16U)
<> 147:30b64687e01f 13813 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13814 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
<> 147:30b64687e01f 13815 #define TSC_IOCCR_G5_IO2_Pos (17U)
<> 147:30b64687e01f 13816 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13817 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
<> 147:30b64687e01f 13818 #define TSC_IOCCR_G5_IO3_Pos (18U)
<> 147:30b64687e01f 13819 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 13820 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
<> 147:30b64687e01f 13821 #define TSC_IOCCR_G5_IO4_Pos (19U)
<> 147:30b64687e01f 13822 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 13823 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
<> 147:30b64687e01f 13824 #define TSC_IOCCR_G6_IO1_Pos (20U)
<> 147:30b64687e01f 13825 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13826 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
<> 147:30b64687e01f 13827 #define TSC_IOCCR_G6_IO2_Pos (21U)
<> 147:30b64687e01f 13828 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13829 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
<> 147:30b64687e01f 13830 #define TSC_IOCCR_G6_IO3_Pos (22U)
<> 147:30b64687e01f 13831 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 13832 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
<> 147:30b64687e01f 13833 #define TSC_IOCCR_G6_IO4_Pos (23U)
<> 147:30b64687e01f 13834 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 13835 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
<> 147:30b64687e01f 13836 #define TSC_IOCCR_G7_IO1_Pos (24U)
<> 147:30b64687e01f 13837 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13838 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
<> 147:30b64687e01f 13839 #define TSC_IOCCR_G7_IO2_Pos (25U)
<> 147:30b64687e01f 13840 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 13841 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
<> 147:30b64687e01f 13842 #define TSC_IOCCR_G7_IO3_Pos (26U)
<> 147:30b64687e01f 13843 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 13844 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
<> 147:30b64687e01f 13845 #define TSC_IOCCR_G7_IO4_Pos (27U)
<> 147:30b64687e01f 13846 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 13847 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
<> 147:30b64687e01f 13848 #define TSC_IOCCR_G8_IO1_Pos (28U)
<> 147:30b64687e01f 13849 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 13850 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
<> 147:30b64687e01f 13851 #define TSC_IOCCR_G8_IO2_Pos (29U)
<> 147:30b64687e01f 13852 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 147:30b64687e01f 13853 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
<> 147:30b64687e01f 13854 #define TSC_IOCCR_G8_IO3_Pos (30U)
<> 147:30b64687e01f 13855 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 147:30b64687e01f 13856 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
<> 147:30b64687e01f 13857 #define TSC_IOCCR_G8_IO4_Pos (31U)
<> 147:30b64687e01f 13858 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 147:30b64687e01f 13859 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
<> 147:30b64687e01f 13860
<> 147:30b64687e01f 13861 /******************* Bit definition for TSC_IOGCSR register *****************/
<> 147:30b64687e01f 13862 #define TSC_IOGCSR_G1E_Pos (0U)
<> 147:30b64687e01f 13863 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13864 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
<> 147:30b64687e01f 13865 #define TSC_IOGCSR_G2E_Pos (1U)
<> 147:30b64687e01f 13866 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13867 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
<> 147:30b64687e01f 13868 #define TSC_IOGCSR_G3E_Pos (2U)
<> 147:30b64687e01f 13869 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13870 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
<> 147:30b64687e01f 13871 #define TSC_IOGCSR_G4E_Pos (3U)
<> 147:30b64687e01f 13872 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13873 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
<> 147:30b64687e01f 13874 #define TSC_IOGCSR_G5E_Pos (4U)
<> 147:30b64687e01f 13875 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13876 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
<> 147:30b64687e01f 13877 #define TSC_IOGCSR_G6E_Pos (5U)
<> 147:30b64687e01f 13878 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13879 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
<> 147:30b64687e01f 13880 #define TSC_IOGCSR_G7E_Pos (6U)
<> 147:30b64687e01f 13881 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13882 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
<> 147:30b64687e01f 13883 #define TSC_IOGCSR_G8E_Pos (7U)
<> 147:30b64687e01f 13884 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13885 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
<> 147:30b64687e01f 13886 #define TSC_IOGCSR_G1S_Pos (16U)
<> 147:30b64687e01f 13887 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13888 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
<> 147:30b64687e01f 13889 #define TSC_IOGCSR_G2S_Pos (17U)
<> 147:30b64687e01f 13890 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13891 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
<> 147:30b64687e01f 13892 #define TSC_IOGCSR_G3S_Pos (18U)
<> 147:30b64687e01f 13893 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 13894 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
<> 147:30b64687e01f 13895 #define TSC_IOGCSR_G4S_Pos (19U)
<> 147:30b64687e01f 13896 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 13897 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
<> 147:30b64687e01f 13898 #define TSC_IOGCSR_G5S_Pos (20U)
<> 147:30b64687e01f 13899 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13900 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
<> 147:30b64687e01f 13901 #define TSC_IOGCSR_G6S_Pos (21U)
<> 147:30b64687e01f 13902 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13903 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
<> 147:30b64687e01f 13904 #define TSC_IOGCSR_G7S_Pos (22U)
<> 147:30b64687e01f 13905 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 13906 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
<> 147:30b64687e01f 13907 #define TSC_IOGCSR_G8S_Pos (23U)
<> 147:30b64687e01f 13908 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 13909 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
<> 147:30b64687e01f 13910
<> 147:30b64687e01f 13911 /******************* Bit definition for TSC_IOGXCR register *****************/
<> 147:30b64687e01f 13912 #define TSC_IOGXCR_CNT_Pos (0U)
<> 147:30b64687e01f 13913 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
<> 147:30b64687e01f 13914 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
<> 147:30b64687e01f 13915
<> 147:30b64687e01f 13916 /******************************************************************************/
<> 147:30b64687e01f 13917 /* */
<> 147:30b64687e01f 13918 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<> 147:30b64687e01f 13919 /* */
<> 147:30b64687e01f 13920 /******************************************************************************/
<> 147:30b64687e01f 13921
<> 147:30b64687e01f 13922 /*
<> 147:30b64687e01f 13923 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 147:30b64687e01f 13924 */
<> 147:30b64687e01f 13925
<> 147:30b64687e01f 13926 /* Support of 7 bits data length feature */
<> 147:30b64687e01f 13927 #define USART_7BITS_SUPPORT
<> 147:30b64687e01f 13928
<> 147:30b64687e01f 13929 /****************** Bit definition for USART_CR1 register *******************/
<> 147:30b64687e01f 13930 #define USART_CR1_UE_Pos (0U)
<> 147:30b64687e01f 13931 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 13932 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
<> 147:30b64687e01f 13933 #define USART_CR1_UESM_Pos (1U)
<> 147:30b64687e01f 13934 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 13935 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
<> 147:30b64687e01f 13936 #define USART_CR1_RE_Pos (2U)
<> 147:30b64687e01f 13937 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 13938 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
<> 147:30b64687e01f 13939 #define USART_CR1_TE_Pos (3U)
<> 147:30b64687e01f 13940 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 13941 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
<> 147:30b64687e01f 13942 #define USART_CR1_IDLEIE_Pos (4U)
<> 147:30b64687e01f 13943 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 13944 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
<> 147:30b64687e01f 13945 #define USART_CR1_RXNEIE_Pos (5U)
<> 147:30b64687e01f 13946 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 13947 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
<> 147:30b64687e01f 13948 #define USART_CR1_TCIE_Pos (6U)
<> 147:30b64687e01f 13949 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 13950 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
<> 147:30b64687e01f 13951 #define USART_CR1_TXEIE_Pos (7U)
<> 147:30b64687e01f 13952 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 13953 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
<> 147:30b64687e01f 13954 #define USART_CR1_PEIE_Pos (8U)
<> 147:30b64687e01f 13955 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 13956 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
<> 147:30b64687e01f 13957 #define USART_CR1_PS_Pos (9U)
<> 147:30b64687e01f 13958 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 13959 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
<> 147:30b64687e01f 13960 #define USART_CR1_PCE_Pos (10U)
<> 147:30b64687e01f 13961 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 13962 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
<> 147:30b64687e01f 13963 #define USART_CR1_WAKE_Pos (11U)
<> 147:30b64687e01f 13964 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 13965 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
<> 147:30b64687e01f 13966 #define USART_CR1_M0_Pos (12U)
<> 147:30b64687e01f 13967 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 13968 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */
<> 147:30b64687e01f 13969 #define USART_CR1_MME_Pos (13U)
<> 147:30b64687e01f 13970 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 13971 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
<> 147:30b64687e01f 13972 #define USART_CR1_CMIE_Pos (14U)
<> 147:30b64687e01f 13973 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 13974 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
<> 147:30b64687e01f 13975 #define USART_CR1_OVER8_Pos (15U)
<> 147:30b64687e01f 13976 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 13977 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
<> 147:30b64687e01f 13978 #define USART_CR1_DEDT_Pos (16U)
<> 147:30b64687e01f 13979 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
<> 147:30b64687e01f 13980 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
<> 147:30b64687e01f 13981 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 13982 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 13983 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 13984 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 13985 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 13986 #define USART_CR1_DEAT_Pos (21U)
<> 147:30b64687e01f 13987 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
<> 147:30b64687e01f 13988 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
<> 147:30b64687e01f 13989 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 13990 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 13991 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 13992 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
<> 147:30b64687e01f 13993 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
<> 147:30b64687e01f 13994 #define USART_CR1_RTOIE_Pos (26U)
<> 147:30b64687e01f 13995 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
<> 147:30b64687e01f 13996 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
<> 147:30b64687e01f 13997 #define USART_CR1_EOBIE_Pos (27U)
<> 147:30b64687e01f 13998 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
<> 147:30b64687e01f 13999 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
<> 147:30b64687e01f 14000 #define USART_CR1_M1_Pos (28U)
<> 147:30b64687e01f 14001 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
<> 147:30b64687e01f 14002 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */
<> 147:30b64687e01f 14003 #define USART_CR1_M_Pos (12U)
<> 147:30b64687e01f 14004 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
<> 147:30b64687e01f 14005 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */
<> 147:30b64687e01f 14006
<> 147:30b64687e01f 14007 /****************** Bit definition for USART_CR2 register *******************/
<> 147:30b64687e01f 14008 #define USART_CR2_ADDM7_Pos (4U)
<> 147:30b64687e01f 14009 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 14010 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
<> 147:30b64687e01f 14011 #define USART_CR2_LBDL_Pos (5U)
<> 147:30b64687e01f 14012 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 14013 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
<> 147:30b64687e01f 14014 #define USART_CR2_LBDIE_Pos (6U)
<> 147:30b64687e01f 14015 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 14016 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
<> 147:30b64687e01f 14017 #define USART_CR2_LBCL_Pos (8U)
<> 147:30b64687e01f 14018 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 14019 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
<> 147:30b64687e01f 14020 #define USART_CR2_CPHA_Pos (9U)
<> 147:30b64687e01f 14021 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 14022 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
<> 147:30b64687e01f 14023 #define USART_CR2_CPOL_Pos (10U)
<> 147:30b64687e01f 14024 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 14025 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
<> 147:30b64687e01f 14026 #define USART_CR2_CLKEN_Pos (11U)
<> 147:30b64687e01f 14027 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 14028 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
<> 147:30b64687e01f 14029 #define USART_CR2_STOP_Pos (12U)
<> 147:30b64687e01f 14030 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
<> 147:30b64687e01f 14031 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
<> 147:30b64687e01f 14032 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 14033 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 14034 #define USART_CR2_LINEN_Pos (14U)
<> 147:30b64687e01f 14035 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 14036 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
<> 147:30b64687e01f 14037 #define USART_CR2_SWAP_Pos (15U)
<> 147:30b64687e01f 14038 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 14039 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
<> 147:30b64687e01f 14040 #define USART_CR2_RXINV_Pos (16U)
<> 147:30b64687e01f 14041 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 14042 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
<> 147:30b64687e01f 14043 #define USART_CR2_TXINV_Pos (17U)
<> 147:30b64687e01f 14044 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 14045 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
<> 147:30b64687e01f 14046 #define USART_CR2_DATAINV_Pos (18U)
<> 147:30b64687e01f 14047 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 14048 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
<> 147:30b64687e01f 14049 #define USART_CR2_MSBFIRST_Pos (19U)
<> 147:30b64687e01f 14050 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 14051 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
<> 147:30b64687e01f 14052 #define USART_CR2_ABREN_Pos (20U)
<> 147:30b64687e01f 14053 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 14054 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
<> 147:30b64687e01f 14055 #define USART_CR2_ABRMODE_Pos (21U)
<> 147:30b64687e01f 14056 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
<> 147:30b64687e01f 14057 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
<> 147:30b64687e01f 14058 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 14059 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 14060 #define USART_CR2_RTOEN_Pos (23U)
<> 147:30b64687e01f 14061 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
<> 147:30b64687e01f 14062 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
<> 147:30b64687e01f 14063 #define USART_CR2_ADD_Pos (24U)
<> 147:30b64687e01f 14064 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 14065 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
<> 147:30b64687e01f 14066
<> 147:30b64687e01f 14067 /****************** Bit definition for USART_CR3 register *******************/
<> 147:30b64687e01f 14068 #define USART_CR3_EIE_Pos (0U)
<> 147:30b64687e01f 14069 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 14070 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
<> 147:30b64687e01f 14071 #define USART_CR3_IREN_Pos (1U)
<> 147:30b64687e01f 14072 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 14073 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
<> 147:30b64687e01f 14074 #define USART_CR3_IRLP_Pos (2U)
<> 147:30b64687e01f 14075 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 14076 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
<> 147:30b64687e01f 14077 #define USART_CR3_HDSEL_Pos (3U)
<> 147:30b64687e01f 14078 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 14079 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
<> 147:30b64687e01f 14080 #define USART_CR3_NACK_Pos (4U)
<> 147:30b64687e01f 14081 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 14082 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
<> 147:30b64687e01f 14083 #define USART_CR3_SCEN_Pos (5U)
<> 147:30b64687e01f 14084 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 14085 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
<> 147:30b64687e01f 14086 #define USART_CR3_DMAR_Pos (6U)
<> 147:30b64687e01f 14087 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 14088 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
<> 147:30b64687e01f 14089 #define USART_CR3_DMAT_Pos (7U)
<> 147:30b64687e01f 14090 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 14091 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
<> 147:30b64687e01f 14092 #define USART_CR3_RTSE_Pos (8U)
<> 147:30b64687e01f 14093 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 14094 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
<> 147:30b64687e01f 14095 #define USART_CR3_CTSE_Pos (9U)
<> 147:30b64687e01f 14096 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 14097 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
<> 147:30b64687e01f 14098 #define USART_CR3_CTSIE_Pos (10U)
<> 147:30b64687e01f 14099 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 14100 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
<> 147:30b64687e01f 14101 #define USART_CR3_ONEBIT_Pos (11U)
<> 147:30b64687e01f 14102 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 14103 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
<> 147:30b64687e01f 14104 #define USART_CR3_OVRDIS_Pos (12U)
<> 147:30b64687e01f 14105 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 14106 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
<> 147:30b64687e01f 14107 #define USART_CR3_DDRE_Pos (13U)
<> 147:30b64687e01f 14108 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
<> 147:30b64687e01f 14109 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
<> 147:30b64687e01f 14110 #define USART_CR3_DEM_Pos (14U)
<> 147:30b64687e01f 14111 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 14112 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
<> 147:30b64687e01f 14113 #define USART_CR3_DEP_Pos (15U)
<> 147:30b64687e01f 14114 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 14115 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
<> 147:30b64687e01f 14116 #define USART_CR3_SCARCNT_Pos (17U)
<> 147:30b64687e01f 14117 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
<> 147:30b64687e01f 14118 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
<> 147:30b64687e01f 14119 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 14120 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 14121 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 14122 #define USART_CR3_WUS_Pos (20U)
<> 147:30b64687e01f 14123 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
<> 147:30b64687e01f 14124 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
<> 147:30b64687e01f 14125 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 14126 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 14127 #define USART_CR3_WUFIE_Pos (22U)
<> 147:30b64687e01f 14128 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 14129 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
<> 147:30b64687e01f 14130
<> 147:30b64687e01f 14131 /****************** Bit definition for USART_BRR register *******************/
<> 147:30b64687e01f 14132 #define USART_BRR_DIV_FRACTION_Pos (0U)
<> 147:30b64687e01f 14133 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
<> 147:30b64687e01f 14134 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
<> 147:30b64687e01f 14135 #define USART_BRR_DIV_MANTISSA_Pos (4U)
<> 147:30b64687e01f 14136 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
<> 147:30b64687e01f 14137 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
<> 147:30b64687e01f 14138
<> 147:30b64687e01f 14139 /****************** Bit definition for USART_GTPR register ******************/
<> 147:30b64687e01f 14140 #define USART_GTPR_PSC_Pos (0U)
<> 147:30b64687e01f 14141 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
<> 147:30b64687e01f 14142 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
<> 147:30b64687e01f 14143 #define USART_GTPR_GT_Pos (8U)
<> 147:30b64687e01f 14144 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
<> 147:30b64687e01f 14145 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
<> 147:30b64687e01f 14146
<> 147:30b64687e01f 14147
<> 147:30b64687e01f 14148 /******************* Bit definition for USART_RTOR register *****************/
<> 147:30b64687e01f 14149 #define USART_RTOR_RTO_Pos (0U)
<> 147:30b64687e01f 14150 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
<> 147:30b64687e01f 14151 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
<> 147:30b64687e01f 14152 #define USART_RTOR_BLEN_Pos (24U)
<> 147:30b64687e01f 14153 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
<> 147:30b64687e01f 14154 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
<> 147:30b64687e01f 14155
<> 147:30b64687e01f 14156 /******************* Bit definition for USART_RQR register ******************/
<> 147:30b64687e01f 14157 #define USART_RQR_ABRRQ_Pos (0U)
<> 147:30b64687e01f 14158 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 14159 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
<> 147:30b64687e01f 14160 #define USART_RQR_SBKRQ_Pos (1U)
<> 147:30b64687e01f 14161 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 14162 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
<> 147:30b64687e01f 14163 #define USART_RQR_MMRQ_Pos (2U)
<> 147:30b64687e01f 14164 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 14165 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
<> 147:30b64687e01f 14166 #define USART_RQR_RXFRQ_Pos (3U)
<> 147:30b64687e01f 14167 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 14168 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
<> 147:30b64687e01f 14169 #define USART_RQR_TXFRQ_Pos (4U)
<> 147:30b64687e01f 14170 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 14171 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
<> 147:30b64687e01f 14172
<> 147:30b64687e01f 14173 /******************* Bit definition for USART_ISR register ******************/
<> 147:30b64687e01f 14174 #define USART_ISR_PE_Pos (0U)
<> 147:30b64687e01f 14175 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 14176 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
<> 147:30b64687e01f 14177 #define USART_ISR_FE_Pos (1U)
<> 147:30b64687e01f 14178 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 14179 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
<> 147:30b64687e01f 14180 #define USART_ISR_NE_Pos (2U)
<> 147:30b64687e01f 14181 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 14182 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
<> 147:30b64687e01f 14183 #define USART_ISR_ORE_Pos (3U)
<> 147:30b64687e01f 14184 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 14185 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
<> 147:30b64687e01f 14186 #define USART_ISR_IDLE_Pos (4U)
<> 147:30b64687e01f 14187 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 14188 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
<> 147:30b64687e01f 14189 #define USART_ISR_RXNE_Pos (5U)
<> 147:30b64687e01f 14190 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 14191 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
<> 147:30b64687e01f 14192 #define USART_ISR_TC_Pos (6U)
<> 147:30b64687e01f 14193 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 14194 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
<> 147:30b64687e01f 14195 #define USART_ISR_TXE_Pos (7U)
<> 147:30b64687e01f 14196 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 14197 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
<> 147:30b64687e01f 14198 #define USART_ISR_LBDF_Pos (8U)
<> 147:30b64687e01f 14199 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 14200 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
<> 147:30b64687e01f 14201 #define USART_ISR_CTSIF_Pos (9U)
<> 147:30b64687e01f 14202 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 14203 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
<> 147:30b64687e01f 14204 #define USART_ISR_CTS_Pos (10U)
<> 147:30b64687e01f 14205 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
<> 147:30b64687e01f 14206 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
<> 147:30b64687e01f 14207 #define USART_ISR_RTOF_Pos (11U)
<> 147:30b64687e01f 14208 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 14209 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
<> 147:30b64687e01f 14210 #define USART_ISR_EOBF_Pos (12U)
<> 147:30b64687e01f 14211 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 14212 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
<> 147:30b64687e01f 14213 #define USART_ISR_ABRE_Pos (14U)
<> 147:30b64687e01f 14214 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
<> 147:30b64687e01f 14215 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
<> 147:30b64687e01f 14216 #define USART_ISR_ABRF_Pos (15U)
<> 147:30b64687e01f 14217 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
<> 147:30b64687e01f 14218 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
<> 147:30b64687e01f 14219 #define USART_ISR_BUSY_Pos (16U)
<> 147:30b64687e01f 14220 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
<> 147:30b64687e01f 14221 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
<> 147:30b64687e01f 14222 #define USART_ISR_CMF_Pos (17U)
<> 147:30b64687e01f 14223 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 14224 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
<> 147:30b64687e01f 14225 #define USART_ISR_SBKF_Pos (18U)
<> 147:30b64687e01f 14226 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
<> 147:30b64687e01f 14227 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
<> 147:30b64687e01f 14228 #define USART_ISR_RWU_Pos (19U)
<> 147:30b64687e01f 14229 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
<> 147:30b64687e01f 14230 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
<> 147:30b64687e01f 14231 #define USART_ISR_WUF_Pos (20U)
<> 147:30b64687e01f 14232 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 14233 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
<> 147:30b64687e01f 14234 #define USART_ISR_TEACK_Pos (21U)
<> 147:30b64687e01f 14235 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
<> 147:30b64687e01f 14236 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
<> 147:30b64687e01f 14237 #define USART_ISR_REACK_Pos (22U)
<> 147:30b64687e01f 14238 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
<> 147:30b64687e01f 14239 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
<> 147:30b64687e01f 14240
<> 147:30b64687e01f 14241 /******************* Bit definition for USART_ICR register ******************/
<> 147:30b64687e01f 14242 #define USART_ICR_PECF_Pos (0U)
<> 147:30b64687e01f 14243 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 14244 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
<> 147:30b64687e01f 14245 #define USART_ICR_FECF_Pos (1U)
<> 147:30b64687e01f 14246 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 14247 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
<> 147:30b64687e01f 14248 #define USART_ICR_NCF_Pos (2U)
<> 147:30b64687e01f 14249 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 14250 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
<> 147:30b64687e01f 14251 #define USART_ICR_ORECF_Pos (3U)
<> 147:30b64687e01f 14252 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 14253 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
<> 147:30b64687e01f 14254 #define USART_ICR_IDLECF_Pos (4U)
<> 147:30b64687e01f 14255 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 14256 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
<> 147:30b64687e01f 14257 #define USART_ICR_TCCF_Pos (6U)
<> 147:30b64687e01f 14258 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 14259 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
<> 147:30b64687e01f 14260 #define USART_ICR_LBDCF_Pos (8U)
<> 147:30b64687e01f 14261 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 14262 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
<> 147:30b64687e01f 14263 #define USART_ICR_CTSCF_Pos (9U)
<> 147:30b64687e01f 14264 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 14265 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
<> 147:30b64687e01f 14266 #define USART_ICR_RTOCF_Pos (11U)
<> 147:30b64687e01f 14267 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
<> 147:30b64687e01f 14268 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
<> 147:30b64687e01f 14269 #define USART_ICR_EOBCF_Pos (12U)
<> 147:30b64687e01f 14270 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
<> 147:30b64687e01f 14271 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
<> 147:30b64687e01f 14272 #define USART_ICR_CMCF_Pos (17U)
<> 147:30b64687e01f 14273 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
<> 147:30b64687e01f 14274 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
<> 147:30b64687e01f 14275 #define USART_ICR_WUCF_Pos (20U)
<> 147:30b64687e01f 14276 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
<> 147:30b64687e01f 14277 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
<> 147:30b64687e01f 14278
<> 147:30b64687e01f 14279 /******************* Bit definition for USART_RDR register ******************/
<> 147:30b64687e01f 14280 #define USART_RDR_RDR_Pos (0U)
<> 147:30b64687e01f 14281 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
<> 147:30b64687e01f 14282 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
<> 147:30b64687e01f 14283
<> 147:30b64687e01f 14284 /******************* Bit definition for USART_TDR register ******************/
<> 147:30b64687e01f 14285 #define USART_TDR_TDR_Pos (0U)
<> 147:30b64687e01f 14286 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
<> 147:30b64687e01f 14287 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
<> 147:30b64687e01f 14288
<> 147:30b64687e01f 14289 /******************************************************************************/
<> 147:30b64687e01f 14290 /* */
<> 147:30b64687e01f 14291 /* USB Device General registers */
<> 147:30b64687e01f 14292 /* */
<> 147:30b64687e01f 14293 /******************************************************************************/
<> 147:30b64687e01f 14294 #define USB_CNTR (USB_BASE + 0x40U) /*!< Control register */
<> 147:30b64687e01f 14295 #define USB_ISTR (USB_BASE + 0x44U) /*!< Interrupt status register */
<> 147:30b64687e01f 14296 #define USB_FNR (USB_BASE + 0x48U) /*!< Frame number register */
<> 147:30b64687e01f 14297 #define USB_DADDR (USB_BASE + 0x4CU) /*!< Device address register */
<> 147:30b64687e01f 14298 #define USB_BTABLE (USB_BASE + 0x50U) /*!< Buffer Table address register */
<> 147:30b64687e01f 14299 #define USB_LPMCSR (USB_BASE + 0x54U) /*!< LPM Control and Status register */
<> 147:30b64687e01f 14300
<> 147:30b64687e01f 14301 /**************************** ISTR interrupt events *************************/
<> 147:30b64687e01f 14302 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
<> 147:30b64687e01f 14303 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
<> 147:30b64687e01f 14304 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
<> 147:30b64687e01f 14305 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
<> 147:30b64687e01f 14306 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
<> 147:30b64687e01f 14307 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
<> 147:30b64687e01f 14308 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
<> 147:30b64687e01f 14309 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
<> 147:30b64687e01f 14310 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
<> 147:30b64687e01f 14311 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
<> 147:30b64687e01f 14312 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
<> 147:30b64687e01f 14313
<> 147:30b64687e01f 14314 /* Legacy defines */
<> 147:30b64687e01f 14315 #define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
<> 147:30b64687e01f 14316
<> 147:30b64687e01f 14317 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
<> 147:30b64687e01f 14318 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
<> 147:30b64687e01f 14319 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
<> 147:30b64687e01f 14320 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
<> 147:30b64687e01f 14321 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
<> 147:30b64687e01f 14322 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
<> 147:30b64687e01f 14323 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
<> 147:30b64687e01f 14324 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
<> 147:30b64687e01f 14325 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
<> 147:30b64687e01f 14326
<> 147:30b64687e01f 14327 /* Legacy defines */
<> 147:30b64687e01f 14328 #define USB_CLR_PMAOVRM USB_CLR_PMAOVR
<> 147:30b64687e01f 14329
<> 147:30b64687e01f 14330 /************************* CNTR control register bits definitions ***********/
<> 147:30b64687e01f 14331 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
<> 147:30b64687e01f 14332 #define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
<> 147:30b64687e01f 14333 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
<> 147:30b64687e01f 14334 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
<> 147:30b64687e01f 14335 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
<> 147:30b64687e01f 14336 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
<> 147:30b64687e01f 14337 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
<> 147:30b64687e01f 14338 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
<> 147:30b64687e01f 14339 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
<> 147:30b64687e01f 14340 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
<> 147:30b64687e01f 14341 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
<> 147:30b64687e01f 14342 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
<> 147:30b64687e01f 14343 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
<> 147:30b64687e01f 14344 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
<> 147:30b64687e01f 14345 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
<> 147:30b64687e01f 14346
<> 147:30b64687e01f 14347 /* Legacy defines */
<> 147:30b64687e01f 14348 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
<> 147:30b64687e01f 14349 #define USB_CNTR_LP_MODE USB_CNTR_LPMODE
<> 147:30b64687e01f 14350
<> 147:30b64687e01f 14351 /*************************** LPM register bits definitions ******************/
<> 147:30b64687e01f 14352 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
<> 147:30b64687e01f 14353 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
<> 147:30b64687e01f 14354 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
<> 147:30b64687e01f 14355 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
<> 147:30b64687e01f 14356
<> 147:30b64687e01f 14357 /******************** FNR Frame Number Register bit definitions ************/
<> 147:30b64687e01f 14358 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
<> 147:30b64687e01f 14359 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
<> 147:30b64687e01f 14360 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
<> 147:30b64687e01f 14361 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
<> 147:30b64687e01f 14362 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
<> 147:30b64687e01f 14363
<> 147:30b64687e01f 14364 /******************** DADDR Device ADDRess bit definitions ****************/
<> 147:30b64687e01f 14365 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
<> 147:30b64687e01f 14366 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
<> 147:30b64687e01f 14367
<> 147:30b64687e01f 14368 /****************************** Endpoint register *************************/
<> 147:30b64687e01f 14369 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
<> 147:30b64687e01f 14370 #define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */
<> 147:30b64687e01f 14371 #define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */
<> 147:30b64687e01f 14372 #define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */
<> 147:30b64687e01f 14373 #define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */
<> 147:30b64687e01f 14374 #define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */
<> 147:30b64687e01f 14375 #define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */
<> 147:30b64687e01f 14376 #define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */
<> 147:30b64687e01f 14377 /* bit positions */
<> 147:30b64687e01f 14378 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
<> 147:30b64687e01f 14379 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
<> 147:30b64687e01f 14380 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
<> 147:30b64687e01f 14381 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
<> 147:30b64687e01f 14382 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
<> 147:30b64687e01f 14383 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
<> 147:30b64687e01f 14384 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
<> 147:30b64687e01f 14385 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
<> 147:30b64687e01f 14386 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
<> 147:30b64687e01f 14387 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
<> 147:30b64687e01f 14388
<> 147:30b64687e01f 14389 /* EndPoint REGister MASK (no toggle fields) */
<> 147:30b64687e01f 14390 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
<> 147:30b64687e01f 14391 /*!< EP_TYPE[1:0] EndPoint TYPE */
<> 147:30b64687e01f 14392 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
<> 147:30b64687e01f 14393 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
<> 147:30b64687e01f 14394 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
<> 147:30b64687e01f 14395 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
<> 147:30b64687e01f 14396 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
<> 147:30b64687e01f 14397 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
<> 147:30b64687e01f 14398
<> 147:30b64687e01f 14399 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
<> 147:30b64687e01f 14400 /*!< STAT_TX[1:0] STATus for TX transfer */
<> 147:30b64687e01f 14401 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
<> 147:30b64687e01f 14402 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
<> 147:30b64687e01f 14403 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
<> 147:30b64687e01f 14404 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
<> 147:30b64687e01f 14405 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
<> 147:30b64687e01f 14406 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
<> 147:30b64687e01f 14407 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
<> 147:30b64687e01f 14408 /*!< STAT_RX[1:0] STATus for RX transfer */
<> 147:30b64687e01f 14409 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
<> 147:30b64687e01f 14410 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
<> 147:30b64687e01f 14411 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
<> 147:30b64687e01f 14412 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
<> 147:30b64687e01f 14413 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 147:30b64687e01f 14414 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 147:30b64687e01f 14415 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
<> 147:30b64687e01f 14416
<> 147:30b64687e01f 14417 /******************************************************************************/
<> 147:30b64687e01f 14418 /* */
<> 147:30b64687e01f 14419 /* Window WATCHDOG */
<> 147:30b64687e01f 14420 /* */
<> 147:30b64687e01f 14421 /******************************************************************************/
<> 147:30b64687e01f 14422 /******************* Bit definition for WWDG_CR register ********************/
<> 147:30b64687e01f 14423 #define WWDG_CR_T_Pos (0U)
<> 147:30b64687e01f 14424 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
<> 147:30b64687e01f 14425 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 147:30b64687e01f 14426 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 14427 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 14428 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 14429 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 14430 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 14431 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 14432 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 14433
<> 147:30b64687e01f 14434 /* Legacy defines */
<> 147:30b64687e01f 14435 #define WWDG_CR_T0 WWDG_CR_T_0
<> 147:30b64687e01f 14436 #define WWDG_CR_T1 WWDG_CR_T_1
<> 147:30b64687e01f 14437 #define WWDG_CR_T2 WWDG_CR_T_2
<> 147:30b64687e01f 14438 #define WWDG_CR_T3 WWDG_CR_T_3
<> 147:30b64687e01f 14439 #define WWDG_CR_T4 WWDG_CR_T_4
<> 147:30b64687e01f 14440 #define WWDG_CR_T5 WWDG_CR_T_5
<> 147:30b64687e01f 14441 #define WWDG_CR_T6 WWDG_CR_T_6
<> 147:30b64687e01f 14442
<> 147:30b64687e01f 14443 #define WWDG_CR_WDGA_Pos (7U)
<> 147:30b64687e01f 14444 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 14445 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
<> 147:30b64687e01f 14446
<> 147:30b64687e01f 14447 /******************* Bit definition for WWDG_CFR register *******************/
<> 147:30b64687e01f 14448 #define WWDG_CFR_W_Pos (0U)
<> 147:30b64687e01f 14449 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
<> 147:30b64687e01f 14450 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
<> 147:30b64687e01f 14451 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 14452 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
<> 147:30b64687e01f 14453 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
<> 147:30b64687e01f 14454 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
<> 147:30b64687e01f 14455 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
<> 147:30b64687e01f 14456 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
<> 147:30b64687e01f 14457 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
<> 147:30b64687e01f 14458
<> 147:30b64687e01f 14459 /* Legacy defines */
<> 147:30b64687e01f 14460 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 147:30b64687e01f 14461 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 147:30b64687e01f 14462 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 147:30b64687e01f 14463 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 147:30b64687e01f 14464 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 147:30b64687e01f 14465 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 147:30b64687e01f 14466 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 147:30b64687e01f 14467
<> 147:30b64687e01f 14468 #define WWDG_CFR_WDGTB_Pos (7U)
<> 147:30b64687e01f 14469 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
<> 147:30b64687e01f 14470 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
<> 147:30b64687e01f 14471 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
<> 147:30b64687e01f 14472 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
<> 147:30b64687e01f 14473
<> 147:30b64687e01f 14474 /* Legacy defines */
<> 147:30b64687e01f 14475 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 147:30b64687e01f 14476 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 147:30b64687e01f 14477
<> 147:30b64687e01f 14478 #define WWDG_CFR_EWI_Pos (9U)
<> 147:30b64687e01f 14479 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
<> 147:30b64687e01f 14480 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
<> 147:30b64687e01f 14481
<> 147:30b64687e01f 14482 /******************* Bit definition for WWDG_SR register ********************/
<> 147:30b64687e01f 14483 #define WWDG_SR_EWIF_Pos (0U)
<> 147:30b64687e01f 14484 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
<> 147:30b64687e01f 14485 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
<> 147:30b64687e01f 14486
<> 147:30b64687e01f 14487 /**
<> 147:30b64687e01f 14488 * @}
<> 147:30b64687e01f 14489 */
<> 147:30b64687e01f 14490
<> 147:30b64687e01f 14491 /**
<> 147:30b64687e01f 14492 * @}
<> 147:30b64687e01f 14493 */
<> 147:30b64687e01f 14494
<> 147:30b64687e01f 14495 /** @addtogroup Exported_macros
<> 147:30b64687e01f 14496 * @{
<> 147:30b64687e01f 14497 */
<> 147:30b64687e01f 14498
<> 147:30b64687e01f 14499 /****************************** ADC Instances *********************************/
<> 147:30b64687e01f 14500 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
<> 147:30b64687e01f 14501 ((INSTANCE) == ADC2) || \
<> 147:30b64687e01f 14502 ((INSTANCE) == ADC3) || \
<> 147:30b64687e01f 14503 ((INSTANCE) == ADC4))
<> 147:30b64687e01f 14504
<> 147:30b64687e01f 14505 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
<> 147:30b64687e01f 14506 ((INSTANCE) == ADC3))
<> 147:30b64687e01f 14507
<> 147:30b64687e01f 14508 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
<> 147:30b64687e01f 14509 ((INSTANCE) == ADC34_COMMON))
<> 147:30b64687e01f 14510
<> 147:30b64687e01f 14511 /****************************** CAN Instances *********************************/
<> 147:30b64687e01f 14512 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
<> 147:30b64687e01f 14513
<> 147:30b64687e01f 14514 /****************************** COMP Instances ********************************/
<> 147:30b64687e01f 14515 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
<> 147:30b64687e01f 14516 ((INSTANCE) == COMP2) || \
<> 147:30b64687e01f 14517 ((INSTANCE) == COMP3) || \
<> 147:30b64687e01f 14518 ((INSTANCE) == COMP4) || \
<> 147:30b64687e01f 14519 ((INSTANCE) == COMP5) || \
<> 147:30b64687e01f 14520 ((INSTANCE) == COMP6) || \
<> 147:30b64687e01f 14521 ((INSTANCE) == COMP7))
<> 147:30b64687e01f 14522
<> 147:30b64687e01f 14523 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (((COMMON_INSTANCE) == COMP12_COMMON) || \
<> 147:30b64687e01f 14524 ((COMMON_INSTANCE) == COMP34_COMMON) || \
<> 147:30b64687e01f 14525 ((COMMON_INSTANCE) == COMP56_COMMON))
<> 147:30b64687e01f 14526
<> 147:30b64687e01f 14527
<> 147:30b64687e01f 14528 /******************** COMP Instances with window mode capability **************/
<> 147:30b64687e01f 14529 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
<> 147:30b64687e01f 14530 ((INSTANCE) == COMP4) || \
<> 147:30b64687e01f 14531 ((INSTANCE) == COMP6))
<> 147:30b64687e01f 14532
<> 147:30b64687e01f 14533 /****************************** CRC Instances *********************************/
<> 147:30b64687e01f 14534 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 147:30b64687e01f 14535
<> 147:30b64687e01f 14536 /****************************** DAC Instances *********************************/
<> 147:30b64687e01f 14537 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
<> 147:30b64687e01f 14538
<> 147:30b64687e01f 14539 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
<> 147:30b64687e01f 14540 ((((INSTANCE) == DAC1) && \
<> 147:30b64687e01f 14541 (((CHANNEL) == DAC_CHANNEL_1) || \
<> 147:30b64687e01f 14542 ((CHANNEL) == DAC_CHANNEL_2))))
<> 147:30b64687e01f 14543
<> 147:30b64687e01f 14544 /****************************** DMA Instances *********************************/
<> 147:30b64687e01f 14545 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 147:30b64687e01f 14546 ((INSTANCE) == DMA1_Channel2) || \
<> 147:30b64687e01f 14547 ((INSTANCE) == DMA1_Channel3) || \
<> 147:30b64687e01f 14548 ((INSTANCE) == DMA1_Channel4) || \
<> 147:30b64687e01f 14549 ((INSTANCE) == DMA1_Channel5) || \
<> 147:30b64687e01f 14550 ((INSTANCE) == DMA1_Channel6) || \
<> 147:30b64687e01f 14551 ((INSTANCE) == DMA1_Channel7) || \
<> 147:30b64687e01f 14552 ((INSTANCE) == DMA2_Channel1) || \
<> 147:30b64687e01f 14553 ((INSTANCE) == DMA2_Channel2) || \
<> 147:30b64687e01f 14554 ((INSTANCE) == DMA2_Channel3) || \
<> 147:30b64687e01f 14555 ((INSTANCE) == DMA2_Channel4) || \
<> 147:30b64687e01f 14556 ((INSTANCE) == DMA2_Channel5))
<> 147:30b64687e01f 14557
<> 147:30b64687e01f 14558 /****************************** GPIO Instances ********************************/
<> 147:30b64687e01f 14559 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 147:30b64687e01f 14560 ((INSTANCE) == GPIOB) || \
<> 147:30b64687e01f 14561 ((INSTANCE) == GPIOC) || \
<> 147:30b64687e01f 14562 ((INSTANCE) == GPIOD) || \
<> 147:30b64687e01f 14563 ((INSTANCE) == GPIOE) || \
<> 147:30b64687e01f 14564 ((INSTANCE) == GPIOF) || \
<> 147:30b64687e01f 14565 ((INSTANCE) == GPIOG) || \
<> 147:30b64687e01f 14566 ((INSTANCE) == GPIOH))
<> 147:30b64687e01f 14567
<> 147:30b64687e01f 14568 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 147:30b64687e01f 14569 ((INSTANCE) == GPIOB) || \
<> 147:30b64687e01f 14570 ((INSTANCE) == GPIOC) || \
<> 147:30b64687e01f 14571 ((INSTANCE) == GPIOD) || \
<> 147:30b64687e01f 14572 ((INSTANCE) == GPIOE) || \
<> 147:30b64687e01f 14573 ((INSTANCE) == GPIOF) || \
<> 147:30b64687e01f 14574 ((INSTANCE) == GPIOG) || \
<> 147:30b64687e01f 14575 ((INSTANCE) == GPIOH))
<> 147:30b64687e01f 14576
<> 147:30b64687e01f 14577 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 147:30b64687e01f 14578 ((INSTANCE) == GPIOB) || \
<> 147:30b64687e01f 14579 ((INSTANCE) == GPIOC) || \
<> 147:30b64687e01f 14580 ((INSTANCE) == GPIOD) || \
<> 147:30b64687e01f 14581 ((INSTANCE) == GPIOE) || \
<> 147:30b64687e01f 14582 ((INSTANCE) == GPIOF) || \
<> 147:30b64687e01f 14583 ((INSTANCE) == GPIOG) || \
<> 147:30b64687e01f 14584 ((INSTANCE) == GPIOH))
<> 147:30b64687e01f 14585
<> 147:30b64687e01f 14586 /****************************** I2C Instances *********************************/
<> 147:30b64687e01f 14587 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 147:30b64687e01f 14588 ((INSTANCE) == I2C2) || \
<> 147:30b64687e01f 14589 ((INSTANCE) == I2C3))
<> 147:30b64687e01f 14590
<> 147:30b64687e01f 14591 /****************** I2C Instances : wakeup capability from stop modes *********/
<> 147:30b64687e01f 14592 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
<> 147:30b64687e01f 14593
<> 147:30b64687e01f 14594 /****************************** I2S Instances *********************************/
<> 147:30b64687e01f 14595 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
<> 147:30b64687e01f 14596 ((INSTANCE) == SPI3))
<> 147:30b64687e01f 14597 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext) || \
<> 147:30b64687e01f 14598 ((INSTANCE) == I2S3ext))
<> 147:30b64687e01f 14599
<> 147:30b64687e01f 14600 /****************************** OPAMP Instances *******************************/
<> 147:30b64687e01f 14601 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
<> 147:30b64687e01f 14602 ((INSTANCE) == OPAMP2) || \
<> 147:30b64687e01f 14603 ((INSTANCE) == OPAMP3) || \
<> 147:30b64687e01f 14604 ((INSTANCE) == OPAMP4))
<> 147:30b64687e01f 14605
<> 147:30b64687e01f 14606 /****************************** IWDG Instances ********************************/
<> 147:30b64687e01f 14607 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 147:30b64687e01f 14608
<> 147:30b64687e01f 14609 /****************************** RTC Instances *********************************/
<> 147:30b64687e01f 14610 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 147:30b64687e01f 14611
<> 147:30b64687e01f 14612 /****************************** SMBUS Instances *******************************/
<> 147:30b64687e01f 14613 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 147:30b64687e01f 14614 ((INSTANCE) == I2C2) || \
<> 147:30b64687e01f 14615 ((INSTANCE) == I2C3))
<> 147:30b64687e01f 14616
<> 147:30b64687e01f 14617 /****************************** SPI Instances *********************************/
<> 147:30b64687e01f 14618 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 147:30b64687e01f 14619 ((INSTANCE) == SPI2) || \
<> 147:30b64687e01f 14620 ((INSTANCE) == SPI3) || \
<> 147:30b64687e01f 14621 ((INSTANCE) == SPI4))
<> 147:30b64687e01f 14622
<> 147:30b64687e01f 14623 /******************* TIM Instances : All supported instances ******************/
<> 147:30b64687e01f 14624 #define IS_TIM_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14625 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14626 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14627 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14628 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14629 ((INSTANCE) == TIM6) || \
<> 147:30b64687e01f 14630 ((INSTANCE) == TIM7) || \
<> 147:30b64687e01f 14631 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14632 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14633 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14634 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14635 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14636
<> 147:30b64687e01f 14637 /******************* TIM Instances : at least 1 capture/compare channel *******/
<> 147:30b64687e01f 14638 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14639 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14640 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14641 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14642 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14643 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14644 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14645 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14646 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14647 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14648
<> 147:30b64687e01f 14649 /****************** TIM Instances : at least 2 capture/compare channels *******/
<> 147:30b64687e01f 14650 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14651 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14652 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14653 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14654 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14655 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14656 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14657 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14658
<> 147:30b64687e01f 14659 /****************** TIM Instances : at least 3 capture/compare channels *******/
<> 147:30b64687e01f 14660 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14661 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14662 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14663 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14664 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14665 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14666 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14667
<> 147:30b64687e01f 14668 /****************** TIM Instances : at least 4 capture/compare channels *******/
<> 147:30b64687e01f 14669 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14670 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14671 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14672 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14673 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14674 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14675 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14676
<> 147:30b64687e01f 14677 /****************** TIM Instances : at least 5 capture/compare channels *******/
<> 147:30b64687e01f 14678 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14679 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14680 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14681 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14682
<> 147:30b64687e01f 14683 /****************** TIM Instances : at least 6 capture/compare channels *******/
<> 147:30b64687e01f 14684 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14685 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14686 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14687 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14688
<> 147:30b64687e01f 14689 /************************** TIM Instances : Advanced-control timers ***********/
<> 147:30b64687e01f 14690
<> 147:30b64687e01f 14691 /****************** TIM Instances : supporting clock selection ****************/
<> 147:30b64687e01f 14692 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14693 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14694 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14695 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14696 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14697 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14698 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14699 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14700
<> 147:30b64687e01f 14701 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
<> 147:30b64687e01f 14702 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14703 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14704 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14705 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14706 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14707 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14708 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14709
<> 147:30b64687e01f 14710 /****************** TIM Instances : supporting external clock mode 2 **********/
<> 147:30b64687e01f 14711 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14712 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14713 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14714 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14715 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14716 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14717 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14718
<> 147:30b64687e01f 14719 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
<> 147:30b64687e01f 14720 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14721 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14722 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14723 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14724 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14725 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14726 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14727 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14728
<> 147:30b64687e01f 14729 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
<> 147:30b64687e01f 14730 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14731 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14732 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14733 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14734 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14735 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14736 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14737 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14738
<> 147:30b64687e01f 14739 /****************** TIM Instances : supporting OCxREF clear *******************/
<> 147:30b64687e01f 14740 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14741 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14742 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14743 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14744 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14745 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14746 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14747
<> 147:30b64687e01f 14748 /****************** TIM Instances : supporting encoder interface **************/
<> 147:30b64687e01f 14749 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14750 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14751 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14752 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14753 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14754 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14755 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14756
<> 147:30b64687e01f 14757 /****************** TIM Instances : supporting Hall interface *****************/
<> 147:30b64687e01f 14758 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14759 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14760 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14761 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14762
<> 147:30b64687e01f 14763 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14764 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14765 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14766 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14767
<> 147:30b64687e01f 14768 /**************** TIM Instances : external trigger input available ************/
<> 147:30b64687e01f 14769 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14770 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14771 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14772 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14773 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14774 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14775
<> 147:30b64687e01f 14776 /****************** TIM Instances : supporting input XOR function *************/
<> 147:30b64687e01f 14777 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14778 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14779 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14780 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14781 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14782 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14783 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14784 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14785
<> 147:30b64687e01f 14786 /****************** TIM Instances : supporting master mode ********************/
<> 147:30b64687e01f 14787 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14788 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14789 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14790 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14791 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14792 ((INSTANCE) == TIM6) || \
<> 147:30b64687e01f 14793 ((INSTANCE) == TIM7) || \
<> 147:30b64687e01f 14794 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14795 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14796 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14797
<> 147:30b64687e01f 14798 /****************** TIM Instances : supporting slave mode *********************/
<> 147:30b64687e01f 14799 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14800 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14801 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14802 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14803 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14804 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14805 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14806 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14807
<> 147:30b64687e01f 14808 /****************** TIM Instances : supporting synchronization ****************/
<> 147:30b64687e01f 14809 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14810 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14811 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14812 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14813 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14814 ((INSTANCE) == TIM6) || \
<> 147:30b64687e01f 14815 ((INSTANCE) == TIM7) || \
<> 147:30b64687e01f 14816 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14817 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14818 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14819
<> 147:30b64687e01f 14820 /****************** TIM Instances : supporting 32 bits counter ****************/
<> 147:30b64687e01f 14821 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14822 ((INSTANCE) == TIM2)
<> 147:30b64687e01f 14823
<> 147:30b64687e01f 14824 /****************** TIM Instances : supporting DMA burst **********************/
<> 147:30b64687e01f 14825 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14826 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14827 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14828 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14829 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14830 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14831 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14832 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14833 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14834 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14835
<> 147:30b64687e01f 14836 /****************** TIM Instances : supporting the break function *************/
<> 147:30b64687e01f 14837 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14838 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14839 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14840 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14841 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14842 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14843 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14844
<> 147:30b64687e01f 14845 /****************** TIM Instances : supporting input/output channel(s) ********/
<> 147:30b64687e01f 14846 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 147:30b64687e01f 14847 ((((INSTANCE) == TIM1) && \
<> 147:30b64687e01f 14848 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14849 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14850 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 14851 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 147:30b64687e01f 14852 ((CHANNEL) == TIM_CHANNEL_5) || \
<> 147:30b64687e01f 14853 ((CHANNEL) == TIM_CHANNEL_6))) \
<> 147:30b64687e01f 14854 || \
<> 147:30b64687e01f 14855 (((INSTANCE) == TIM2) && \
<> 147:30b64687e01f 14856 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14857 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14858 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 14859 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 14860 || \
<> 147:30b64687e01f 14861 (((INSTANCE) == TIM3) && \
<> 147:30b64687e01f 14862 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14863 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14864 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 14865 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 14866 || \
<> 147:30b64687e01f 14867 (((INSTANCE) == TIM4) && \
<> 147:30b64687e01f 14868 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14869 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14870 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 14871 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 14872 || \
<> 147:30b64687e01f 14873 (((INSTANCE) == TIM8) && \
<> 147:30b64687e01f 14874 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14875 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14876 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 14877 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 147:30b64687e01f 14878 ((CHANNEL) == TIM_CHANNEL_5) || \
<> 147:30b64687e01f 14879 ((CHANNEL) == TIM_CHANNEL_6))) \
<> 147:30b64687e01f 14880 || \
<> 147:30b64687e01f 14881 (((INSTANCE) == TIM15) && \
<> 147:30b64687e01f 14882 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14883 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 147:30b64687e01f 14884 || \
<> 147:30b64687e01f 14885 (((INSTANCE) == TIM16) && \
<> 147:30b64687e01f 14886 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 147:30b64687e01f 14887 || \
<> 147:30b64687e01f 14888 (((INSTANCE) == TIM17) && \
<> 147:30b64687e01f 14889 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 147:30b64687e01f 14890 || \
<> 147:30b64687e01f 14891 (((INSTANCE) == TIM20) && \
<> 147:30b64687e01f 14892 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14893 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14894 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 14895 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 147:30b64687e01f 14896 ((CHANNEL) == TIM_CHANNEL_5) || \
<> 147:30b64687e01f 14897 ((CHANNEL) == TIM_CHANNEL_6))))
<> 147:30b64687e01f 14898
<> 147:30b64687e01f 14899 /****************** TIM Instances : supporting complementary output(s) ********/
<> 147:30b64687e01f 14900 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 147:30b64687e01f 14901 ((((INSTANCE) == TIM1) && \
<> 147:30b64687e01f 14902 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14903 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14904 ((CHANNEL) == TIM_CHANNEL_3))) \
<> 147:30b64687e01f 14905 || \
<> 147:30b64687e01f 14906 (((INSTANCE) == TIM8) && \
<> 147:30b64687e01f 14907 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14908 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14909 ((CHANNEL) == TIM_CHANNEL_3))) \
<> 147:30b64687e01f 14910 || \
<> 147:30b64687e01f 14911 (((INSTANCE) == TIM15) && \
<> 147:30b64687e01f 14912 ((CHANNEL) == TIM_CHANNEL_1)) \
<> 147:30b64687e01f 14913 || \
<> 147:30b64687e01f 14914 (((INSTANCE) == TIM16) && \
<> 147:30b64687e01f 14915 ((CHANNEL) == TIM_CHANNEL_1)) \
<> 147:30b64687e01f 14916 || \
<> 147:30b64687e01f 14917 (((INSTANCE) == TIM17) && \
<> 147:30b64687e01f 14918 ((CHANNEL) == TIM_CHANNEL_1)) \
<> 147:30b64687e01f 14919 || \
<> 147:30b64687e01f 14920 (((INSTANCE) == TIM20) && \
<> 147:30b64687e01f 14921 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 14922 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 14923 ((CHANNEL) == TIM_CHANNEL_3))))
<> 147:30b64687e01f 14924
<> 147:30b64687e01f 14925 /****************** TIM Instances : supporting counting mode selection ********/
<> 147:30b64687e01f 14926 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14927 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14928 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14929 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14930 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14931 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14932 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14933
<> 147:30b64687e01f 14934 /****************** TIM Instances : supporting repetition counter *************/
<> 147:30b64687e01f 14935 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14936 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14937 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14938 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14939 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14940 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14941 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14942
<> 147:30b64687e01f 14943 /****************** TIM Instances : supporting clock division *****************/
<> 147:30b64687e01f 14944 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14945 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14946 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14947 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14948 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14949 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14950 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14951 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14952 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14953 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14954
<> 147:30b64687e01f 14955 /****************** TIM Instances : supporting 2 break inputs *****************/
<> 147:30b64687e01f 14956 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14957 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14958 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14959 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14960
<> 147:30b64687e01f 14961 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
<> 147:30b64687e01f 14962 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14963 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14964 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14965 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14966
<> 147:30b64687e01f 14967 /****************** TIM Instances : supporting DMA generation on Update events*/
<> 147:30b64687e01f 14968 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14969 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14970 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14971 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14972 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14973 ((INSTANCE) == TIM6) || \
<> 147:30b64687e01f 14974 ((INSTANCE) == TIM7) || \
<> 147:30b64687e01f 14975 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14976 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14977 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14978 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14979 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14980
<> 147:30b64687e01f 14981 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
<> 147:30b64687e01f 14982 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14983 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14984 ((INSTANCE) == TIM2) || \
<> 147:30b64687e01f 14985 ((INSTANCE) == TIM3) || \
<> 147:30b64687e01f 14986 ((INSTANCE) == TIM4) || \
<> 147:30b64687e01f 14987 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14988 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14989 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14990 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 14991 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 14992
<> 147:30b64687e01f 14993 /****************** TIM Instances : supporting commutation event generation ***/
<> 147:30b64687e01f 14994 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 14995 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 14996 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 14997 ((INSTANCE) == TIM15) || \
<> 147:30b64687e01f 14998 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 14999 ((INSTANCE) == TIM17) || \
<> 147:30b64687e01f 15000 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 15001
<> 147:30b64687e01f 15002 /****************** TIM Instances : supporting remapping capability ***********/
<> 147:30b64687e01f 15003 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
<> 147:30b64687e01f 15004 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 15005 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 15006 ((INSTANCE) == TIM16) || \
<> 147:30b64687e01f 15007 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 15008
<> 147:30b64687e01f 15009 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
<> 147:30b64687e01f 15010 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
<> 147:30b64687e01f 15011 (((INSTANCE) == TIM1) || \
<> 147:30b64687e01f 15012 ((INSTANCE) == TIM8) || \
<> 147:30b64687e01f 15013 ((INSTANCE) == TIM20))
<> 147:30b64687e01f 15014
<> 147:30b64687e01f 15015 /****************************** TSC Instances *********************************/
<> 147:30b64687e01f 15016 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
<> 147:30b64687e01f 15017
<> 147:30b64687e01f 15018 /******************** USART Instances : Synchronous mode **********************/
<> 147:30b64687e01f 15019 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15020 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15021 ((INSTANCE) == USART3))
<> 147:30b64687e01f 15022
<> 147:30b64687e01f 15023 /****************** USART Instances : Auto Baud Rate detection ****************/
<> 147:30b64687e01f 15024 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15025 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15026 ((INSTANCE) == USART3))
<> 147:30b64687e01f 15027
<> 147:30b64687e01f 15028 /******************** UART Instances : Asynchronous mode **********************/
<> 147:30b64687e01f 15029 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15030 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15031 ((INSTANCE) == USART3) || \
<> 147:30b64687e01f 15032 ((INSTANCE) == UART4) || \
<> 147:30b64687e01f 15033 ((INSTANCE) == UART5))
<> 147:30b64687e01f 15034
<> 147:30b64687e01f 15035 /******************** UART Instances : Half-Duplex mode **********************/
<> 147:30b64687e01f 15036 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15037 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15038 ((INSTANCE) == USART3) || \
<> 147:30b64687e01f 15039 ((INSTANCE) == UART4) || \
<> 147:30b64687e01f 15040 ((INSTANCE) == UART5))
<> 147:30b64687e01f 15041
<> 147:30b64687e01f 15042 /******************** UART Instances : LIN mode **********************/
<> 147:30b64687e01f 15043 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15044 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15045 ((INSTANCE) == USART3) || \
<> 147:30b64687e01f 15046 ((INSTANCE) == UART4) || \
<> 147:30b64687e01f 15047 ((INSTANCE) == UART5))
<> 147:30b64687e01f 15048
<> 147:30b64687e01f 15049 /******************** UART Instances : Wake-up from Stop mode **********************/
<> 147:30b64687e01f 15050 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15051 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15052 ((INSTANCE) == USART3) || \
<> 147:30b64687e01f 15053 ((INSTANCE) == UART4) || \
<> 147:30b64687e01f 15054 ((INSTANCE) == UART5))
<> 147:30b64687e01f 15055
<> 147:30b64687e01f 15056 /****************** UART Instances : Hardware Flow control ********************/
<> 147:30b64687e01f 15057 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15058 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15059 ((INSTANCE) == USART3))
<> 147:30b64687e01f 15060
<> 147:30b64687e01f 15061 /****************** UART Instances : Auto Baud Rate detection *****************/
<> 147:30b64687e01f 15062 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15063 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15064 ((INSTANCE) == USART3))
<> 147:30b64687e01f 15065
<> 147:30b64687e01f 15066 /****************** UART Instances : Driver Enable ****************************/
<> 147:30b64687e01f 15067 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15068 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15069 ((INSTANCE) == USART3))
<> 147:30b64687e01f 15070
<> 147:30b64687e01f 15071 /********************* UART Instances : Smard card mode ***********************/
<> 147:30b64687e01f 15072 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15073 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15074 ((INSTANCE) == USART3))
<> 147:30b64687e01f 15075
<> 147:30b64687e01f 15076 /*********************** UART Instances : IRDA mode ***************************/
<> 147:30b64687e01f 15077 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 147:30b64687e01f 15078 ((INSTANCE) == USART2) || \
<> 147:30b64687e01f 15079 ((INSTANCE) == USART3) || \
<> 147:30b64687e01f 15080 ((INSTANCE) == UART4) || \
<> 147:30b64687e01f 15081 ((INSTANCE) == UART5))
<> 147:30b64687e01f 15082
<> 147:30b64687e01f 15083 /******************** UART Instances : Support of continuous communication using DMA ****/
<> 147:30b64687e01f 15084 #define IS_UART_DMA_INSTANCE(INSTANCE) (1)
<> 147:30b64687e01f 15085
<> 147:30b64687e01f 15086 /****************************** USB Instances *********************************/
<> 147:30b64687e01f 15087 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
<> 147:30b64687e01f 15088
<> 147:30b64687e01f 15089 /****************************** WWDG Instances ********************************/
<> 147:30b64687e01f 15090 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 147:30b64687e01f 15091
<> 147:30b64687e01f 15092 /**
<> 147:30b64687e01f 15093 * @}
<> 147:30b64687e01f 15094 */
<> 147:30b64687e01f 15095
<> 147:30b64687e01f 15096
<> 147:30b64687e01f 15097 /******************************************************************************/
<> 147:30b64687e01f 15098 /* For a painless codes migration between the STM32F3xx device product */
<> 147:30b64687e01f 15099 /* lines, the aliases defined below are put in place to overcome the */
<> 147:30b64687e01f 15100 /* differences in the interrupt handlers and IRQn definitions. */
<> 147:30b64687e01f 15101 /* No need to update developed interrupt code when moving across */
<> 147:30b64687e01f 15102 /* product lines within the same STM32F3 Family */
<> 147:30b64687e01f 15103 /******************************************************************************/
<> 147:30b64687e01f 15104
<> 147:30b64687e01f 15105 /* Aliases for __IRQn */
<> 147:30b64687e01f 15106 #define ADC1_IRQn ADC1_2_IRQn
<> 147:30b64687e01f 15107 #define SDADC1_IRQn ADC4_IRQn
<> 147:30b64687e01f 15108 #define COMP1_2_IRQn COMP1_2_3_IRQn
<> 147:30b64687e01f 15109 #define COMP2_IRQn COMP1_2_3_IRQn
<> 147:30b64687e01f 15110 #define COMP_IRQn COMP1_2_3_IRQn
<> 147:30b64687e01f 15111 #define COMP4_6_IRQn COMP4_5_6_IRQn
<> 147:30b64687e01f 15112 #define HRTIM1_FLT_IRQn I2C3_ER_IRQn
<> 147:30b64687e01f 15113 #define HRTIM1_TIME_IRQn I2C3_EV_IRQn
<> 147:30b64687e01f 15114 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
<> 147:30b64687e01f 15115 #define TIM18_DAC2_IRQn TIM1_CC_IRQn
<> 147:30b64687e01f 15116 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
<> 147:30b64687e01f 15117 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
<> 147:30b64687e01f 15118 #define TIM19_IRQn TIM20_UP_IRQn
<> 147:30b64687e01f 15119 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn
<> 147:30b64687e01f 15120 #define TIM7_DAC2_IRQn TIM7_IRQn
<> 147:30b64687e01f 15121 #define TIM12_IRQn TIM8_BRK_IRQn
<> 147:30b64687e01f 15122 #define TIM14_IRQn TIM8_TRG_COM_IRQn
<> 147:30b64687e01f 15123 #define TIM13_IRQn TIM8_UP_IRQn
<> 147:30b64687e01f 15124 #define CEC_IRQn USBWakeUp_IRQn
<> 147:30b64687e01f 15125 #define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
<> 147:30b64687e01f 15126 #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
<> 147:30b64687e01f 15127 #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
<> 147:30b64687e01f 15128
<> 147:30b64687e01f 15129
<> 147:30b64687e01f 15130 /* Aliases for __IRQHandler */
<> 147:30b64687e01f 15131 #define ADC1_IRQHandler ADC1_2_IRQHandler
<> 147:30b64687e01f 15132 #define SDADC1_IRQHandler ADC4_IRQHandler
<> 147:30b64687e01f 15133 #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
<> 147:30b64687e01f 15134 #define COMP2_IRQHandler COMP1_2_3_IRQHandler
<> 147:30b64687e01f 15135 #define COMP_IRQHandler COMP1_2_3_IRQHandler
<> 147:30b64687e01f 15136 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
<> 147:30b64687e01f 15137 #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
<> 147:30b64687e01f 15138 #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
<> 147:30b64687e01f 15139 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
<> 147:30b64687e01f 15140 #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
<> 147:30b64687e01f 15141 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
<> 147:30b64687e01f 15142 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
<> 147:30b64687e01f 15143 #define TIM19_IRQHandler TIM20_UP_IRQHandler
<> 147:30b64687e01f 15144 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
<> 147:30b64687e01f 15145 #define TIM7_DAC2_IRQHandler TIM7_IRQHandler
<> 147:30b64687e01f 15146 #define TIM12_IRQHandler TIM8_BRK_IRQHandler
<> 147:30b64687e01f 15147 #define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
<> 147:30b64687e01f 15148 #define TIM13_IRQHandler TIM8_UP_IRQHandler
<> 147:30b64687e01f 15149 #define CEC_IRQHandler USBWakeUp_IRQHandler
<> 147:30b64687e01f 15150 #define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
<> 147:30b64687e01f 15151 #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
<> 147:30b64687e01f 15152 #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
<> 147:30b64687e01f 15153
<> 147:30b64687e01f 15154
<> 147:30b64687e01f 15155 #ifdef __cplusplus
<> 147:30b64687e01f 15156 }
<> 147:30b64687e01f 15157 #endif /* __cplusplus */
<> 147:30b64687e01f 15158
<> 147:30b64687e01f 15159 #endif /* __STM32F303xE_H */
<> 147:30b64687e01f 15160
<> 147:30b64687e01f 15161 /**
<> 147:30b64687e01f 15162 * @}
<> 147:30b64687e01f 15163 */
<> 147:30b64687e01f 15164
<> 147:30b64687e01f 15165 /**
<> 147:30b64687e01f 15166 * @}
<> 147:30b64687e01f 15167 */
<> 147:30b64687e01f 15168
<> 147:30b64687e01f 15169 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/