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Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c@184:08ed48f1de7f, 2018-04-19 (annotated)

Committer:: AnnaBridge
Date:: Thu Apr 19 17:12:19 2018 +0100
Revision:: 184:08ed48f1de7f
Parent:: 182:a56a73fd2a6f
Child:: 187:0387e8f68319

mbed-dev library. Release version 161

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:7d866c31b3c5	1	/* mbed Microcontroller Library
AnnaBridge	172:7d866c31b3c5	2	* Copyright (c) 2015-2016 Nuvoton
AnnaBridge	172:7d866c31b3c5	3	*
AnnaBridge	172:7d866c31b3c5	4	* Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge	172:7d866c31b3c5	5	* you may not use this file except in compliance with the License.
AnnaBridge	172:7d866c31b3c5	6	* You may obtain a copy of the License at
AnnaBridge	172:7d866c31b3c5	7	*
AnnaBridge	172:7d866c31b3c5	8	* http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge	172:7d866c31b3c5	9	*
AnnaBridge	172:7d866c31b3c5	10	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	172:7d866c31b3c5	11	* distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge	172:7d866c31b3c5	12	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	172:7d866c31b3c5	13	* See the License for the specific language governing permissions and
AnnaBridge	172:7d866c31b3c5	14	* limitations under the License.
AnnaBridge	172:7d866c31b3c5	15	*/
AnnaBridge	172:7d866c31b3c5	16
AnnaBridge	172:7d866c31b3c5	17	#include "us_ticker_api.h"
AnnaBridge	172:7d866c31b3c5	18	#include "sleep_api.h"
AnnaBridge	172:7d866c31b3c5	19	#include "mbed_assert.h"
AnnaBridge	172:7d866c31b3c5	20	#include "nu_modutil.h"
AnnaBridge	172:7d866c31b3c5	21	#include "nu_miscutil.h"
AnnaBridge	172:7d866c31b3c5	22
AnnaBridge	182:a56a73fd2a6f	23	/* Micro seconds per second */
AnnaBridge	182:a56a73fd2a6f	24	#define NU_US_PER_SEC 1000000
AnnaBridge	182:a56a73fd2a6f	25	/* Timer clock per us_ticker tick */
AnnaBridge	182:a56a73fd2a6f	26	#define NU_TMRCLK_PER_TICK 1
AnnaBridge	182:a56a73fd2a6f	27	/* Timer clock per second */
AnnaBridge	182:a56a73fd2a6f	28	#define NU_TMRCLK_PER_SEC (1000 * 1000)
AnnaBridge	182:a56a73fd2a6f	29	/* Timer max counter bit size */
AnnaBridge	182:a56a73fd2a6f	30	#define NU_TMR_MAXCNT_BITSIZE 24
AnnaBridge	182:a56a73fd2a6f	31	/* Timer max counter */
AnnaBridge	182:a56a73fd2a6f	32	#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
AnnaBridge	172:7d866c31b3c5	33
AnnaBridge	172:7d866c31b3c5	34	static void tmr0_vec(void);
AnnaBridge	172:7d866c31b3c5	35
AnnaBridge	182:a56a73fd2a6f	36	static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
AnnaBridge	172:7d866c31b3c5	37
AnnaBridge	182:a56a73fd2a6f	38	#define TIMER_MODINIT timer0_modinit
AnnaBridge	182:a56a73fd2a6f	39
AnnaBridge	182:a56a73fd2a6f	40	static int ticker_inited = 0;
AnnaBridge	172:7d866c31b3c5	41
AnnaBridge	172:7d866c31b3c5	42	#define TMR_CMP_MIN 2
AnnaBridge	172:7d866c31b3c5	43	#define TMR_CMP_MAX 0xFFFFFFu
AnnaBridge	172:7d866c31b3c5	44
AnnaBridge	172:7d866c31b3c5	45	void us_ticker_init(void)
AnnaBridge	172:7d866c31b3c5	46	{
AnnaBridge	182:a56a73fd2a6f	47	if (ticker_inited) {
AnnaBridge	172:7d866c31b3c5	48	return;
AnnaBridge	172:7d866c31b3c5	49	}
AnnaBridge	182:a56a73fd2a6f	50	ticker_inited = 1;
AnnaBridge	172:7d866c31b3c5	51
AnnaBridge	172:7d866c31b3c5	52	// Reset IP
AnnaBridge	182:a56a73fd2a6f	53	SYS_ResetModule(TIMER_MODINIT.rsetidx);
AnnaBridge	172:7d866c31b3c5	54
AnnaBridge	172:7d866c31b3c5	55	// Select IP clock source
AnnaBridge	182:a56a73fd2a6f	56	CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
AnnaBridge	182:a56a73fd2a6f	57
AnnaBridge	172:7d866c31b3c5	58	// Enable IP clock
AnnaBridge	182:a56a73fd2a6f	59	CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
AnnaBridge	172:7d866c31b3c5	60
AnnaBridge	184:08ed48f1de7f	61	TIMER_T timer_base = (TIMER_T ) NU_MODBASE(TIMER_MODINIT.modname);
AnnaBridge	184:08ed48f1de7f	62
AnnaBridge	172:7d866c31b3c5	63	// Timer for normal counter
AnnaBridge	184:08ed48f1de7f	64	uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
AnnaBridge	182:a56a73fd2a6f	65	uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
AnnaBridge	182:a56a73fd2a6f	66	MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
AnnaBridge	182:a56a73fd2a6f	67	MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
AnnaBridge	182:a56a73fd2a6f	68	uint32_t cmp_timer = TMR_CMP_MAX;
AnnaBridge	182:a56a73fd2a6f	69	MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
AnnaBridge	172:7d866c31b3c5	70	// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
AnnaBridge	184:08ed48f1de7f	71	timer_base->CTL = TIMER_CONTINUOUS_MODE \| prescale_timer/* \| TIMER_CTL_CNTDATEN_Msk*/;
AnnaBridge	184:08ed48f1de7f	72	timer_base->CMP = cmp_timer;
AnnaBridge	172:7d866c31b3c5	73
AnnaBridge	182:a56a73fd2a6f	74	NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
AnnaBridge	172:7d866c31b3c5	75
AnnaBridge	182:a56a73fd2a6f	76	NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
AnnaBridge	172:7d866c31b3c5	77
AnnaBridge	184:08ed48f1de7f	78	TIMER_EnableInt(timer_base);
AnnaBridge	184:08ed48f1de7f	79
AnnaBridge	184:08ed48f1de7f	80	TIMER_Start(timer_base);
AnnaBridge	184:08ed48f1de7f	81	/* Wait for timer to start counting and raise active flag */
AnnaBridge	184:08ed48f1de7f	82	while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
AnnaBridge	172:7d866c31b3c5	83	}
AnnaBridge	172:7d866c31b3c5	84
AnnaBridge	172:7d866c31b3c5	85	uint32_t us_ticker_read()
AnnaBridge	172:7d866c31b3c5	86	{
AnnaBridge	182:a56a73fd2a6f	87	if (! ticker_inited) {
AnnaBridge	172:7d866c31b3c5	88	us_ticker_init();
AnnaBridge	172:7d866c31b3c5	89	}
AnnaBridge	172:7d866c31b3c5	90
AnnaBridge	184:08ed48f1de7f	91	TIMER_T timer_base = (TIMER_T ) NU_MODBASE(TIMER_MODINIT.modname);
AnnaBridge	172:7d866c31b3c5	92
AnnaBridge	182:a56a73fd2a6f	93	return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
AnnaBridge	182:a56a73fd2a6f	94	}
AnnaBridge	172:7d866c31b3c5	95
AnnaBridge	182:a56a73fd2a6f	96	void us_ticker_set_interrupt(timestamp_t timestamp)
AnnaBridge	182:a56a73fd2a6f	97	{
AnnaBridge	182:a56a73fd2a6f	98	/* In continuous mode, counter will be reset to zero with the following sequence:
AnnaBridge	182:a56a73fd2a6f	99	* 1. Stop counting
AnnaBridge	182:a56a73fd2a6f	100	* 2. Configure new CMP value
AnnaBridge	182:a56a73fd2a6f	101	* 3. Restart counting
AnnaBridge	182:a56a73fd2a6f	102	*
AnnaBridge	182:a56a73fd2a6f	103	* This behavior is not what we want. To fix it, we could configure new CMP value
AnnaBridge	182:a56a73fd2a6f	104	* without stopping counting first.
AnnaBridge	182:a56a73fd2a6f	105	*/
AnnaBridge	184:08ed48f1de7f	106	TIMER_T timer_base = (TIMER_T ) NU_MODBASE(TIMER_MODINIT.modname);
AnnaBridge	172:7d866c31b3c5	107
AnnaBridge	182:a56a73fd2a6f	108	/* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
AnnaBridge	182:a56a73fd2a6f	109	* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
AnnaBridge	182:a56a73fd2a6f	110	uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
AnnaBridge	182:a56a73fd2a6f	111	cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
AnnaBridge	182:a56a73fd2a6f	112	timer_base->CMP = cmp_timer;
AnnaBridge	172:7d866c31b3c5	113	}
AnnaBridge	172:7d866c31b3c5	114
AnnaBridge	172:7d866c31b3c5	115	void us_ticker_disable_interrupt(void)
AnnaBridge	172:7d866c31b3c5	116	{
AnnaBridge	182:a56a73fd2a6f	117	TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
AnnaBridge	172:7d866c31b3c5	118	}
AnnaBridge	172:7d866c31b3c5	119
AnnaBridge	172:7d866c31b3c5	120	void us_ticker_clear_interrupt(void)
AnnaBridge	172:7d866c31b3c5	121	{
AnnaBridge	182:a56a73fd2a6f	122	TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
AnnaBridge	172:7d866c31b3c5	123	}
AnnaBridge	172:7d866c31b3c5	124
AnnaBridge	172:7d866c31b3c5	125	void us_ticker_fire_interrupt(void)
AnnaBridge	172:7d866c31b3c5	126	{
AnnaBridge	172:7d866c31b3c5	127	// NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
AnnaBridge	172:7d866c31b3c5	128	// This prevents a recursive loop under heavy load which can lead to a stack overflow.
AnnaBridge	182:a56a73fd2a6f	129	NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
AnnaBridge	182:a56a73fd2a6f	130	}
AnnaBridge	182:a56a73fd2a6f	131
AnnaBridge	182:a56a73fd2a6f	132	const ticker_info_t* us_ticker_get_info()
AnnaBridge	182:a56a73fd2a6f	133	{
AnnaBridge	182:a56a73fd2a6f	134	static const ticker_info_t info = {
AnnaBridge	182:a56a73fd2a6f	135	NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
AnnaBridge	182:a56a73fd2a6f	136	NU_TMR_MAXCNT_BITSIZE
AnnaBridge	182:a56a73fd2a6f	137	};
AnnaBridge	182:a56a73fd2a6f	138	return &info;
AnnaBridge	172:7d866c31b3c5	139	}
AnnaBridge	172:7d866c31b3c5	140
AnnaBridge	172:7d866c31b3c5	141	static void tmr0_vec(void)
AnnaBridge	172:7d866c31b3c5	142	{
AnnaBridge	182:a56a73fd2a6f	143	TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
AnnaBridge	182:a56a73fd2a6f	144
AnnaBridge	182:a56a73fd2a6f	145	// NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
AnnaBridge	182:a56a73fd2a6f	146	us_ticker_irq_handler();
AnnaBridge	172:7d866c31b3c5	147	}