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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h@187:0387e8f68319, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:40:20 2018 +0100
Revision:
187:0387e8f68319
Parent:
165:e614a9f1c9e2 
mbed-dev library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_can.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of CAN HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 165:e614a9f1c9e2 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 37 #ifndef __STM32F1xx_HAL_CAN_H
AnnaBridge 165:e614a9f1c9e2 38 #define __STM32F1xx_HAL_CAN_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
AnnaBridge 165:e614a9f1c9e2 43
<> 144:ef7eb2e8f9f7 44 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
<> 144:ef7eb2e8f9f7 45 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup CAN
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup CAN_Exported_Types CAN Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
AnnaBridge 165:e614a9f1c9e2 61 */
AnnaBridge 165:e614a9f1c9e2 62
AnnaBridge 165:e614a9f1c9e2 63 /**
AnnaBridge 165:e614a9f1c9e2 64 * @brief HAL State structures definition
AnnaBridge 165:e614a9f1c9e2 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
AnnaBridge 165:e614a9f1c9e2 68 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
AnnaBridge 165:e614a9f1c9e2 69 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
AnnaBridge 165:e614a9f1c9e2 70 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 71 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 72 HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 73 HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 74 HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 75 HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 76 HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 77 HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
AnnaBridge 165:e614a9f1c9e2 78 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
AnnaBridge 165:e614a9f1c9e2 79 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 }HAL_CAN_StateTypeDef;
<> 144:ef7eb2e8f9f7 82
AnnaBridge 165:e614a9f1c9e2 83 /**
<> 144:ef7eb2e8f9f7 84 * @brief CAN init structure definition
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86 typedef struct
<> 144:ef7eb2e8f9f7 87 {
AnnaBridge 165:e614a9f1c9e2 88 uint32_t Prescaler; /*!< Specifies the length of a time quantum.
AnnaBridge 165:e614a9f1c9e2 89 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
AnnaBridge 165:e614a9f1c9e2 90
<> 144:ef7eb2e8f9f7 91 uint32_t Mode; /*!< Specifies the CAN operating mode.
<> 144:ef7eb2e8f9f7 92 This parameter can be a value of @ref CAN_operating_mode */
<> 144:ef7eb2e8f9f7 93
AnnaBridge 165:e614a9f1c9e2 94 uint32_t SJW; /*!< Specifies the maximum number of time quanta
AnnaBridge 165:e614a9f1c9e2 95 the CAN hardware is allowed to lengthen or
<> 144:ef7eb2e8f9f7 96 shorten a bit to perform resynchronization.
<> 144:ef7eb2e8f9f7 97 This parameter can be a value of @ref CAN_synchronisation_jump_width */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
<> 144:ef7eb2e8f9f7 100 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
AnnaBridge 165:e614a9f1c9e2 104
<> 144:ef7eb2e8f9f7 105 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
<> 144:ef7eb2e8f9f7 106 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 107
AnnaBridge 165:e614a9f1c9e2 108 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
AnnaBridge 165:e614a9f1c9e2 109 This parameter can be set to ENABLE or DISABLE */
AnnaBridge 165:e614a9f1c9e2 110
AnnaBridge 165:e614a9f1c9e2 111 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
AnnaBridge 165:e614a9f1c9e2 112 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
AnnaBridge 165:e614a9f1c9e2 115 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 116
AnnaBridge 165:e614a9f1c9e2 117 uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
AnnaBridge 165:e614a9f1c9e2 118 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
AnnaBridge 165:e614a9f1c9e2 121 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 122 }CAN_InitTypeDef;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief CAN Tx message structure definition
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef struct
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 uint32_t StdId; /*!< Specifies the standard identifier.
AnnaBridge 165:e614a9f1c9e2 130 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
AnnaBridge 165:e614a9f1c9e2 131
<> 144:ef7eb2e8f9f7 132 uint32_t ExtId; /*!< Specifies the extended identifier.
AnnaBridge 165:e614a9f1c9e2 133 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
AnnaBridge 165:e614a9f1c9e2 134
<> 144:ef7eb2e8f9f7 135 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
AnnaBridge 165:e614a9f1c9e2 136 This parameter can be a value of @ref CAN_Identifier_Type */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
<> 144:ef7eb2e8f9f7 139 This parameter can be a value of @ref CAN_remote_transmission_request */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
AnnaBridge 165:e614a9f1c9e2 142 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
<> 144:ef7eb2e8f9f7 143
AnnaBridge 165:e614a9f1c9e2 144 uint8_t Data[8]; /*!< Contains the data to be transmitted.
AnnaBridge 165:e614a9f1c9e2 145 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
AnnaBridge 165:e614a9f1c9e2 146
<> 144:ef7eb2e8f9f7 147 }CanTxMsgTypeDef;
<> 144:ef7eb2e8f9f7 148
AnnaBridge 165:e614a9f1c9e2 149 /**
AnnaBridge 165:e614a9f1c9e2 150 * @brief CAN Rx message structure definition
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 typedef struct
<> 144:ef7eb2e8f9f7 153 {
<> 144:ef7eb2e8f9f7 154 uint32_t StdId; /*!< Specifies the standard identifier.
AnnaBridge 165:e614a9f1c9e2 155 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 uint32_t ExtId; /*!< Specifies the extended identifier.
AnnaBridge 165:e614a9f1c9e2 158 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
AnnaBridge 165:e614a9f1c9e2 161 This parameter can be a value of @ref CAN_Identifier_Type */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 uint32_t RTR; /*!< Specifies the type of frame for the received message.
<> 144:ef7eb2e8f9f7 164 This parameter can be a value of @ref CAN_remote_transmission_request */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 uint32_t DLC; /*!< Specifies the length of the frame that will be received.
AnnaBridge 165:e614a9f1c9e2 167 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
<> 144:ef7eb2e8f9f7 168
AnnaBridge 165:e614a9f1c9e2 169 uint8_t Data[8]; /*!< Contains the data to be received.
AnnaBridge 165:e614a9f1c9e2 170 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
AnnaBridge 165:e614a9f1c9e2 173 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 174
AnnaBridge 165:e614a9f1c9e2 175 uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
AnnaBridge 165:e614a9f1c9e2 176 This parameter can be CAN_FIFO0 or CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 }CanRxMsgTypeDef;
<> 144:ef7eb2e8f9f7 179
AnnaBridge 165:e614a9f1c9e2 180 /**
AnnaBridge 165:e614a9f1c9e2 181 * @brief CAN handle Structure definition
AnnaBridge 165:e614a9f1c9e2 182 */
<> 144:ef7eb2e8f9f7 183 typedef struct
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 CAN_TypeDef *Instance; /*!< Register base address */
AnnaBridge 165:e614a9f1c9e2 186
<> 144:ef7eb2e8f9f7 187 CAN_InitTypeDef Init; /*!< CAN required parameters */
AnnaBridge 165:e614a9f1c9e2 188
<> 144:ef7eb2e8f9f7 189 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
<> 144:ef7eb2e8f9f7 190
AnnaBridge 165:e614a9f1c9e2 191 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
AnnaBridge 165:e614a9f1c9e2 192
AnnaBridge 165:e614a9f1c9e2 193 CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
AnnaBridge 165:e614a9f1c9e2 194
<> 144:ef7eb2e8f9f7 195 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
AnnaBridge 165:e614a9f1c9e2 196
AnnaBridge 165:e614a9f1c9e2 197 HAL_LockTypeDef Lock; /*!< CAN locking object */
AnnaBridge 165:e614a9f1c9e2 198
<> 144:ef7eb2e8f9f7 199 __IO uint32_t ErrorCode; /*!< CAN Error code */
AnnaBridge 165:e614a9f1c9e2 200
<> 144:ef7eb2e8f9f7 201 }CAN_HandleTypeDef;
AnnaBridge 165:e614a9f1c9e2 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @}
<> 144:ef7eb2e8f9f7 205 */
AnnaBridge 165:e614a9f1c9e2 206
<> 144:ef7eb2e8f9f7 207 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 208 /** @defgroup CAN_Exported_Constants CAN Exported Constants
<> 144:ef7eb2e8f9f7 209 * @{
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @defgroup CAN_Error_Code CAN Error Code
<> 144:ef7eb2e8f9f7 213 * @{
<> 144:ef7eb2e8f9f7 214 */
AnnaBridge 165:e614a9f1c9e2 215 #define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 165:e614a9f1c9e2 216 #define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
AnnaBridge 165:e614a9f1c9e2 217 #define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
AnnaBridge 165:e614a9f1c9e2 218 #define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
AnnaBridge 165:e614a9f1c9e2 219 #define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
AnnaBridge 165:e614a9f1c9e2 220 #define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
AnnaBridge 165:e614a9f1c9e2 221 #define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
AnnaBridge 165:e614a9f1c9e2 222 #define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
AnnaBridge 165:e614a9f1c9e2 223 #define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
AnnaBridge 165:e614a9f1c9e2 224 #define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
AnnaBridge 165:e614a9f1c9e2 225 #define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
AnnaBridge 165:e614a9f1c9e2 226 #define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
AnnaBridge 165:e614a9f1c9e2 227 #define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @}
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** @defgroup CAN_InitStatus CAN initialization Status
<> 144:ef7eb2e8f9f7 233 * @{
<> 144:ef7eb2e8f9f7 234 */
AnnaBridge 165:e614a9f1c9e2 235 #define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
AnnaBridge 165:e614a9f1c9e2 236 #define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @}
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @defgroup CAN_operating_mode CAN Operating Mode
<> 144:ef7eb2e8f9f7 242 * @{
<> 144:ef7eb2e8f9f7 243 */
AnnaBridge 165:e614a9f1c9e2 244 #define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
<> 144:ef7eb2e8f9f7 245 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
<> 144:ef7eb2e8f9f7 246 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
<> 144:ef7eb2e8f9f7 247 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @}
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
AnnaBridge 165:e614a9f1c9e2 255 #define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 256 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 257 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 258 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
AnnaBridge 165:e614a9f1c9e2 266 #define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 267 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 268 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 269 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 270 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
<> 144:ef7eb2e8f9f7 271 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
<> 144:ef7eb2e8f9f7 272 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
<> 144:ef7eb2e8f9f7 273 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
<> 144:ef7eb2e8f9f7 274 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
<> 144:ef7eb2e8f9f7 275 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
<> 144:ef7eb2e8f9f7 276 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
<> 144:ef7eb2e8f9f7 277 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
<> 144:ef7eb2e8f9f7 278 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
<> 144:ef7eb2e8f9f7 279 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
<> 144:ef7eb2e8f9f7 280 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
<> 144:ef7eb2e8f9f7 281 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @}
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285
AnnaBridge 165:e614a9f1c9e2 286 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
<> 144:ef7eb2e8f9f7 287 * @{
<> 144:ef7eb2e8f9f7 288 */
AnnaBridge 165:e614a9f1c9e2 289 #define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 290 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 291 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 292 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 293 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
<> 144:ef7eb2e8f9f7 294 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
<> 144:ef7eb2e8f9f7 295 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
<> 144:ef7eb2e8f9f7 296 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
AnnaBridge 165:e614a9f1c9e2 301 /** @defgroup CAN_filter_mode CAN Filter Mode
<> 144:ef7eb2e8f9f7 302 * @{
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
<> 144:ef7eb2e8f9f7 305 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @}
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /** @defgroup CAN_filter_scale CAN Filter Scale
<> 144:ef7eb2e8f9f7 311 * @{
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
<> 144:ef7eb2e8f9f7 314 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @}
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
<> 144:ef7eb2e8f9f7 323 #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
AnnaBridge 165:e614a9f1c9e2 328 /** @defgroup CAN_Identifier_Type CAN Identifier Type
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
AnnaBridge 165:e614a9f1c9e2 331 #define CAN_ID_STD 0x00000000U /*!< Standard Id */
AnnaBridge 165:e614a9f1c9e2 332 #define CAN_ID_EXT 0x00000004U /*!< Extended Id */
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @}
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
<> 144:ef7eb2e8f9f7 338 * @{
<> 144:ef7eb2e8f9f7 339 */
AnnaBridge 165:e614a9f1c9e2 340 #define CAN_RTR_DATA 0x00000000U /*!< Data frame */
AnnaBridge 165:e614a9f1c9e2 341 #define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @}
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /** @defgroup CAN_transmit_constants CAN Transmit Constants
<> 144:ef7eb2e8f9f7 347 * @{
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
<> 144:ef7eb2e8f9f7 358 #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup CAN_flags CAN Flags
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
<> 144:ef7eb2e8f9f7 367 and CAN_ClearFlag() functions. */
AnnaBridge 165:e614a9f1c9e2 368 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
<> 144:ef7eb2e8f9f7 369 CAN_GetFlagStatus() function. */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Transmit Flags */
<> 144:ef7eb2e8f9f7 372 #define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
<> 144:ef7eb2e8f9f7 373 #define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
<> 144:ef7eb2e8f9f7 374 #define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
<> 144:ef7eb2e8f9f7 375 #define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
<> 144:ef7eb2e8f9f7 376 #define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
<> 144:ef7eb2e8f9f7 377 #define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
<> 144:ef7eb2e8f9f7 378 #define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
<> 144:ef7eb2e8f9f7 379 #define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
<> 144:ef7eb2e8f9f7 380 #define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Receive Flags */
<> 144:ef7eb2e8f9f7 383 #define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
<> 144:ef7eb2e8f9f7 384 #define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 #define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
<> 144:ef7eb2e8f9f7 387 #define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Operating Mode Flags */
<> 144:ef7eb2e8f9f7 390 #define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
<> 144:ef7eb2e8f9f7 391 #define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
<> 144:ef7eb2e8f9f7 392 #define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
AnnaBridge 165:e614a9f1c9e2 393
<> 144:ef7eb2e8f9f7 394 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
<> 144:ef7eb2e8f9f7 395 In this case the SLAK bit can be polled.*/
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Error Flags */
<> 144:ef7eb2e8f9f7 398 #define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
<> 144:ef7eb2e8f9f7 399 #define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
<> 144:ef7eb2e8f9f7 400 #define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
AnnaBridge 165:e614a9f1c9e2 406 /** @defgroup CAN_Interrupts CAN Interrupts
<> 144:ef7eb2e8f9f7 407 * @{
AnnaBridge 165:e614a9f1c9e2 408 */
<> 144:ef7eb2e8f9f7 409 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Receive Interrupts */
<> 144:ef7eb2e8f9f7 412 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
<> 144:ef7eb2e8f9f7 413 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
<> 144:ef7eb2e8f9f7 414 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
<> 144:ef7eb2e8f9f7 415 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
<> 144:ef7eb2e8f9f7 416 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
<> 144:ef7eb2e8f9f7 417 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Operating Mode Interrupts */
<> 144:ef7eb2e8f9f7 420 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
<> 144:ef7eb2e8f9f7 421 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Error Interrupts */
<> 144:ef7eb2e8f9f7 424 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
<> 144:ef7eb2e8f9f7 425 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
<> 144:ef7eb2e8f9f7 426 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
<> 144:ef7eb2e8f9f7 427 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
<> 144:ef7eb2e8f9f7 428 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @}
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /** @defgroup CAN_Private_Constants CAN Private Constants
<> 144:ef7eb2e8f9f7 438 * @{
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* CAN intermediate shift values used for CAN flags */
AnnaBridge 165:e614a9f1c9e2 442 #define TSR_REGISTER_INDEX 0x5U
AnnaBridge 165:e614a9f1c9e2 443 #define RF0R_REGISTER_INDEX 0x2U
AnnaBridge 165:e614a9f1c9e2 444 #define RF1R_REGISTER_INDEX 0x4U
AnnaBridge 165:e614a9f1c9e2 445 #define MSR_REGISTER_INDEX 0x1U
AnnaBridge 165:e614a9f1c9e2 446 #define ESR_REGISTER_INDEX 0x3U
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
<> 144:ef7eb2e8f9f7 449 /* Transmit Flags */
AnnaBridge 165:e614a9f1c9e2 450 #define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
AnnaBridge 165:e614a9f1c9e2 451 #define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
AnnaBridge 165:e614a9f1c9e2 452 #define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
AnnaBridge 165:e614a9f1c9e2 453 #define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
AnnaBridge 165:e614a9f1c9e2 454 #define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
AnnaBridge 165:e614a9f1c9e2 455 #define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
AnnaBridge 165:e614a9f1c9e2 456 #define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
AnnaBridge 165:e614a9f1c9e2 457 #define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
AnnaBridge 165:e614a9f1c9e2 458 #define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Receive Flags */
AnnaBridge 165:e614a9f1c9e2 461 #define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
AnnaBridge 165:e614a9f1c9e2 462 #define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
<> 144:ef7eb2e8f9f7 463
AnnaBridge 165:e614a9f1c9e2 464 #define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
AnnaBridge 165:e614a9f1c9e2 465 #define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Operating Mode Flags */
AnnaBridge 165:e614a9f1c9e2 468 #define CAN_MSR_WKU_BIT_POSITION 0x00000003U
AnnaBridge 165:e614a9f1c9e2 469 #define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
AnnaBridge 165:e614a9f1c9e2 470 #define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Error Flags */
AnnaBridge 165:e614a9f1c9e2 473 #define CAN_ESR_EWG_BIT_POSITION 0x00000000U
AnnaBridge 165:e614a9f1c9e2 474 #define CAN_ESR_EPV_BIT_POSITION 0x00000001U
AnnaBridge 165:e614a9f1c9e2 475 #define CAN_ESR_BOF_BIT_POSITION 0x00000002U
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Mask used by macro to get/clear CAN flags*/
AnnaBridge 165:e614a9f1c9e2 478 #define CAN_FLAG_MASK 0x000000FFU
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Mailboxes definition */
<> 144:ef7eb2e8f9f7 481 #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
<> 144:ef7eb2e8f9f7 482 #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 483 #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @}
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 489 /** @defgroup CAN_Exported_Macros CAN Exported Macros
<> 144:ef7eb2e8f9f7 490 * @{
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /** @brief Reset CAN handle state
<> 144:ef7eb2e8f9f7 494 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 495 * @retval None
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @brief Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 501 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 502 * @param __INTERRUPT__: CAN Interrupt.
<> 144:ef7eb2e8f9f7 503 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 504 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
<> 144:ef7eb2e8f9f7 505 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
<> 144:ef7eb2e8f9f7 506 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
<> 144:ef7eb2e8f9f7 507 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
<> 144:ef7eb2e8f9f7 508 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
<> 144:ef7eb2e8f9f7 509 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
<> 144:ef7eb2e8f9f7 510 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
<> 144:ef7eb2e8f9f7 511 * @arg CAN_IT_WKU : Wake-up interrupt
<> 144:ef7eb2e8f9f7 512 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
<> 144:ef7eb2e8f9f7 513 * @arg CAN_IT_EWG : Error warning interrupt
<> 144:ef7eb2e8f9f7 514 * @arg CAN_IT_EPV : Error passive interrupt
<> 144:ef7eb2e8f9f7 515 * @arg CAN_IT_BOF : Bus-off interrupt
<> 144:ef7eb2e8f9f7 516 * @arg CAN_IT_LEC : Last error code interrupt
<> 144:ef7eb2e8f9f7 517 * @arg CAN_IT_ERR : Error Interrupt
<> 144:ef7eb2e8f9f7 518 * @retval None.
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @brief Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 524 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 525 * @param __INTERRUPT__: CAN Interrupt.
<> 144:ef7eb2e8f9f7 526 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 527 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
<> 144:ef7eb2e8f9f7 528 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
<> 144:ef7eb2e8f9f7 529 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
<> 144:ef7eb2e8f9f7 530 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
<> 144:ef7eb2e8f9f7 531 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
<> 144:ef7eb2e8f9f7 532 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
<> 144:ef7eb2e8f9f7 533 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
<> 144:ef7eb2e8f9f7 534 * @arg CAN_IT_WKU : Wake-up interrupt
<> 144:ef7eb2e8f9f7 535 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
<> 144:ef7eb2e8f9f7 536 * @arg CAN_IT_EWG : Error warning interrupt
<> 144:ef7eb2e8f9f7 537 * @arg CAN_IT_EPV : Error passive interrupt
<> 144:ef7eb2e8f9f7 538 * @arg CAN_IT_BOF : Bus-off interrupt
<> 144:ef7eb2e8f9f7 539 * @arg CAN_IT_LEC : Last error code interrupt
<> 144:ef7eb2e8f9f7 540 * @arg CAN_IT_ERR : Error Interrupt
<> 144:ef7eb2e8f9f7 541 * @retval None.
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @brief Return the number of pending received messages.
<> 144:ef7eb2e8f9f7 547 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 548 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
<> 144:ef7eb2e8f9f7 549 * @retval The number of pending message.
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
AnnaBridge 165:e614a9f1c9e2 552 ((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /** @brief Check whether the specified CAN flag is set or not.
<> 144:ef7eb2e8f9f7 555 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 556 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 557 * This parameter can be one of the following values:
AnnaBridge 187:0387e8f68319 558 * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag // MBED patch
<> 154:37f96f9d4de2 559 * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
<> 154:37f96f9d4de2 560 * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
<> 144:ef7eb2e8f9f7 561 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
<> 144:ef7eb2e8f9f7 562 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
<> 144:ef7eb2e8f9f7 563 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
<> 144:ef7eb2e8f9f7 564 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
<> 144:ef7eb2e8f9f7 565 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
<> 144:ef7eb2e8f9f7 566 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
<> 144:ef7eb2e8f9f7 567 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
<> 144:ef7eb2e8f9f7 568 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
<> 144:ef7eb2e8f9f7 569 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
<> 144:ef7eb2e8f9f7 570 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
<> 144:ef7eb2e8f9f7 571 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
<> 144:ef7eb2e8f9f7 572 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
<> 144:ef7eb2e8f9f7 573 * @arg CAN_FLAG_WKU: Wake up Flag
<> 144:ef7eb2e8f9f7 574 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 575 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 576 * @arg CAN_FLAG_EWG: Error Warning Flag
<> 144:ef7eb2e8f9f7 577 * @arg CAN_FLAG_EPV: Error Passive Flag
<> 144:ef7eb2e8f9f7 578 * @arg CAN_FLAG_BOF: Bus-Off Flag
<> 144:ef7eb2e8f9f7 579 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge 165:e614a9f1c9e2 582 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
AnnaBridge 165:e614a9f1c9e2 583 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
AnnaBridge 165:e614a9f1c9e2 584 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
AnnaBridge 165:e614a9f1c9e2 585 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 586 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /** @brief Clear the specified CAN pending flag.
<> 144:ef7eb2e8f9f7 589 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 590 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 591 * This parameter can be one of the following values:
AnnaBridge 187:0387e8f68319 592 * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag // MBED patch
<> 154:37f96f9d4de2 593 * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
<> 154:37f96f9d4de2 594 * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
<> 144:ef7eb2e8f9f7 595 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
<> 144:ef7eb2e8f9f7 596 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
<> 144:ef7eb2e8f9f7 597 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
<> 144:ef7eb2e8f9f7 598 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
<> 144:ef7eb2e8f9f7 599 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
<> 144:ef7eb2e8f9f7 600 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
<> 144:ef7eb2e8f9f7 601 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
<> 144:ef7eb2e8f9f7 602 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
<> 144:ef7eb2e8f9f7 603 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
<> 144:ef7eb2e8f9f7 604 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
<> 144:ef7eb2e8f9f7 605 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
<> 144:ef7eb2e8f9f7 606 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
<> 144:ef7eb2e8f9f7 607 * @arg CAN_FLAG_WKU: Wake up Flag
<> 144:ef7eb2e8f9f7 608 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 609 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 612 ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 613 (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 144:ef7eb2e8f9f7 614 (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
AnnaBridge 165:e614a9f1c9e2 615 (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /** @brief Check if the specified CAN interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 618 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 619 * @param __INTERRUPT__: specifies the CAN interrupt source to check.
<> 144:ef7eb2e8f9f7 620 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 621 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
<> 144:ef7eb2e8f9f7 622 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
<> 144:ef7eb2e8f9f7 623 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
<> 144:ef7eb2e8f9f7 624 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
<> 144:ef7eb2e8f9f7 625 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
<> 144:ef7eb2e8f9f7 626 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
<> 144:ef7eb2e8f9f7 627 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
<> 144:ef7eb2e8f9f7 628 * @arg CAN_IT_WKU : Wake-up interrupt
<> 144:ef7eb2e8f9f7 629 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
<> 144:ef7eb2e8f9f7 630 * @arg CAN_IT_EWG : Error warning interrupt
<> 144:ef7eb2e8f9f7 631 * @arg CAN_IT_EPV : Error passive interrupt
<> 144:ef7eb2e8f9f7 632 * @arg CAN_IT_BOF : Bus-off interrupt
<> 144:ef7eb2e8f9f7 633 * @arg CAN_IT_LEC : Last error code interrupt
<> 144:ef7eb2e8f9f7 634 * @arg CAN_IT_ERR : Error Interrupt
<> 144:ef7eb2e8f9f7 635 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @brief Check the transmission status of a CAN Frame.
<> 144:ef7eb2e8f9f7 641 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 642 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
<> 144:ef7eb2e8f9f7 643 * @retval The new status of transmission (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
AnnaBridge 165:e614a9f1c9e2 646 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
AnnaBridge 165:e614a9f1c9e2 647 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
AnnaBridge 165:e614a9f1c9e2 648 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /**
<> 144:ef7eb2e8f9f7 651 * @brief Release the specified receive FIFO.
<> 144:ef7eb2e8f9f7 652 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 653 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
<> 144:ef7eb2e8f9f7 654 * @retval None.
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
AnnaBridge 165:e614a9f1c9e2 657 ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /**
<> 144:ef7eb2e8f9f7 660 * @brief Cancel a transmit request.
<> 144:ef7eb2e8f9f7 661 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 662 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
<> 144:ef7eb2e8f9f7 663 * @retval None.
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
AnnaBridge 165:e614a9f1c9e2 666 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
AnnaBridge 165:e614a9f1c9e2 667 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
AnnaBridge 165:e614a9f1c9e2 668 ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Enable or disables the DBG Freeze for CAN.
<> 144:ef7eb2e8f9f7 672 * @param __HANDLE__: specifies the CAN Handle.
AnnaBridge 165:e614a9f1c9e2 673 * @param __NEWSTATE__: new state of the CAN peripheral.
<> 144:ef7eb2e8f9f7 674 * This parameter can be: ENABLE (CAN reception/transmission is frozen
AnnaBridge 165:e614a9f1c9e2 675 * during debug. Reception FIFOs can still be accessed/controlled normally)
<> 144:ef7eb2e8f9f7 676 * or DISABLE (CAN is working during debug).
<> 144:ef7eb2e8f9f7 677 * @retval None
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
AnnaBridge 165:e614a9f1c9e2 680 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @}
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* Include CAN HAL Extension module */
<> 144:ef7eb2e8f9f7 687 #include "stm32f1xx_hal_can_ex.h"
<> 144:ef7eb2e8f9f7 688
AnnaBridge 165:e614a9f1c9e2 689 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 690 /** @addtogroup CAN_Exported_Functions
<> 144:ef7eb2e8f9f7 691 * @{
<> 144:ef7eb2e8f9f7 692 */
AnnaBridge 165:e614a9f1c9e2 693
<> 144:ef7eb2e8f9f7 694 /** @addtogroup CAN_Exported_Functions_Group1
AnnaBridge 165:e614a9f1c9e2 695 * @brief Initialization and Configuration functions
AnnaBridge 165:e614a9f1c9e2 696 * @{
AnnaBridge 165:e614a9f1c9e2 697 */
AnnaBridge 165:e614a9f1c9e2 698 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 699 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 700 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
<> 144:ef7eb2e8f9f7 701 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 702 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 703 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 704 /**
AnnaBridge 165:e614a9f1c9e2 705 * @}
AnnaBridge 165:e614a9f1c9e2 706 */
AnnaBridge 165:e614a9f1c9e2 707
<> 144:ef7eb2e8f9f7 708 /** @addtogroup CAN_Exported_Functions_Group2
AnnaBridge 165:e614a9f1c9e2 709 * @brief I/O operation functions
AnnaBridge 165:e614a9f1c9e2 710 * @{
AnnaBridge 165:e614a9f1c9e2 711 */
AnnaBridge 165:e614a9f1c9e2 712 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 713 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 714 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 715 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 716 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 717 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 718 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 719 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 720 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 721 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 722 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 723 /**
AnnaBridge 165:e614a9f1c9e2 724 * @}
AnnaBridge 165:e614a9f1c9e2 725 */
AnnaBridge 165:e614a9f1c9e2 726
<> 144:ef7eb2e8f9f7 727 /** @addtogroup CAN_Exported_Functions_Group3
AnnaBridge 165:e614a9f1c9e2 728 * @brief CAN Peripheral State functions
AnnaBridge 165:e614a9f1c9e2 729 * @{
AnnaBridge 165:e614a9f1c9e2 730 */
<> 144:ef7eb2e8f9f7 731 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 732 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 733 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 734 /**
<> 144:ef7eb2e8f9f7 735 * @}
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @}
<> 144:ef7eb2e8f9f7 740 */
<> 144:ef7eb2e8f9f7 741
AnnaBridge 165:e614a9f1c9e2 742 /* Private macros --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 743 /** @defgroup CAN_Private_Macros CAN Private Macros
AnnaBridge 165:e614a9f1c9e2 744 * @{
AnnaBridge 165:e614a9f1c9e2 745 */
AnnaBridge 165:e614a9f1c9e2 746
AnnaBridge 165:e614a9f1c9e2 747 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
AnnaBridge 165:e614a9f1c9e2 748 ((MODE) == CAN_MODE_LOOPBACK)|| \
AnnaBridge 165:e614a9f1c9e2 749 ((MODE) == CAN_MODE_SILENT) || \
AnnaBridge 165:e614a9f1c9e2 750 ((MODE) == CAN_MODE_SILENT_LOOPBACK))
AnnaBridge 165:e614a9f1c9e2 751 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
AnnaBridge 165:e614a9f1c9e2 752 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
AnnaBridge 165:e614a9f1c9e2 753 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
AnnaBridge 165:e614a9f1c9e2 754 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
AnnaBridge 165:e614a9f1c9e2 755 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
AnnaBridge 165:e614a9f1c9e2 756
AnnaBridge 165:e614a9f1c9e2 757 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
AnnaBridge 165:e614a9f1c9e2 758 ((MODE) == CAN_FILTERMODE_IDLIST))
AnnaBridge 165:e614a9f1c9e2 759 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
AnnaBridge 165:e614a9f1c9e2 760 ((SCALE) == CAN_FILTERSCALE_32BIT))
AnnaBridge 165:e614a9f1c9e2 761 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
AnnaBridge 165:e614a9f1c9e2 762 ((FIFO) == CAN_FILTER_FIFO1))
AnnaBridge 165:e614a9f1c9e2 763 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
AnnaBridge 165:e614a9f1c9e2 764
AnnaBridge 165:e614a9f1c9e2 765 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
AnnaBridge 165:e614a9f1c9e2 766 #define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
AnnaBridge 165:e614a9f1c9e2 767 #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
AnnaBridge 165:e614a9f1c9e2 768 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
AnnaBridge 165:e614a9f1c9e2 769
AnnaBridge 165:e614a9f1c9e2 770 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
AnnaBridge 165:e614a9f1c9e2 771 ((IDTYPE) == CAN_ID_EXT))
AnnaBridge 165:e614a9f1c9e2 772 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
AnnaBridge 165:e614a9f1c9e2 773 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
AnnaBridge 165:e614a9f1c9e2 774
AnnaBridge 165:e614a9f1c9e2 775 /**
AnnaBridge 165:e614a9f1c9e2 776 * @}
AnnaBridge 165:e614a9f1c9e2 777 */
AnnaBridge 165:e614a9f1c9e2 778
AnnaBridge 165:e614a9f1c9e2 779 /**
AnnaBridge 165:e614a9f1c9e2 780 * @}
AnnaBridge 165:e614a9f1c9e2 781 */
AnnaBridge 165:e614a9f1c9e2 782
AnnaBridge 165:e614a9f1c9e2 783 /**
AnnaBridge 165:e614a9f1c9e2 784 * @}
AnnaBridge 165:e614a9f1c9e2 785 */
AnnaBridge 165:e614a9f1c9e2 786
AnnaBridge 165:e614a9f1c9e2 787 #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 #endif
<> 144:ef7eb2e8f9f7 792
AnnaBridge 165:e614a9f1c9e2 793 #endif /* __STM32F1xx_HAL_CAN_H */
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/