mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 188:bcfe06ba3d64
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 184:08ed48f1de7f | 1 | /* mbed Microcontroller Library |
AnnaBridge | 184:08ed48f1de7f | 2 | * Copyright (c) 2006-2017 ARM Limited |
AnnaBridge | 184:08ed48f1de7f | 3 | * |
AnnaBridge | 184:08ed48f1de7f | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
AnnaBridge | 184:08ed48f1de7f | 5 | * you may not use this file except in compliance with the License. |
AnnaBridge | 184:08ed48f1de7f | 6 | * You may obtain a copy of the License at |
AnnaBridge | 184:08ed48f1de7f | 7 | * |
AnnaBridge | 184:08ed48f1de7f | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
AnnaBridge | 184:08ed48f1de7f | 9 | * |
AnnaBridge | 184:08ed48f1de7f | 10 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 184:08ed48f1de7f | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
AnnaBridge | 184:08ed48f1de7f | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 184:08ed48f1de7f | 13 | * See the License for the specific language governing permissions and |
AnnaBridge | 184:08ed48f1de7f | 14 | * limitations under the License. |
AnnaBridge | 184:08ed48f1de7f | 15 | */ |
AnnaBridge | 184:08ed48f1de7f | 16 | |
AnnaBridge | 184:08ed48f1de7f | 17 | /** |
AnnaBridge | 184:08ed48f1de7f | 18 | * This file configures the system clock as follows: |
AnnaBridge | 184:08ed48f1de7f | 19 | *----------------------------------------------------------------------------- |
AnnaBridge | 184:08ed48f1de7f | 20 | * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
AnnaBridge | 184:08ed48f1de7f | 21 | * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
AnnaBridge | 184:08ed48f1de7f | 22 | * | 3- USE_PLL_HSI (internal 16 MHz) |
AnnaBridge | 184:08ed48f1de7f | 23 | * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) |
AnnaBridge | 184:08ed48f1de7f | 24 | *----------------------------------------------------------------------------- |
AnnaBridge | 184:08ed48f1de7f | 25 | * SYSCLK(MHz) | 80 |
AnnaBridge | 184:08ed48f1de7f | 26 | * AHBCLK (MHz) | 80 |
AnnaBridge | 184:08ed48f1de7f | 27 | * APB1CLK (MHz) | 80 |
AnnaBridge | 184:08ed48f1de7f | 28 | * APB2CLK (MHz) | 80 |
AnnaBridge | 184:08ed48f1de7f | 29 | * USB capable | YES |
AnnaBridge | 184:08ed48f1de7f | 30 | *----------------------------------------------------------------------------- |
AnnaBridge | 184:08ed48f1de7f | 31 | **/ |
AnnaBridge | 184:08ed48f1de7f | 32 | |
AnnaBridge | 184:08ed48f1de7f | 33 | #include "stm32l4xx.h" |
AnnaBridge | 184:08ed48f1de7f | 34 | #include "nvic_addr.h" |
AnnaBridge | 187:0387e8f68319 | 35 | #include "mbed_error.h" |
AnnaBridge | 184:08ed48f1de7f | 36 | |
AnnaBridge | 184:08ed48f1de7f | 37 | /*!< Uncomment the following line if you need to relocate your vector Table in |
AnnaBridge | 184:08ed48f1de7f | 38 | Internal SRAM. */ |
AnnaBridge | 184:08ed48f1de7f | 39 | /* #define VECT_TAB_SRAM */ |
AnnaBridge | 184:08ed48f1de7f | 40 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
AnnaBridge | 184:08ed48f1de7f | 41 | This value must be a multiple of 0x200. */ |
AnnaBridge | 184:08ed48f1de7f | 42 | |
AnnaBridge | 184:08ed48f1de7f | 43 | |
AnnaBridge | 184:08ed48f1de7f | 44 | // clock source is selected with CLOCK_SOURCE in json config |
AnnaBridge | 184:08ed48f1de7f | 45 | #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) |
AnnaBridge | 184:08ed48f1de7f | 46 | #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) |
AnnaBridge | 184:08ed48f1de7f | 47 | #define USE_PLL_HSI 0x2 // Use HSI internal clock |
AnnaBridge | 184:08ed48f1de7f | 48 | #define USE_PLL_MSI 0x1 // Use MSI internal clock |
AnnaBridge | 184:08ed48f1de7f | 49 | |
AnnaBridge | 184:08ed48f1de7f | 50 | #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) |
AnnaBridge | 184:08ed48f1de7f | 51 | |
AnnaBridge | 184:08ed48f1de7f | 52 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
AnnaBridge | 184:08ed48f1de7f | 53 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
AnnaBridge | 184:08ed48f1de7f | 54 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
AnnaBridge | 184:08ed48f1de7f | 55 | |
AnnaBridge | 184:08ed48f1de7f | 56 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
AnnaBridge | 184:08ed48f1de7f | 57 | uint8_t SetSysClock_PLL_HSI(void); |
AnnaBridge | 184:08ed48f1de7f | 58 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
AnnaBridge | 184:08ed48f1de7f | 59 | |
AnnaBridge | 184:08ed48f1de7f | 60 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
AnnaBridge | 184:08ed48f1de7f | 61 | uint8_t SetSysClock_PLL_MSI(void); |
AnnaBridge | 184:08ed48f1de7f | 62 | #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ |
AnnaBridge | 184:08ed48f1de7f | 63 | |
AnnaBridge | 184:08ed48f1de7f | 64 | |
AnnaBridge | 184:08ed48f1de7f | 65 | /** |
AnnaBridge | 184:08ed48f1de7f | 66 | * @brief Setup the microcontroller system. |
AnnaBridge | 184:08ed48f1de7f | 67 | * @param None |
AnnaBridge | 184:08ed48f1de7f | 68 | * @retval None |
AnnaBridge | 184:08ed48f1de7f | 69 | */ |
AnnaBridge | 184:08ed48f1de7f | 70 | |
AnnaBridge | 184:08ed48f1de7f | 71 | void SystemInit(void) |
AnnaBridge | 184:08ed48f1de7f | 72 | { |
AnnaBridge | 184:08ed48f1de7f | 73 | /* FPU settings ------------------------------------------------------------*/ |
AnnaBridge | 184:08ed48f1de7f | 74 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
AnnaBridge | 187:0387e8f68319 | 75 | SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ |
AnnaBridge | 184:08ed48f1de7f | 76 | #endif |
AnnaBridge | 184:08ed48f1de7f | 77 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
AnnaBridge | 184:08ed48f1de7f | 78 | /* Set MSION bit */ |
AnnaBridge | 184:08ed48f1de7f | 79 | RCC->CR |= RCC_CR_MSION; |
AnnaBridge | 184:08ed48f1de7f | 80 | |
AnnaBridge | 184:08ed48f1de7f | 81 | /* Reset CFGR register */ |
AnnaBridge | 184:08ed48f1de7f | 82 | RCC->CFGR = 0x00000000; |
AnnaBridge | 184:08ed48f1de7f | 83 | |
AnnaBridge | 184:08ed48f1de7f | 84 | /* Reset HSEON, CSSON , HSION, and PLLON bits */ |
AnnaBridge | 184:08ed48f1de7f | 85 | RCC->CR &= (uint32_t)0xEAF6FFFF; |
AnnaBridge | 184:08ed48f1de7f | 86 | |
AnnaBridge | 184:08ed48f1de7f | 87 | /* Reset PLLCFGR register */ |
AnnaBridge | 184:08ed48f1de7f | 88 | RCC->PLLCFGR = 0x00001000; |
AnnaBridge | 184:08ed48f1de7f | 89 | |
AnnaBridge | 184:08ed48f1de7f | 90 | /* Reset HSEBYP bit */ |
AnnaBridge | 184:08ed48f1de7f | 91 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
AnnaBridge | 184:08ed48f1de7f | 92 | |
AnnaBridge | 184:08ed48f1de7f | 93 | /* Disable all interrupts */ |
AnnaBridge | 184:08ed48f1de7f | 94 | RCC->CIER = 0x00000000; |
AnnaBridge | 184:08ed48f1de7f | 95 | |
AnnaBridge | 184:08ed48f1de7f | 96 | /* Configure the Vector Table location add offset address ------------------*/ |
AnnaBridge | 184:08ed48f1de7f | 97 | #ifdef VECT_TAB_SRAM |
AnnaBridge | 184:08ed48f1de7f | 98 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
AnnaBridge | 184:08ed48f1de7f | 99 | #else |
AnnaBridge | 184:08ed48f1de7f | 100 | SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ |
AnnaBridge | 184:08ed48f1de7f | 101 | #endif |
AnnaBridge | 184:08ed48f1de7f | 102 | |
AnnaBridge | 184:08ed48f1de7f | 103 | } |
AnnaBridge | 184:08ed48f1de7f | 104 | |
AnnaBridge | 184:08ed48f1de7f | 105 | |
AnnaBridge | 184:08ed48f1de7f | 106 | /** |
AnnaBridge | 184:08ed48f1de7f | 107 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
AnnaBridge | 184:08ed48f1de7f | 108 | * AHB/APBx prescalers and Flash settings |
AnnaBridge | 184:08ed48f1de7f | 109 | * @note This function should be called only once the RCC clock configuration |
AnnaBridge | 184:08ed48f1de7f | 110 | * is reset to the default reset state (done in SystemInit() function). |
AnnaBridge | 184:08ed48f1de7f | 111 | * @param None |
AnnaBridge | 184:08ed48f1de7f | 112 | * @retval None |
AnnaBridge | 184:08ed48f1de7f | 113 | */ |
AnnaBridge | 184:08ed48f1de7f | 114 | |
AnnaBridge | 184:08ed48f1de7f | 115 | void SetSysClock(void) |
AnnaBridge | 184:08ed48f1de7f | 116 | { |
AnnaBridge | 184:08ed48f1de7f | 117 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) |
AnnaBridge | 184:08ed48f1de7f | 118 | /* 1- Try to start with HSE and external clock */ |
AnnaBridge | 184:08ed48f1de7f | 119 | if (SetSysClock_PLL_HSE(1) == 0) |
AnnaBridge | 184:08ed48f1de7f | 120 | #endif |
AnnaBridge | 184:08ed48f1de7f | 121 | { |
AnnaBridge | 184:08ed48f1de7f | 122 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) |
AnnaBridge | 184:08ed48f1de7f | 123 | /* 2- If fail try to start with HSE and external xtal */ |
AnnaBridge | 184:08ed48f1de7f | 124 | if (SetSysClock_PLL_HSE(0) == 0) |
AnnaBridge | 184:08ed48f1de7f | 125 | #endif |
AnnaBridge | 184:08ed48f1de7f | 126 | { |
AnnaBridge | 184:08ed48f1de7f | 127 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
AnnaBridge | 184:08ed48f1de7f | 128 | /* 3- If fail start with HSI clock */ |
AnnaBridge | 187:0387e8f68319 | 129 | if (SetSysClock_PLL_HSI() == 0) |
AnnaBridge | 184:08ed48f1de7f | 130 | #endif |
AnnaBridge | 184:08ed48f1de7f | 131 | { |
AnnaBridge | 184:08ed48f1de7f | 132 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
AnnaBridge | 184:08ed48f1de7f | 133 | /* 4- If fail start with MSI clock */ |
AnnaBridge | 184:08ed48f1de7f | 134 | if (SetSysClock_PLL_MSI() == 0) |
AnnaBridge | 184:08ed48f1de7f | 135 | #endif |
AnnaBridge | 184:08ed48f1de7f | 136 | { |
AnnaBridge | 187:0387e8f68319 | 137 | { |
AnnaBridge | 187:0387e8f68319 | 138 | error("SetSysClock failed\n"); |
AnnaBridge | 184:08ed48f1de7f | 139 | } |
AnnaBridge | 184:08ed48f1de7f | 140 | } |
AnnaBridge | 184:08ed48f1de7f | 141 | } |
AnnaBridge | 184:08ed48f1de7f | 142 | } |
AnnaBridge | 184:08ed48f1de7f | 143 | } |
AnnaBridge | 184:08ed48f1de7f | 144 | |
AnnaBridge | 184:08ed48f1de7f | 145 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 184:08ed48f1de7f | 146 | #if DEBUG_MCO == 1 |
AnnaBridge | 184:08ed48f1de7f | 147 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); |
AnnaBridge | 184:08ed48f1de7f | 148 | #endif |
AnnaBridge | 184:08ed48f1de7f | 149 | } |
AnnaBridge | 184:08ed48f1de7f | 150 | |
AnnaBridge | 184:08ed48f1de7f | 151 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
AnnaBridge | 184:08ed48f1de7f | 152 | /******************************************************************************/ |
AnnaBridge | 184:08ed48f1de7f | 153 | /* PLL (clocked by HSE) used as System clock source */ |
AnnaBridge | 184:08ed48f1de7f | 154 | /******************************************************************************/ |
AnnaBridge | 184:08ed48f1de7f | 155 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
AnnaBridge | 184:08ed48f1de7f | 156 | { |
AnnaBridge | 184:08ed48f1de7f | 157 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
AnnaBridge | 184:08ed48f1de7f | 158 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
AnnaBridge | 184:08ed48f1de7f | 159 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; |
AnnaBridge | 184:08ed48f1de7f | 160 | |
AnnaBridge | 184:08ed48f1de7f | 161 | // Used to gain time after DeepSleep in case HSI is used |
AnnaBridge | 184:08ed48f1de7f | 162 | if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { |
AnnaBridge | 184:08ed48f1de7f | 163 | return 0; |
AnnaBridge | 184:08ed48f1de7f | 164 | } |
AnnaBridge | 184:08ed48f1de7f | 165 | |
AnnaBridge | 184:08ed48f1de7f | 166 | // Select MSI as system clock source to allow modification of the PLL configuration |
AnnaBridge | 184:08ed48f1de7f | 167 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
AnnaBridge | 184:08ed48f1de7f | 168 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; |
AnnaBridge | 184:08ed48f1de7f | 169 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); |
AnnaBridge | 184:08ed48f1de7f | 170 | |
AnnaBridge | 184:08ed48f1de7f | 171 | // Enable HSE oscillator and activate PLL with HSE as source |
AnnaBridge | 184:08ed48f1de7f | 172 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; |
AnnaBridge | 184:08ed48f1de7f | 173 | if (bypass == 0) { |
AnnaBridge | 184:08ed48f1de7f | 174 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
AnnaBridge | 184:08ed48f1de7f | 175 | } else { |
AnnaBridge | 184:08ed48f1de7f | 176 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN |
AnnaBridge | 184:08ed48f1de7f | 177 | } |
AnnaBridge | 184:08ed48f1de7f | 178 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
AnnaBridge | 184:08ed48f1de7f | 179 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz |
AnnaBridge | 184:08ed48f1de7f | 180 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
AnnaBridge | 184:08ed48f1de7f | 181 | RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) |
AnnaBridge | 184:08ed48f1de7f | 182 | RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) |
AnnaBridge | 184:08ed48f1de7f | 183 | RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) |
AnnaBridge | 184:08ed48f1de7f | 184 | RCC_OscInitStruct.PLL.PLLQ = 2; |
AnnaBridge | 184:08ed48f1de7f | 185 | RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) |
AnnaBridge | 184:08ed48f1de7f | 186 | |
AnnaBridge | 184:08ed48f1de7f | 187 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 188 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 189 | } |
AnnaBridge | 184:08ed48f1de7f | 190 | |
AnnaBridge | 184:08ed48f1de7f | 191 | // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
AnnaBridge | 184:08ed48f1de7f | 192 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
AnnaBridge | 184:08ed48f1de7f | 193 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz |
AnnaBridge | 184:08ed48f1de7f | 194 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz |
AnnaBridge | 184:08ed48f1de7f | 195 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 196 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
AnnaBridge | 184:08ed48f1de7f | 197 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 198 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 199 | } |
AnnaBridge | 184:08ed48f1de7f | 200 | |
AnnaBridge | 184:08ed48f1de7f | 201 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
AnnaBridge | 184:08ed48f1de7f | 202 | RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; |
AnnaBridge | 184:08ed48f1de7f | 203 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; |
AnnaBridge | 184:08ed48f1de7f | 204 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; |
AnnaBridge | 184:08ed48f1de7f | 205 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; |
AnnaBridge | 184:08ed48f1de7f | 206 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; |
AnnaBridge | 184:08ed48f1de7f | 207 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; |
AnnaBridge | 184:08ed48f1de7f | 208 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; |
AnnaBridge | 184:08ed48f1de7f | 209 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; |
AnnaBridge | 184:08ed48f1de7f | 210 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 211 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 212 | } |
AnnaBridge | 184:08ed48f1de7f | 213 | |
AnnaBridge | 184:08ed48f1de7f | 214 | // Disable MSI Oscillator |
AnnaBridge | 184:08ed48f1de7f | 215 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; |
AnnaBridge | 184:08ed48f1de7f | 216 | RCC_OscInitStruct.MSIState = RCC_MSI_OFF; |
AnnaBridge | 184:08ed48f1de7f | 217 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
AnnaBridge | 184:08ed48f1de7f | 218 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
AnnaBridge | 184:08ed48f1de7f | 219 | |
AnnaBridge | 184:08ed48f1de7f | 220 | /* Select HSI as clock source for LPUART1 */ |
AnnaBridge | 184:08ed48f1de7f | 221 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; |
AnnaBridge | 184:08ed48f1de7f | 222 | RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; |
AnnaBridge | 184:08ed48f1de7f | 223 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 224 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 225 | } |
AnnaBridge | 184:08ed48f1de7f | 226 | |
AnnaBridge | 184:08ed48f1de7f | 227 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 184:08ed48f1de7f | 228 | #if DEBUG_MCO == 2 |
AnnaBridge | 187:0387e8f68319 | 229 | if (bypass == 0) { |
AnnaBridge | 187:0387e8f68319 | 230 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz |
AnnaBridge | 187:0387e8f68319 | 231 | } else { |
AnnaBridge | 187:0387e8f68319 | 232 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
AnnaBridge | 187:0387e8f68319 | 233 | } |
AnnaBridge | 184:08ed48f1de7f | 234 | #endif |
AnnaBridge | 184:08ed48f1de7f | 235 | |
AnnaBridge | 184:08ed48f1de7f | 236 | return 1; // OK |
AnnaBridge | 184:08ed48f1de7f | 237 | } |
AnnaBridge | 184:08ed48f1de7f | 238 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
AnnaBridge | 184:08ed48f1de7f | 239 | |
AnnaBridge | 184:08ed48f1de7f | 240 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
AnnaBridge | 184:08ed48f1de7f | 241 | /******************************************************************************/ |
AnnaBridge | 184:08ed48f1de7f | 242 | /* PLL (clocked by HSI) used as System clock source */ |
AnnaBridge | 184:08ed48f1de7f | 243 | /******************************************************************************/ |
AnnaBridge | 184:08ed48f1de7f | 244 | uint8_t SetSysClock_PLL_HSI(void) |
AnnaBridge | 184:08ed48f1de7f | 245 | { |
AnnaBridge | 184:08ed48f1de7f | 246 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
AnnaBridge | 184:08ed48f1de7f | 247 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
AnnaBridge | 184:08ed48f1de7f | 248 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; |
AnnaBridge | 184:08ed48f1de7f | 249 | |
AnnaBridge | 184:08ed48f1de7f | 250 | // Select MSI as system clock source to allow modification of the PLL configuration |
AnnaBridge | 184:08ed48f1de7f | 251 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
AnnaBridge | 184:08ed48f1de7f | 252 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; |
AnnaBridge | 184:08ed48f1de7f | 253 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); |
AnnaBridge | 184:08ed48f1de7f | 254 | |
AnnaBridge | 184:08ed48f1de7f | 255 | // Enable HSI oscillator and activate PLL with HSI as source |
AnnaBridge | 184:08ed48f1de7f | 256 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
AnnaBridge | 184:08ed48f1de7f | 257 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
AnnaBridge | 184:08ed48f1de7f | 258 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
AnnaBridge | 184:08ed48f1de7f | 259 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
AnnaBridge | 184:08ed48f1de7f | 260 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
AnnaBridge | 184:08ed48f1de7f | 261 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz |
AnnaBridge | 184:08ed48f1de7f | 262 | RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) |
AnnaBridge | 184:08ed48f1de7f | 263 | RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) |
AnnaBridge | 184:08ed48f1de7f | 264 | RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) |
AnnaBridge | 184:08ed48f1de7f | 265 | RCC_OscInitStruct.PLL.PLLQ = 2; |
AnnaBridge | 184:08ed48f1de7f | 266 | RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) |
AnnaBridge | 184:08ed48f1de7f | 267 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 268 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 269 | } |
AnnaBridge | 184:08ed48f1de7f | 270 | |
AnnaBridge | 184:08ed48f1de7f | 271 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
AnnaBridge | 184:08ed48f1de7f | 272 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
AnnaBridge | 184:08ed48f1de7f | 273 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz |
AnnaBridge | 184:08ed48f1de7f | 274 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz |
AnnaBridge | 184:08ed48f1de7f | 275 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
AnnaBridge | 184:08ed48f1de7f | 276 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
AnnaBridge | 184:08ed48f1de7f | 277 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 278 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 279 | } |
AnnaBridge | 184:08ed48f1de7f | 280 | |
AnnaBridge | 184:08ed48f1de7f | 281 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
AnnaBridge | 184:08ed48f1de7f | 282 | RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; |
AnnaBridge | 184:08ed48f1de7f | 283 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; |
AnnaBridge | 184:08ed48f1de7f | 284 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; |
AnnaBridge | 184:08ed48f1de7f | 285 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; |
AnnaBridge | 184:08ed48f1de7f | 286 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; |
AnnaBridge | 184:08ed48f1de7f | 287 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; |
AnnaBridge | 184:08ed48f1de7f | 288 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; |
AnnaBridge | 184:08ed48f1de7f | 289 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; |
AnnaBridge | 184:08ed48f1de7f | 290 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 291 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 292 | } |
AnnaBridge | 184:08ed48f1de7f | 293 | |
AnnaBridge | 184:08ed48f1de7f | 294 | // Disable MSI Oscillator |
AnnaBridge | 184:08ed48f1de7f | 295 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; |
AnnaBridge | 184:08ed48f1de7f | 296 | RCC_OscInitStruct.MSIState = RCC_MSI_OFF; |
AnnaBridge | 184:08ed48f1de7f | 297 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
AnnaBridge | 184:08ed48f1de7f | 298 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
AnnaBridge | 184:08ed48f1de7f | 299 | |
AnnaBridge | 184:08ed48f1de7f | 300 | /* Select HSI as clock source for LPUART1 */ |
AnnaBridge | 184:08ed48f1de7f | 301 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; |
AnnaBridge | 184:08ed48f1de7f | 302 | RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; |
AnnaBridge | 184:08ed48f1de7f | 303 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 304 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 305 | } |
AnnaBridge | 184:08ed48f1de7f | 306 | |
AnnaBridge | 184:08ed48f1de7f | 307 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 184:08ed48f1de7f | 308 | #if DEBUG_MCO == 3 |
AnnaBridge | 184:08ed48f1de7f | 309 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
AnnaBridge | 184:08ed48f1de7f | 310 | #endif |
AnnaBridge | 184:08ed48f1de7f | 311 | |
AnnaBridge | 184:08ed48f1de7f | 312 | return 1; // OK |
AnnaBridge | 184:08ed48f1de7f | 313 | } |
AnnaBridge | 184:08ed48f1de7f | 314 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
AnnaBridge | 184:08ed48f1de7f | 315 | |
AnnaBridge | 184:08ed48f1de7f | 316 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
AnnaBridge | 184:08ed48f1de7f | 317 | /******************************************************************************/ |
AnnaBridge | 184:08ed48f1de7f | 318 | /* PLL (clocked by MSI) used as System clock source */ |
AnnaBridge | 184:08ed48f1de7f | 319 | /******************************************************************************/ |
AnnaBridge | 184:08ed48f1de7f | 320 | uint8_t SetSysClock_PLL_MSI(void) |
AnnaBridge | 184:08ed48f1de7f | 321 | { |
AnnaBridge | 184:08ed48f1de7f | 322 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
AnnaBridge | 184:08ed48f1de7f | 323 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
AnnaBridge | 184:08ed48f1de7f | 324 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; |
AnnaBridge | 184:08ed48f1de7f | 325 | |
AnnaBridge | 188:bcfe06ba3d64 | 326 | #if MBED_CONF_TARGET_LSE_AVAILABLE |
AnnaBridge | 184:08ed48f1de7f | 327 | // Enable LSE Oscillator to automatically calibrate the MSI clock |
AnnaBridge | 184:08ed48f1de7f | 328 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; |
AnnaBridge | 184:08ed48f1de7f | 329 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
AnnaBridge | 184:08ed48f1de7f | 330 | RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT |
AnnaBridge | 188:bcfe06ba3d64 | 331 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
AnnaBridge | 188:bcfe06ba3d64 | 332 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 333 | } |
AnnaBridge | 184:08ed48f1de7f | 334 | |
AnnaBridge | 188:bcfe06ba3d64 | 335 | /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ |
AnnaBridge | 184:08ed48f1de7f | 336 | HAL_RCCEx_DisableLSECSS(); |
AnnaBridge | 188:bcfe06ba3d64 | 337 | #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ |
AnnaBridge | 188:bcfe06ba3d64 | 338 | |
AnnaBridge | 184:08ed48f1de7f | 339 | /* Enable MSI Oscillator and activate PLL with MSI as source */ |
AnnaBridge | 184:08ed48f1de7f | 340 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
AnnaBridge | 184:08ed48f1de7f | 341 | RCC_OscInitStruct.MSIState = RCC_MSI_ON; |
AnnaBridge | 184:08ed48f1de7f | 342 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
AnnaBridge | 184:08ed48f1de7f | 343 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
AnnaBridge | 184:08ed48f1de7f | 344 | RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; |
AnnaBridge | 184:08ed48f1de7f | 345 | RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 346 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
AnnaBridge | 184:08ed48f1de7f | 347 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; |
AnnaBridge | 184:08ed48f1de7f | 348 | RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 349 | RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 350 | RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 351 | RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 352 | RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 353 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 354 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 355 | } |
AnnaBridge | 188:bcfe06ba3d64 | 356 | |
AnnaBridge | 188:bcfe06ba3d64 | 357 | #if MBED_CONF_TARGET_LSE_AVAILABLE |
AnnaBridge | 184:08ed48f1de7f | 358 | /* Enable MSI Auto-calibration through LSE */ |
AnnaBridge | 184:08ed48f1de7f | 359 | HAL_RCCEx_EnableMSIPLLMode(); |
AnnaBridge | 188:bcfe06ba3d64 | 360 | #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ |
AnnaBridge | 188:bcfe06ba3d64 | 361 | |
AnnaBridge | 184:08ed48f1de7f | 362 | /* Select MSI output as USB clock source */ |
AnnaBridge | 184:08ed48f1de7f | 363 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; |
AnnaBridge | 184:08ed48f1de7f | 364 | PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 365 | HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |
AnnaBridge | 184:08ed48f1de7f | 366 | |
AnnaBridge | 184:08ed48f1de7f | 367 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
AnnaBridge | 184:08ed48f1de7f | 368 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
AnnaBridge | 184:08ed48f1de7f | 369 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 370 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 371 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 372 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 184:08ed48f1de7f | 373 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 374 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 375 | } |
AnnaBridge | 184:08ed48f1de7f | 376 | |
AnnaBridge | 184:08ed48f1de7f | 377 | /* Select LSE as clock source for LPUART1 */ |
AnnaBridge | 184:08ed48f1de7f | 378 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; |
AnnaBridge | 184:08ed48f1de7f | 379 | PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; |
AnnaBridge | 184:08ed48f1de7f | 380 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { |
AnnaBridge | 184:08ed48f1de7f | 381 | return 0; // FAIL |
AnnaBridge | 184:08ed48f1de7f | 382 | } |
AnnaBridge | 184:08ed48f1de7f | 383 | |
AnnaBridge | 184:08ed48f1de7f | 384 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 184:08ed48f1de7f | 385 | #if DEBUG_MCO == 4 |
AnnaBridge | 184:08ed48f1de7f | 386 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz |
AnnaBridge | 184:08ed48f1de7f | 387 | #endif |
AnnaBridge | 184:08ed48f1de7f | 388 | |
AnnaBridge | 184:08ed48f1de7f | 389 | return 1; // OK |
AnnaBridge | 184:08ed48f1de7f | 390 | } |
AnnaBridge | 184:08ed48f1de7f | 391 | #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ |