mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 180:96ed750bd169
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 156:95d6b41a828b | 1 | /** |
<> | 156:95d6b41a828b | 2 | ****************************************************************************** |
<> | 156:95d6b41a828b | 3 | * @file stm32f0xx_ll_rcc.c |
<> | 156:95d6b41a828b | 4 | * @author MCD Application Team |
<> | 156:95d6b41a828b | 5 | * @brief RCC LL module driver. |
<> | 156:95d6b41a828b | 6 | ****************************************************************************** |
<> | 156:95d6b41a828b | 7 | * @attention |
<> | 156:95d6b41a828b | 8 | * |
<> | 156:95d6b41a828b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 156:95d6b41a828b | 10 | * |
<> | 156:95d6b41a828b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 156:95d6b41a828b | 12 | * are permitted provided that the following conditions are met: |
<> | 156:95d6b41a828b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 156:95d6b41a828b | 14 | * this list of conditions and the following disclaimer. |
<> | 156:95d6b41a828b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 156:95d6b41a828b | 16 | * this list of conditions and the following disclaimer in the documentation |
<> | 156:95d6b41a828b | 17 | * and/or other materials provided with the distribution. |
<> | 156:95d6b41a828b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 156:95d6b41a828b | 19 | * may be used to endorse or promote products derived from this software |
<> | 156:95d6b41a828b | 20 | * without specific prior written permission. |
<> | 156:95d6b41a828b | 21 | * |
<> | 156:95d6b41a828b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 156:95d6b41a828b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 156:95d6b41a828b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 156:95d6b41a828b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 156:95d6b41a828b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 156:95d6b41a828b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 156:95d6b41a828b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 156:95d6b41a828b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 156:95d6b41a828b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 156:95d6b41a828b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 156:95d6b41a828b | 32 | * |
<> | 156:95d6b41a828b | 33 | ****************************************************************************** |
<> | 156:95d6b41a828b | 34 | */ |
<> | 156:95d6b41a828b | 35 | #if defined(USE_FULL_LL_DRIVER) |
<> | 156:95d6b41a828b | 36 | |
<> | 156:95d6b41a828b | 37 | /* Includes ------------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 38 | #include "stm32f0xx_ll_rcc.h" |
<> | 156:95d6b41a828b | 39 | #ifdef USE_FULL_ASSERT |
<> | 156:95d6b41a828b | 40 | #include "stm32_assert.h" |
<> | 156:95d6b41a828b | 41 | #else |
<> | 156:95d6b41a828b | 42 | #define assert_param(expr) ((void)0U) |
<> | 156:95d6b41a828b | 43 | #endif /* USE_FULL_ASSERT */ |
<> | 156:95d6b41a828b | 44 | /** @addtogroup STM32F0xx_LL_Driver |
<> | 156:95d6b41a828b | 45 | * @{ |
<> | 156:95d6b41a828b | 46 | */ |
<> | 156:95d6b41a828b | 47 | |
<> | 156:95d6b41a828b | 48 | #if defined(RCC) |
<> | 156:95d6b41a828b | 49 | |
<> | 156:95d6b41a828b | 50 | /** @defgroup RCC_LL RCC |
<> | 156:95d6b41a828b | 51 | * @{ |
<> | 156:95d6b41a828b | 52 | */ |
<> | 156:95d6b41a828b | 53 | |
<> | 156:95d6b41a828b | 54 | /* Private types -------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 55 | /* Private variables ---------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 56 | |
<> | 156:95d6b41a828b | 57 | /* Private constants ---------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 58 | /* Private macros ------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 59 | /** @addtogroup RCC_LL_Private_Macros |
<> | 156:95d6b41a828b | 60 | * @{ |
<> | 156:95d6b41a828b | 61 | */ |
<> | 156:95d6b41a828b | 62 | #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) |
<> | 156:95d6b41a828b | 63 | #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ |
<> | 156:95d6b41a828b | 64 | || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ |
<> | 156:95d6b41a828b | 65 | || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) |
<> | 156:95d6b41a828b | 66 | #elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) |
<> | 156:95d6b41a828b | 67 | #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ |
<> | 156:95d6b41a828b | 68 | || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) |
<> | 156:95d6b41a828b | 69 | #elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) |
<> | 156:95d6b41a828b | 70 | #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ |
<> | 156:95d6b41a828b | 71 | || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) |
<> | 156:95d6b41a828b | 72 | #else |
<> | 156:95d6b41a828b | 73 | #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) |
<> | 156:95d6b41a828b | 74 | #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ |
<> | 156:95d6b41a828b | 75 | |
<> | 156:95d6b41a828b | 76 | #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) |
<> | 156:95d6b41a828b | 77 | |
<> | 156:95d6b41a828b | 78 | #if defined(USB) |
<> | 156:95d6b41a828b | 79 | #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) |
<> | 156:95d6b41a828b | 80 | #endif /* USB */ |
<> | 156:95d6b41a828b | 81 | |
<> | 156:95d6b41a828b | 82 | #if defined(CEC) |
<> | 156:95d6b41a828b | 83 | #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) |
<> | 156:95d6b41a828b | 84 | #endif /* CEC */ |
<> | 156:95d6b41a828b | 85 | |
<> | 156:95d6b41a828b | 86 | /** |
<> | 156:95d6b41a828b | 87 | * @} |
<> | 156:95d6b41a828b | 88 | */ |
<> | 156:95d6b41a828b | 89 | |
<> | 156:95d6b41a828b | 90 | /* Private function prototypes -----------------------------------------------*/ |
<> | 156:95d6b41a828b | 91 | /** @defgroup RCC_LL_Private_Functions RCC Private functions |
<> | 156:95d6b41a828b | 92 | * @{ |
<> | 156:95d6b41a828b | 93 | */ |
<> | 156:95d6b41a828b | 94 | uint32_t RCC_GetSystemClockFreq(void); |
<> | 156:95d6b41a828b | 95 | uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); |
<> | 156:95d6b41a828b | 96 | uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); |
<> | 156:95d6b41a828b | 97 | uint32_t RCC_PLL_GetFreqDomain_SYS(void); |
<> | 156:95d6b41a828b | 98 | /** |
<> | 156:95d6b41a828b | 99 | * @} |
<> | 156:95d6b41a828b | 100 | */ |
<> | 156:95d6b41a828b | 101 | |
<> | 156:95d6b41a828b | 102 | |
<> | 156:95d6b41a828b | 103 | /* Exported functions --------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 104 | /** @addtogroup RCC_LL_Exported_Functions |
<> | 156:95d6b41a828b | 105 | * @{ |
<> | 156:95d6b41a828b | 106 | */ |
<> | 156:95d6b41a828b | 107 | |
<> | 156:95d6b41a828b | 108 | /** @addtogroup RCC_LL_EF_Init |
<> | 156:95d6b41a828b | 109 | * @{ |
<> | 156:95d6b41a828b | 110 | */ |
<> | 156:95d6b41a828b | 111 | |
<> | 156:95d6b41a828b | 112 | /** |
<> | 156:95d6b41a828b | 113 | * @brief Reset the RCC clock configuration to the default reset state. |
<> | 156:95d6b41a828b | 114 | * @note The default reset state of the clock configuration is given below: |
<> | 156:95d6b41a828b | 115 | * - HSI ON and used as system clock source |
<> | 156:95d6b41a828b | 116 | * - HSE and PLL OFF |
<> | 156:95d6b41a828b | 117 | * - AHB and APB1 prescaler set to 1. |
<> | 156:95d6b41a828b | 118 | * - CSS, MCO OFF |
<> | 156:95d6b41a828b | 119 | * - All interrupts disabled |
<> | 156:95d6b41a828b | 120 | * @note This function doesn't modify the configuration of the |
<> | 156:95d6b41a828b | 121 | * - Peripheral clocks |
<> | 156:95d6b41a828b | 122 | * - LSI, LSE and RTC clocks |
<> | 156:95d6b41a828b | 123 | * @retval An ErrorStatus enumeration value: |
<> | 156:95d6b41a828b | 124 | * - SUCCESS: RCC registers are de-initialized |
<> | 156:95d6b41a828b | 125 | * - ERROR: not applicable |
<> | 156:95d6b41a828b | 126 | */ |
<> | 156:95d6b41a828b | 127 | ErrorStatus LL_RCC_DeInit(void) |
<> | 156:95d6b41a828b | 128 | { |
<> | 156:95d6b41a828b | 129 | uint32_t vl_mask = 0U; |
<> | 156:95d6b41a828b | 130 | |
<> | 156:95d6b41a828b | 131 | /* Set HSION bit */ |
<> | 156:95d6b41a828b | 132 | LL_RCC_HSI_Enable(); |
<> | 156:95d6b41a828b | 133 | |
<> | 156:95d6b41a828b | 134 | /* Set HSITRIM bits to the reset value*/ |
<> | 156:95d6b41a828b | 135 | LL_RCC_HSI_SetCalibTrimming(0x10U); |
<> | 156:95d6b41a828b | 136 | |
<> | 156:95d6b41a828b | 137 | /* Reset SW, HPRE, PPRE and MCOSEL bits */ |
<> | 156:95d6b41a828b | 138 | vl_mask = 0xFFFFFFFFU; |
<> | 156:95d6b41a828b | 139 | CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); |
<> | 156:95d6b41a828b | 140 | LL_RCC_WriteReg(CFGR, vl_mask); |
<> | 156:95d6b41a828b | 141 | |
<> | 156:95d6b41a828b | 142 | /* Reset HSEON, CSSON, PLLON bits */ |
<> | 156:95d6b41a828b | 143 | vl_mask = 0xFFFFFFFFU; |
<> | 156:95d6b41a828b | 144 | CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); |
<> | 156:95d6b41a828b | 145 | LL_RCC_WriteReg(CR, vl_mask); |
<> | 156:95d6b41a828b | 146 | |
<> | 156:95d6b41a828b | 147 | /* Reset HSEBYP bit */ |
<> | 156:95d6b41a828b | 148 | LL_RCC_HSE_DisableBypass(); |
Anna Bridge |
180:96ed750bd169 | 149 | |
<> | 156:95d6b41a828b | 150 | /* Reset CFGR register */ |
<> | 156:95d6b41a828b | 151 | LL_RCC_WriteReg(CFGR, 0x00000000U); |
<> | 156:95d6b41a828b | 152 | |
<> | 156:95d6b41a828b | 153 | #if defined(RCC_HSI48_SUPPORT) |
<> | 156:95d6b41a828b | 154 | /* Reset CR2 register */ |
<> | 156:95d6b41a828b | 155 | LL_RCC_WriteReg(CR2, 0x00000000U); |
<> | 156:95d6b41a828b | 156 | |
<> | 156:95d6b41a828b | 157 | /* Disable HSI48 */ |
<> | 156:95d6b41a828b | 158 | LL_RCC_HSI48_Disable(); |
<> | 156:95d6b41a828b | 159 | |
<> | 156:95d6b41a828b | 160 | #endif /*RCC_HSI48_SUPPORT*/ |
<> | 156:95d6b41a828b | 161 | /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ |
<> | 156:95d6b41a828b | 162 | LL_RCC_HSI14_SetCalibTrimming(0x10U); |
<> | 156:95d6b41a828b | 163 | LL_RCC_HSI14_Disable(); |
<> | 156:95d6b41a828b | 164 | LL_RCC_HSI14_EnableADCControl(); |
<> | 156:95d6b41a828b | 165 | |
<> | 156:95d6b41a828b | 166 | /* Reset CFGR2 register */ |
<> | 156:95d6b41a828b | 167 | LL_RCC_WriteReg(CFGR2, 0x00000000U); |
<> | 156:95d6b41a828b | 168 | |
<> | 156:95d6b41a828b | 169 | /* Reset CFGR3 register */ |
<> | 156:95d6b41a828b | 170 | LL_RCC_WriteReg(CFGR3, 0x00000000U); |
<> | 156:95d6b41a828b | 171 | |
<> | 156:95d6b41a828b | 172 | /* Clear pending flags */ |
<> | 156:95d6b41a828b | 173 | #if defined(RCC_HSI48_SUPPORT) |
<> | 156:95d6b41a828b | 174 | vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); |
<> | 156:95d6b41a828b | 175 | #else |
<> | 156:95d6b41a828b | 176 | vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); |
<> | 156:95d6b41a828b | 177 | #endif /* RCC_HSI48_SUPPORT */ |
<> | 156:95d6b41a828b | 178 | SET_BIT(RCC->CIR, vl_mask); |
<> | 156:95d6b41a828b | 179 | |
<> | 156:95d6b41a828b | 180 | /* Disable all interrupts */ |
<> | 156:95d6b41a828b | 181 | LL_RCC_WriteReg(CIR, 0x00000000U); |
<> | 156:95d6b41a828b | 182 | |
<> | 156:95d6b41a828b | 183 | return SUCCESS; |
<> | 156:95d6b41a828b | 184 | } |
<> | 156:95d6b41a828b | 185 | |
<> | 156:95d6b41a828b | 186 | /** |
<> | 156:95d6b41a828b | 187 | * @} |
<> | 156:95d6b41a828b | 188 | */ |
<> | 156:95d6b41a828b | 189 | |
<> | 156:95d6b41a828b | 190 | /** @addtogroup RCC_LL_EF_Get_Freq |
<> | 156:95d6b41a828b | 191 | * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks |
<> | 156:95d6b41a828b | 192 | * and different peripheral clocks available on the device. |
<> | 156:95d6b41a828b | 193 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) |
<> | 156:95d6b41a828b | 194 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) |
<> | 156:95d6b41a828b | 195 | * @note If SYSCLK source is PLL, function returns values based on |
<> | 156:95d6b41a828b | 196 | * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. |
<> | 156:95d6b41a828b | 197 | * @note (**) HSI_VALUE is a defined constant but the real value may vary |
<> | 156:95d6b41a828b | 198 | * depending on the variations in voltage and temperature. |
<> | 156:95d6b41a828b | 199 | * @note (***) HSE_VALUE is a defined constant, user has to ensure that |
<> | 156:95d6b41a828b | 200 | * HSE_VALUE is same as the real frequency of the crystal used. |
<> | 156:95d6b41a828b | 201 | * Otherwise, this function may have wrong result. |
<> | 156:95d6b41a828b | 202 | * @note The result of this function could be incorrect when using fractional |
<> | 156:95d6b41a828b | 203 | * value for HSE crystal. |
<> | 156:95d6b41a828b | 204 | * @note This function can be used by the user application to compute the |
<> | 156:95d6b41a828b | 205 | * baud-rate for the communication peripherals or configure other parameters. |
<> | 156:95d6b41a828b | 206 | * @{ |
<> | 156:95d6b41a828b | 207 | */ |
<> | 156:95d6b41a828b | 208 | |
<> | 156:95d6b41a828b | 209 | /** |
<> | 156:95d6b41a828b | 210 | * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks |
<> | 156:95d6b41a828b | 211 | * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function |
<> | 156:95d6b41a828b | 212 | * must be called to update structure fields. Otherwise, any |
<> | 156:95d6b41a828b | 213 | * configuration based on this function will be incorrect. |
<> | 156:95d6b41a828b | 214 | * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies |
<> | 156:95d6b41a828b | 215 | * @retval None |
<> | 156:95d6b41a828b | 216 | */ |
<> | 156:95d6b41a828b | 217 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) |
<> | 156:95d6b41a828b | 218 | { |
<> | 156:95d6b41a828b | 219 | /* Get SYSCLK frequency */ |
<> | 156:95d6b41a828b | 220 | RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); |
<> | 156:95d6b41a828b | 221 | |
<> | 156:95d6b41a828b | 222 | /* HCLK clock frequency */ |
<> | 156:95d6b41a828b | 223 | RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); |
<> | 156:95d6b41a828b | 224 | |
<> | 156:95d6b41a828b | 225 | /* PCLK1 clock frequency */ |
<> | 156:95d6b41a828b | 226 | RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); |
<> | 156:95d6b41a828b | 227 | } |
<> | 156:95d6b41a828b | 228 | |
<> | 156:95d6b41a828b | 229 | /** |
<> | 156:95d6b41a828b | 230 | * @brief Return USARTx clock frequency |
<> | 156:95d6b41a828b | 231 | * @param USARTxSource This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 232 | * @arg @ref LL_RCC_USART1_CLKSOURCE |
<> | 156:95d6b41a828b | 233 | * @arg @ref LL_RCC_USART2_CLKSOURCE (*) |
<> | 156:95d6b41a828b | 234 | * @arg @ref LL_RCC_USART3_CLKSOURCE (*) |
<> | 156:95d6b41a828b | 235 | * |
<> | 156:95d6b41a828b | 236 | * (*) value not defined in all devices. |
<> | 156:95d6b41a828b | 237 | * @retval USART clock frequency (in Hz) |
<> | 156:95d6b41a828b | 238 | * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready |
<> | 156:95d6b41a828b | 239 | */ |
<> | 156:95d6b41a828b | 240 | uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) |
<> | 156:95d6b41a828b | 241 | { |
<> | 156:95d6b41a828b | 242 | uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
<> | 156:95d6b41a828b | 243 | |
<> | 156:95d6b41a828b | 244 | /* Check parameter */ |
<> | 156:95d6b41a828b | 245 | assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); |
<> | 156:95d6b41a828b | 246 | #if defined(RCC_CFGR3_USART1SW) |
<> | 156:95d6b41a828b | 247 | if (USARTxSource == LL_RCC_USART1_CLKSOURCE) |
<> | 156:95d6b41a828b | 248 | { |
<> | 156:95d6b41a828b | 249 | /* USART1CLK clock frequency */ |
<> | 156:95d6b41a828b | 250 | switch (LL_RCC_GetUSARTClockSource(USARTxSource)) |
<> | 156:95d6b41a828b | 251 | { |
<> | 156:95d6b41a828b | 252 | case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ |
<> | 156:95d6b41a828b | 253 | usart_frequency = RCC_GetSystemClockFreq(); |
<> | 156:95d6b41a828b | 254 | break; |
<> | 156:95d6b41a828b | 255 | |
<> | 156:95d6b41a828b | 256 | case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ |
<> | 156:95d6b41a828b | 257 | if (LL_RCC_HSI_IsReady()) |
<> | 156:95d6b41a828b | 258 | { |
<> | 156:95d6b41a828b | 259 | usart_frequency = HSI_VALUE; |
<> | 156:95d6b41a828b | 260 | } |
<> | 156:95d6b41a828b | 261 | break; |
<> | 156:95d6b41a828b | 262 | |
<> | 156:95d6b41a828b | 263 | case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ |
<> | 156:95d6b41a828b | 264 | if (LL_RCC_LSE_IsReady()) |
<> | 156:95d6b41a828b | 265 | { |
<> | 156:95d6b41a828b | 266 | usart_frequency = LSE_VALUE; |
<> | 156:95d6b41a828b | 267 | } |
<> | 156:95d6b41a828b | 268 | break; |
<> | 156:95d6b41a828b | 269 | |
<> | 156:95d6b41a828b | 270 | case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ |
<> | 156:95d6b41a828b | 271 | default: |
<> | 156:95d6b41a828b | 272 | usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
<> | 156:95d6b41a828b | 273 | break; |
<> | 156:95d6b41a828b | 274 | } |
<> | 156:95d6b41a828b | 275 | } |
<> | 156:95d6b41a828b | 276 | #endif /* RCC_CFGR3_USART1SW */ |
<> | 156:95d6b41a828b | 277 | |
<> | 156:95d6b41a828b | 278 | #if defined(RCC_CFGR3_USART2SW) |
<> | 156:95d6b41a828b | 279 | if (USARTxSource == LL_RCC_USART2_CLKSOURCE) |
<> | 156:95d6b41a828b | 280 | { |
<> | 156:95d6b41a828b | 281 | /* USART2CLK clock frequency */ |
<> | 156:95d6b41a828b | 282 | switch (LL_RCC_GetUSARTClockSource(USARTxSource)) |
<> | 156:95d6b41a828b | 283 | { |
<> | 156:95d6b41a828b | 284 | case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ |
<> | 156:95d6b41a828b | 285 | usart_frequency = RCC_GetSystemClockFreq(); |
<> | 156:95d6b41a828b | 286 | break; |
<> | 156:95d6b41a828b | 287 | |
<> | 156:95d6b41a828b | 288 | case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ |
<> | 156:95d6b41a828b | 289 | if (LL_RCC_HSI_IsReady()) |
<> | 156:95d6b41a828b | 290 | { |
<> | 156:95d6b41a828b | 291 | usart_frequency = HSI_VALUE; |
<> | 156:95d6b41a828b | 292 | } |
<> | 156:95d6b41a828b | 293 | break; |
<> | 156:95d6b41a828b | 294 | |
<> | 156:95d6b41a828b | 295 | case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ |
<> | 156:95d6b41a828b | 296 | if (LL_RCC_LSE_IsReady()) |
<> | 156:95d6b41a828b | 297 | { |
<> | 156:95d6b41a828b | 298 | usart_frequency = LSE_VALUE; |
<> | 156:95d6b41a828b | 299 | } |
<> | 156:95d6b41a828b | 300 | break; |
<> | 156:95d6b41a828b | 301 | |
<> | 156:95d6b41a828b | 302 | case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ |
<> | 156:95d6b41a828b | 303 | default: |
<> | 156:95d6b41a828b | 304 | usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
<> | 156:95d6b41a828b | 305 | break; |
<> | 156:95d6b41a828b | 306 | } |
<> | 156:95d6b41a828b | 307 | } |
<> | 156:95d6b41a828b | 308 | #endif /* RCC_CFGR3_USART2SW */ |
<> | 156:95d6b41a828b | 309 | |
<> | 156:95d6b41a828b | 310 | #if defined(RCC_CFGR3_USART3SW) |
<> | 156:95d6b41a828b | 311 | if (USARTxSource == LL_RCC_USART3_CLKSOURCE) |
<> | 156:95d6b41a828b | 312 | { |
<> | 156:95d6b41a828b | 313 | /* USART3CLK clock frequency */ |
<> | 156:95d6b41a828b | 314 | switch (LL_RCC_GetUSARTClockSource(USARTxSource)) |
<> | 156:95d6b41a828b | 315 | { |
<> | 156:95d6b41a828b | 316 | case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ |
<> | 156:95d6b41a828b | 317 | usart_frequency = RCC_GetSystemClockFreq(); |
<> | 156:95d6b41a828b | 318 | break; |
<> | 156:95d6b41a828b | 319 | |
<> | 156:95d6b41a828b | 320 | case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ |
<> | 156:95d6b41a828b | 321 | if (LL_RCC_HSI_IsReady()) |
<> | 156:95d6b41a828b | 322 | { |
<> | 156:95d6b41a828b | 323 | usart_frequency = HSI_VALUE; |
<> | 156:95d6b41a828b | 324 | } |
<> | 156:95d6b41a828b | 325 | break; |
<> | 156:95d6b41a828b | 326 | |
<> | 156:95d6b41a828b | 327 | case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ |
<> | 156:95d6b41a828b | 328 | if (LL_RCC_LSE_IsReady()) |
<> | 156:95d6b41a828b | 329 | { |
<> | 156:95d6b41a828b | 330 | usart_frequency = LSE_VALUE; |
<> | 156:95d6b41a828b | 331 | } |
<> | 156:95d6b41a828b | 332 | break; |
<> | 156:95d6b41a828b | 333 | |
<> | 156:95d6b41a828b | 334 | case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ |
<> | 156:95d6b41a828b | 335 | default: |
<> | 156:95d6b41a828b | 336 | usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
<> | 156:95d6b41a828b | 337 | break; |
<> | 156:95d6b41a828b | 338 | } |
<> | 156:95d6b41a828b | 339 | } |
<> | 156:95d6b41a828b | 340 | |
<> | 156:95d6b41a828b | 341 | #endif /* RCC_CFGR3_USART3SW */ |
<> | 156:95d6b41a828b | 342 | return usart_frequency; |
<> | 156:95d6b41a828b | 343 | } |
<> | 156:95d6b41a828b | 344 | |
<> | 156:95d6b41a828b | 345 | /** |
<> | 156:95d6b41a828b | 346 | * @brief Return I2Cx clock frequency |
<> | 156:95d6b41a828b | 347 | * @param I2CxSource This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 348 | * @arg @ref LL_RCC_I2C1_CLKSOURCE |
<> | 156:95d6b41a828b | 349 | * @retval I2C clock frequency (in Hz) |
<> | 156:95d6b41a828b | 350 | * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready |
<> | 156:95d6b41a828b | 351 | */ |
<> | 156:95d6b41a828b | 352 | uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) |
<> | 156:95d6b41a828b | 353 | { |
<> | 156:95d6b41a828b | 354 | uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
<> | 156:95d6b41a828b | 355 | |
<> | 156:95d6b41a828b | 356 | /* Check parameter */ |
<> | 156:95d6b41a828b | 357 | assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); |
<> | 156:95d6b41a828b | 358 | |
<> | 156:95d6b41a828b | 359 | /* I2C1 CLK clock frequency */ |
<> | 156:95d6b41a828b | 360 | if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) |
<> | 156:95d6b41a828b | 361 | { |
<> | 156:95d6b41a828b | 362 | switch (LL_RCC_GetI2CClockSource(I2CxSource)) |
<> | 156:95d6b41a828b | 363 | { |
<> | 156:95d6b41a828b | 364 | case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ |
<> | 156:95d6b41a828b | 365 | i2c_frequency = RCC_GetSystemClockFreq(); |
<> | 156:95d6b41a828b | 366 | break; |
<> | 156:95d6b41a828b | 367 | |
<> | 156:95d6b41a828b | 368 | case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ |
<> | 156:95d6b41a828b | 369 | default: |
<> | 156:95d6b41a828b | 370 | if (LL_RCC_HSI_IsReady()) |
<> | 156:95d6b41a828b | 371 | { |
<> | 156:95d6b41a828b | 372 | i2c_frequency = HSI_VALUE; |
<> | 156:95d6b41a828b | 373 | } |
<> | 156:95d6b41a828b | 374 | break; |
<> | 156:95d6b41a828b | 375 | } |
<> | 156:95d6b41a828b | 376 | } |
<> | 156:95d6b41a828b | 377 | |
<> | 156:95d6b41a828b | 378 | return i2c_frequency; |
<> | 156:95d6b41a828b | 379 | } |
<> | 156:95d6b41a828b | 380 | |
<> | 156:95d6b41a828b | 381 | #if defined(USB) |
<> | 156:95d6b41a828b | 382 | /** |
<> | 156:95d6b41a828b | 383 | * @brief Return USBx clock frequency |
<> | 156:95d6b41a828b | 384 | * @param USBxSource This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 385 | * @arg @ref LL_RCC_USB_CLKSOURCE |
<> | 156:95d6b41a828b | 386 | * @retval USB clock frequency (in Hz) |
<> | 156:95d6b41a828b | 387 | * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready |
<> | 156:95d6b41a828b | 388 | * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected |
<> | 156:95d6b41a828b | 389 | */ |
<> | 156:95d6b41a828b | 390 | uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) |
<> | 156:95d6b41a828b | 391 | { |
<> | 156:95d6b41a828b | 392 | uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
<> | 156:95d6b41a828b | 393 | |
<> | 156:95d6b41a828b | 394 | /* Check parameter */ |
<> | 156:95d6b41a828b | 395 | assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); |
<> | 156:95d6b41a828b | 396 | |
<> | 156:95d6b41a828b | 397 | /* USBCLK clock frequency */ |
<> | 156:95d6b41a828b | 398 | switch (LL_RCC_GetUSBClockSource(USBxSource)) |
<> | 156:95d6b41a828b | 399 | { |
<> | 156:95d6b41a828b | 400 | case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ |
<> | 156:95d6b41a828b | 401 | if (LL_RCC_PLL_IsReady()) |
<> | 156:95d6b41a828b | 402 | { |
<> | 156:95d6b41a828b | 403 | usb_frequency = RCC_PLL_GetFreqDomain_SYS(); |
<> | 156:95d6b41a828b | 404 | } |
<> | 156:95d6b41a828b | 405 | break; |
<> | 156:95d6b41a828b | 406 | |
<> | 156:95d6b41a828b | 407 | #if defined(RCC_CFGR3_USBSW_HSI48) |
<> | 156:95d6b41a828b | 408 | case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ |
<> | 156:95d6b41a828b | 409 | default: |
<> | 156:95d6b41a828b | 410 | if (LL_RCC_HSI48_IsReady()) |
<> | 156:95d6b41a828b | 411 | { |
<> | 156:95d6b41a828b | 412 | usb_frequency = HSI48_VALUE; |
<> | 156:95d6b41a828b | 413 | } |
<> | 156:95d6b41a828b | 414 | break; |
<> | 156:95d6b41a828b | 415 | #else |
<> | 156:95d6b41a828b | 416 | case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ |
<> | 156:95d6b41a828b | 417 | default: |
<> | 156:95d6b41a828b | 418 | usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; |
<> | 156:95d6b41a828b | 419 | break; |
<> | 156:95d6b41a828b | 420 | #endif /* RCC_CFGR3_USBSW_HSI48 */ |
<> | 156:95d6b41a828b | 421 | } |
<> | 156:95d6b41a828b | 422 | |
<> | 156:95d6b41a828b | 423 | return usb_frequency; |
<> | 156:95d6b41a828b | 424 | } |
<> | 156:95d6b41a828b | 425 | #endif /* USB */ |
<> | 156:95d6b41a828b | 426 | |
<> | 156:95d6b41a828b | 427 | #if defined(CEC) |
<> | 156:95d6b41a828b | 428 | /** |
<> | 156:95d6b41a828b | 429 | * @brief Return CECx clock frequency |
<> | 156:95d6b41a828b | 430 | * @param CECxSource This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 431 | * @arg @ref LL_RCC_CEC_CLKSOURCE |
<> | 156:95d6b41a828b | 432 | * @retval CEC clock frequency (in Hz) |
<> | 156:95d6b41a828b | 433 | * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready |
<> | 156:95d6b41a828b | 434 | */ |
<> | 156:95d6b41a828b | 435 | uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) |
<> | 156:95d6b41a828b | 436 | { |
<> | 156:95d6b41a828b | 437 | uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
<> | 156:95d6b41a828b | 438 | |
<> | 156:95d6b41a828b | 439 | /* Check parameter */ |
<> | 156:95d6b41a828b | 440 | assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); |
<> | 156:95d6b41a828b | 441 | |
<> | 156:95d6b41a828b | 442 | /* CECCLK clock frequency */ |
<> | 156:95d6b41a828b | 443 | switch (LL_RCC_GetCECClockSource(CECxSource)) |
<> | 156:95d6b41a828b | 444 | { |
<> | 156:95d6b41a828b | 445 | case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ |
<> | 156:95d6b41a828b | 446 | if (LL_RCC_HSI_IsReady()) |
<> | 156:95d6b41a828b | 447 | { |
<> | 156:95d6b41a828b | 448 | cec_frequency = HSI_VALUE / 244U; |
<> | 156:95d6b41a828b | 449 | } |
<> | 156:95d6b41a828b | 450 | break; |
<> | 156:95d6b41a828b | 451 | |
<> | 156:95d6b41a828b | 452 | case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ |
<> | 156:95d6b41a828b | 453 | default: |
<> | 156:95d6b41a828b | 454 | if (LL_RCC_LSE_IsReady()) |
<> | 156:95d6b41a828b | 455 | { |
<> | 156:95d6b41a828b | 456 | cec_frequency = LSE_VALUE; |
<> | 156:95d6b41a828b | 457 | } |
<> | 156:95d6b41a828b | 458 | break; |
<> | 156:95d6b41a828b | 459 | } |
<> | 156:95d6b41a828b | 460 | |
<> | 156:95d6b41a828b | 461 | return cec_frequency; |
<> | 156:95d6b41a828b | 462 | } |
<> | 156:95d6b41a828b | 463 | #endif /* CEC */ |
<> | 156:95d6b41a828b | 464 | |
<> | 156:95d6b41a828b | 465 | /** |
<> | 156:95d6b41a828b | 466 | * @} |
<> | 156:95d6b41a828b | 467 | */ |
<> | 156:95d6b41a828b | 468 | |
<> | 156:95d6b41a828b | 469 | /** |
<> | 156:95d6b41a828b | 470 | * @} |
<> | 156:95d6b41a828b | 471 | */ |
<> | 156:95d6b41a828b | 472 | |
<> | 156:95d6b41a828b | 473 | /** @addtogroup RCC_LL_Private_Functions |
<> | 156:95d6b41a828b | 474 | * @{ |
<> | 156:95d6b41a828b | 475 | */ |
<> | 156:95d6b41a828b | 476 | |
<> | 156:95d6b41a828b | 477 | /** |
<> | 156:95d6b41a828b | 478 | * @brief Return SYSTEM clock frequency |
<> | 156:95d6b41a828b | 479 | * @retval SYSTEM clock frequency (in Hz) |
<> | 156:95d6b41a828b | 480 | */ |
<> | 156:95d6b41a828b | 481 | uint32_t RCC_GetSystemClockFreq(void) |
<> | 156:95d6b41a828b | 482 | { |
<> | 156:95d6b41a828b | 483 | uint32_t frequency = 0U; |
<> | 156:95d6b41a828b | 484 | |
<> | 156:95d6b41a828b | 485 | /* Get SYSCLK source -------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 486 | switch (LL_RCC_GetSysClkSource()) |
<> | 156:95d6b41a828b | 487 | { |
<> | 156:95d6b41a828b | 488 | case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ |
<> | 156:95d6b41a828b | 489 | frequency = HSI_VALUE; |
<> | 156:95d6b41a828b | 490 | break; |
<> | 156:95d6b41a828b | 491 | |
<> | 156:95d6b41a828b | 492 | case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ |
<> | 156:95d6b41a828b | 493 | frequency = HSE_VALUE; |
<> | 156:95d6b41a828b | 494 | break; |
<> | 156:95d6b41a828b | 495 | |
<> | 156:95d6b41a828b | 496 | case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ |
<> | 156:95d6b41a828b | 497 | frequency = RCC_PLL_GetFreqDomain_SYS(); |
<> | 156:95d6b41a828b | 498 | break; |
<> | 156:95d6b41a828b | 499 | |
Anna Bridge |
180:96ed750bd169 | 500 | #if defined(RCC_HSI48_SUPPORT) |
Anna Bridge |
180:96ed750bd169 | 501 | case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ |
Anna Bridge |
180:96ed750bd169 | 502 | frequency = HSI48_VALUE; |
Anna Bridge |
180:96ed750bd169 | 503 | break; |
Anna Bridge |
180:96ed750bd169 | 504 | #endif /* RCC_HSI48_SUPPORT */ |
Anna Bridge |
180:96ed750bd169 | 505 | |
<> | 156:95d6b41a828b | 506 | default: |
<> | 156:95d6b41a828b | 507 | frequency = HSI_VALUE; |
<> | 156:95d6b41a828b | 508 | break; |
<> | 156:95d6b41a828b | 509 | } |
<> | 156:95d6b41a828b | 510 | |
<> | 156:95d6b41a828b | 511 | return frequency; |
<> | 156:95d6b41a828b | 512 | } |
<> | 156:95d6b41a828b | 513 | |
<> | 156:95d6b41a828b | 514 | /** |
<> | 156:95d6b41a828b | 515 | * @brief Return HCLK clock frequency |
<> | 156:95d6b41a828b | 516 | * @param SYSCLK_Frequency SYSCLK clock frequency |
<> | 156:95d6b41a828b | 517 | * @retval HCLK clock frequency (in Hz) |
<> | 156:95d6b41a828b | 518 | */ |
<> | 156:95d6b41a828b | 519 | uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) |
<> | 156:95d6b41a828b | 520 | { |
<> | 156:95d6b41a828b | 521 | /* HCLK clock frequency */ |
<> | 156:95d6b41a828b | 522 | return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); |
<> | 156:95d6b41a828b | 523 | } |
<> | 156:95d6b41a828b | 524 | |
<> | 156:95d6b41a828b | 525 | /** |
<> | 156:95d6b41a828b | 526 | * @brief Return PCLK1 clock frequency |
<> | 156:95d6b41a828b | 527 | * @param HCLK_Frequency HCLK clock frequency |
<> | 156:95d6b41a828b | 528 | * @retval PCLK1 clock frequency (in Hz) |
<> | 156:95d6b41a828b | 529 | */ |
<> | 156:95d6b41a828b | 530 | uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) |
<> | 156:95d6b41a828b | 531 | { |
<> | 156:95d6b41a828b | 532 | /* PCLK1 clock frequency */ |
<> | 156:95d6b41a828b | 533 | return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); |
<> | 156:95d6b41a828b | 534 | } |
<> | 156:95d6b41a828b | 535 | /** |
<> | 156:95d6b41a828b | 536 | * @brief Return PLL clock frequency used for system domain |
<> | 156:95d6b41a828b | 537 | * @retval PLL clock frequency (in Hz) |
<> | 156:95d6b41a828b | 538 | */ |
<> | 156:95d6b41a828b | 539 | uint32_t RCC_PLL_GetFreqDomain_SYS(void) |
<> | 156:95d6b41a828b | 540 | { |
<> | 156:95d6b41a828b | 541 | uint32_t pllinputfreq = 0U, pllsource = 0U; |
<> | 156:95d6b41a828b | 542 | |
<> | 156:95d6b41a828b | 543 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ |
<> | 156:95d6b41a828b | 544 | |
<> | 156:95d6b41a828b | 545 | /* Get PLL source */ |
<> | 156:95d6b41a828b | 546 | pllsource = LL_RCC_PLL_GetMainSource(); |
<> | 156:95d6b41a828b | 547 | |
<> | 156:95d6b41a828b | 548 | switch (pllsource) |
<> | 156:95d6b41a828b | 549 | { |
<> | 156:95d6b41a828b | 550 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
<> | 156:95d6b41a828b | 551 | case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ |
<> | 156:95d6b41a828b | 552 | pllinputfreq = HSI_VALUE; |
<> | 156:95d6b41a828b | 553 | #else |
<> | 156:95d6b41a828b | 554 | case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ |
Anna Bridge |
180:96ed750bd169 | 555 | pllinputfreq = HSI_VALUE / 2U; |
<> | 156:95d6b41a828b | 556 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
<> | 156:95d6b41a828b | 557 | break; |
<> | 156:95d6b41a828b | 558 | |
Anna Bridge |
180:96ed750bd169 | 559 | #if defined(RCC_HSI48_SUPPORT) |
<> | 156:95d6b41a828b | 560 | case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ |
<> | 156:95d6b41a828b | 561 | pllinputfreq = HSI48_VALUE; |
<> | 156:95d6b41a828b | 562 | break; |
Anna Bridge |
180:96ed750bd169 | 563 | #endif /* RCC_HSI48_SUPPORT */ |
<> | 156:95d6b41a828b | 564 | |
<> | 156:95d6b41a828b | 565 | case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ |
<> | 156:95d6b41a828b | 566 | pllinputfreq = HSE_VALUE; |
<> | 156:95d6b41a828b | 567 | break; |
<> | 156:95d6b41a828b | 568 | |
<> | 156:95d6b41a828b | 569 | default: |
<> | 156:95d6b41a828b | 570 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
<> | 156:95d6b41a828b | 571 | pllinputfreq = HSI_VALUE; |
<> | 156:95d6b41a828b | 572 | #else |
Anna Bridge |
180:96ed750bd169 | 573 | pllinputfreq = HSI_VALUE / 2U; |
<> | 156:95d6b41a828b | 574 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
<> | 156:95d6b41a828b | 575 | break; |
<> | 156:95d6b41a828b | 576 | } |
<> | 156:95d6b41a828b | 577 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
<> | 156:95d6b41a828b | 578 | return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); |
<> | 156:95d6b41a828b | 579 | #else |
<> | 156:95d6b41a828b | 580 | return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); |
<> | 156:95d6b41a828b | 581 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
<> | 156:95d6b41a828b | 582 | } |
<> | 156:95d6b41a828b | 583 | /** |
<> | 156:95d6b41a828b | 584 | * @} |
<> | 156:95d6b41a828b | 585 | */ |
<> | 156:95d6b41a828b | 586 | |
<> | 156:95d6b41a828b | 587 | /** |
<> | 156:95d6b41a828b | 588 | * @} |
<> | 156:95d6b41a828b | 589 | */ |
<> | 156:95d6b41a828b | 590 | |
<> | 156:95d6b41a828b | 591 | #endif /* defined(RCC) */ |
<> | 156:95d6b41a828b | 592 | |
<> | 156:95d6b41a828b | 593 | /** |
<> | 156:95d6b41a828b | 594 | * @} |
<> | 156:95d6b41a828b | 595 | */ |
<> | 156:95d6b41a828b | 596 | |
<> | 156:95d6b41a828b | 597 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 156:95d6b41a828b | 598 | |
<> | 156:95d6b41a828b | 599 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |