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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_A/irq_ctrl.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 180:96ed750bd169 1 /**************************************************************************//**
Anna Bridge 180:96ed750bd169 2 * @file irq_ctrl.h
Anna Bridge 180:96ed750bd169 3 * @brief Interrupt Controller API header file
Anna Bridge 180:96ed750bd169 4 * @version V1.0.0
Anna Bridge 180:96ed750bd169 5 * @date 23. June 2017
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 180:96ed750bd169 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 186:707f6e361f3e 25 #if defined ( __ICCARM__ )
Anna Bridge 186:707f6e361f3e 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 186:707f6e361f3e 27 #elif defined (__clang__)
Anna Bridge 186:707f6e361f3e 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 186:707f6e361f3e 29 #endif
Anna Bridge 186:707f6e361f3e 30
Anna Bridge 180:96ed750bd169 31 #ifndef IRQ_CTRL_H_
Anna Bridge 180:96ed750bd169 32 #define IRQ_CTRL_H_
Anna Bridge 180:96ed750bd169 33
Anna Bridge 180:96ed750bd169 34 #include <stdint.h>
Anna Bridge 180:96ed750bd169 35
Anna Bridge 180:96ed750bd169 36 #ifndef IRQHANDLER_T
Anna Bridge 180:96ed750bd169 37 #define IRQHANDLER_T
Anna Bridge 180:96ed750bd169 38 /// Interrupt handler data type
Anna Bridge 180:96ed750bd169 39 typedef void (*IRQHandler_t) (void);
Anna Bridge 180:96ed750bd169 40 #endif
Anna Bridge 180:96ed750bd169 41
Anna Bridge 180:96ed750bd169 42 #ifndef IRQN_ID_T
Anna Bridge 180:96ed750bd169 43 #define IRQN_ID_T
Anna Bridge 180:96ed750bd169 44 /// Interrupt ID number data type
Anna Bridge 180:96ed750bd169 45 typedef int32_t IRQn_ID_t;
Anna Bridge 180:96ed750bd169 46 #endif
Anna Bridge 180:96ed750bd169 47
Anna Bridge 180:96ed750bd169 48 /* Interrupt mode bit-masks */
Anna Bridge 180:96ed750bd169 49 #define IRQ_MODE_TRIG_Pos (0U)
Anna Bridge 180:96ed750bd169 50 #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
Anna Bridge 180:96ed750bd169 51 #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
Anna Bridge 180:96ed750bd169 52 #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
Anna Bridge 180:96ed750bd169 53 #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
Anna Bridge 180:96ed750bd169 54 #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
Anna Bridge 180:96ed750bd169 55 #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
Anna Bridge 180:96ed750bd169 56 #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
Anna Bridge 180:96ed750bd169 57 #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
Anna Bridge 180:96ed750bd169 58
Anna Bridge 180:96ed750bd169 59 #define IRQ_MODE_TYPE_Pos (3U)
Anna Bridge 180:96ed750bd169 60 #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
Anna Bridge 180:96ed750bd169 61 #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
Anna Bridge 180:96ed750bd169 62 #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
Anna Bridge 180:96ed750bd169 63
Anna Bridge 180:96ed750bd169 64 #define IRQ_MODE_DOMAIN_Pos (4U)
Anna Bridge 180:96ed750bd169 65 #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
Anna Bridge 180:96ed750bd169 66 #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
Anna Bridge 180:96ed750bd169 67 #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
Anna Bridge 180:96ed750bd169 68
Anna Bridge 180:96ed750bd169 69 #define IRQ_MODE_CPU_Pos (5U)
Anna Bridge 180:96ed750bd169 70 #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
Anna Bridge 180:96ed750bd169 71 #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
Anna Bridge 180:96ed750bd169 72 #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
Anna Bridge 180:96ed750bd169 73 #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
Anna Bridge 180:96ed750bd169 74 #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
Anna Bridge 180:96ed750bd169 75 #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
Anna Bridge 180:96ed750bd169 76 #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
Anna Bridge 180:96ed750bd169 77 #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
Anna Bridge 180:96ed750bd169 78 #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
Anna Bridge 180:96ed750bd169 79 #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
Anna Bridge 180:96ed750bd169 80
Anna Bridge 180:96ed750bd169 81 #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
Anna Bridge 180:96ed750bd169 82
Anna Bridge 180:96ed750bd169 83 /* Interrupt priority bit-masks */
Anna Bridge 180:96ed750bd169 84 #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
Anna Bridge 180:96ed750bd169 85 #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
Anna Bridge 180:96ed750bd169 86
Anna Bridge 180:96ed750bd169 87 /// Initialize interrupt controller.
Anna Bridge 180:96ed750bd169 88 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 89 int32_t IRQ_Initialize (void);
Anna Bridge 180:96ed750bd169 90
Anna Bridge 180:96ed750bd169 91 /// Register interrupt handler.
Anna Bridge 180:96ed750bd169 92 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 93 /// \param[in] handler interrupt handler function address
Anna Bridge 180:96ed750bd169 94 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 95 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
Anna Bridge 180:96ed750bd169 96
Anna Bridge 180:96ed750bd169 97 /// Get the registered interrupt handler.
Anna Bridge 180:96ed750bd169 98 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 99 /// \return registered interrupt handler function address.
Anna Bridge 180:96ed750bd169 100 IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 101
Anna Bridge 180:96ed750bd169 102 /// Enable interrupt.
Anna Bridge 180:96ed750bd169 103 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 104 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 105 int32_t IRQ_Enable (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 106
Anna Bridge 180:96ed750bd169 107 /// Disable interrupt.
Anna Bridge 180:96ed750bd169 108 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 109 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 110 int32_t IRQ_Disable (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 111
Anna Bridge 180:96ed750bd169 112 /// Get interrupt enable state.
Anna Bridge 180:96ed750bd169 113 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 114 /// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
Anna Bridge 180:96ed750bd169 115 uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 116
Anna Bridge 180:96ed750bd169 117 /// Configure interrupt request mode.
Anna Bridge 180:96ed750bd169 118 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 119 /// \param[in] mode mode configuration
Anna Bridge 180:96ed750bd169 120 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 121 int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
Anna Bridge 180:96ed750bd169 122
Anna Bridge 180:96ed750bd169 123 /// Get interrupt mode configuration.
Anna Bridge 180:96ed750bd169 124 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 125 /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
Anna Bridge 180:96ed750bd169 126 uint32_t IRQ_GetMode (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 127
Anna Bridge 180:96ed750bd169 128 /// Get ID number of current interrupt request (IRQ).
Anna Bridge 180:96ed750bd169 129 /// \return interrupt ID number.
Anna Bridge 180:96ed750bd169 130 IRQn_ID_t IRQ_GetActiveIRQ (void);
Anna Bridge 180:96ed750bd169 131
Anna Bridge 180:96ed750bd169 132 /// Get ID number of current fast interrupt request (FIQ).
Anna Bridge 180:96ed750bd169 133 /// \return interrupt ID number.
Anna Bridge 180:96ed750bd169 134 IRQn_ID_t IRQ_GetActiveFIQ (void);
Anna Bridge 180:96ed750bd169 135
Anna Bridge 180:96ed750bd169 136 /// Signal end of interrupt processing.
Anna Bridge 180:96ed750bd169 137 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 138 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 139 int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 140
Anna Bridge 180:96ed750bd169 141 /// Set interrupt pending flag.
Anna Bridge 180:96ed750bd169 142 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 143 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 144 int32_t IRQ_SetPending (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 145
Anna Bridge 180:96ed750bd169 146 /// Get interrupt pending flag.
Anna Bridge 180:96ed750bd169 147 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 148 /// \return 0 - interrupt is not pending, 1 - interrupt is pending.
Anna Bridge 180:96ed750bd169 149 uint32_t IRQ_GetPending (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 150
Anna Bridge 180:96ed750bd169 151 /// Clear interrupt pending flag.
Anna Bridge 180:96ed750bd169 152 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 153 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 154 int32_t IRQ_ClearPending (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 155
Anna Bridge 180:96ed750bd169 156 /// Set interrupt priority value.
Anna Bridge 180:96ed750bd169 157 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 158 /// \param[in] priority interrupt priority value
Anna Bridge 180:96ed750bd169 159 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 160 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
Anna Bridge 180:96ed750bd169 161
Anna Bridge 180:96ed750bd169 162 /// Get interrupt priority.
Anna Bridge 180:96ed750bd169 163 /// \param[in] irqn interrupt ID number
Anna Bridge 180:96ed750bd169 164 /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
Anna Bridge 180:96ed750bd169 165 uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
Anna Bridge 180:96ed750bd169 166
Anna Bridge 180:96ed750bd169 167 /// Set priority masking threshold.
Anna Bridge 180:96ed750bd169 168 /// \param[in] priority priority masking threshold value
Anna Bridge 180:96ed750bd169 169 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 170 int32_t IRQ_SetPriorityMask (uint32_t priority);
Anna Bridge 180:96ed750bd169 171
Anna Bridge 180:96ed750bd169 172 /// Get priority masking threshold
Anna Bridge 180:96ed750bd169 173 /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
Anna Bridge 180:96ed750bd169 174 uint32_t IRQ_GetPriorityMask (void);
Anna Bridge 180:96ed750bd169 175
Anna Bridge 180:96ed750bd169 176 /// Set priority grouping field split point
Anna Bridge 180:96ed750bd169 177 /// \param[in] bits number of MSB bits included in the group priority field comparison
Anna Bridge 180:96ed750bd169 178 /// \return 0 on success, -1 on error.
Anna Bridge 180:96ed750bd169 179 int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
Anna Bridge 180:96ed750bd169 180
Anna Bridge 180:96ed750bd169 181 /// Get priority grouping field split point
Anna Bridge 180:96ed750bd169 182 /// \return current number of MSB bits included in the group priority field comparison with
Anna Bridge 180:96ed750bd169 183 /// optional IRQ_PRIORITY_ERROR bit set.
Anna Bridge 180:96ed750bd169 184 uint32_t IRQ_GetPriorityGroupBits (void);
Anna Bridge 180:96ed750bd169 185
Anna Bridge 180:96ed750bd169 186 #endif // IRQ_CTRL_H_