mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c@46:cb4f85f96d35, 2016-01-11 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Jan 11 09:45:10 2016 +0000
- Revision:
- 46:cb4f85f96d35
- Parent:
- 43:e3d4af315dd8
- Child:
- 56:05912f50f004
Synchronized with git revision 4ac44bdea62a5e1c4bf1be085e313c27005955a4
Full URL: https://github.com/mbedmicro/mbed/commit/4ac44bdea62a5e1c4bf1be085e313c27005955a4/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file system_stm32f0xx.c |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
bogdanm | 0:9b334a45a8ff | 5 | * @version V2.2.2 |
bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. |
bogdanm | 0:9b334a45a8ff | 8 | * |
bogdanm | 0:9b334a45a8ff | 9 | * 1. This file provides two functions and one global variable to be called from |
bogdanm | 0:9b334a45a8ff | 10 | * user application: |
bogdanm | 0:9b334a45a8ff | 11 | * - SystemInit(): This function is called at startup just after reset and |
bogdanm | 0:9b334a45a8ff | 12 | * before branch to main program. This call is made inside |
bogdanm | 0:9b334a45a8ff | 13 | * the "startup_stm32f0xx.s" file. |
bogdanm | 0:9b334a45a8ff | 14 | * |
bogdanm | 0:9b334a45a8ff | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
bogdanm | 0:9b334a45a8ff | 16 | * by the user application to setup the SysTick |
bogdanm | 0:9b334a45a8ff | 17 | * timer or configure other parameters. |
bogdanm | 0:9b334a45a8ff | 18 | * |
bogdanm | 0:9b334a45a8ff | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
bogdanm | 0:9b334a45a8ff | 20 | * be called whenever the core clock is changed |
bogdanm | 0:9b334a45a8ff | 21 | * during program execution. |
bogdanm | 0:9b334a45a8ff | 22 | * |
bogdanm | 0:9b334a45a8ff | 23 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
bogdanm | 0:9b334a45a8ff | 24 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to |
bogdanm | 0:9b334a45a8ff | 25 | * configure the system clock before to branch to main program. |
bogdanm | 0:9b334a45a8ff | 26 | * |
bogdanm | 0:9b334a45a8ff | 27 | * 3. This file configures the system clock as follows: |
bogdanm | 0:9b334a45a8ff | 28 | *============================================================================= |
bogdanm | 0:9b334a45a8ff | 29 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
bogdanm | 0:9b334a45a8ff | 30 | * | (external 8 MHz clock) | (internal 48 MHz) |
bogdanm | 0:9b334a45a8ff | 31 | * | 2- PLL_HSE_XTAL | |
bogdanm | 0:9b334a45a8ff | 32 | * | (external 8 MHz xtal) | |
bogdanm | 0:9b334a45a8ff | 33 | *----------------------------------------------------------------------------- |
bogdanm | 0:9b334a45a8ff | 34 | * SYSCLK(MHz) | 48 | 48 |
bogdanm | 0:9b334a45a8ff | 35 | *----------------------------------------------------------------------------- |
bogdanm | 0:9b334a45a8ff | 36 | * AHBCLK (MHz) | 48 | 48 |
bogdanm | 0:9b334a45a8ff | 37 | *----------------------------------------------------------------------------- |
bogdanm | 0:9b334a45a8ff | 38 | * APB1CLK (MHz) | 48 | 48 |
bogdanm | 0:9b334a45a8ff | 39 | *----------------------------------------------------------------------------- |
bogdanm | 0:9b334a45a8ff | 40 | * USB capable (48 MHz precise clock) | YES | YES |
bogdanm | 0:9b334a45a8ff | 41 | *============================================================================= |
bogdanm | 0:9b334a45a8ff | 42 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 43 | * @attention |
bogdanm | 0:9b334a45a8ff | 44 | * |
bogdanm | 0:9b334a45a8ff | 45 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 46 | * |
bogdanm | 0:9b334a45a8ff | 47 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 48 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 49 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 50 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 51 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 52 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 53 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 54 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 55 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 56 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 57 | * |
bogdanm | 0:9b334a45a8ff | 58 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 59 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 60 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 61 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 62 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 63 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 64 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 65 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 66 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 67 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 68 | * |
bogdanm | 0:9b334a45a8ff | 69 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 70 | */ |
bogdanm | 0:9b334a45a8ff | 71 | |
bogdanm | 0:9b334a45a8ff | 72 | /** @addtogroup CMSIS |
bogdanm | 0:9b334a45a8ff | 73 | * @{ |
bogdanm | 0:9b334a45a8ff | 74 | */ |
bogdanm | 0:9b334a45a8ff | 75 | |
bogdanm | 0:9b334a45a8ff | 76 | /** @addtogroup stm32f0xx_system |
bogdanm | 0:9b334a45a8ff | 77 | * @{ |
bogdanm | 0:9b334a45a8ff | 78 | */ |
bogdanm | 0:9b334a45a8ff | 79 | |
bogdanm | 0:9b334a45a8ff | 80 | /** @addtogroup STM32F0xx_System_Private_Includes |
bogdanm | 0:9b334a45a8ff | 81 | * @{ |
bogdanm | 0:9b334a45a8ff | 82 | */ |
bogdanm | 0:9b334a45a8ff | 83 | |
bogdanm | 0:9b334a45a8ff | 84 | #include "stm32f0xx.h" |
bogdanm | 0:9b334a45a8ff | 85 | /** |
bogdanm | 0:9b334a45a8ff | 86 | * @} |
bogdanm | 0:9b334a45a8ff | 87 | */ |
bogdanm | 0:9b334a45a8ff | 88 | |
bogdanm | 0:9b334a45a8ff | 89 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions |
bogdanm | 0:9b334a45a8ff | 90 | * @{ |
bogdanm | 0:9b334a45a8ff | 91 | */ |
bogdanm | 0:9b334a45a8ff | 92 | |
bogdanm | 0:9b334a45a8ff | 93 | /** |
bogdanm | 0:9b334a45a8ff | 94 | * @} |
bogdanm | 0:9b334a45a8ff | 95 | */ |
bogdanm | 0:9b334a45a8ff | 96 | |
bogdanm | 0:9b334a45a8ff | 97 | /** @addtogroup STM32F0xx_System_Private_Defines |
bogdanm | 0:9b334a45a8ff | 98 | * @{ |
bogdanm | 0:9b334a45a8ff | 99 | */ |
bogdanm | 0:9b334a45a8ff | 100 | #if !defined (HSE_VALUE) |
bogdanm | 0:9b334a45a8ff | 101 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
bogdanm | 0:9b334a45a8ff | 102 | This value can be provided and adapted by the user application. */ |
bogdanm | 0:9b334a45a8ff | 103 | #endif /* HSE_VALUE */ |
bogdanm | 0:9b334a45a8ff | 104 | |
bogdanm | 0:9b334a45a8ff | 105 | #if !defined (HSI_VALUE) |
bogdanm | 0:9b334a45a8ff | 106 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. |
bogdanm | 0:9b334a45a8ff | 107 | This value can be provided and adapted by the user application. */ |
bogdanm | 0:9b334a45a8ff | 108 | #endif /* HSI_VALUE */ |
bogdanm | 0:9b334a45a8ff | 109 | |
bogdanm | 0:9b334a45a8ff | 110 | /** |
bogdanm | 0:9b334a45a8ff | 111 | * @} |
bogdanm | 0:9b334a45a8ff | 112 | */ |
bogdanm | 0:9b334a45a8ff | 113 | |
bogdanm | 0:9b334a45a8ff | 114 | /** @addtogroup STM32F0xx_System_Private_Macros |
bogdanm | 0:9b334a45a8ff | 115 | * @{ |
bogdanm | 0:9b334a45a8ff | 116 | */ |
bogdanm | 0:9b334a45a8ff | 117 | |
bogdanm | 0:9b334a45a8ff | 118 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
bogdanm | 0:9b334a45a8ff | 119 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
bogdanm | 0:9b334a45a8ff | 120 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
bogdanm | 0:9b334a45a8ff | 121 | |
bogdanm | 0:9b334a45a8ff | 122 | /** |
bogdanm | 0:9b334a45a8ff | 123 | * @} |
bogdanm | 0:9b334a45a8ff | 124 | */ |
bogdanm | 0:9b334a45a8ff | 125 | |
bogdanm | 0:9b334a45a8ff | 126 | /** @addtogroup STM32F0xx_System_Private_Variables |
bogdanm | 0:9b334a45a8ff | 127 | * @{ |
bogdanm | 0:9b334a45a8ff | 128 | */ |
bogdanm | 0:9b334a45a8ff | 129 | /* This variable is updated in three ways: |
bogdanm | 0:9b334a45a8ff | 130 | 1) by calling CMSIS function SystemCoreClockUpdate() |
bogdanm | 0:9b334a45a8ff | 131 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
bogdanm | 0:9b334a45a8ff | 132 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
bogdanm | 0:9b334a45a8ff | 133 | Note: If you use this function to configure the system clock there is no need to |
bogdanm | 0:9b334a45a8ff | 134 | call the 2 first functions listed above, since SystemCoreClock variable is |
bogdanm | 0:9b334a45a8ff | 135 | updated automatically. |
bogdanm | 0:9b334a45a8ff | 136 | */ |
bogdanm | 0:9b334a45a8ff | 137 | uint32_t SystemCoreClock = 48000000; |
bogdanm | 0:9b334a45a8ff | 138 | |
bogdanm | 0:9b334a45a8ff | 139 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
bogdanm | 0:9b334a45a8ff | 140 | |
bogdanm | 0:9b334a45a8ff | 141 | /** |
bogdanm | 0:9b334a45a8ff | 142 | * @} |
bogdanm | 0:9b334a45a8ff | 143 | */ |
bogdanm | 0:9b334a45a8ff | 144 | |
bogdanm | 0:9b334a45a8ff | 145 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes |
bogdanm | 0:9b334a45a8ff | 146 | * @{ |
bogdanm | 0:9b334a45a8ff | 147 | */ |
bogdanm | 0:9b334a45a8ff | 148 | |
bogdanm | 0:9b334a45a8ff | 149 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
bogdanm | 0:9b334a45a8ff | 150 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
bogdanm | 0:9b334a45a8ff | 151 | #endif |
bogdanm | 0:9b334a45a8ff | 152 | |
bogdanm | 0:9b334a45a8ff | 153 | uint8_t SetSysClock_PLL_HSI(void); |
bogdanm | 0:9b334a45a8ff | 154 | |
bogdanm | 0:9b334a45a8ff | 155 | /** |
bogdanm | 0:9b334a45a8ff | 156 | * @} |
bogdanm | 0:9b334a45a8ff | 157 | */ |
bogdanm | 0:9b334a45a8ff | 158 | |
bogdanm | 0:9b334a45a8ff | 159 | /** @addtogroup STM32F0xx_System_Private_Functions |
bogdanm | 0:9b334a45a8ff | 160 | * @{ |
bogdanm | 0:9b334a45a8ff | 161 | */ |
bogdanm | 0:9b334a45a8ff | 162 | |
mbed_official | 43:e3d4af315dd8 | 163 | |
bogdanm | 0:9b334a45a8ff | 164 | /** |
bogdanm | 0:9b334a45a8ff | 165 | * @brief Setup the microcontroller system. |
bogdanm | 0:9b334a45a8ff | 166 | * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. |
bogdanm | 0:9b334a45a8ff | 167 | * @param None |
bogdanm | 0:9b334a45a8ff | 168 | * @retval None |
bogdanm | 0:9b334a45a8ff | 169 | */ |
bogdanm | 0:9b334a45a8ff | 170 | void SystemInit(void) |
bogdanm | 0:9b334a45a8ff | 171 | { |
bogdanm | 0:9b334a45a8ff | 172 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
bogdanm | 0:9b334a45a8ff | 173 | /* Set HSION bit */ |
bogdanm | 0:9b334a45a8ff | 174 | RCC->CR |= (uint32_t)0x00000001; |
bogdanm | 0:9b334a45a8ff | 175 | |
bogdanm | 0:9b334a45a8ff | 176 | #if defined (STM32F051x8) || defined (STM32F058x8) |
bogdanm | 0:9b334a45a8ff | 177 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ |
bogdanm | 0:9b334a45a8ff | 178 | RCC->CFGR &= (uint32_t)0xF8FFB80C; |
bogdanm | 0:9b334a45a8ff | 179 | #else |
bogdanm | 0:9b334a45a8ff | 180 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ |
bogdanm | 0:9b334a45a8ff | 181 | RCC->CFGR &= (uint32_t)0x08FFB80C; |
bogdanm | 0:9b334a45a8ff | 182 | #endif /* STM32F051x8 or STM32F058x8 */ |
bogdanm | 0:9b334a45a8ff | 183 | |
bogdanm | 0:9b334a45a8ff | 184 | /* Reset HSEON, CSSON and PLLON bits */ |
bogdanm | 0:9b334a45a8ff | 185 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
bogdanm | 0:9b334a45a8ff | 186 | |
bogdanm | 0:9b334a45a8ff | 187 | /* Reset HSEBYP bit */ |
bogdanm | 0:9b334a45a8ff | 188 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
bogdanm | 0:9b334a45a8ff | 189 | |
bogdanm | 0:9b334a45a8ff | 190 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
bogdanm | 0:9b334a45a8ff | 191 | RCC->CFGR &= (uint32_t)0xFFC0FFFF; |
bogdanm | 0:9b334a45a8ff | 192 | |
bogdanm | 0:9b334a45a8ff | 193 | /* Reset PREDIV[3:0] bits */ |
bogdanm | 0:9b334a45a8ff | 194 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; |
bogdanm | 0:9b334a45a8ff | 195 | |
bogdanm | 0:9b334a45a8ff | 196 | #if defined (STM32F072xB) || defined (STM32F078xx) |
bogdanm | 0:9b334a45a8ff | 197 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
bogdanm | 0:9b334a45a8ff | 198 | RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; |
bogdanm | 0:9b334a45a8ff | 199 | #elif defined (STM32F071xB) |
bogdanm | 0:9b334a45a8ff | 200 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
bogdanm | 0:9b334a45a8ff | 201 | RCC->CFGR3 &= (uint32_t)0xFFFFCEAC; |
bogdanm | 0:9b334a45a8ff | 202 | #elif defined (STM32F091xC) || defined (STM32F098xx) |
bogdanm | 0:9b334a45a8ff | 203 | /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
bogdanm | 0:9b334a45a8ff | 204 | RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; |
bogdanm | 0:9b334a45a8ff | 205 | #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) |
bogdanm | 0:9b334a45a8ff | 206 | /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ |
bogdanm | 0:9b334a45a8ff | 207 | RCC->CFGR3 &= (uint32_t)0xFFFFFEEC; |
bogdanm | 0:9b334a45a8ff | 208 | #elif defined (STM32F051x8) || defined (STM32F058xx) |
bogdanm | 0:9b334a45a8ff | 209 | /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
bogdanm | 0:9b334a45a8ff | 210 | RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; |
bogdanm | 0:9b334a45a8ff | 211 | #elif defined (STM32F042x6) || defined (STM32F048xx) |
bogdanm | 0:9b334a45a8ff | 212 | /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
bogdanm | 0:9b334a45a8ff | 213 | RCC->CFGR3 &= (uint32_t)0xFFFFFE2C; |
bogdanm | 0:9b334a45a8ff | 214 | #elif defined (STM32F070x6) || defined (STM32F070xB) |
bogdanm | 0:9b334a45a8ff | 215 | /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ |
bogdanm | 0:9b334a45a8ff | 216 | RCC->CFGR3 &= (uint32_t)0xFFFFFE6C; |
bogdanm | 0:9b334a45a8ff | 217 | /* Set default USB clock to PLLCLK, since there is no HSI48 */ |
bogdanm | 0:9b334a45a8ff | 218 | RCC->CFGR3 |= (uint32_t)0x00000080; |
bogdanm | 0:9b334a45a8ff | 219 | #else |
bogdanm | 0:9b334a45a8ff | 220 | #warning "No target selected" |
bogdanm | 0:9b334a45a8ff | 221 | #endif |
bogdanm | 0:9b334a45a8ff | 222 | |
bogdanm | 0:9b334a45a8ff | 223 | /* Reset HSI14 bit */ |
bogdanm | 0:9b334a45a8ff | 224 | RCC->CR2 &= (uint32_t)0xFFFFFFFE; |
bogdanm | 0:9b334a45a8ff | 225 | |
bogdanm | 0:9b334a45a8ff | 226 | /* Disable all interrupts */ |
bogdanm | 0:9b334a45a8ff | 227 | RCC->CIR = 0x00000000; |
mbed_official | 43:e3d4af315dd8 | 228 | |
mbed_official | 46:cb4f85f96d35 | 229 | /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */ |
mbed_official | 46:cb4f85f96d35 | 230 | RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; |
mbed_official | 46:cb4f85f96d35 | 231 | |
mbed_official | 43:e3d4af315dd8 | 232 | /* Configure the Cube driver */ |
mbed_official | 43:e3d4af315dd8 | 233 | SystemCoreClock = 8000000; // At this stage the HSI is used as system clock |
mbed_official | 43:e3d4af315dd8 | 234 | HAL_Init(); |
mbed_official | 43:e3d4af315dd8 | 235 | |
mbed_official | 43:e3d4af315dd8 | 236 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 43:e3d4af315dd8 | 237 | AHB/APBx prescalers and Flash settings */ |
mbed_official | 43:e3d4af315dd8 | 238 | SetSysClock(); |
mbed_official | 43:e3d4af315dd8 | 239 | |
bogdanm | 0:9b334a45a8ff | 240 | } |
bogdanm | 0:9b334a45a8ff | 241 | |
bogdanm | 0:9b334a45a8ff | 242 | /** |
bogdanm | 0:9b334a45a8ff | 243 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
bogdanm | 0:9b334a45a8ff | 244 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
bogdanm | 0:9b334a45a8ff | 245 | * be used by the user application to setup the SysTick timer or configure |
bogdanm | 0:9b334a45a8ff | 246 | * other parameters. |
bogdanm | 0:9b334a45a8ff | 247 | * |
bogdanm | 0:9b334a45a8ff | 248 | * @note Each time the core clock (HCLK) changes, this function must be called |
bogdanm | 0:9b334a45a8ff | 249 | * to update SystemCoreClock variable value. Otherwise, any configuration |
bogdanm | 0:9b334a45a8ff | 250 | * based on this variable will be incorrect. |
bogdanm | 0:9b334a45a8ff | 251 | * |
bogdanm | 0:9b334a45a8ff | 252 | * @note - The system frequency computed by this function is not the real |
bogdanm | 0:9b334a45a8ff | 253 | * frequency in the chip. It is calculated based on the predefined |
bogdanm | 0:9b334a45a8ff | 254 | * constant and the selected clock source: |
bogdanm | 0:9b334a45a8ff | 255 | * |
bogdanm | 0:9b334a45a8ff | 256 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
bogdanm | 0:9b334a45a8ff | 257 | * |
bogdanm | 0:9b334a45a8ff | 258 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
bogdanm | 0:9b334a45a8ff | 259 | * |
bogdanm | 0:9b334a45a8ff | 260 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
bogdanm | 0:9b334a45a8ff | 261 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
bogdanm | 0:9b334a45a8ff | 262 | * |
bogdanm | 0:9b334a45a8ff | 263 | * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
bogdanm | 0:9b334a45a8ff | 264 | * 8 MHz) but the real value may vary depending on the variations |
bogdanm | 0:9b334a45a8ff | 265 | * in voltage and temperature. |
bogdanm | 0:9b334a45a8ff | 266 | * |
bogdanm | 0:9b334a45a8ff | 267 | * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
bogdanm | 0:9b334a45a8ff | 268 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
bogdanm | 0:9b334a45a8ff | 269 | * frequency of the crystal used. Otherwise, this function may |
bogdanm | 0:9b334a45a8ff | 270 | * have wrong result. |
bogdanm | 0:9b334a45a8ff | 271 | * |
bogdanm | 0:9b334a45a8ff | 272 | * - The result of this function could be not correct when using fractional |
bogdanm | 0:9b334a45a8ff | 273 | * value for HSE crystal. |
bogdanm | 0:9b334a45a8ff | 274 | * |
bogdanm | 0:9b334a45a8ff | 275 | * @param None |
bogdanm | 0:9b334a45a8ff | 276 | * @retval None |
bogdanm | 0:9b334a45a8ff | 277 | */ |
bogdanm | 0:9b334a45a8ff | 278 | void SystemCoreClockUpdate (void) |
bogdanm | 0:9b334a45a8ff | 279 | { |
bogdanm | 0:9b334a45a8ff | 280 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; |
bogdanm | 0:9b334a45a8ff | 281 | |
bogdanm | 0:9b334a45a8ff | 282 | /* Get SYSCLK source -------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 283 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
bogdanm | 0:9b334a45a8ff | 284 | |
bogdanm | 0:9b334a45a8ff | 285 | switch (tmp) |
bogdanm | 0:9b334a45a8ff | 286 | { |
bogdanm | 0:9b334a45a8ff | 287 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ |
bogdanm | 0:9b334a45a8ff | 288 | SystemCoreClock = HSI_VALUE; |
bogdanm | 0:9b334a45a8ff | 289 | break; |
bogdanm | 0:9b334a45a8ff | 290 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ |
bogdanm | 0:9b334a45a8ff | 291 | SystemCoreClock = HSE_VALUE; |
bogdanm | 0:9b334a45a8ff | 292 | break; |
bogdanm | 0:9b334a45a8ff | 293 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ |
bogdanm | 0:9b334a45a8ff | 294 | /* Get PLL clock source and multiplication factor ----------------------*/ |
bogdanm | 0:9b334a45a8ff | 295 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; |
bogdanm | 0:9b334a45a8ff | 296 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
bogdanm | 0:9b334a45a8ff | 297 | pllmull = ( pllmull >> 18) + 2; |
bogdanm | 0:9b334a45a8ff | 298 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; |
bogdanm | 0:9b334a45a8ff | 299 | |
bogdanm | 0:9b334a45a8ff | 300 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) |
bogdanm | 0:9b334a45a8ff | 301 | { |
bogdanm | 0:9b334a45a8ff | 302 | /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ |
bogdanm | 0:9b334a45a8ff | 303 | SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; |
bogdanm | 0:9b334a45a8ff | 304 | } |
bogdanm | 0:9b334a45a8ff | 305 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) |
bogdanm | 0:9b334a45a8ff | 306 | else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) |
bogdanm | 0:9b334a45a8ff | 307 | { |
bogdanm | 0:9b334a45a8ff | 308 | /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ |
bogdanm | 0:9b334a45a8ff | 309 | SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; |
bogdanm | 0:9b334a45a8ff | 310 | } |
bogdanm | 0:9b334a45a8ff | 311 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ |
bogdanm | 0:9b334a45a8ff | 312 | else |
bogdanm | 0:9b334a45a8ff | 313 | { |
bogdanm | 0:9b334a45a8ff | 314 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ |
bogdanm | 0:9b334a45a8ff | 315 | || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ |
bogdanm | 0:9b334a45a8ff | 316 | || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
bogdanm | 0:9b334a45a8ff | 317 | /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ |
bogdanm | 0:9b334a45a8ff | 318 | SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; |
bogdanm | 0:9b334a45a8ff | 319 | #else |
bogdanm | 0:9b334a45a8ff | 320 | /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ |
bogdanm | 0:9b334a45a8ff | 321 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
bogdanm | 0:9b334a45a8ff | 322 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || |
bogdanm | 0:9b334a45a8ff | 323 | STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || |
bogdanm | 0:9b334a45a8ff | 324 | STM32F091xC || STM32F098xx || STM32F030xC */ |
bogdanm | 0:9b334a45a8ff | 325 | } |
bogdanm | 0:9b334a45a8ff | 326 | break; |
bogdanm | 0:9b334a45a8ff | 327 | default: /* HSI used as system clock */ |
bogdanm | 0:9b334a45a8ff | 328 | SystemCoreClock = HSI_VALUE; |
bogdanm | 0:9b334a45a8ff | 329 | break; |
bogdanm | 0:9b334a45a8ff | 330 | } |
bogdanm | 0:9b334a45a8ff | 331 | /* Compute HCLK clock frequency ----------------*/ |
bogdanm | 0:9b334a45a8ff | 332 | /* Get HCLK prescaler */ |
bogdanm | 0:9b334a45a8ff | 333 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
bogdanm | 0:9b334a45a8ff | 334 | /* HCLK clock frequency */ |
bogdanm | 0:9b334a45a8ff | 335 | SystemCoreClock >>= tmp; |
bogdanm | 0:9b334a45a8ff | 336 | } |
bogdanm | 0:9b334a45a8ff | 337 | |
bogdanm | 0:9b334a45a8ff | 338 | /** |
bogdanm | 0:9b334a45a8ff | 339 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
bogdanm | 0:9b334a45a8ff | 340 | * AHB/APBx prescalers and Flash settings |
bogdanm | 0:9b334a45a8ff | 341 | * @note This function should be called only once the RCC clock configuration |
bogdanm | 0:9b334a45a8ff | 342 | * is reset to the default reset state (done in SystemInit() function). |
bogdanm | 0:9b334a45a8ff | 343 | * @param None |
bogdanm | 0:9b334a45a8ff | 344 | * @retval None |
bogdanm | 0:9b334a45a8ff | 345 | */ |
bogdanm | 0:9b334a45a8ff | 346 | void SetSysClock(void) |
bogdanm | 0:9b334a45a8ff | 347 | { |
bogdanm | 0:9b334a45a8ff | 348 | /* 1- Try to start with HSE and external clock */ |
bogdanm | 0:9b334a45a8ff | 349 | #if USE_PLL_HSE_EXTC != 0 |
bogdanm | 0:9b334a45a8ff | 350 | if (SetSysClock_PLL_HSE(1) == 0) |
bogdanm | 0:9b334a45a8ff | 351 | #endif |
bogdanm | 0:9b334a45a8ff | 352 | { |
bogdanm | 0:9b334a45a8ff | 353 | /* 2- If fail try to start with HSE and external xtal */ |
bogdanm | 0:9b334a45a8ff | 354 | #if USE_PLL_HSE_XTAL != 0 |
bogdanm | 0:9b334a45a8ff | 355 | if (SetSysClock_PLL_HSE(0) == 0) |
bogdanm | 0:9b334a45a8ff | 356 | #endif |
bogdanm | 0:9b334a45a8ff | 357 | { |
bogdanm | 0:9b334a45a8ff | 358 | /* 3- If fail start with HSI clock */ |
bogdanm | 0:9b334a45a8ff | 359 | if (SetSysClock_PLL_HSI() == 0) |
bogdanm | 0:9b334a45a8ff | 360 | { |
bogdanm | 0:9b334a45a8ff | 361 | while(1) |
bogdanm | 0:9b334a45a8ff | 362 | { |
bogdanm | 0:9b334a45a8ff | 363 | // [TODO] Put something here to tell the user that a problem occured... |
bogdanm | 0:9b334a45a8ff | 364 | } |
bogdanm | 0:9b334a45a8ff | 365 | } |
bogdanm | 0:9b334a45a8ff | 366 | } |
bogdanm | 0:9b334a45a8ff | 367 | } |
bogdanm | 0:9b334a45a8ff | 368 | |
bogdanm | 0:9b334a45a8ff | 369 | // Output clock on MCO pin(PA8) for debugging purpose |
bogdanm | 0:9b334a45a8ff | 370 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz |
bogdanm | 0:9b334a45a8ff | 371 | } |
bogdanm | 0:9b334a45a8ff | 372 | |
bogdanm | 0:9b334a45a8ff | 373 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
bogdanm | 0:9b334a45a8ff | 374 | /******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 375 | /* PLL (clocked by HSE) used as System clock source */ |
bogdanm | 0:9b334a45a8ff | 376 | /******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 377 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
bogdanm | 0:9b334a45a8ff | 378 | { |
bogdanm | 0:9b334a45a8ff | 379 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
bogdanm | 0:9b334a45a8ff | 380 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
bogdanm | 0:9b334a45a8ff | 381 | //Select HSI as system clock source to allow modification of the PLL configuration |
bogdanm | 0:9b334a45a8ff | 382 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
bogdanm | 0:9b334a45a8ff | 383 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; |
bogdanm | 0:9b334a45a8ff | 384 | if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
bogdanm | 0:9b334a45a8ff | 385 | { |
bogdanm | 0:9b334a45a8ff | 386 | return 0; // FAIL |
bogdanm | 0:9b334a45a8ff | 387 | } |
bogdanm | 0:9b334a45a8ff | 388 | |
bogdanm | 0:9b334a45a8ff | 389 | |
bogdanm | 0:9b334a45a8ff | 390 | // Select HSE oscillator as PLL source |
bogdanm | 0:9b334a45a8ff | 391 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
bogdanm | 0:9b334a45a8ff | 392 | if (bypass == 0) { |
bogdanm | 0:9b334a45a8ff | 393 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
bogdanm | 0:9b334a45a8ff | 394 | } else { |
bogdanm | 0:9b334a45a8ff | 395 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only |
bogdanm | 0:9b334a45a8ff | 396 | } |
bogdanm | 0:9b334a45a8ff | 397 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
bogdanm | 0:9b334a45a8ff | 398 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
bogdanm | 0:9b334a45a8ff | 399 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; |
bogdanm | 0:9b334a45a8ff | 400 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
bogdanm | 0:9b334a45a8ff | 401 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
bogdanm | 0:9b334a45a8ff | 402 | return 0; // FAIL |
bogdanm | 0:9b334a45a8ff | 403 | } |
bogdanm | 0:9b334a45a8ff | 404 | |
bogdanm | 0:9b334a45a8ff | 405 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
bogdanm | 0:9b334a45a8ff | 406 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
bogdanm | 0:9b334a45a8ff | 407 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
bogdanm | 0:9b334a45a8ff | 408 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
bogdanm | 0:9b334a45a8ff | 409 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
bogdanm | 0:9b334a45a8ff | 410 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
bogdanm | 0:9b334a45a8ff | 411 | return 0; // FAIL |
bogdanm | 0:9b334a45a8ff | 412 | } |
bogdanm | 0:9b334a45a8ff | 413 | |
bogdanm | 0:9b334a45a8ff | 414 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz |
bogdanm | 0:9b334a45a8ff | 415 | |
bogdanm | 0:9b334a45a8ff | 416 | return 1; // OK |
bogdanm | 0:9b334a45a8ff | 417 | } |
bogdanm | 0:9b334a45a8ff | 418 | #endif |
bogdanm | 0:9b334a45a8ff | 419 | |
bogdanm | 0:9b334a45a8ff | 420 | /******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 421 | /* PLL (clocked by HSI) used as System clock source */ |
bogdanm | 0:9b334a45a8ff | 422 | /******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 423 | uint8_t SetSysClock_PLL_HSI(void) |
bogdanm | 0:9b334a45a8ff | 424 | { |
bogdanm | 0:9b334a45a8ff | 425 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
bogdanm | 0:9b334a45a8ff | 426 | RCC_OscInitTypeDef RCC_OscInitStruct; |
bogdanm | 0:9b334a45a8ff | 427 | |
bogdanm | 0:9b334a45a8ff | 428 | // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) |
bogdanm | 0:9b334a45a8ff | 429 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
bogdanm | 0:9b334a45a8ff | 430 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
bogdanm | 0:9b334a45a8ff | 431 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
bogdanm | 0:9b334a45a8ff | 432 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 |
bogdanm | 0:9b334a45a8ff | 433 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; |
bogdanm | 0:9b334a45a8ff | 434 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
bogdanm | 0:9b334a45a8ff | 435 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
bogdanm | 0:9b334a45a8ff | 436 | return 0; // FAIL |
bogdanm | 0:9b334a45a8ff | 437 | } |
bogdanm | 0:9b334a45a8ff | 438 | |
bogdanm | 0:9b334a45a8ff | 439 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
bogdanm | 0:9b334a45a8ff | 440 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
bogdanm | 0:9b334a45a8ff | 441 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
bogdanm | 0:9b334a45a8ff | 442 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
bogdanm | 0:9b334a45a8ff | 443 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
bogdanm | 0:9b334a45a8ff | 444 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
bogdanm | 0:9b334a45a8ff | 445 | return 0; // FAIL |
bogdanm | 0:9b334a45a8ff | 446 | } |
bogdanm | 0:9b334a45a8ff | 447 | |
bogdanm | 0:9b334a45a8ff | 448 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz |
bogdanm | 0:9b334a45a8ff | 449 | |
bogdanm | 0:9b334a45a8ff | 450 | return 1; // OK |
bogdanm | 0:9b334a45a8ff | 451 | } |
bogdanm | 0:9b334a45a8ff | 452 | |
bogdanm | 0:9b334a45a8ff | 453 | /* Used for the different timeouts in the HAL */ |
bogdanm | 0:9b334a45a8ff | 454 | void SysTick_Handler(void) |
bogdanm | 0:9b334a45a8ff | 455 | { |
bogdanm | 0:9b334a45a8ff | 456 | HAL_IncTick(); |
bogdanm | 0:9b334a45a8ff | 457 | } |
bogdanm | 0:9b334a45a8ff | 458 | |
bogdanm | 0:9b334a45a8ff | 459 | /** |
bogdanm | 0:9b334a45a8ff | 460 | * @} |
bogdanm | 0:9b334a45a8ff | 461 | */ |
bogdanm | 0:9b334a45a8ff | 462 | |
bogdanm | 0:9b334a45a8ff | 463 | /** |
bogdanm | 0:9b334a45a8ff | 464 | * @} |
bogdanm | 0:9b334a45a8ff | 465 | */ |
bogdanm | 0:9b334a45a8ff | 466 | |
bogdanm | 0:9b334a45a8ff | 467 | /** |
bogdanm | 0:9b334a45a8ff | 468 | * @} |
bogdanm | 0:9b334a45a8ff | 469 | */ |
bogdanm | 0:9b334a45a8ff | 470 | |
bogdanm | 0:9b334a45a8ff | 471 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
bogdanm | 0:9b334a45a8ff | 472 |