mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c@144:ef7eb2e8f9f7
- Child:
- 156:95d6b41a828b
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f0xx_hal_cec.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.4.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 27-May-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief CEC HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 9 | * functionalities of the High Definition Multimedia Interface |
<> | 144:ef7eb2e8f9f7 | 10 | * Consumer Electronics Control Peripheral (CEC). |
<> | 144:ef7eb2e8f9f7 | 11 | * + Initialization and de-initialization function |
<> | 144:ef7eb2e8f9f7 | 12 | * + IO operation function |
<> | 144:ef7eb2e8f9f7 | 13 | * + Peripheral Control function |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 16 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 18 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 19 | [..] |
<> | 144:ef7eb2e8f9f7 | 20 | The CEC HAL driver can be used as follows: |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | (#) Declare a CEC_HandleTypeDef handle structure. |
<> | 144:ef7eb2e8f9f7 | 23 | (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: |
<> | 144:ef7eb2e8f9f7 | 24 | (++) Enable the CEC interface clock. |
<> | 144:ef7eb2e8f9f7 | 25 | (++) CEC pins configuration: |
<> | 144:ef7eb2e8f9f7 | 26 | (+++) Enable the clock for the CEC GPIOs. |
<> | 144:ef7eb2e8f9f7 | 27 | (+++) Configure these CEC pins as alternate function pull-up. |
<> | 144:ef7eb2e8f9f7 | 28 | (++) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 29 | and HAL_CEC_Receive_IT() APIs): |
<> | 144:ef7eb2e8f9f7 | 30 | (+++) Configure the CEC interrupt priority. |
<> | 144:ef7eb2e8f9f7 | 31 | (+++) Enable the NVIC CEC IRQ handle. |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in |
<> | 144:ef7eb2e8f9f7 | 34 | in case of Bit Rising Error, Error-Bit generation conditions, device logical |
<> | 144:ef7eb2e8f9f7 | 35 | address and Listen mode in the hcec Init structure. |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. |
<> | 144:ef7eb2e8f9f7 | 38 | (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
<> | 144:ef7eb2e8f9f7 | 39 | by calling the customed HAL_CEC_MspInit() API. |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | -@@- The specific CEC interrupts (Transmission complete interrupt, |
<> | 144:ef7eb2e8f9f7 | 42 | RXNE interrupt and Error Interrupts) will be managed using the macros |
<> | 144:ef7eb2e8f9f7 | 43 | __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit |
<> | 144:ef7eb2e8f9f7 | 44 | and receive process. |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 47 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 48 | * @attention |
<> | 144:ef7eb2e8f9f7 | 49 | * |
<> | 144:ef7eb2e8f9f7 | 50 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 51 | * |
<> | 144:ef7eb2e8f9f7 | 52 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 53 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 54 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 55 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 56 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 57 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 58 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 59 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 60 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 61 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 62 | * |
<> | 144:ef7eb2e8f9f7 | 63 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 64 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 65 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 66 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 67 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 68 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 69 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 70 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 71 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 72 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 73 | * |
<> | 144:ef7eb2e8f9f7 | 74 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 75 | */ |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 78 | #include "stm32f0xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | #ifdef HAL_CEC_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | #if defined(STM32F042x6) || defined(STM32F048xx) ||\ |
<> | 144:ef7eb2e8f9f7 | 83 | defined(STM32F051x8) || defined(STM32F058xx) ||\ |
<> | 144:ef7eb2e8f9f7 | 84 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ |
<> | 144:ef7eb2e8f9f7 | 85 | defined(STM32F091xC) || defined (STM32F098xx) |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | /** @addtogroup STM32F0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 88 | * @{ |
<> | 144:ef7eb2e8f9f7 | 89 | */ |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | /** @defgroup CEC CEC |
<> | 144:ef7eb2e8f9f7 | 92 | * @brief HAL CEC module driver |
<> | 144:ef7eb2e8f9f7 | 93 | * @{ |
<> | 144:ef7eb2e8f9f7 | 94 | */ |
<> | 144:ef7eb2e8f9f7 | 95 | |
<> | 144:ef7eb2e8f9f7 | 96 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 97 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 98 | /** @defgroup CEC_Private_Constants CEC Private Constants |
<> | 144:ef7eb2e8f9f7 | 99 | * @{ |
<> | 144:ef7eb2e8f9f7 | 100 | */ |
<> | 144:ef7eb2e8f9f7 | 101 | #define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \ |
<> | 144:ef7eb2e8f9f7 | 102 | | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \ |
<> | 144:ef7eb2e8f9f7 | 103 | | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN) |
<> | 144:ef7eb2e8f9f7 | 104 | /** |
<> | 144:ef7eb2e8f9f7 | 105 | * @} |
<> | 144:ef7eb2e8f9f7 | 106 | */ |
<> | 144:ef7eb2e8f9f7 | 107 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 108 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 109 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 110 | /** @defgroup CEC_Private_Functions CEC Private Functions |
<> | 144:ef7eb2e8f9f7 | 111 | * @{ |
<> | 144:ef7eb2e8f9f7 | 112 | */ |
<> | 144:ef7eb2e8f9f7 | 113 | static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec); |
<> | 144:ef7eb2e8f9f7 | 114 | static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); |
<> | 144:ef7eb2e8f9f7 | 115 | /** |
<> | 144:ef7eb2e8f9f7 | 116 | * @} |
<> | 144:ef7eb2e8f9f7 | 117 | */ |
<> | 144:ef7eb2e8f9f7 | 118 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | /** @defgroup CEC_Exported_Functions CEC Exported Functions |
<> | 144:ef7eb2e8f9f7 | 121 | * @{ |
<> | 144:ef7eb2e8f9f7 | 122 | */ |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | /** @defgroup CEC_Exported_Functions_Group1 Initialization/de-initialization function |
<> | 144:ef7eb2e8f9f7 | 125 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 126 | * |
<> | 144:ef7eb2e8f9f7 | 127 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 128 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 129 | ##### Initialization and Configuration functions ##### |
<> | 144:ef7eb2e8f9f7 | 130 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 131 | [..] |
<> | 144:ef7eb2e8f9f7 | 132 | This subsection provides a set of functions allowing to initialize the CEC |
<> | 144:ef7eb2e8f9f7 | 133 | (+) The following parameters need to be configured: |
<> | 144:ef7eb2e8f9f7 | 134 | (++) SignalFreeTime |
<> | 144:ef7eb2e8f9f7 | 135 | (++) Tolerance |
<> | 144:ef7eb2e8f9f7 | 136 | (++) BRERxStop (RX stopped or not upon Bit Rising Error) |
<> | 144:ef7eb2e8f9f7 | 137 | (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error) |
<> | 144:ef7eb2e8f9f7 | 138 | (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error) |
<> | 144:ef7eb2e8f9f7 | 139 | (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error) |
<> | 144:ef7eb2e8f9f7 | 140 | (++) SignalFreeTimeOption (SFT Timer start definition) |
<> | 144:ef7eb2e8f9f7 | 141 | (++) OwnAddress (CEC device address) |
<> | 144:ef7eb2e8f9f7 | 142 | (++) ListenMode |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 145 | * @{ |
<> | 144:ef7eb2e8f9f7 | 146 | */ |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | /** |
<> | 144:ef7eb2e8f9f7 | 149 | * @brief Initializes the CEC mode according to the specified |
<> | 144:ef7eb2e8f9f7 | 150 | * parameters in the CEC_InitTypeDef and creates the associated handle . |
<> | 144:ef7eb2e8f9f7 | 151 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 152 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 153 | */ |
<> | 144:ef7eb2e8f9f7 | 154 | HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 155 | { |
<> | 144:ef7eb2e8f9f7 | 156 | uint32_t tmpreg = 0x0; |
<> | 144:ef7eb2e8f9f7 | 157 | |
<> | 144:ef7eb2e8f9f7 | 158 | /* Check the CEC handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 159 | if(hcec == NULL) |
<> | 144:ef7eb2e8f9f7 | 160 | { |
<> | 144:ef7eb2e8f9f7 | 161 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 162 | } |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 165 | assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); |
<> | 144:ef7eb2e8f9f7 | 166 | assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime)); |
<> | 144:ef7eb2e8f9f7 | 167 | assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); |
<> | 144:ef7eb2e8f9f7 | 168 | assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop)); |
<> | 144:ef7eb2e8f9f7 | 169 | assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen)); |
<> | 144:ef7eb2e8f9f7 | 170 | assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen)); |
<> | 144:ef7eb2e8f9f7 | 171 | assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen)); |
<> | 144:ef7eb2e8f9f7 | 172 | assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); |
<> | 144:ef7eb2e8f9f7 | 173 | assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress)); |
<> | 144:ef7eb2e8f9f7 | 174 | assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); |
<> | 144:ef7eb2e8f9f7 | 175 | assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | if(hcec->State == HAL_CEC_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 178 | { |
<> | 144:ef7eb2e8f9f7 | 179 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 180 | hcec->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 181 | /* Init the low level hardware : GPIO, CLOCK */ |
<> | 144:ef7eb2e8f9f7 | 182 | HAL_CEC_MspInit(hcec); |
<> | 144:ef7eb2e8f9f7 | 183 | } |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | hcec->State = HAL_CEC_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | /* Disable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 188 | __HAL_CEC_DISABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | tmpreg = hcec->Init.SignalFreeTime; |
<> | 144:ef7eb2e8f9f7 | 191 | tmpreg |= hcec->Init.Tolerance; |
<> | 144:ef7eb2e8f9f7 | 192 | tmpreg |= hcec->Init.BRERxStop; |
<> | 144:ef7eb2e8f9f7 | 193 | tmpreg |= hcec->Init.BREErrorBitGen; |
<> | 144:ef7eb2e8f9f7 | 194 | tmpreg |= hcec->Init.LBPEErrorBitGen; |
<> | 144:ef7eb2e8f9f7 | 195 | tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen; |
<> | 144:ef7eb2e8f9f7 | 196 | tmpreg |= hcec->Init.SignalFreeTimeOption; |
<> | 144:ef7eb2e8f9f7 | 197 | tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS); |
<> | 144:ef7eb2e8f9f7 | 198 | tmpreg |= hcec->Init.ListenMode; |
<> | 144:ef7eb2e8f9f7 | 199 | |
<> | 144:ef7eb2e8f9f7 | 200 | /* Write to CEC Control Register */ |
<> | 144:ef7eb2e8f9f7 | 201 | MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg); |
<> | 144:ef7eb2e8f9f7 | 202 | |
<> | 144:ef7eb2e8f9f7 | 203 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 204 | __HAL_CEC_ENABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 209 | } |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | |
<> | 144:ef7eb2e8f9f7 | 213 | /** |
<> | 144:ef7eb2e8f9f7 | 214 | * @brief DeInitializes the CEC peripheral |
<> | 144:ef7eb2e8f9f7 | 215 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 216 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 217 | */ |
<> | 144:ef7eb2e8f9f7 | 218 | HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 219 | { |
<> | 144:ef7eb2e8f9f7 | 220 | /* Check the CEC handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 221 | if(hcec == NULL) |
<> | 144:ef7eb2e8f9f7 | 222 | { |
<> | 144:ef7eb2e8f9f7 | 223 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 224 | } |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 227 | assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | hcec->State = HAL_CEC_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 230 | |
<> | 144:ef7eb2e8f9f7 | 231 | /* DeInit the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 232 | HAL_CEC_MspDeInit(hcec); |
<> | 144:ef7eb2e8f9f7 | 233 | /* Disable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 234 | __HAL_CEC_DISABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 237 | hcec->State = HAL_CEC_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | /* Process Unlock */ |
<> | 144:ef7eb2e8f9f7 | 240 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 243 | } |
<> | 144:ef7eb2e8f9f7 | 244 | |
<> | 144:ef7eb2e8f9f7 | 245 | /** |
<> | 144:ef7eb2e8f9f7 | 246 | * @brief CEC MSP Init |
<> | 144:ef7eb2e8f9f7 | 247 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 248 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 249 | */ |
<> | 144:ef7eb2e8f9f7 | 250 | __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 251 | { |
<> | 144:ef7eb2e8f9f7 | 252 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 253 | UNUSED(hcec); |
<> | 144:ef7eb2e8f9f7 | 254 | |
<> | 144:ef7eb2e8f9f7 | 255 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 256 | the HAL_CEC_MspInit can be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 257 | */ |
<> | 144:ef7eb2e8f9f7 | 258 | } |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | /** |
<> | 144:ef7eb2e8f9f7 | 261 | * @brief CEC MSP DeInit |
<> | 144:ef7eb2e8f9f7 | 262 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 263 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 264 | */ |
<> | 144:ef7eb2e8f9f7 | 265 | __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 266 | { |
<> | 144:ef7eb2e8f9f7 | 267 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 268 | UNUSED(hcec); |
<> | 144:ef7eb2e8f9f7 | 269 | |
<> | 144:ef7eb2e8f9f7 | 270 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 271 | the HAL_CEC_MspDeInit can be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 272 | */ |
<> | 144:ef7eb2e8f9f7 | 273 | } |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | /** |
<> | 144:ef7eb2e8f9f7 | 276 | * @} |
<> | 144:ef7eb2e8f9f7 | 277 | */ |
<> | 144:ef7eb2e8f9f7 | 278 | |
<> | 144:ef7eb2e8f9f7 | 279 | /** @defgroup CEC_Exported_Functions_Group2 IO operation function |
<> | 144:ef7eb2e8f9f7 | 280 | * @brief CEC Transmit/Receive functions |
<> | 144:ef7eb2e8f9f7 | 281 | * |
<> | 144:ef7eb2e8f9f7 | 282 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 283 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 284 | ##### IO operation function ##### |
<> | 144:ef7eb2e8f9f7 | 285 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 286 | This subsection provides a set of functions allowing to manage the CEC data transfers. |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) |
<> | 144:ef7eb2e8f9f7 | 289 | logical addresses (4-bit long addresses, 0xF for broadcast messages destination) |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | (#) There are two mode of transfer: |
<> | 144:ef7eb2e8f9f7 | 292 | (+) Blocking mode: The communication is performed in polling mode. |
<> | 144:ef7eb2e8f9f7 | 293 | The HAL status of all data processing is returned by the same function |
<> | 144:ef7eb2e8f9f7 | 294 | after finishing transfer. |
<> | 144:ef7eb2e8f9f7 | 295 | (+) Non Blocking mode: The communication is performed using Interrupts. |
<> | 144:ef7eb2e8f9f7 | 296 | These API's return the HAL status. |
<> | 144:ef7eb2e8f9f7 | 297 | The end of the data processing will be indicated through the |
<> | 144:ef7eb2e8f9f7 | 298 | dedicated CEC IRQ when using Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 299 | The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks |
<> | 144:ef7eb2e8f9f7 | 300 | will be executed respectivelly at the end of the transmit or Receive process |
<> | 144:ef7eb2e8f9f7 | 301 | The HAL_CEC_ErrorCallback()user callback will be executed when a communication |
<> | 144:ef7eb2e8f9f7 | 302 | error is detected |
<> | 144:ef7eb2e8f9f7 | 303 | |
<> | 144:ef7eb2e8f9f7 | 304 | (#) Blocking mode API s are : |
<> | 144:ef7eb2e8f9f7 | 305 | (+) HAL_CEC_Transmit() |
<> | 144:ef7eb2e8f9f7 | 306 | (+) HAL_CEC_Receive() |
<> | 144:ef7eb2e8f9f7 | 307 | |
<> | 144:ef7eb2e8f9f7 | 308 | (#) Non-Blocking mode API s with Interrupt are : |
<> | 144:ef7eb2e8f9f7 | 309 | (+) HAL_CEC_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 310 | (+) HAL_CEC_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 311 | (+) HAL_CEC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 312 | |
<> | 144:ef7eb2e8f9f7 | 313 | (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: |
<> | 144:ef7eb2e8f9f7 | 314 | (+) HAL_CEC_TxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 315 | (+) HAL_CEC_RxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 316 | (+) HAL_CEC_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 319 | * @{ |
<> | 144:ef7eb2e8f9f7 | 320 | */ |
<> | 144:ef7eb2e8f9f7 | 321 | |
<> | 144:ef7eb2e8f9f7 | 322 | /** |
<> | 144:ef7eb2e8f9f7 | 323 | * @brief Send data in blocking mode |
<> | 144:ef7eb2e8f9f7 | 324 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 325 | * @param DestinationAddress: destination logical address |
<> | 144:ef7eb2e8f9f7 | 326 | * @param pData: pointer to input byte data buffer |
<> | 144:ef7eb2e8f9f7 | 327 | * @param Size: amount of data to be sent in bytes (without counting the header). |
<> | 144:ef7eb2e8f9f7 | 328 | * 0 means only the header is sent (ping operation). |
<> | 144:ef7eb2e8f9f7 | 329 | * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). |
<> | 144:ef7eb2e8f9f7 | 330 | * @param Timeout: Timeout duration. |
<> | 144:ef7eb2e8f9f7 | 331 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 332 | */ |
<> | 144:ef7eb2e8f9f7 | 333 | HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 334 | { |
<> | 144:ef7eb2e8f9f7 | 335 | uint8_t temp = 0; |
<> | 144:ef7eb2e8f9f7 | 336 | uint32_t tempisr = 0; |
<> | 144:ef7eb2e8f9f7 | 337 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 338 | |
<> | 144:ef7eb2e8f9f7 | 339 | if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) |
<> | 144:ef7eb2e8f9f7 | 340 | { |
<> | 144:ef7eb2e8f9f7 | 341 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 342 | if((pData == NULL ) && (Size > 0)) |
<> | 144:ef7eb2e8f9f7 | 343 | { |
<> | 144:ef7eb2e8f9f7 | 344 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 345 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 346 | } |
<> | 144:ef7eb2e8f9f7 | 347 | |
<> | 144:ef7eb2e8f9f7 | 348 | assert_param(IS_CEC_ADDRESS(DestinationAddress)); |
<> | 144:ef7eb2e8f9f7 | 349 | assert_param(IS_CEC_MSGSIZE(Size)); |
<> | 144:ef7eb2e8f9f7 | 350 | |
<> | 144:ef7eb2e8f9f7 | 351 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 352 | __HAL_LOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | hcec->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 357 | |
<> | 144:ef7eb2e8f9f7 | 358 | /* case no data to be sent, sender is only pinging the system */ |
<> | 144:ef7eb2e8f9f7 | 359 | if (Size == 0) |
<> | 144:ef7eb2e8f9f7 | 360 | { |
<> | 144:ef7eb2e8f9f7 | 361 | /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ |
<> | 144:ef7eb2e8f9f7 | 362 | __HAL_CEC_LAST_BYTE_TX_SET(hcec); |
<> | 144:ef7eb2e8f9f7 | 363 | } |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | /* send header block */ |
<> | 144:ef7eb2e8f9f7 | 366 | temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; |
<> | 144:ef7eb2e8f9f7 | 367 | hcec->Instance->TXDR = temp; |
<> | 144:ef7eb2e8f9f7 | 368 | /* Set TX Start of Message (TXSOM) bit */ |
<> | 144:ef7eb2e8f9f7 | 369 | __HAL_CEC_FIRST_BYTE_TX_SET(hcec); |
<> | 144:ef7eb2e8f9f7 | 370 | |
<> | 144:ef7eb2e8f9f7 | 371 | while (hcec->TxXferCount > 0) |
<> | 144:ef7eb2e8f9f7 | 372 | { |
<> | 144:ef7eb2e8f9f7 | 373 | hcec->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 374 | |
<> | 144:ef7eb2e8f9f7 | 375 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 376 | while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR)) |
<> | 144:ef7eb2e8f9f7 | 377 | { |
<> | 144:ef7eb2e8f9f7 | 378 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 379 | { |
<> | 144:ef7eb2e8f9f7 | 380 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 381 | { |
<> | 144:ef7eb2e8f9f7 | 382 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 383 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 384 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 385 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 386 | } |
<> | 144:ef7eb2e8f9f7 | 387 | } |
<> | 144:ef7eb2e8f9f7 | 388 | |
<> | 144:ef7eb2e8f9f7 | 389 | /* check whether error occured while waiting for TXBR to be set: |
<> | 144:ef7eb2e8f9f7 | 390 | * has Tx underrun occurred ? |
<> | 144:ef7eb2e8f9f7 | 391 | * has Tx error occurred ? |
<> | 144:ef7eb2e8f9f7 | 392 | * has Tx Missing Acknowledge error occurred ? |
<> | 144:ef7eb2e8f9f7 | 393 | * has Arbitration Loss error occurred ? */ |
<> | 144:ef7eb2e8f9f7 | 394 | tempisr = hcec->Instance->ISR; |
<> | 144:ef7eb2e8f9f7 | 395 | if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) |
<> | 144:ef7eb2e8f9f7 | 396 | { |
<> | 144:ef7eb2e8f9f7 | 397 | /* copy ISR for error handling purposes */ |
<> | 144:ef7eb2e8f9f7 | 398 | hcec->ErrorCode = tempisr; |
<> | 144:ef7eb2e8f9f7 | 399 | /* clear all error flags by default */ |
<> | 144:ef7eb2e8f9f7 | 400 | __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); |
<> | 144:ef7eb2e8f9f7 | 401 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 402 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 403 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 404 | } |
<> | 144:ef7eb2e8f9f7 | 405 | } |
<> | 144:ef7eb2e8f9f7 | 406 | /* TXBR to clear BEFORE writing TXDR register */ |
<> | 144:ef7eb2e8f9f7 | 407 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); |
<> | 144:ef7eb2e8f9f7 | 408 | if (hcec->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 409 | { |
<> | 144:ef7eb2e8f9f7 | 410 | /* if last byte transmission, set TX End of Message (TXEOM) bit */ |
<> | 144:ef7eb2e8f9f7 | 411 | __HAL_CEC_LAST_BYTE_TX_SET(hcec); |
<> | 144:ef7eb2e8f9f7 | 412 | } |
<> | 144:ef7eb2e8f9f7 | 413 | hcec->Instance->TXDR = *pData++; |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | /* error check after TX byte write up */ |
<> | 144:ef7eb2e8f9f7 | 416 | tempisr = hcec->Instance->ISR; |
<> | 144:ef7eb2e8f9f7 | 417 | if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) |
<> | 144:ef7eb2e8f9f7 | 418 | { |
<> | 144:ef7eb2e8f9f7 | 419 | /* copy ISR for error handling purposes */ |
<> | 144:ef7eb2e8f9f7 | 420 | hcec->ErrorCode = tempisr; |
<> | 144:ef7eb2e8f9f7 | 421 | /* clear all error flags by default */ |
<> | 144:ef7eb2e8f9f7 | 422 | __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); |
<> | 144:ef7eb2e8f9f7 | 423 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 424 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 425 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 426 | } |
<> | 144:ef7eb2e8f9f7 | 427 | } /* end while (while (hcec->TxXferCount > 0)) */ |
<> | 144:ef7eb2e8f9f7 | 428 | |
<> | 144:ef7eb2e8f9f7 | 429 | |
<> | 144:ef7eb2e8f9f7 | 430 | /* if no error up to this point, check that transmission is |
<> | 144:ef7eb2e8f9f7 | 431 | * complete, that is wait until TXEOM is reset */ |
<> | 144:ef7eb2e8f9f7 | 432 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 433 | |
<> | 144:ef7eb2e8f9f7 | 434 | while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM)) |
<> | 144:ef7eb2e8f9f7 | 435 | { |
<> | 144:ef7eb2e8f9f7 | 436 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 437 | { |
<> | 144:ef7eb2e8f9f7 | 438 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 439 | { |
<> | 144:ef7eb2e8f9f7 | 440 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 441 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 442 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 443 | } |
<> | 144:ef7eb2e8f9f7 | 444 | } |
<> | 144:ef7eb2e8f9f7 | 445 | } |
<> | 144:ef7eb2e8f9f7 | 446 | |
<> | 144:ef7eb2e8f9f7 | 447 | /* Final error check once all bytes have been transmitted */ |
<> | 144:ef7eb2e8f9f7 | 448 | tempisr = hcec->Instance->ISR; |
<> | 144:ef7eb2e8f9f7 | 449 | if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0) |
<> | 144:ef7eb2e8f9f7 | 450 | { |
<> | 144:ef7eb2e8f9f7 | 451 | /* copy ISR for error handling purposes */ |
<> | 144:ef7eb2e8f9f7 | 452 | hcec->ErrorCode = tempisr; |
<> | 144:ef7eb2e8f9f7 | 453 | /* clear all error flags by default */ |
<> | 144:ef7eb2e8f9f7 | 454 | __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)); |
<> | 144:ef7eb2e8f9f7 | 455 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 456 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 457 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 458 | } |
<> | 144:ef7eb2e8f9f7 | 459 | |
<> | 144:ef7eb2e8f9f7 | 460 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 461 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 462 | |
<> | 144:ef7eb2e8f9f7 | 463 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 464 | } |
<> | 144:ef7eb2e8f9f7 | 465 | else |
<> | 144:ef7eb2e8f9f7 | 466 | { |
<> | 144:ef7eb2e8f9f7 | 467 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 468 | } |
<> | 144:ef7eb2e8f9f7 | 469 | } |
<> | 144:ef7eb2e8f9f7 | 470 | |
<> | 144:ef7eb2e8f9f7 | 471 | /** |
<> | 144:ef7eb2e8f9f7 | 472 | * @brief Receive data in blocking mode. Must be invoked when RXBR has been set. |
<> | 144:ef7eb2e8f9f7 | 473 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 474 | * @param pData: pointer to received data buffer. |
<> | 144:ef7eb2e8f9f7 | 475 | * @param Timeout: Timeout duration. |
<> | 144:ef7eb2e8f9f7 | 476 | * Note that the received data size is not known beforehand, the latter is known |
<> | 144:ef7eb2e8f9f7 | 477 | * when the reception is complete and is stored in hcec->RxXferSize. |
<> | 144:ef7eb2e8f9f7 | 478 | * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). |
<> | 144:ef7eb2e8f9f7 | 479 | * If only a header is received, hcec->RxXferSize = 0 |
<> | 144:ef7eb2e8f9f7 | 480 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 481 | */ |
<> | 144:ef7eb2e8f9f7 | 482 | HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 483 | { |
<> | 144:ef7eb2e8f9f7 | 484 | uint32_t temp; |
<> | 144:ef7eb2e8f9f7 | 485 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 486 | |
<> | 144:ef7eb2e8f9f7 | 487 | if (hcec->State == HAL_CEC_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 488 | { |
<> | 144:ef7eb2e8f9f7 | 489 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 490 | if (pData == NULL ) |
<> | 144:ef7eb2e8f9f7 | 491 | { |
<> | 144:ef7eb2e8f9f7 | 492 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 493 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 494 | } |
<> | 144:ef7eb2e8f9f7 | 495 | |
<> | 144:ef7eb2e8f9f7 | 496 | hcec->RxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 497 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 498 | __HAL_LOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 499 | |
<> | 144:ef7eb2e8f9f7 | 500 | |
<> | 144:ef7eb2e8f9f7 | 501 | /* Rx loop until CEC_FLAG_RXEND is set */ |
<> | 144:ef7eb2e8f9f7 | 502 | while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) |
<> | 144:ef7eb2e8f9f7 | 503 | { |
<> | 144:ef7eb2e8f9f7 | 504 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 505 | /* Wait for next byte to be received */ |
<> | 144:ef7eb2e8f9f7 | 506 | while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) |
<> | 144:ef7eb2e8f9f7 | 507 | { |
<> | 144:ef7eb2e8f9f7 | 508 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 509 | { |
<> | 144:ef7eb2e8f9f7 | 510 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 511 | { |
<> | 144:ef7eb2e8f9f7 | 512 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 513 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 514 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 515 | } |
<> | 144:ef7eb2e8f9f7 | 516 | } |
<> | 144:ef7eb2e8f9f7 | 517 | /* any error so far ? |
<> | 144:ef7eb2e8f9f7 | 518 | * has Rx Missing Acknowledge occurred ? |
<> | 144:ef7eb2e8f9f7 | 519 | * has Rx Long Bit Period error occurred ? |
<> | 144:ef7eb2e8f9f7 | 520 | * has Rx Short Bit Period error occurred ? |
<> | 144:ef7eb2e8f9f7 | 521 | * has Rx Bit Rising error occurred ? |
<> | 144:ef7eb2e8f9f7 | 522 | * has Rx Overrun error occurred ? */ |
<> | 144:ef7eb2e8f9f7 | 523 | temp = (uint32_t) (hcec->Instance->ISR); |
<> | 144:ef7eb2e8f9f7 | 524 | if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0) |
<> | 144:ef7eb2e8f9f7 | 525 | { |
<> | 144:ef7eb2e8f9f7 | 526 | /* copy ISR for error handling purposes */ |
<> | 144:ef7eb2e8f9f7 | 527 | hcec->ErrorCode = temp; |
<> | 144:ef7eb2e8f9f7 | 528 | /* clear all error flags by default */ |
<> | 144:ef7eb2e8f9f7 | 529 | __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)); |
<> | 144:ef7eb2e8f9f7 | 530 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 531 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 532 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 533 | } |
<> | 144:ef7eb2e8f9f7 | 534 | } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) */ |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | |
<> | 144:ef7eb2e8f9f7 | 537 | /* read received data */ |
<> | 144:ef7eb2e8f9f7 | 538 | *pData++ = hcec->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 539 | temp = (uint32_t) (hcec->Instance->ISR); |
<> | 144:ef7eb2e8f9f7 | 540 | /* end of message ? */ |
<> | 144:ef7eb2e8f9f7 | 541 | if ((temp & CEC_FLAG_RXEND) != 0) |
<> | 144:ef7eb2e8f9f7 | 542 | { |
<> | 144:ef7eb2e8f9f7 | 543 | assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize)); |
<> | 144:ef7eb2e8f9f7 | 544 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); |
<> | 144:ef7eb2e8f9f7 | 545 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 546 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 547 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 548 | } |
<> | 144:ef7eb2e8f9f7 | 549 | |
<> | 144:ef7eb2e8f9f7 | 550 | /* clear Rx-Byte Received flag */ |
<> | 144:ef7eb2e8f9f7 | 551 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR); |
<> | 144:ef7eb2e8f9f7 | 552 | /* increment payload byte counter */ |
<> | 144:ef7eb2e8f9f7 | 553 | hcec->RxXferSize++; |
<> | 144:ef7eb2e8f9f7 | 554 | } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) */ |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | /* if the instructions below are executed, it means RXEND was set when RXBR was |
<> | 144:ef7eb2e8f9f7 | 557 | * set for the first time: |
<> | 144:ef7eb2e8f9f7 | 558 | * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))" |
<> | 144:ef7eb2e8f9f7 | 559 | * loop has not been executed and this means a single byte has been sent */ |
<> | 144:ef7eb2e8f9f7 | 560 | *pData++ = hcec->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 561 | /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ |
<> | 144:ef7eb2e8f9f7 | 562 | hcec->RxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 563 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); |
<> | 144:ef7eb2e8f9f7 | 564 | |
<> | 144:ef7eb2e8f9f7 | 565 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 566 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 567 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 568 | } |
<> | 144:ef7eb2e8f9f7 | 569 | else |
<> | 144:ef7eb2e8f9f7 | 570 | { |
<> | 144:ef7eb2e8f9f7 | 571 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 572 | } |
<> | 144:ef7eb2e8f9f7 | 573 | } |
<> | 144:ef7eb2e8f9f7 | 574 | |
<> | 144:ef7eb2e8f9f7 | 575 | |
<> | 144:ef7eb2e8f9f7 | 576 | /** |
<> | 144:ef7eb2e8f9f7 | 577 | * @brief Send data in interrupt mode |
<> | 144:ef7eb2e8f9f7 | 578 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 579 | * @param DestinationAddress: destination logical address |
<> | 144:ef7eb2e8f9f7 | 580 | * @param pData: pointer to input byte data buffer |
<> | 144:ef7eb2e8f9f7 | 581 | * @param Size: amount of data to be sent in bytes (without counting the header). |
<> | 144:ef7eb2e8f9f7 | 582 | * 0 means only the header is sent (ping operation). |
<> | 144:ef7eb2e8f9f7 | 583 | * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). |
<> | 144:ef7eb2e8f9f7 | 584 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 585 | */ |
<> | 144:ef7eb2e8f9f7 | 586 | HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) |
<> | 144:ef7eb2e8f9f7 | 587 | { |
<> | 144:ef7eb2e8f9f7 | 588 | uint8_t temp = 0; |
<> | 144:ef7eb2e8f9f7 | 589 | /* if the IP isn't already busy and if there is no previous transmission |
<> | 144:ef7eb2e8f9f7 | 590 | already pending due to arbitration lost */ |
<> | 144:ef7eb2e8f9f7 | 591 | if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX)) |
<> | 144:ef7eb2e8f9f7 | 592 | && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) |
<> | 144:ef7eb2e8f9f7 | 593 | { |
<> | 144:ef7eb2e8f9f7 | 594 | if((pData == NULL ) && (Size > 0)) |
<> | 144:ef7eb2e8f9f7 | 595 | { |
<> | 144:ef7eb2e8f9f7 | 596 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 597 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 598 | } |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | assert_param(IS_CEC_ADDRESS(DestinationAddress)); |
<> | 144:ef7eb2e8f9f7 | 601 | assert_param(IS_CEC_MSGSIZE(Size)); |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 604 | __HAL_LOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 605 | hcec->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 606 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 607 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 608 | |
<> | 144:ef7eb2e8f9f7 | 609 | /* Disable Peripheral to write CEC_IER register */ |
<> | 144:ef7eb2e8f9f7 | 610 | __HAL_CEC_DISABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 611 | |
<> | 144:ef7eb2e8f9f7 | 612 | /* Enable the following two CEC Transmission interrupts as |
<> | 144:ef7eb2e8f9f7 | 613 | * well as the following CEC Transmission Errors interrupts: |
<> | 144:ef7eb2e8f9f7 | 614 | * Tx Byte Request IT |
<> | 144:ef7eb2e8f9f7 | 615 | * End of Transmission IT |
<> | 144:ef7eb2e8f9f7 | 616 | * Tx Missing Acknowledge IT |
<> | 144:ef7eb2e8f9f7 | 617 | * Tx-Error IT |
<> | 144:ef7eb2e8f9f7 | 618 | * Tx-Buffer Underrun IT |
<> | 144:ef7eb2e8f9f7 | 619 | * Tx arbitration lost */ |
<> | 144:ef7eb2e8f9f7 | 620 | __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); |
<> | 144:ef7eb2e8f9f7 | 621 | |
<> | 144:ef7eb2e8f9f7 | 622 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 623 | __HAL_CEC_ENABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 624 | |
<> | 144:ef7eb2e8f9f7 | 625 | /* initialize the number of bytes to send, |
<> | 144:ef7eb2e8f9f7 | 626 | * 0 means only one header is sent (ping operation) */ |
<> | 144:ef7eb2e8f9f7 | 627 | hcec->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 628 | |
<> | 144:ef7eb2e8f9f7 | 629 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 630 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 631 | |
<> | 144:ef7eb2e8f9f7 | 632 | /* in case of no payload (Size = 0), sender is only pinging the system; |
<> | 144:ef7eb2e8f9f7 | 633 | * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ |
<> | 144:ef7eb2e8f9f7 | 634 | if (Size == 0) |
<> | 144:ef7eb2e8f9f7 | 635 | { |
<> | 144:ef7eb2e8f9f7 | 636 | __HAL_CEC_LAST_BYTE_TX_SET(hcec); |
<> | 144:ef7eb2e8f9f7 | 637 | } |
<> | 144:ef7eb2e8f9f7 | 638 | |
<> | 144:ef7eb2e8f9f7 | 639 | /* send header block */ |
<> | 144:ef7eb2e8f9f7 | 640 | temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; |
<> | 144:ef7eb2e8f9f7 | 641 | hcec->Instance->TXDR = temp; |
<> | 144:ef7eb2e8f9f7 | 642 | /* Set TX Start of Message (TXSOM) bit */ |
<> | 144:ef7eb2e8f9f7 | 643 | __HAL_CEC_FIRST_BYTE_TX_SET(hcec); |
<> | 144:ef7eb2e8f9f7 | 644 | |
<> | 144:ef7eb2e8f9f7 | 645 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 646 | } |
<> | 144:ef7eb2e8f9f7 | 647 | /* if the IP is already busy or if there is a previous transmission |
<> | 144:ef7eb2e8f9f7 | 648 | already pending due to arbitration loss */ |
<> | 144:ef7eb2e8f9f7 | 649 | else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 650 | || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 651 | { |
<> | 144:ef7eb2e8f9f7 | 652 | __HAL_LOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 653 | /* set state to BUSY TX, in case it wasn't set already (case |
<> | 144:ef7eb2e8f9f7 | 654 | * of transmission new attempt after arbitration loss) */ |
<> | 144:ef7eb2e8f9f7 | 655 | if (hcec->State != HAL_CEC_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 656 | { |
<> | 144:ef7eb2e8f9f7 | 657 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 658 | } |
<> | 144:ef7eb2e8f9f7 | 659 | |
<> | 144:ef7eb2e8f9f7 | 660 | /* if all data have been sent */ |
<> | 144:ef7eb2e8f9f7 | 661 | if(hcec->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 662 | { |
<> | 144:ef7eb2e8f9f7 | 663 | /* Disable Peripheral to write CEC_IER register */ |
<> | 144:ef7eb2e8f9f7 | 664 | __HAL_CEC_DISABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 665 | |
<> | 144:ef7eb2e8f9f7 | 666 | /* Disable the CEC Transmission Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 667 | __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); |
<> | 144:ef7eb2e8f9f7 | 668 | /* Disable the CEC Transmission Error Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 669 | __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); |
<> | 144:ef7eb2e8f9f7 | 670 | |
<> | 144:ef7eb2e8f9f7 | 671 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 672 | __HAL_CEC_ENABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 673 | |
<> | 144:ef7eb2e8f9f7 | 674 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); |
<> | 144:ef7eb2e8f9f7 | 675 | |
<> | 144:ef7eb2e8f9f7 | 676 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 677 | /* Call the Process Unlocked before calling the Tx call back API to give the possibility to |
<> | 144:ef7eb2e8f9f7 | 678 | start again the Transmission under the Tx call back API */ |
<> | 144:ef7eb2e8f9f7 | 679 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 680 | |
<> | 144:ef7eb2e8f9f7 | 681 | HAL_CEC_TxCpltCallback(hcec); |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 684 | } |
<> | 144:ef7eb2e8f9f7 | 685 | else |
<> | 144:ef7eb2e8f9f7 | 686 | { |
<> | 144:ef7eb2e8f9f7 | 687 | if (hcec->TxXferCount == 1) |
<> | 144:ef7eb2e8f9f7 | 688 | { |
<> | 144:ef7eb2e8f9f7 | 689 | /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ |
<> | 144:ef7eb2e8f9f7 | 690 | __HAL_CEC_LAST_BYTE_TX_SET(hcec); |
<> | 144:ef7eb2e8f9f7 | 691 | } |
<> | 144:ef7eb2e8f9f7 | 692 | /* clear Tx-Byte request flag */ |
<> | 144:ef7eb2e8f9f7 | 693 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); |
<> | 144:ef7eb2e8f9f7 | 694 | hcec->Instance->TXDR = *hcec->pTxBuffPtr++; |
<> | 144:ef7eb2e8f9f7 | 695 | hcec->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 696 | |
<> | 144:ef7eb2e8f9f7 | 697 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 698 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 699 | |
<> | 144:ef7eb2e8f9f7 | 700 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 701 | } |
<> | 144:ef7eb2e8f9f7 | 702 | } |
<> | 144:ef7eb2e8f9f7 | 703 | else |
<> | 144:ef7eb2e8f9f7 | 704 | { |
<> | 144:ef7eb2e8f9f7 | 705 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 706 | } |
<> | 144:ef7eb2e8f9f7 | 707 | } |
<> | 144:ef7eb2e8f9f7 | 708 | |
<> | 144:ef7eb2e8f9f7 | 709 | |
<> | 144:ef7eb2e8f9f7 | 710 | /** |
<> | 144:ef7eb2e8f9f7 | 711 | * @brief Receive data in interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 712 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 713 | * @param pData: pointer to received data buffer. |
<> | 144:ef7eb2e8f9f7 | 714 | * Note that the received data size is not known beforehand, the latter is known |
<> | 144:ef7eb2e8f9f7 | 715 | * when the reception is complete and is stored in hcec->RxXferSize. |
<> | 144:ef7eb2e8f9f7 | 716 | * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). |
<> | 144:ef7eb2e8f9f7 | 717 | * If only a header is received, hcec->RxXferSize = 0 |
<> | 144:ef7eb2e8f9f7 | 718 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 719 | */ |
<> | 144:ef7eb2e8f9f7 | 720 | HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) |
<> | 144:ef7eb2e8f9f7 | 721 | { |
<> | 144:ef7eb2e8f9f7 | 722 | if(hcec->State == HAL_CEC_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 723 | { |
<> | 144:ef7eb2e8f9f7 | 724 | if(pData == NULL ) |
<> | 144:ef7eb2e8f9f7 | 725 | { |
<> | 144:ef7eb2e8f9f7 | 726 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 727 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 728 | } |
<> | 144:ef7eb2e8f9f7 | 729 | |
<> | 144:ef7eb2e8f9f7 | 730 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 731 | __HAL_LOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 732 | hcec->RxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 733 | hcec->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 734 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 735 | /* the IP is moving to a ready to receive state */ |
<> | 144:ef7eb2e8f9f7 | 736 | hcec->State = HAL_CEC_STATE_STANDBY_RX; |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | /* Disable Peripheral to write CEC_IER register */ |
<> | 144:ef7eb2e8f9f7 | 739 | __HAL_CEC_DISABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 740 | |
<> | 144:ef7eb2e8f9f7 | 741 | /* Enable the following CEC Reception Error Interrupts: |
<> | 144:ef7eb2e8f9f7 | 742 | * Rx overrun |
<> | 144:ef7eb2e8f9f7 | 743 | * Rx bit rising error |
<> | 144:ef7eb2e8f9f7 | 744 | * Rx short bit period error |
<> | 144:ef7eb2e8f9f7 | 745 | * Rx long bit period error |
<> | 144:ef7eb2e8f9f7 | 746 | * Rx missing acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 747 | __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR); |
<> | 144:ef7eb2e8f9f7 | 748 | |
<> | 144:ef7eb2e8f9f7 | 749 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 750 | __HAL_UNLOCK(hcec); |
<> | 144:ef7eb2e8f9f7 | 751 | |
<> | 144:ef7eb2e8f9f7 | 752 | /* Enable the following two CEC Reception interrupts: |
<> | 144:ef7eb2e8f9f7 | 753 | * Rx Byte Received IT |
<> | 144:ef7eb2e8f9f7 | 754 | * End of Reception IT */ |
<> | 144:ef7eb2e8f9f7 | 755 | __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND); |
<> | 144:ef7eb2e8f9f7 | 756 | |
<> | 144:ef7eb2e8f9f7 | 757 | __HAL_CEC_ENABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 758 | |
<> | 144:ef7eb2e8f9f7 | 759 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 760 | } |
<> | 144:ef7eb2e8f9f7 | 761 | else |
<> | 144:ef7eb2e8f9f7 | 762 | { |
<> | 144:ef7eb2e8f9f7 | 763 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | } |
<> | 144:ef7eb2e8f9f7 | 766 | |
<> | 144:ef7eb2e8f9f7 | 767 | /** |
<> | 144:ef7eb2e8f9f7 | 768 | * @brief Get size of the received frame. |
<> | 144:ef7eb2e8f9f7 | 769 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 770 | * @retval Frame size |
<> | 144:ef7eb2e8f9f7 | 771 | */ |
<> | 144:ef7eb2e8f9f7 | 772 | uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 773 | { |
<> | 144:ef7eb2e8f9f7 | 774 | return hcec->RxXferSize; |
<> | 144:ef7eb2e8f9f7 | 775 | } |
<> | 144:ef7eb2e8f9f7 | 776 | |
<> | 144:ef7eb2e8f9f7 | 777 | /** |
<> | 144:ef7eb2e8f9f7 | 778 | * @brief This function handles CEC interrupt requests. |
<> | 144:ef7eb2e8f9f7 | 779 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 780 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 781 | */ |
<> | 144:ef7eb2e8f9f7 | 782 | void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 783 | { |
<> | 144:ef7eb2e8f9f7 | 784 | /* save interrupts register for further error or interrupts handling purposes */ |
<> | 144:ef7eb2e8f9f7 | 785 | hcec->ErrorCode = hcec->Instance->ISR; |
<> | 144:ef7eb2e8f9f7 | 786 | /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 787 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 788 | { |
<> | 144:ef7eb2e8f9f7 | 789 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE); |
<> | 144:ef7eb2e8f9f7 | 790 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 791 | } |
<> | 144:ef7eb2e8f9f7 | 792 | |
<> | 144:ef7eb2e8f9f7 | 793 | /* CEC transmit error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 794 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 795 | { |
<> | 144:ef7eb2e8f9f7 | 796 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR); |
<> | 144:ef7eb2e8f9f7 | 797 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 798 | } |
<> | 144:ef7eb2e8f9f7 | 799 | |
<> | 144:ef7eb2e8f9f7 | 800 | /* CEC TX underrun error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 801 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 802 | { |
<> | 144:ef7eb2e8f9f7 | 803 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR); |
<> | 144:ef7eb2e8f9f7 | 804 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 805 | } |
<> | 144:ef7eb2e8f9f7 | 806 | |
<> | 144:ef7eb2e8f9f7 | 807 | /* CEC TX arbitration error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 808 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 809 | { |
<> | 144:ef7eb2e8f9f7 | 810 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); |
<> | 144:ef7eb2e8f9f7 | 811 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 812 | } |
<> | 144:ef7eb2e8f9f7 | 813 | |
<> | 144:ef7eb2e8f9f7 | 814 | /* CEC RX overrun error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 815 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 816 | { |
<> | 144:ef7eb2e8f9f7 | 817 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR); |
<> | 144:ef7eb2e8f9f7 | 818 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 819 | } |
<> | 144:ef7eb2e8f9f7 | 820 | |
<> | 144:ef7eb2e8f9f7 | 821 | /* CEC RX bit rising error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 822 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 823 | { |
<> | 144:ef7eb2e8f9f7 | 824 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE); |
<> | 144:ef7eb2e8f9f7 | 825 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 826 | } |
<> | 144:ef7eb2e8f9f7 | 827 | |
<> | 144:ef7eb2e8f9f7 | 828 | /* CEC RX short bit period error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 829 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 830 | { |
<> | 144:ef7eb2e8f9f7 | 831 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE); |
<> | 144:ef7eb2e8f9f7 | 832 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 833 | } |
<> | 144:ef7eb2e8f9f7 | 834 | |
<> | 144:ef7eb2e8f9f7 | 835 | /* CEC RX long bit period error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 836 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 837 | { |
<> | 144:ef7eb2e8f9f7 | 838 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE); |
<> | 144:ef7eb2e8f9f7 | 839 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 840 | } |
<> | 144:ef7eb2e8f9f7 | 841 | |
<> | 144:ef7eb2e8f9f7 | 842 | /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 843 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 844 | { |
<> | 144:ef7eb2e8f9f7 | 845 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE); |
<> | 144:ef7eb2e8f9f7 | 846 | hcec->State = HAL_CEC_STATE_ERROR; |
<> | 144:ef7eb2e8f9f7 | 847 | } |
<> | 144:ef7eb2e8f9f7 | 848 | |
<> | 144:ef7eb2e8f9f7 | 849 | if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0) |
<> | 144:ef7eb2e8f9f7 | 850 | { |
<> | 144:ef7eb2e8f9f7 | 851 | HAL_CEC_ErrorCallback(hcec); |
<> | 144:ef7eb2e8f9f7 | 852 | } |
<> | 144:ef7eb2e8f9f7 | 853 | |
<> | 144:ef7eb2e8f9f7 | 854 | /* CEC RX byte received interrupt ---------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 855 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 856 | { |
<> | 144:ef7eb2e8f9f7 | 857 | /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ |
<> | 144:ef7eb2e8f9f7 | 858 | CEC_Receive_IT(hcec); |
<> | 144:ef7eb2e8f9f7 | 859 | } |
<> | 144:ef7eb2e8f9f7 | 860 | |
<> | 144:ef7eb2e8f9f7 | 861 | /* CEC RX end received interrupt ---------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 862 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 863 | { |
<> | 144:ef7eb2e8f9f7 | 864 | /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ |
<> | 144:ef7eb2e8f9f7 | 865 | CEC_Receive_IT(hcec); |
<> | 144:ef7eb2e8f9f7 | 866 | } |
<> | 144:ef7eb2e8f9f7 | 867 | |
<> | 144:ef7eb2e8f9f7 | 868 | |
<> | 144:ef7eb2e8f9f7 | 869 | /* CEC TX byte request interrupt ------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 870 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 871 | { |
<> | 144:ef7eb2e8f9f7 | 872 | /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */ |
<> | 144:ef7eb2e8f9f7 | 873 | CEC_Transmit_IT(hcec); |
<> | 144:ef7eb2e8f9f7 | 874 | } |
<> | 144:ef7eb2e8f9f7 | 875 | |
<> | 144:ef7eb2e8f9f7 | 876 | /* CEC TX end interrupt ------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 877 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 878 | { |
<> | 144:ef7eb2e8f9f7 | 879 | /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */ |
<> | 144:ef7eb2e8f9f7 | 880 | CEC_Transmit_IT(hcec); |
<> | 144:ef7eb2e8f9f7 | 881 | } |
<> | 144:ef7eb2e8f9f7 | 882 | |
<> | 144:ef7eb2e8f9f7 | 883 | } |
<> | 144:ef7eb2e8f9f7 | 884 | |
<> | 144:ef7eb2e8f9f7 | 885 | |
<> | 144:ef7eb2e8f9f7 | 886 | /** |
<> | 144:ef7eb2e8f9f7 | 887 | * @brief Tx Transfer completed callback |
<> | 144:ef7eb2e8f9f7 | 888 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 889 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 890 | */ |
<> | 144:ef7eb2e8f9f7 | 891 | __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 892 | { |
<> | 144:ef7eb2e8f9f7 | 893 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 894 | UNUSED(hcec); |
<> | 144:ef7eb2e8f9f7 | 895 | |
<> | 144:ef7eb2e8f9f7 | 896 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 897 | the HAL_CEC_TxCpltCallback can be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 898 | */ |
<> | 144:ef7eb2e8f9f7 | 899 | } |
<> | 144:ef7eb2e8f9f7 | 900 | |
<> | 144:ef7eb2e8f9f7 | 901 | /** |
<> | 144:ef7eb2e8f9f7 | 902 | * @brief Rx Transfer completed callback |
<> | 144:ef7eb2e8f9f7 | 903 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 904 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 905 | */ |
<> | 144:ef7eb2e8f9f7 | 906 | __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 907 | { |
<> | 144:ef7eb2e8f9f7 | 908 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 909 | UNUSED(hcec); |
<> | 144:ef7eb2e8f9f7 | 910 | |
<> | 144:ef7eb2e8f9f7 | 911 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 912 | the HAL_CEC_TxCpltCallback can be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 913 | */ |
<> | 144:ef7eb2e8f9f7 | 914 | } |
<> | 144:ef7eb2e8f9f7 | 915 | |
<> | 144:ef7eb2e8f9f7 | 916 | /** |
<> | 144:ef7eb2e8f9f7 | 917 | * @brief CEC error callbacks |
<> | 144:ef7eb2e8f9f7 | 918 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 919 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 920 | */ |
<> | 144:ef7eb2e8f9f7 | 921 | __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 922 | { |
<> | 144:ef7eb2e8f9f7 | 923 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 924 | UNUSED(hcec); |
<> | 144:ef7eb2e8f9f7 | 925 | |
<> | 144:ef7eb2e8f9f7 | 926 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 927 | the HAL_CEC_ErrorCallback can be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 928 | */ |
<> | 144:ef7eb2e8f9f7 | 929 | } |
<> | 144:ef7eb2e8f9f7 | 930 | |
<> | 144:ef7eb2e8f9f7 | 931 | /** |
<> | 144:ef7eb2e8f9f7 | 932 | * @} |
<> | 144:ef7eb2e8f9f7 | 933 | */ |
<> | 144:ef7eb2e8f9f7 | 934 | |
<> | 144:ef7eb2e8f9f7 | 935 | /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function |
<> | 144:ef7eb2e8f9f7 | 936 | * @brief CEC control functions |
<> | 144:ef7eb2e8f9f7 | 937 | * |
<> | 144:ef7eb2e8f9f7 | 938 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 939 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 940 | ##### Peripheral Control function ##### |
<> | 144:ef7eb2e8f9f7 | 941 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 942 | [..] |
<> | 144:ef7eb2e8f9f7 | 943 | This subsection provides a set of functions allowing to control the CEC. |
<> | 144:ef7eb2e8f9f7 | 944 | (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. |
<> | 144:ef7eb2e8f9f7 | 945 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 946 | * @{ |
<> | 144:ef7eb2e8f9f7 | 947 | */ |
<> | 144:ef7eb2e8f9f7 | 948 | |
<> | 144:ef7eb2e8f9f7 | 949 | /** |
<> | 144:ef7eb2e8f9f7 | 950 | * @brief return the CEC state |
<> | 144:ef7eb2e8f9f7 | 951 | * @param hcec: CEC handle |
<> | 144:ef7eb2e8f9f7 | 952 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 953 | */ |
<> | 144:ef7eb2e8f9f7 | 954 | HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 955 | { |
<> | 144:ef7eb2e8f9f7 | 956 | return hcec->State; |
<> | 144:ef7eb2e8f9f7 | 957 | } |
<> | 144:ef7eb2e8f9f7 | 958 | |
<> | 144:ef7eb2e8f9f7 | 959 | /** |
<> | 144:ef7eb2e8f9f7 | 960 | * @brief Return the CEC error code |
<> | 144:ef7eb2e8f9f7 | 961 | * @param hcec : pointer to a CEC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 962 | * the configuration information for the specified CEC. |
<> | 144:ef7eb2e8f9f7 | 963 | * @retval CEC Error Code |
<> | 144:ef7eb2e8f9f7 | 964 | */ |
<> | 144:ef7eb2e8f9f7 | 965 | uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 966 | { |
<> | 144:ef7eb2e8f9f7 | 967 | return hcec->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 968 | } |
<> | 144:ef7eb2e8f9f7 | 969 | |
<> | 144:ef7eb2e8f9f7 | 970 | /** |
<> | 144:ef7eb2e8f9f7 | 971 | * @} |
<> | 144:ef7eb2e8f9f7 | 972 | */ |
<> | 144:ef7eb2e8f9f7 | 973 | |
<> | 144:ef7eb2e8f9f7 | 974 | /** |
<> | 144:ef7eb2e8f9f7 | 975 | * @} |
<> | 144:ef7eb2e8f9f7 | 976 | */ |
<> | 144:ef7eb2e8f9f7 | 977 | |
<> | 144:ef7eb2e8f9f7 | 978 | /** @defgroup CEC_Private_Functions CEC Private Functions |
<> | 144:ef7eb2e8f9f7 | 979 | * @{ |
<> | 144:ef7eb2e8f9f7 | 980 | */ |
<> | 144:ef7eb2e8f9f7 | 981 | |
<> | 144:ef7eb2e8f9f7 | 982 | /** |
<> | 144:ef7eb2e8f9f7 | 983 | * @brief Send data in interrupt mode |
<> | 144:ef7eb2e8f9f7 | 984 | * @param hcec: CEC handle. |
<> | 144:ef7eb2e8f9f7 | 985 | * Function called under interruption only, once |
<> | 144:ef7eb2e8f9f7 | 986 | * interruptions have been enabled by HAL_CEC_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 987 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 988 | */ |
<> | 144:ef7eb2e8f9f7 | 989 | static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 990 | { |
<> | 144:ef7eb2e8f9f7 | 991 | /* if the IP is already busy or if there is a previous transmission |
<> | 144:ef7eb2e8f9f7 | 992 | already pending due to arbitration loss */ |
<> | 144:ef7eb2e8f9f7 | 993 | if ((hcec->State == HAL_CEC_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 994 | || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 995 | { |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | /* set state to BUSY TX, in case it wasn't set already (case |
<> | 144:ef7eb2e8f9f7 | 998 | * of transmission new attempt after arbitration loss) */ |
<> | 144:ef7eb2e8f9f7 | 999 | if (hcec->State != HAL_CEC_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 1000 | { |
<> | 144:ef7eb2e8f9f7 | 1001 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 1002 | } |
<> | 144:ef7eb2e8f9f7 | 1003 | |
<> | 144:ef7eb2e8f9f7 | 1004 | /* if all data have been sent */ |
<> | 144:ef7eb2e8f9f7 | 1005 | if(hcec->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 1006 | { |
<> | 144:ef7eb2e8f9f7 | 1007 | /* Disable Peripheral to write CEC_IER register */ |
<> | 144:ef7eb2e8f9f7 | 1008 | __HAL_CEC_DISABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 1009 | |
<> | 144:ef7eb2e8f9f7 | 1010 | /* Disable the CEC Transmission Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1011 | __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); |
<> | 144:ef7eb2e8f9f7 | 1012 | /* Disable the CEC Transmission Error Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1013 | __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); |
<> | 144:ef7eb2e8f9f7 | 1014 | |
<> | 144:ef7eb2e8f9f7 | 1015 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1016 | __HAL_CEC_ENABLE(hcec); |
<> | 144:ef7eb2e8f9f7 | 1017 | |
<> | 144:ef7eb2e8f9f7 | 1018 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); |
<> | 144:ef7eb2e8f9f7 | 1019 | |
<> | 144:ef7eb2e8f9f7 | 1020 | /* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */ |
<> | 144:ef7eb2e8f9f7 | 1021 | if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IT_RXBR|CEC_IT_RXEND) ) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1022 | { |
<> | 144:ef7eb2e8f9f7 | 1023 | hcec->State = HAL_CEC_STATE_STANDBY_RX; |
<> | 144:ef7eb2e8f9f7 | 1024 | } |
<> | 144:ef7eb2e8f9f7 | 1025 | else |
<> | 144:ef7eb2e8f9f7 | 1026 | { |
<> | 144:ef7eb2e8f9f7 | 1027 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1028 | } |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 144:ef7eb2e8f9f7 | 1030 | HAL_CEC_TxCpltCallback(hcec); |
<> | 144:ef7eb2e8f9f7 | 1031 | |
<> | 144:ef7eb2e8f9f7 | 1032 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1033 | } |
<> | 144:ef7eb2e8f9f7 | 1034 | else |
<> | 144:ef7eb2e8f9f7 | 1035 | { |
<> | 144:ef7eb2e8f9f7 | 1036 | if (hcec->TxXferCount == 1) |
<> | 144:ef7eb2e8f9f7 | 1037 | { |
<> | 144:ef7eb2e8f9f7 | 1038 | /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ |
<> | 144:ef7eb2e8f9f7 | 1039 | __HAL_CEC_LAST_BYTE_TX_SET(hcec); |
<> | 144:ef7eb2e8f9f7 | 1040 | } |
<> | 144:ef7eb2e8f9f7 | 1041 | /* clear Tx-Byte request flag */ |
<> | 144:ef7eb2e8f9f7 | 1042 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); |
<> | 144:ef7eb2e8f9f7 | 1043 | hcec->Instance->TXDR = *hcec->pTxBuffPtr++; |
<> | 144:ef7eb2e8f9f7 | 1044 | hcec->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 1045 | |
<> | 144:ef7eb2e8f9f7 | 1046 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1047 | } |
<> | 144:ef7eb2e8f9f7 | 1048 | } |
<> | 144:ef7eb2e8f9f7 | 1049 | else |
<> | 144:ef7eb2e8f9f7 | 1050 | { |
<> | 144:ef7eb2e8f9f7 | 1051 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1052 | } |
<> | 144:ef7eb2e8f9f7 | 1053 | } |
<> | 144:ef7eb2e8f9f7 | 1054 | |
<> | 144:ef7eb2e8f9f7 | 1055 | |
<> | 144:ef7eb2e8f9f7 | 1056 | /** |
<> | 144:ef7eb2e8f9f7 | 1057 | * @brief Receive data in interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 1058 | * @param hcec: CEC handle. |
<> | 144:ef7eb2e8f9f7 | 1059 | * Function called under interruption only, once |
<> | 144:ef7eb2e8f9f7 | 1060 | * interruptions have been enabled by HAL_CEC_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 1061 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1062 | */ |
<> | 144:ef7eb2e8f9f7 | 1063 | static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) |
<> | 144:ef7eb2e8f9f7 | 1064 | { |
<> | 144:ef7eb2e8f9f7 | 1065 | uint32_t tempisr; |
<> | 144:ef7eb2e8f9f7 | 1066 | |
<> | 144:ef7eb2e8f9f7 | 1067 | /* Three different conditions are tested to carry out the RX IT processing: |
<> | 144:ef7eb2e8f9f7 | 1068 | * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and |
<> | 144:ef7eb2e8f9f7 | 1069 | * the reception of the first byte is starting |
<> | 144:ef7eb2e8f9f7 | 1070 | * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 1071 | * and a new byte is being received |
<> | 144:ef7eb2e8f9f7 | 1072 | * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 1073 | * but has been interrupted by a new message reception or discarded due to |
<> | 144:ef7eb2e8f9f7 | 1074 | * arbitration loss: the reception of the first or higher priority message |
<> | 144:ef7eb2e8f9f7 | 1075 | * (the arbitration winner) is starting */ |
<> | 144:ef7eb2e8f9f7 | 1076 | if ((hcec->State == HAL_CEC_STATE_STANDBY_RX) |
<> | 144:ef7eb2e8f9f7 | 1077 | || (hcec->State == HAL_CEC_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 1078 | || (hcec->State == HAL_CEC_STATE_BUSY_TX)) |
<> | 144:ef7eb2e8f9f7 | 1079 | { |
<> | 144:ef7eb2e8f9f7 | 1080 | /* reception is starting */ |
<> | 144:ef7eb2e8f9f7 | 1081 | hcec->State = HAL_CEC_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1082 | tempisr = (uint32_t) (hcec->Instance->ISR); |
<> | 144:ef7eb2e8f9f7 | 1083 | if ((tempisr & CEC_FLAG_RXBR) != 0) |
<> | 144:ef7eb2e8f9f7 | 1084 | { |
<> | 144:ef7eb2e8f9f7 | 1085 | /* read received byte */ |
<> | 144:ef7eb2e8f9f7 | 1086 | *hcec->pRxBuffPtr++ = hcec->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 1087 | /* if last byte has been received */ |
<> | 144:ef7eb2e8f9f7 | 1088 | if ((tempisr & CEC_FLAG_RXEND) != 0) |
<> | 144:ef7eb2e8f9f7 | 1089 | { |
<> | 144:ef7eb2e8f9f7 | 1090 | /* clear IT */ |
<> | 144:ef7eb2e8f9f7 | 1091 | __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND); |
<> | 144:ef7eb2e8f9f7 | 1092 | /* RX interrupts are not disabled at this point. |
<> | 144:ef7eb2e8f9f7 | 1093 | * Indeed, to disable the IT, the IP must be disabled first |
<> | 144:ef7eb2e8f9f7 | 1094 | * which resets the TXSOM flag. In case of arbitration loss, |
<> | 144:ef7eb2e8f9f7 | 1095 | * this leads to a transmission abort. |
<> | 144:ef7eb2e8f9f7 | 1096 | * Therefore, RX interruptions disabling if so required, |
<> | 144:ef7eb2e8f9f7 | 1097 | * is done in HAL_CEC_RxCpltCallback */ |
<> | 144:ef7eb2e8f9f7 | 1098 | |
<> | 144:ef7eb2e8f9f7 | 1099 | /* IP state is moved to READY. |
<> | 144:ef7eb2e8f9f7 | 1100 | * If the IP must remain in standby mode to listen |
<> | 144:ef7eb2e8f9f7 | 1101 | * any new message, it is up to HAL_CEC_RxCpltCallback |
<> | 144:ef7eb2e8f9f7 | 1102 | * to move it again to HAL_CEC_STATE_STANDBY_RX */ |
<> | 144:ef7eb2e8f9f7 | 1103 | hcec->State = HAL_CEC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1104 | |
<> | 144:ef7eb2e8f9f7 | 1105 | HAL_CEC_RxCpltCallback(hcec); |
<> | 144:ef7eb2e8f9f7 | 1106 | |
<> | 144:ef7eb2e8f9f7 | 1107 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1108 | } |
<> | 144:ef7eb2e8f9f7 | 1109 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); |
<> | 144:ef7eb2e8f9f7 | 1110 | |
<> | 144:ef7eb2e8f9f7 | 1111 | hcec->RxXferSize++; |
<> | 144:ef7eb2e8f9f7 | 1112 | |
<> | 144:ef7eb2e8f9f7 | 1113 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1114 | } |
<> | 144:ef7eb2e8f9f7 | 1115 | else |
<> | 144:ef7eb2e8f9f7 | 1116 | { |
<> | 144:ef7eb2e8f9f7 | 1117 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1118 | } |
<> | 144:ef7eb2e8f9f7 | 1119 | } |
<> | 144:ef7eb2e8f9f7 | 1120 | else |
<> | 144:ef7eb2e8f9f7 | 1121 | { |
<> | 144:ef7eb2e8f9f7 | 1122 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1123 | } |
<> | 144:ef7eb2e8f9f7 | 1124 | } |
<> | 144:ef7eb2e8f9f7 | 1125 | |
<> | 144:ef7eb2e8f9f7 | 1126 | /** |
<> | 144:ef7eb2e8f9f7 | 1127 | * @} |
<> | 144:ef7eb2e8f9f7 | 1128 | */ |
<> | 144:ef7eb2e8f9f7 | 1129 | |
<> | 144:ef7eb2e8f9f7 | 1130 | /** |
<> | 144:ef7eb2e8f9f7 | 1131 | * @} |
<> | 144:ef7eb2e8f9f7 | 1132 | */ |
<> | 144:ef7eb2e8f9f7 | 1133 | |
<> | 144:ef7eb2e8f9f7 | 1134 | /** |
<> | 144:ef7eb2e8f9f7 | 1135 | * @} |
<> | 144:ef7eb2e8f9f7 | 1136 | */ |
<> | 144:ef7eb2e8f9f7 | 1137 | |
<> | 144:ef7eb2e8f9f7 | 1138 | #endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */ |
<> | 144:ef7eb2e8f9f7 | 1139 | /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ |
<> | 144:ef7eb2e8f9f7 | 1140 | /* defined(STM32F091xC) || defined (STM32F098xx) */ |
<> | 144:ef7eb2e8f9f7 | 1141 | |
<> | 144:ef7eb2e8f9f7 | 1142 | #endif /* HAL_CEC_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 1143 | |
<> | 144:ef7eb2e8f9f7 | 1144 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |