mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cortex.h
- Revision:
- 167:e84263d55307
- Parent:
- 149:156823d33999
--- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cortex.h Thu Jun 08 15:02:37 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cortex.h Wed Jun 21 17:46:44 2017 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.1.3
- * @date 29-June-2016
+ * @version V1.2.1
+ * @date 14-April-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,11 +54,11 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
* @{
*/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
@@ -105,16 +105,16 @@
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
-#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
+#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
/**
* @}
*/
@@ -122,8 +122,8 @@
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
-#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
@@ -133,10 +133,11 @@
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
-#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
-#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
-#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
-#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
+#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
+#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
+#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
+#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
/**
* @}
*/
@@ -144,8 +145,8 @@
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
-#define MPU_REGION_ENABLE ((uint8_t)0x01U)
-#define MPU_REGION_DISABLE ((uint8_t)0x00U)
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -153,8 +154,8 @@
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
@@ -162,8 +163,8 @@
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -171,8 +172,8 @@
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -180,8 +181,8 @@
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
@@ -189,9 +190,9 @@
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
@@ -199,47 +200,47 @@
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
-/**
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
@@ -247,14 +248,14 @@
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
@@ -273,8 +274,8 @@
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
+ * @{
+ */
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
@@ -287,12 +288,9 @@
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@@ -302,6 +300,12 @@
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
/**
* @}
*/
@@ -310,7 +314,7 @@
* @}
*/
-/* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
@@ -397,57 +401,14 @@
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
- * @brief CORTEX private functions
- * @{
*/
-#if (__MPU_PRESENT == 1)
-/**
- * @brief Disables the MPU
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU */
- MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
- * @brief Enables the MPU
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
+/* Private functions ---------------------------------------------------------*/
/**
* @}
