Diff: targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h

Revision:

165:e614a9f1c9e2

Parent:

154:37f96f9d4de2

Child:

187:0387e8f68319

--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h	Wed May 10 12:06:41 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h	Fri May 26 12:39:01 2017 +0100
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f1xx_ll_pwr.h
   * @author  MCD Application Team
-  * @version $VERSION$
-  * @date    $DATE$
+  * @version V1.1.0
+  * @date    14-April-2017
   * @brief   Header file of PWR LL module.
   ******************************************************************************
   * @attention
@@ -93,7 +93,7 @@
   * @{
   */
 #define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
 #define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
 /**
   * @}
@@ -102,8 +102,8 @@
 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
  * @{
  */
-#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage regulator in low-power mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
 /**
   * @}
   */
@@ -125,7 +125,7 @@
 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
   * @{
   */
-#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)        /*!< WKUP pin 1 : PA0 */
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin 1 : PA0 */
 /**
   * @}
   */
@@ -206,7 +206,7 @@
 }
 
 /**
-  * @brief  Set voltage regulator mode during deep sleep mode
+  * @brief  Set voltage Regulator mode during deep sleep mode
   * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
   * @param  RegulMode This parameter can be one of the following values:
   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
@@ -219,7 +219,7 @@
 }
 
 /**
-  * @brief  Get voltage regulator mode during deep sleep mode
+  * @brief  Get voltage Regulator mode during deep sleep mode
   * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
@@ -231,7 +231,7 @@
 }
 
 /**
-  * @brief  Set power down mode when CPU enters deepsleep
+  * @brief  Set Power Down mode when CPU enters deepsleep
   * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
   * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
   * @param  PDMode This parameter can be one of the following values:
@@ -246,7 +246,7 @@
 }
 
 /**
-  * @brief  Get power down mode when CPU enters deepsleep
+  * @brief  Get Power Down mode when CPU enters deepsleep
   * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
   * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
   * @retval Returned value can be one of the following values:
@@ -420,6 +420,11 @@
 {
   SET_BIT(PWR->CR, PWR_CR_CWUF);
 }
+
+/**
+  * @}
+  */
+
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup PWR_LL_EF_Init De-initialization function
   * @{
@@ -438,10 +443,6 @@
   * @}
   */
 
-/**
-  * @}
-  */
-
 #endif /* defined(PWR) */
 
 /**