Diff: cmsis/TARGET_CORTEX_M/cmsis_armclang.h

Revision:

188:bcfe06ba3d64

Parent:

186:707f6e361f3e

--- a/cmsis/TARGET_CORTEX_M/cmsis_armclang.h	Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h	Thu Nov 08 11:46:34 2018 +0000
@@ -237,7 +237,7 @@
  */
 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
   return(result);
@@ -252,7 +252,7 @@
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
   return(result);
@@ -291,7 +291,7 @@
  */
 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, msp" : "=r" (result) );
   return(result);
@@ -306,7 +306,7 @@
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
   return(result);
@@ -346,7 +346,7 @@
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
   return(result);
@@ -581,7 +581,7 @@
     // without main extensions, the non-secure PSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
   return result;
 #endif
@@ -603,7 +603,7 @@
   // without main extensions, the non-secure PSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
   return result;
 #endif
@@ -669,7 +669,7 @@
   // without main extensions, the non-secure MSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
   return result;
 #endif
@@ -691,7 +691,7 @@
   // without main extensions, the non-secure MSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
   return result;
 #endif
@@ -742,10 +742,6 @@
 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
 /**
   \brief   Get FPSCR
   \details Returns the current value of the Floating Point Status/Control register.
@@ -770,10 +766,6 @@
 #define __set_FPSCR(x)      ((void)(x))
 #endif
 
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
 
 /*@} end of CMSIS_Core_RegAccFunctions */