Diff: targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c

Revision:

175:af195413fb11

Parent:

173:e131a1973e81

Child:

187:0387e8f68319

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c	Wed Oct 11 12:45:49 2017 +0100
@@ -30,12 +30,7 @@
 
 #include "xdot_low_power.h"
 #include "stdio.h"
-
-#if defined(NDEBUG) && NDEBUG == 1
-#define xdot_lp_debug(...) do {} while(0)
-#else
-#define xdot_lp_debug(...) printf(__VA_ARGS__)
-#endif
+#include "mbed_debug.h"
 
 static uint32_t portA[6];
 static uint32_t portB[6];
@@ -236,7 +231,7 @@
     HSERCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
     HSERCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
     if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) {
-        xdot_lp_debug("OSC initialization failed - initiating soft reset\r\n");
+        debug("OSC initialization failed - initiating soft reset\r\n");
         NVIC_SystemReset();
     }
 
@@ -247,7 +242,7 @@
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        xdot_lp_debug("PLL initialization failed - initiating soft reset\r\n");
+        debug("PLL initialization failed - initiating soft reset\r\n");
         NVIC_SystemReset();
     }
 
@@ -260,7 +255,7 @@
         HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
         HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
         if ( ret != HAL_OK ) {
-            xdot_lp_debug("HSI initialization failed - ADC will not function properly\r\n");
+            debug("HSI initialization failed - ADC will not function properly\r\n");
         }
     }