Diff: targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c

Revision:

180:96ed750bd169

Parent:

156:95d6b41a828b

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_utils.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   UTILS LL module driver.
   ******************************************************************************
   * @attention
@@ -60,15 +58,15 @@
   */
 
 /* Defines used for PLL range */
-#define UTILS_PLL_OUTPUT_MIN        ((uint32_t)16000000U)        /*!< Frequency min for PLL output, in Hz  */
-#define UTILS_PLL_OUTPUT_MAX        ((uint32_t)48000000U)        /*!< Frequency max for PLL output, in Hz  */
+#define UTILS_PLL_OUTPUT_MIN        16000000U           /*!< Frequency min for PLL output, in Hz  */
+#define UTILS_PLL_OUTPUT_MAX        48000000U    /*!< Frequency max for PLL output, in Hz  */
 
 /* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN     ((uint32_t)4000000U)         /*!< Frequency min for HSE frequency, in Hz   */
-#define UTILS_HSE_FREQUENCY_MAX     ((uint32_t)32000000U)        /*!< Frequency max for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MIN      4000000U       /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     32000000U       /*!< Frequency max for HSE frequency, in Hz   */
 
 /* Defines used for FLASH latency according to SYSCLK Frequency */
-#define UTILS_LATENCY1_FREQ         ((uint32_t)24000000U)        /*!< SYSCLK frequency to set FLASH latency 1 */
+#define UTILS_LATENCY1_FREQ         24000000U        /*!< SYSCLK frequency to set FLASH latency 1 */
 /**
   * @}
   */
@@ -133,7 +131,9 @@
   */
 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+#if defined(FLASH_ACR_LATENCY)
 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+#endif /* FLASH_ACR_LATENCY */
 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
 static ErrorStatus UTILS_PLL_IsBusy(void);
 /**
@@ -268,7 +268,6 @@
     /* Force PREDIV value to 2 */
     UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
     /* Calculate the new PLL output frequency */
     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
 
@@ -426,7 +425,7 @@
 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
       LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
 #else
-      LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
+    LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
 
     /* Enable PLL and switch system clock to PLL */
@@ -460,6 +459,7 @@
   *          - SUCCESS: Latency has been modified
   *          - ERROR: Latency cannot be modified
   */
+#if defined(FLASH_ACR_LATENCY)
 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
 {
   ErrorStatus status = SUCCESS;
@@ -491,6 +491,7 @@
   }
   return status;
 }
+#endif /* FLASH_ACR_LATENCY */
 
 /**
   * @brief  Function to check that PLL can be modified
@@ -536,7 +537,6 @@
     status = ERROR;
   }
 
-
   return status;
 }
 
@@ -558,7 +558,7 @@
   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
 
   /* Calculate current SYSCLK frequency */
-  sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >>  RCC_POSITION_HPRE]);
+  sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
 
   /* Increasing the number of wait states because of higher CPU frequency */
   if (sysclk_frequency_current < SYSCLK_Frequency)