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mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.h
- Revision:
- 184:08ed48f1de7f
- Parent:
- 149:156823d33999
- Child:
- 186:707f6e361f3e
--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.h Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.h Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
******************************************************************************
* @file stm32l1xx_hal_adc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 01-July-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -201,36 +199,36 @@
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
+#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32L1 device: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32L1 device: End Of Sampling flag raised */
/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
+#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
+#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
@@ -267,11 +265,11 @@
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
-#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
-#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
/**
* @}
*/
@@ -279,7 +277,7 @@
/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
* @{
*/
-#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
+#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
/**
@@ -289,7 +287,7 @@
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
-#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */
@@ -300,7 +298,7 @@
/** @defgroup ADC_Data_align ADC Data_align
* @{
*/
-#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_RIGHT (0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
@@ -309,7 +307,7 @@
/** @defgroup ADC_Scan_mode ADC Scan mode
* @{
*/
-#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
+#define ADC_SCAN_DISABLE (0x00000000U)
#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
/**
* @}
@@ -318,7 +316,7 @@
/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
* @{
*/
-#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
@@ -345,7 +343,7 @@
#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START ((uint32_t)0x00000010)
+#define ADC_SOFTWARE_START (0x00000010U)
/**
* @}
*/
@@ -353,7 +351,7 @@
/** @defgroup ADC_EOCSelection ADC EOCSelection
* @{
*/
-#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
+#define ADC_EOC_SEQ_CONV (0x00000000U)
#define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
/**
* @}
@@ -366,7 +364,7 @@
/* feature limited to enable or disable settings: */
/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
-#define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000)
+#define ADC_AUTOWAIT_DISABLE (0x00000000U)
#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
@@ -382,7 +380,7 @@
/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
* @{
*/
-#define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000)
+#define ADC_AUTOPOWEROFF_DISABLE (0x00000000U)
#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */
#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
@@ -395,13 +393,13 @@
* @{
*/
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
+#define ADC_CHANNELS_BANK_A (0x00000000U)
#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
((BANK) == ADC_CHANNELS_BANK_B) )
#else
-#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
+#define ADC_CHANNELS_BANK_A (0x00000000U)
#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
@@ -414,7 +412,7 @@
*/
/* Note: Depending on devices, some channels may not be available on package */
/* pins. Refer to device datasheet for channels availability. */
-#define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */
+#define ADC_CHANNEL_0 (0x00000000U) /* Channel different in bank A and bank B */
#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
@@ -467,7 +465,7 @@
/** @defgroup ADC_sampling_times ADC sampling times
* @{
*/
-#define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /*!< Sampling time 4 ADC clock cycles */
+#define ADC_SAMPLETIME_4CYCLES (0x00000000U) /*!< Sampling time 4 ADC clock cycles */
#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */
#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */
#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
@@ -554,35 +552,35 @@
/** @defgroup ADC_regular_rank ADC rank into regular group
* @{
*/
-#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
-#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
-#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
-#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
-#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
-#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
-#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
-#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
-#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
-#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
-#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
-#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
-#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
-#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
-#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
-#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
-#define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011)
-#define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012)
-#define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013)
-#define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014)
-#define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015)
-#define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016)
-#define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017)
-#define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018)
-#define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019)
-#define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A)
-#define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B)
+#define ADC_REGULAR_RANK_1 (0x00000001U)
+#define ADC_REGULAR_RANK_2 (0x00000002U)
+#define ADC_REGULAR_RANK_3 (0x00000003U)
+#define ADC_REGULAR_RANK_4 (0x00000004U)
+#define ADC_REGULAR_RANK_5 (0x00000005U)
+#define ADC_REGULAR_RANK_6 (0x00000006U)
+#define ADC_REGULAR_RANK_7 (0x00000007U)
+#define ADC_REGULAR_RANK_8 (0x00000008U)
+#define ADC_REGULAR_RANK_9 (0x00000009U)
+#define ADC_REGULAR_RANK_10 (0x0000000AU)
+#define ADC_REGULAR_RANK_11 (0x0000000BU)
+#define ADC_REGULAR_RANK_12 (0x0000000CU)
+#define ADC_REGULAR_RANK_13 (0x0000000DU)
+#define ADC_REGULAR_RANK_14 (0x0000000EU)
+#define ADC_REGULAR_RANK_15 (0x0000000FU)
+#define ADC_REGULAR_RANK_16 (0x00000010U)
+#define ADC_REGULAR_RANK_17 (0x00000011U)
+#define ADC_REGULAR_RANK_18 (0x00000012U)
+#define ADC_REGULAR_RANK_19 (0x00000013U)
+#define ADC_REGULAR_RANK_20 (0x00000014U)
+#define ADC_REGULAR_RANK_21 (0x00000015U)
+#define ADC_REGULAR_RANK_22 (0x00000016U)
+#define ADC_REGULAR_RANK_23 (0x00000017U)
+#define ADC_REGULAR_RANK_24 (0x00000018U)
+#define ADC_REGULAR_RANK_25 (0x00000019U)
+#define ADC_REGULAR_RANK_26 (0x0000001AU)
+#define ADC_REGULAR_RANK_27 (0x0000001BU)
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C)
+#define ADC_REGULAR_RANK_28 (0x0000001CU)
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
/**
* @}
@@ -591,7 +589,7 @@
/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
* @{
*/
-#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000U)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
@@ -663,7 +661,7 @@
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000)
+#define ADC_EXTERNALTRIG_T9_CC2 (0x00000000U)
#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@@ -1200,19 +1198,19 @@
*
*/
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \
- ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) || \
- (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) || \
- (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) || \
- (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= ((uint32_t)0x003F))) )
+ ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) || \
+ (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) || \
+ (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= (0x00FFU))) || \
+ (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= (0x003FU))) )
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U)))
#else
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U)))
#endif
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
/**
* @}
