mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Child:
161:2cc1468da177
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /**************************************************************************//**
<> 153:fa9ff456f731 2 * @file efr32mg1p232f256gm48.h
<> 153:fa9ff456f731 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 153:fa9ff456f731 4 * for EFR32MG1P232F256GM48
<> 153:fa9ff456f731 5 * @version 5.0.0
<> 153:fa9ff456f731 6 ******************************************************************************
<> 153:fa9ff456f731 7 * @section License
<> 153:fa9ff456f731 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 153:fa9ff456f731 9 ******************************************************************************
<> 153:fa9ff456f731 10 *
<> 153:fa9ff456f731 11 * Permission is granted to anyone to use this software for any purpose,
<> 153:fa9ff456f731 12 * including commercial applications, and to alter it and redistribute it
<> 153:fa9ff456f731 13 * freely, subject to the following restrictions:
<> 153:fa9ff456f731 14 *
<> 153:fa9ff456f731 15 * 1. The origin of this software must not be misrepresented; you must not
<> 153:fa9ff456f731 16 * claim that you wrote the original software.@n
<> 153:fa9ff456f731 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 153:fa9ff456f731 18 * misrepresented as being the original software.@n
<> 153:fa9ff456f731 19 * 3. This notice may not be removed or altered from any source distribution.
<> 153:fa9ff456f731 20 *
<> 153:fa9ff456f731 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 153:fa9ff456f731 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 153:fa9ff456f731 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 153:fa9ff456f731 24 * kind, including, but not limited to, any implied warranties of
<> 153:fa9ff456f731 25 * merchantability or fitness for any particular purpose or warranties against
<> 153:fa9ff456f731 26 * infringement of any proprietary rights of a third party.
<> 153:fa9ff456f731 27 *
<> 153:fa9ff456f731 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 153:fa9ff456f731 29 * incidental, or special damages, or any other relief, or for any claim by
<> 153:fa9ff456f731 30 * any third party, arising from your use of this Software.
<> 153:fa9ff456f731 31 *
<> 153:fa9ff456f731 32 *****************************************************************************/
<> 153:fa9ff456f731 33
<> 153:fa9ff456f731 34 #ifndef EFR32MG1P232F256GM48_H
<> 153:fa9ff456f731 35 #define EFR32MG1P232F256GM48_H
<> 153:fa9ff456f731 36
<> 153:fa9ff456f731 37 #ifdef __cplusplus
<> 153:fa9ff456f731 38 extern "C" {
<> 153:fa9ff456f731 39 #endif
<> 153:fa9ff456f731 40
<> 153:fa9ff456f731 41 /**************************************************************************//**
<> 153:fa9ff456f731 42 * @addtogroup Parts
<> 153:fa9ff456f731 43 * @{
<> 153:fa9ff456f731 44 *****************************************************************************/
<> 153:fa9ff456f731 45
<> 153:fa9ff456f731 46 /**************************************************************************//**
<> 153:fa9ff456f731 47 * @defgroup EFR32MG1P232F256GM48 EFR32MG1P232F256GM48
<> 153:fa9ff456f731 48 * @{
<> 153:fa9ff456f731 49 *****************************************************************************/
<> 153:fa9ff456f731 50
<> 153:fa9ff456f731 51 /** Interrupt Number Definition */
<> 153:fa9ff456f731 52 typedef enum IRQn
<> 153:fa9ff456f731 53 {
<> 153:fa9ff456f731 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
<> 153:fa9ff456f731 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
<> 153:fa9ff456f731 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
<> 153:fa9ff456f731 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
<> 153:fa9ff456f731 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
<> 153:fa9ff456f731 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
<> 153:fa9ff456f731 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
<> 153:fa9ff456f731 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
<> 153:fa9ff456f731 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
<> 153:fa9ff456f731 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
<> 153:fa9ff456f731 64
<> 153:fa9ff456f731 65 /****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
<> 153:fa9ff456f731 66
<> 153:fa9ff456f731 67 EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
<> 153:fa9ff456f731 68 WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
<> 153:fa9ff456f731 69 LDMA_IRQn = 8, /*!< 8 EFR32 LDMA Interrupt */
<> 153:fa9ff456f731 70 GPIO_EVEN_IRQn = 9, /*!< 9 EFR32 GPIO_EVEN Interrupt */
<> 153:fa9ff456f731 71 TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */
<> 153:fa9ff456f731 72 USART0_RX_IRQn = 11, /*!< 11 EFR32 USART0_RX Interrupt */
<> 153:fa9ff456f731 73 USART0_TX_IRQn = 12, /*!< 12 EFR32 USART0_TX Interrupt */
<> 153:fa9ff456f731 74 ACMP0_IRQn = 13, /*!< 13 EFR32 ACMP0 Interrupt */
<> 153:fa9ff456f731 75 ADC0_IRQn = 14, /*!< 14 EFR32 ADC0 Interrupt */
<> 153:fa9ff456f731 76 IDAC0_IRQn = 15, /*!< 15 EFR32 IDAC0 Interrupt */
<> 153:fa9ff456f731 77 I2C0_IRQn = 16, /*!< 16 EFR32 I2C0 Interrupt */
<> 153:fa9ff456f731 78 GPIO_ODD_IRQn = 17, /*!< 17 EFR32 GPIO_ODD Interrupt */
<> 153:fa9ff456f731 79 TIMER1_IRQn = 18, /*!< 18 EFR32 TIMER1 Interrupt */
<> 153:fa9ff456f731 80 USART1_RX_IRQn = 19, /*!< 19 EFR32 USART1_RX Interrupt */
<> 153:fa9ff456f731 81 USART1_TX_IRQn = 20, /*!< 20 EFR32 USART1_TX Interrupt */
<> 153:fa9ff456f731 82 LEUART0_IRQn = 21, /*!< 21 EFR32 LEUART0 Interrupt */
<> 153:fa9ff456f731 83 PCNT0_IRQn = 22, /*!< 22 EFR32 PCNT0 Interrupt */
<> 153:fa9ff456f731 84 CMU_IRQn = 23, /*!< 23 EFR32 CMU Interrupt */
<> 153:fa9ff456f731 85 MSC_IRQn = 24, /*!< 24 EFR32 MSC Interrupt */
<> 153:fa9ff456f731 86 CRYPTO_IRQn = 25, /*!< 25 EFR32 CRYPTO Interrupt */
<> 153:fa9ff456f731 87 LETIMER0_IRQn = 26, /*!< 26 EFR32 LETIMER0 Interrupt */
<> 153:fa9ff456f731 88 RTCC_IRQn = 29, /*!< 29 EFR32 RTCC Interrupt */
<> 153:fa9ff456f731 89 CRYOTIMER_IRQn = 31, /*!< 31 EFR32 CRYOTIMER Interrupt */
<> 153:fa9ff456f731 90 FPUEH_IRQn = 33, /*!< 33 EFR32 FPUEH Interrupt */
<> 153:fa9ff456f731 91 } IRQn_Type;
<> 153:fa9ff456f731 92
<> 153:fa9ff456f731 93 /**************************************************************************//**
<> 153:fa9ff456f731 94 * @defgroup EFR32MG1P232F256GM48_Core EFR32MG1P232F256GM48 Core
<> 153:fa9ff456f731 95 * @{
<> 153:fa9ff456f731 96 * @brief Processor and Core Peripheral Section
<> 153:fa9ff456f731 97 *****************************************************************************/
<> 153:fa9ff456f731 98 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 153:fa9ff456f731 99 #define __FPU_PRESENT 1 /**< Presence of FPU */
<> 153:fa9ff456f731 100 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 153:fa9ff456f731 101 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 153:fa9ff456f731 102 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 153:fa9ff456f731 103
<> 153:fa9ff456f731 104 /** @} End of group EFR32MG1P232F256GM48_Core */
<> 153:fa9ff456f731 105
<> 153:fa9ff456f731 106 /**************************************************************************//**
<> 153:fa9ff456f731 107 * @defgroup EFR32MG1P232F256GM48_Part EFR32MG1P232F256GM48 Part
<> 153:fa9ff456f731 108 * @{
<> 153:fa9ff456f731 109 ******************************************************************************/
<> 153:fa9ff456f731 110
<> 153:fa9ff456f731 111 /** Part family */
<> 153:fa9ff456f731 112 #define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
<> 153:fa9ff456f731 113 #define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
<> 153:fa9ff456f731 114 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
<> 153:fa9ff456f731 115 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
<> 153:fa9ff456f731 116 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
<> 153:fa9ff456f731 117 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
<> 153:fa9ff456f731 118 #define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */
<> 153:fa9ff456f731 119 #define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */
<> 153:fa9ff456f731 120 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */
<> 153:fa9ff456f731 121 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */
<> 153:fa9ff456f731 122
<> 153:fa9ff456f731 123 /* If part number is not defined as compiler option, define it */
<> 153:fa9ff456f731 124 #if !defined(EFR32MG1P232F256GM48)
<> 153:fa9ff456f731 125 #define EFR32MG1P232F256GM48 1 /**< MIGHTY Gecko Part */
<> 153:fa9ff456f731 126 #endif
<> 153:fa9ff456f731 127
<> 153:fa9ff456f731 128 /** Configure part number */
<> 153:fa9ff456f731 129 #define PART_NUMBER "EFR32MG1P232F256GM48" /**< Part Number */
<> 153:fa9ff456f731 130
<> 153:fa9ff456f731 131 /** Memory Base addresses and limits */
<> 153:fa9ff456f731 132 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
<> 153:fa9ff456f731 133 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 153:fa9ff456f731 134 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
<> 153:fa9ff456f731 135 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 153:fa9ff456f731 136 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 153:fa9ff456f731 137 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
<> 153:fa9ff456f731 138 #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
<> 153:fa9ff456f731 139 #define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */
<> 153:fa9ff456f731 140 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
<> 153:fa9ff456f731 141 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
<> 153:fa9ff456f731 142 #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
<> 153:fa9ff456f731 143 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */
<> 153:fa9ff456f731 144 #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
<> 153:fa9ff456f731 145 #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
<> 153:fa9ff456f731 146 #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
<> 153:fa9ff456f731 147 #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */
<> 153:fa9ff456f731 148 #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
<> 153:fa9ff456f731 149 #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
<> 153:fa9ff456f731 150 #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
<> 153:fa9ff456f731 151 #define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */
<> 153:fa9ff456f731 152 #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
<> 153:fa9ff456f731 153 #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
<> 153:fa9ff456f731 154 #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
<> 153:fa9ff456f731 155 #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */
<> 153:fa9ff456f731 156 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
<> 153:fa9ff456f731 157 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
<> 153:fa9ff456f731 158 #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
<> 153:fa9ff456f731 159 #define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */
<> 153:fa9ff456f731 160 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 153:fa9ff456f731 161 #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
<> 153:fa9ff456f731 162 #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
<> 153:fa9ff456f731 163 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 153:fa9ff456f731 164 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 153:fa9ff456f731 165 #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
<> 153:fa9ff456f731 166 #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
<> 153:fa9ff456f731 167 #define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
<> 153:fa9ff456f731 168
<> 153:fa9ff456f731 169 /** Bit banding area */
<> 153:fa9ff456f731 170 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 153:fa9ff456f731 171 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 153:fa9ff456f731 172
<> 153:fa9ff456f731 173 /** Flash and SRAM limits for EFR32MG1P232F256GM48 */
<> 153:fa9ff456f731 174 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 153:fa9ff456f731 175 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
<> 153:fa9ff456f731 176 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
<> 153:fa9ff456f731 177 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 153:fa9ff456f731 178 #define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
<> 153:fa9ff456f731 179 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
<> 153:fa9ff456f731 180 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 153:fa9ff456f731 181 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
<> 153:fa9ff456f731 182 #define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
<> 153:fa9ff456f731 183
<> 153:fa9ff456f731 184 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 153:fa9ff456f731 185 #define AFCHAN_MAX 72
<> 153:fa9ff456f731 186 #define AFCHANLOC_MAX 32
<> 153:fa9ff456f731 187 /** Analog AF channels */
<> 153:fa9ff456f731 188 #define AFACHAN_MAX 61
<> 153:fa9ff456f731 189
<> 153:fa9ff456f731 190 /* Part number capabilities */
<> 153:fa9ff456f731 191
<> 153:fa9ff456f731 192 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 153:fa9ff456f731 193 #define TIMER_COUNT 2 /**< 2 TIMERs available */
<> 153:fa9ff456f731 194 #define USART_PRESENT /**< USART is available in this part */
<> 153:fa9ff456f731 195 #define USART_COUNT 2 /**< 2 USARTs available */
<> 153:fa9ff456f731 196 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 153:fa9ff456f731 197 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
<> 153:fa9ff456f731 198 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 153:fa9ff456f731 199 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 153:fa9ff456f731 200 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 153:fa9ff456f731 201 #define PCNT_COUNT 1 /**< 1 PCNTs available */
<> 153:fa9ff456f731 202 #define I2C_PRESENT /**< I2C is available in this part */
<> 153:fa9ff456f731 203 #define I2C_COUNT 1 /**< 1 I2Cs available */
<> 153:fa9ff456f731 204 #define ADC_PRESENT /**< ADC is available in this part */
<> 153:fa9ff456f731 205 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 153:fa9ff456f731 206 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 153:fa9ff456f731 207 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 153:fa9ff456f731 208 #define IDAC_PRESENT /**< IDAC is available in this part */
<> 153:fa9ff456f731 209 #define IDAC_COUNT 1 /**< 1 IDACs available */
<> 153:fa9ff456f731 210 #define WDOG_PRESENT /**< WDOG is available in this part */
<> 153:fa9ff456f731 211 #define WDOG_COUNT 1 /**< 1 WDOGs available */
<> 153:fa9ff456f731 212 #define MSC_PRESENT
<> 153:fa9ff456f731 213 #define MSC_COUNT 1
<> 153:fa9ff456f731 214 #define EMU_PRESENT
<> 153:fa9ff456f731 215 #define EMU_COUNT 1
<> 153:fa9ff456f731 216 #define RMU_PRESENT
<> 153:fa9ff456f731 217 #define RMU_COUNT 1
<> 153:fa9ff456f731 218 #define CMU_PRESENT
<> 153:fa9ff456f731 219 #define CMU_COUNT 1
<> 153:fa9ff456f731 220 #define CRYPTO_PRESENT
<> 153:fa9ff456f731 221 #define CRYPTO_COUNT 1
<> 153:fa9ff456f731 222 #define GPIO_PRESENT
<> 153:fa9ff456f731 223 #define GPIO_COUNT 1
<> 153:fa9ff456f731 224 #define PRS_PRESENT
<> 153:fa9ff456f731 225 #define PRS_COUNT 1
<> 153:fa9ff456f731 226 #define LDMA_PRESENT
<> 153:fa9ff456f731 227 #define LDMA_COUNT 1
<> 153:fa9ff456f731 228 #define FPUEH_PRESENT
<> 153:fa9ff456f731 229 #define FPUEH_COUNT 1
<> 153:fa9ff456f731 230 #define GPCRC_PRESENT
<> 153:fa9ff456f731 231 #define GPCRC_COUNT 1
<> 153:fa9ff456f731 232 #define CRYOTIMER_PRESENT
<> 153:fa9ff456f731 233 #define CRYOTIMER_COUNT 1
<> 153:fa9ff456f731 234 #define RTCC_PRESENT
<> 153:fa9ff456f731 235 #define RTCC_COUNT 1
<> 153:fa9ff456f731 236 #define BOOTLOADER_PRESENT
<> 153:fa9ff456f731 237 #define BOOTLOADER_COUNT 1
<> 153:fa9ff456f731 238
<> 153:fa9ff456f731 239 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 153:fa9ff456f731 240 #include "system_efr32mg1p.h" /* System Header File */
<> 153:fa9ff456f731 241
<> 153:fa9ff456f731 242 /** @} End of group EFR32MG1P232F256GM48_Part */
<> 153:fa9ff456f731 243
<> 153:fa9ff456f731 244 /**************************************************************************//**
<> 153:fa9ff456f731 245 * @defgroup EFR32MG1P232F256GM48_Peripheral_TypeDefs EFR32MG1P232F256GM48 Peripheral TypeDefs
<> 153:fa9ff456f731 246 * @{
<> 153:fa9ff456f731 247 * @brief Device Specific Peripheral Register Structures
<> 153:fa9ff456f731 248 *****************************************************************************/
<> 153:fa9ff456f731 249
<> 153:fa9ff456f731 250 #include "efr32mg1p_msc.h"
<> 153:fa9ff456f731 251 #include "efr32mg1p_emu.h"
<> 153:fa9ff456f731 252 #include "efr32mg1p_rmu.h"
<> 153:fa9ff456f731 253 #include "efr32mg1p_cmu.h"
<> 153:fa9ff456f731 254 #include "efr32mg1p_crypto.h"
<> 153:fa9ff456f731 255 #include "efr32mg1p_gpio_p.h"
<> 153:fa9ff456f731 256 #include "efr32mg1p_gpio.h"
<> 153:fa9ff456f731 257 #include "efr32mg1p_prs_ch.h"
<> 153:fa9ff456f731 258 #include "efr32mg1p_prs.h"
<> 153:fa9ff456f731 259 #include "efr32mg1p_ldma_ch.h"
<> 153:fa9ff456f731 260 #include "efr32mg1p_ldma.h"
<> 153:fa9ff456f731 261 #include "efr32mg1p_fpueh.h"
<> 153:fa9ff456f731 262 #include "efr32mg1p_gpcrc.h"
<> 153:fa9ff456f731 263 #include "efr32mg1p_timer_cc.h"
<> 153:fa9ff456f731 264 #include "efr32mg1p_timer.h"
<> 153:fa9ff456f731 265 #include "efr32mg1p_usart.h"
<> 153:fa9ff456f731 266 #include "efr32mg1p_leuart.h"
<> 153:fa9ff456f731 267 #include "efr32mg1p_letimer.h"
<> 153:fa9ff456f731 268 #include "efr32mg1p_cryotimer.h"
<> 153:fa9ff456f731 269 #include "efr32mg1p_pcnt.h"
<> 153:fa9ff456f731 270 #include "efr32mg1p_i2c.h"
<> 153:fa9ff456f731 271 #include "efr32mg1p_adc.h"
<> 153:fa9ff456f731 272 #include "efr32mg1p_acmp.h"
<> 153:fa9ff456f731 273 #include "efr32mg1p_idac.h"
<> 153:fa9ff456f731 274 #include "efr32mg1p_rtcc_cc.h"
<> 153:fa9ff456f731 275 #include "efr32mg1p_rtcc_ret.h"
<> 153:fa9ff456f731 276 #include "efr32mg1p_rtcc.h"
<> 153:fa9ff456f731 277 #include "efr32mg1p_wdog_pch.h"
<> 153:fa9ff456f731 278 #include "efr32mg1p_wdog.h"
<> 153:fa9ff456f731 279 #include "efr32mg1p_dma_descriptor.h"
<> 153:fa9ff456f731 280 #include "efr32mg1p_devinfo.h"
<> 153:fa9ff456f731 281 #include "efr32mg1p_romtable.h"
<> 153:fa9ff456f731 282
<> 153:fa9ff456f731 283 /** @} End of group EFR32MG1P232F256GM48_Peripheral_TypeDefs */
<> 153:fa9ff456f731 284
<> 153:fa9ff456f731 285 /**************************************************************************//**
<> 153:fa9ff456f731 286 * @defgroup EFR32MG1P232F256GM48_Peripheral_Base EFR32MG1P232F256GM48 Peripheral Memory Map
<> 153:fa9ff456f731 287 * @{
<> 153:fa9ff456f731 288 *****************************************************************************/
<> 153:fa9ff456f731 289
<> 153:fa9ff456f731 290 #define MSC_BASE (0x400E0000UL) /**< MSC base address */
<> 153:fa9ff456f731 291 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
<> 153:fa9ff456f731 292 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
<> 153:fa9ff456f731 293 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
<> 153:fa9ff456f731 294 #define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
<> 153:fa9ff456f731 295 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
<> 153:fa9ff456f731 296 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
<> 153:fa9ff456f731 297 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
<> 153:fa9ff456f731 298 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
<> 153:fa9ff456f731 299 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
<> 153:fa9ff456f731 300 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
<> 153:fa9ff456f731 301 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
<> 153:fa9ff456f731 302 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
<> 153:fa9ff456f731 303 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
<> 153:fa9ff456f731 304 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
<> 153:fa9ff456f731 305 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
<> 153:fa9ff456f731 306 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
<> 153:fa9ff456f731 307 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
<> 153:fa9ff456f731 308 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
<> 153:fa9ff456f731 309 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 153:fa9ff456f731 310 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
<> 153:fa9ff456f731 311 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
<> 153:fa9ff456f731 312 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
<> 153:fa9ff456f731 313 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */
<> 153:fa9ff456f731 314 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
<> 153:fa9ff456f731 315 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 153:fa9ff456f731 316 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 153:fa9ff456f731 317 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 153:fa9ff456f731 318 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 153:fa9ff456f731 319
<> 153:fa9ff456f731 320 /** @} End of group EFR32MG1P232F256GM48_Peripheral_Base */
<> 153:fa9ff456f731 321
<> 153:fa9ff456f731 322 /**************************************************************************//**
<> 153:fa9ff456f731 323 * @defgroup EFR32MG1P232F256GM48_Peripheral_Declaration EFR32MG1P232F256GM48 Peripheral Declarations
<> 153:fa9ff456f731 324 * @{
<> 153:fa9ff456f731 325 *****************************************************************************/
<> 153:fa9ff456f731 326
<> 153:fa9ff456f731 327 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 153:fa9ff456f731 328 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 153:fa9ff456f731 329 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 153:fa9ff456f731 330 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 153:fa9ff456f731 331 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
<> 153:fa9ff456f731 332 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 153:fa9ff456f731 333 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 153:fa9ff456f731 334 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
<> 153:fa9ff456f731 335 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
<> 153:fa9ff456f731 336 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
<> 153:fa9ff456f731 337 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 153:fa9ff456f731 338 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 153:fa9ff456f731 339 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 153:fa9ff456f731 340 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 153:fa9ff456f731 341 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 153:fa9ff456f731 342 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 153:fa9ff456f731 343 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
<> 153:fa9ff456f731 344 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 153:fa9ff456f731 345 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 153:fa9ff456f731 346 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 153:fa9ff456f731 347 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 153:fa9ff456f731 348 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 153:fa9ff456f731 349 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
<> 153:fa9ff456f731 350 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
<> 153:fa9ff456f731 351 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
<> 153:fa9ff456f731 352 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 153:fa9ff456f731 353 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 153:fa9ff456f731 354
<> 153:fa9ff456f731 355 /** @} End of group EFR32MG1P232F256GM48_Peripheral_Declaration */
<> 153:fa9ff456f731 356
<> 153:fa9ff456f731 357 /**************************************************************************//**
<> 153:fa9ff456f731 358 * @defgroup EFR32MG1P232F256GM48_Peripheral_Offsets EFR32MG1P232F256GM48 Peripheral Offsets
<> 153:fa9ff456f731 359 * @{
<> 153:fa9ff456f731 360 *****************************************************************************/
<> 153:fa9ff456f731 361
<> 153:fa9ff456f731 362 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
<> 153:fa9ff456f731 363 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
<> 153:fa9ff456f731 364 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
<> 153:fa9ff456f731 365 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
<> 153:fa9ff456f731 366 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
<> 153:fa9ff456f731 367 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
<> 153:fa9ff456f731 368 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
<> 153:fa9ff456f731 369 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
<> 153:fa9ff456f731 370 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
<> 153:fa9ff456f731 371 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
<> 153:fa9ff456f731 372
<> 153:fa9ff456f731 373 /** @} End of group EFR32MG1P232F256GM48_Peripheral_Offsets */
<> 153:fa9ff456f731 374
<> 153:fa9ff456f731 375
<> 153:fa9ff456f731 376 /**************************************************************************//**
<> 153:fa9ff456f731 377 * @defgroup EFR32MG1P232F256GM48_BitFields EFR32MG1P232F256GM48 Bit Fields
<> 153:fa9ff456f731 378 * @{
<> 153:fa9ff456f731 379 *****************************************************************************/
<> 153:fa9ff456f731 380
<> 153:fa9ff456f731 381 #include "efr32mg1p_prs_signals.h"
<> 153:fa9ff456f731 382 #include "efr32mg1p_dmareq.h"
<> 153:fa9ff456f731 383
<> 153:fa9ff456f731 384 /**************************************************************************//**
<> 153:fa9ff456f731 385 * @defgroup EFR32MG1P232F256GM48_UNLOCK EFR32MG1P232F256GM48 Unlock Codes
<> 153:fa9ff456f731 386 * @{
<> 153:fa9ff456f731 387 *****************************************************************************/
<> 153:fa9ff456f731 388 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 153:fa9ff456f731 389 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 153:fa9ff456f731 390 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
<> 153:fa9ff456f731 391 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 153:fa9ff456f731 392 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 153:fa9ff456f731 393 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 153:fa9ff456f731 394 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
<> 153:fa9ff456f731 395
<> 153:fa9ff456f731 396 /** @} End of group EFR32MG1P232F256GM48_UNLOCK */
<> 153:fa9ff456f731 397
<> 153:fa9ff456f731 398 /** @} End of group EFR32MG1P232F256GM48_BitFields */
<> 153:fa9ff456f731 399
<> 153:fa9ff456f731 400 /**************************************************************************//**
<> 153:fa9ff456f731 401 * @defgroup EFR32MG1P232F256GM48_Alternate_Function EFR32MG1P232F256GM48 Alternate Function
<> 153:fa9ff456f731 402 * @{
<> 153:fa9ff456f731 403 *****************************************************************************/
<> 153:fa9ff456f731 404
<> 153:fa9ff456f731 405 #include "efr32mg1p_af_ports.h"
<> 153:fa9ff456f731 406 #include "efr32mg1p_af_pins.h"
<> 153:fa9ff456f731 407
<> 153:fa9ff456f731 408 /** @} End of group EFR32MG1P232F256GM48_Alternate_Function */
<> 153:fa9ff456f731 409
<> 153:fa9ff456f731 410 /**************************************************************************//**
<> 153:fa9ff456f731 411 * @brief Set the value of a bit field within a register.
<> 153:fa9ff456f731 412 *
<> 153:fa9ff456f731 413 * @param REG
<> 153:fa9ff456f731 414 * The register to update
<> 153:fa9ff456f731 415 * @param MASK
<> 153:fa9ff456f731 416 * The mask for the bit field to update
<> 153:fa9ff456f731 417 * @param VALUE
<> 153:fa9ff456f731 418 * The value to write to the bit field
<> 153:fa9ff456f731 419 * @param OFFSET
<> 153:fa9ff456f731 420 * The number of bits that the field is offset within the register.
<> 153:fa9ff456f731 421 * 0 (zero) means LSB.
<> 153:fa9ff456f731 422 *****************************************************************************/
<> 153:fa9ff456f731 423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 153:fa9ff456f731 424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 153:fa9ff456f731 425
<> 153:fa9ff456f731 426 /** @} End of group EFR32MG1P232F256GM48 */
<> 153:fa9ff456f731 427
<> 153:fa9ff456f731 428 /** @} End of group Parts */
<> 153:fa9ff456f731 429
<> 153:fa9ff456f731 430 #ifdef __cplusplus
<> 153:fa9ff456f731 431 }
<> 153:fa9ff456f731 432 #endif
<> 153:fa9ff456f731 433 #endif /* EFR32MG1P232F256GM48_H */