mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
151:5eaa88a5bcc7
Child:
186:707f6e361f3e
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_i2c.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 153:fa9ff456f731 5 * @version $VERSION$
<> 153:fa9ff456f731 6 * @date $DATE$
<> 144:ef7eb2e8f9f7 7 * @brief Header file of I2C HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 153:fa9ff456f731 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L0xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L0xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 153:fa9ff456f731 53 /** @addtogroup I2C
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 153:fa9ff456f731 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup I2C_Exported_Types I2C Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
<> 144:ef7eb2e8f9f7 63 * @brief I2C Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
<> 144:ef7eb2e8f9f7 69 This parameter calculated by referring to I2C initialization
<> 144:ef7eb2e8f9f7 70 section in Reference manual */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 144:ef7eb2e8f9f7 73 This parameter can be a 7-bit or 10-bit address. */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
<> 153:fa9ff456f731 76 This parameter can be a value of @ref I2C_ADDRESSING_MODE */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 153:fa9ff456f731 79 This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 82 This parameter can be a 7-bit address. */
<> 144:ef7eb2e8f9f7 83
<> 153:fa9ff456f731 84 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
<> 153:fa9ff456f731 85 This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 153:fa9ff456f731 88 This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 153:fa9ff456f731 91 This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 }I2C_InitTypeDef;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @}
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /** @defgroup HAL_state_structure_definition HAL state structure definition
<> 153:fa9ff456f731 100 * @brief HAL State structure definition
<> 153:fa9ff456f731 101 * @note HAL I2C State value coding follow below described bitmap :\n
<> 153:fa9ff456f731 102 * b7-b6 Error information\n
<> 153:fa9ff456f731 103 * 00 : No Error\n
<> 153:fa9ff456f731 104 * 01 : Abort (Abort user request on going)\n
<> 153:fa9ff456f731 105 * 10 : Timeout\n
<> 153:fa9ff456f731 106 * 11 : Error\n
<> 153:fa9ff456f731 107 * b5 IP initilisation status\n
<> 153:fa9ff456f731 108 * 0 : Reset (IP not initialized)\n
<> 153:fa9ff456f731 109 * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
<> 153:fa9ff456f731 110 * b4 (not used)\n
<> 153:fa9ff456f731 111 * x : Should be set to 0\n
<> 153:fa9ff456f731 112 * b3\n
<> 153:fa9ff456f731 113 * 0 : Ready or Busy (No Listen mode ongoing)\n
<> 153:fa9ff456f731 114 * 1 : Listen (IP in Address Listen Mode)\n
<> 153:fa9ff456f731 115 * b2 Intrinsic process state\n
<> 153:fa9ff456f731 116 * 0 : Ready\n
<> 153:fa9ff456f731 117 * 1 : Busy (IP busy with some configuration or internal operations)\n
<> 153:fa9ff456f731 118 * b1 Rx state\n
<> 153:fa9ff456f731 119 * 0 : Ready (no Rx operation ongoing)\n
<> 153:fa9ff456f731 120 * 1 : Busy (Rx operation ongoing)\n
<> 153:fa9ff456f731 121 * b0 Tx state\n
<> 153:fa9ff456f731 122 * 0 : Ready (no Tx operation ongoing)\n
<> 153:fa9ff456f731 123 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 typedef enum
<> 144:ef7eb2e8f9f7 127 {
<> 153:fa9ff456f731 128 HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
<> 153:fa9ff456f731 129 HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
<> 153:fa9ff456f731 130 HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
<> 153:fa9ff456f731 131 HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
<> 153:fa9ff456f731 132 HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 153:fa9ff456f731 133 HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
<> 153:fa9ff456f731 134 HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
<> 153:fa9ff456f731 135 process is ongoing */
<> 153:fa9ff456f731 136 HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
<> 153:fa9ff456f731 137 process is ongoing */
<> 153:fa9ff456f731 138 HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
<> 153:fa9ff456f731 139 HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
<> 153:fa9ff456f731 140 HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
<> 153:fa9ff456f731 141
<> 144:ef7eb2e8f9f7 142 }HAL_I2C_StateTypeDef;
<> 144:ef7eb2e8f9f7 143
<> 153:fa9ff456f731 144 /**
<> 153:fa9ff456f731 145 * @}
<> 153:fa9ff456f731 146 */
<> 153:fa9ff456f731 147
<> 153:fa9ff456f731 148 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
<> 153:fa9ff456f731 149 * @brief HAL Mode structure definition
<> 153:fa9ff456f731 150 * @note HAL I2C Mode value coding follow below described bitmap :\n
<> 153:fa9ff456f731 151 * b7 (not used)\n
<> 153:fa9ff456f731 152 * x : Should be set to 0\n
<> 153:fa9ff456f731 153 * b6\n
<> 153:fa9ff456f731 154 * 0 : None\n
<> 153:fa9ff456f731 155 * 1 : Memory (HAL I2C communication is in Memory Mode)\n
<> 153:fa9ff456f731 156 * b5\n
<> 153:fa9ff456f731 157 * 0 : None\n
<> 153:fa9ff456f731 158 * 1 : Slave (HAL I2C communication is in Slave Mode)\n
<> 153:fa9ff456f731 159 * b4\n
<> 153:fa9ff456f731 160 * 0 : None\n
<> 153:fa9ff456f731 161 * 1 : Master (HAL I2C communication is in Master Mode)\n
<> 153:fa9ff456f731 162 * b3-b2-b1-b0 (not used)\n
<> 153:fa9ff456f731 163 * xxxx : Should be set to 0000
<> 153:fa9ff456f731 164 * @{
<> 153:fa9ff456f731 165 */
<> 153:fa9ff456f731 166 typedef enum
<> 153:fa9ff456f731 167 {
<> 153:fa9ff456f731 168 HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
<> 153:fa9ff456f731 169 HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
<> 153:fa9ff456f731 170 HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
<> 153:fa9ff456f731 171 HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
<> 153:fa9ff456f731 172
<> 153:fa9ff456f731 173 }HAL_I2C_ModeTypeDef;
<> 153:fa9ff456f731 174
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 153:fa9ff456f731 179 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
<> 153:fa9ff456f731 180 * @brief I2C Error Code definition
<> 144:ef7eb2e8f9f7 181 * @{
<> 153:fa9ff456f731 182 */
<> 153:fa9ff456f731 183 #define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
<> 153:fa9ff456f731 184 #define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
<> 153:fa9ff456f731 185 #define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
<> 153:fa9ff456f731 186 #define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
<> 153:fa9ff456f731 187 #define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
<> 153:fa9ff456f731 188 #define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 153:fa9ff456f731 189 #define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
<> 153:fa9ff456f731 190 #define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
<> 153:fa9ff456f731 191 /**
<> 144:ef7eb2e8f9f7 192 * @}
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194
<> 153:fa9ff456f731 195 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
<> 153:fa9ff456f731 196 * @brief I2C handle Structure definition
<> 144:ef7eb2e8f9f7 197 * @{
<> 144:ef7eb2e8f9f7 198 */
<> 153:fa9ff456f731 199 typedef struct __I2C_HandleTypeDef
<> 144:ef7eb2e8f9f7 200 {
<> 153:fa9ff456f731 201 I2C_TypeDef *Instance; /*!< I2C registers base address */
<> 153:fa9ff456f731 202
<> 153:fa9ff456f731 203 I2C_InitTypeDef Init; /*!< I2C communication parameters */
<> 153:fa9ff456f731 204
<> 153:fa9ff456f731 205 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
<> 153:fa9ff456f731 206
<> 153:fa9ff456f731 207 uint16_t XferSize; /*!< I2C transfer size */
<> 153:fa9ff456f731 208
<> 153:fa9ff456f731 209 __IO uint16_t XferCount; /*!< I2C transfer counter */
<> 153:fa9ff456f731 210
<> 153:fa9ff456f731 211 __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
<> 153:fa9ff456f731 212 be a value of @ref I2C_XFEROPTIONS */
<> 153:fa9ff456f731 213
<> 153:fa9ff456f731 214 __IO uint32_t PreviousState; /*!< I2C communication Previous state */
<> 144:ef7eb2e8f9f7 215
<> 153:fa9ff456f731 216 HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
<> 153:fa9ff456f731 217
<> 153:fa9ff456f731 218 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
<> 153:fa9ff456f731 219
<> 153:fa9ff456f731 220 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
<> 153:fa9ff456f731 221
<> 153:fa9ff456f731 222 HAL_LockTypeDef Lock; /*!< I2C locking object */
<> 144:ef7eb2e8f9f7 223
<> 153:fa9ff456f731 224 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
<> 153:fa9ff456f731 225
<> 153:fa9ff456f731 226 __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
<> 153:fa9ff456f731 227
<> 153:fa9ff456f731 228 __IO uint32_t ErrorCode; /*!< I2C Error code */
<> 153:fa9ff456f731 229
<> 153:fa9ff456f731 230 __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
<> 144:ef7eb2e8f9f7 231 }I2C_HandleTypeDef;
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @}
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 153:fa9ff456f731 238 */
<> 144:ef7eb2e8f9f7 239 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @defgroup I2C_Exported_Constants I2C Exported Constants
<> 144:ef7eb2e8f9f7 242 * @{
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 153:fa9ff456f731 245 /** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
<> 144:ef7eb2e8f9f7 246 * @{
<> 144:ef7eb2e8f9f7 247 */
<> 153:fa9ff456f731 248 #define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
<> 153:fa9ff456f731 249 #define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
<> 153:fa9ff456f731 250 #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
<> 153:fa9ff456f731 251 #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
<> 153:fa9ff456f731 252 #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 153:fa9ff456f731 257 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 153:fa9ff456f731 260 #define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
<> 153:fa9ff456f731 261 #define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @}
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 153:fa9ff456f731 266 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
<> 153:fa9ff456f731 267 * @{
<> 153:fa9ff456f731 268 */
<> 153:fa9ff456f731 269 #define I2C_DUALADDRESS_DISABLE (0x00000000U)
<> 153:fa9ff456f731 270 #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
<> 153:fa9ff456f731 271 /**
<> 153:fa9ff456f731 272 * @}
<> 153:fa9ff456f731 273 */
<> 153:fa9ff456f731 274
<> 153:fa9ff456f731 275 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
<> 144:ef7eb2e8f9f7 276 * @{
<> 144:ef7eb2e8f9f7 277 */
<> 151:5eaa88a5bcc7 278 #define I2C_OA2_NOMASK ((uint8_t)0x00U)
<> 151:5eaa88a5bcc7 279 #define I2C_OA2_MASK01 ((uint8_t)0x01U)
<> 151:5eaa88a5bcc7 280 #define I2C_OA2_MASK02 ((uint8_t)0x02U)
<> 151:5eaa88a5bcc7 281 #define I2C_OA2_MASK03 ((uint8_t)0x03U)
<> 151:5eaa88a5bcc7 282 #define I2C_OA2_MASK04 ((uint8_t)0x04U)
<> 151:5eaa88a5bcc7 283 #define I2C_OA2_MASK05 ((uint8_t)0x05U)
<> 151:5eaa88a5bcc7 284 #define I2C_OA2_MASK06 ((uint8_t)0x06U)
<> 151:5eaa88a5bcc7 285 #define I2C_OA2_MASK07 ((uint8_t)0x07U)
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 153:fa9ff456f731 290 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 153:fa9ff456f731 293 #define I2C_GENERALCALL_DISABLE (0x00000000U)
<> 153:fa9ff456f731 294 #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @}
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298
<> 153:fa9ff456f731 299 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
<> 144:ef7eb2e8f9f7 300 * @{
<> 144:ef7eb2e8f9f7 301 */
<> 153:fa9ff456f731 302 #define I2C_NOSTRETCH_DISABLE (0x00000000U)
<> 153:fa9ff456f731 303 #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @}
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 153:fa9ff456f731 308 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
<> 144:ef7eb2e8f9f7 309 * @{
<> 144:ef7eb2e8f9f7 310 */
<> 153:fa9ff456f731 311 #define I2C_MEMADD_SIZE_8BIT (0x00000001U)
<> 153:fa9ff456f731 312 #define I2C_MEMADD_SIZE_16BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 153:fa9ff456f731 315 */
<> 144:ef7eb2e8f9f7 316
<> 153:fa9ff456f731 317 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
<> 153:fa9ff456f731 318 * @{
<> 153:fa9ff456f731 319 */
<> 153:fa9ff456f731 320 #define I2C_DIRECTION_TRANSMIT (0x00000000U)
<> 153:fa9ff456f731 321 #define I2C_DIRECTION_RECEIVE (0x00000001U)
<> 153:fa9ff456f731 322 /**
<> 153:fa9ff456f731 323 * @}
<> 153:fa9ff456f731 324 */
<> 153:fa9ff456f731 325
<> 153:fa9ff456f731 326 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
<> 144:ef7eb2e8f9f7 327 * @{
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define I2C_RELOAD_MODE I2C_CR2_RELOAD
<> 144:ef7eb2e8f9f7 330 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
<> 153:fa9ff456f731 331 #define I2C_SOFTEND_MODE (0x00000000U)
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 153:fa9ff456f731 336 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
<> 144:ef7eb2e8f9f7 337 * @{
<> 144:ef7eb2e8f9f7 338 */
<> 153:fa9ff456f731 339 #define I2C_NO_STARTSTOP (0x00000000U)
<> 153:fa9ff456f731 340 #define I2C_GENERATE_STOP I2C_CR2_STOP
<> 153:fa9ff456f731 341 #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
<> 153:fa9ff456f731 342 #define I2C_GENERATE_START_WRITE I2C_CR2_START
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @}
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
<> 144:ef7eb2e8f9f7 348 * @brief I2C Interrupt definition
<> 144:ef7eb2e8f9f7 349 * Elements values convention: 0xXXXXXXXX
<> 144:ef7eb2e8f9f7 350 * - XXXXXXXX : Interrupt control mask
<> 144:ef7eb2e8f9f7 351 * @{
<> 144:ef7eb2e8f9f7 352 */
<> 153:fa9ff456f731 353 #define I2C_IT_ERRI I2C_CR1_ERRIE
<> 153:fa9ff456f731 354 #define I2C_IT_TCI I2C_CR1_TCIE
<> 153:fa9ff456f731 355 #define I2C_IT_STOPI I2C_CR1_STOPIE
<> 153:fa9ff456f731 356 #define I2C_IT_NACKI I2C_CR1_NACKIE
<> 153:fa9ff456f731 357 #define I2C_IT_ADDRI I2C_CR1_ADDRIE
<> 153:fa9ff456f731 358 #define I2C_IT_RXI I2C_CR1_RXIE
<> 153:fa9ff456f731 359 #define I2C_IT_TXI I2C_CR1_TXIE
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @}
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /** @defgroup I2C_Flag_definition I2C Flag definition
<> 144:ef7eb2e8f9f7 365 * @{
<> 153:fa9ff456f731 366 */
<> 153:fa9ff456f731 367 #define I2C_FLAG_TXE I2C_ISR_TXE
<> 153:fa9ff456f731 368 #define I2C_FLAG_TXIS I2C_ISR_TXIS
<> 153:fa9ff456f731 369 #define I2C_FLAG_RXNE I2C_ISR_RXNE
<> 153:fa9ff456f731 370 #define I2C_FLAG_ADDR I2C_ISR_ADDR
<> 153:fa9ff456f731 371 #define I2C_FLAG_AF I2C_ISR_NACKF
<> 153:fa9ff456f731 372 #define I2C_FLAG_STOPF I2C_ISR_STOPF
<> 153:fa9ff456f731 373 #define I2C_FLAG_TC I2C_ISR_TC
<> 153:fa9ff456f731 374 #define I2C_FLAG_TCR I2C_ISR_TCR
<> 153:fa9ff456f731 375 #define I2C_FLAG_BERR I2C_ISR_BERR
<> 153:fa9ff456f731 376 #define I2C_FLAG_ARLO I2C_ISR_ARLO
<> 153:fa9ff456f731 377 #define I2C_FLAG_OVR I2C_ISR_OVR
<> 153:fa9ff456f731 378 #define I2C_FLAG_PECERR I2C_ISR_PECERR
<> 153:fa9ff456f731 379 #define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
<> 153:fa9ff456f731 380 #define I2C_FLAG_ALERT I2C_ISR_ALERT
<> 153:fa9ff456f731 381 #define I2C_FLAG_BUSY I2C_ISR_BUSY
<> 153:fa9ff456f731 382 #define I2C_FLAG_DIR I2C_ISR_DIR
<> 153:fa9ff456f731 383 /**
<> 153:fa9ff456f731 384 * @}
<> 153:fa9ff456f731 385 */
<> 153:fa9ff456f731 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /** @defgroup I2C_Exported_Macros I2C Exported Macros
<> 144:ef7eb2e8f9f7 394 * @{
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 153:fa9ff456f731 397 /** @brief Reset I2C handle state.
<> 153:fa9ff456f731 398 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 399 * @retval None
<> 144:ef7eb2e8f9f7 400 */
<> 153:fa9ff456f731 401 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
<> 144:ef7eb2e8f9f7 402
<> 153:fa9ff456f731 403 /** @brief Enable the specified I2C interrupt.
<> 153:fa9ff456f731 404 * @param __HANDLE__ specifies the I2C Handle.
<> 153:fa9ff456f731 405 * @param __INTERRUPT__ specifies the interrupt source to enable.
<> 144:ef7eb2e8f9f7 406 * This parameter can be one of the following values:
<> 153:fa9ff456f731 407 * @arg @ref I2C_IT_ERRI Errors interrupt enable
<> 153:fa9ff456f731 408 * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
<> 153:fa9ff456f731 409 * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
<> 153:fa9ff456f731 410 * @arg @ref I2C_IT_NACKI NACK received interrupt enable
<> 153:fa9ff456f731 411 * @arg @ref I2C_IT_ADDRI Address match interrupt enable
<> 153:fa9ff456f731 412 * @arg @ref I2C_IT_RXI RX interrupt enable
<> 153:fa9ff456f731 413 * @arg @ref I2C_IT_TXI TX interrupt enable
<> 153:fa9ff456f731 414 *
<> 144:ef7eb2e8f9f7 415 * @retval None
<> 144:ef7eb2e8f9f7 416 */
<> 153:fa9ff456f731 417 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 418
<> 153:fa9ff456f731 419 /** @brief Disable the specified I2C interrupt.
<> 153:fa9ff456f731 420 * @param __HANDLE__ specifies the I2C Handle.
<> 153:fa9ff456f731 421 * @param __INTERRUPT__ specifies the interrupt source to disable.
<> 144:ef7eb2e8f9f7 422 * This parameter can be one of the following values:
<> 153:fa9ff456f731 423 * @arg @ref I2C_IT_ERRI Errors interrupt enable
<> 153:fa9ff456f731 424 * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
<> 153:fa9ff456f731 425 * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
<> 153:fa9ff456f731 426 * @arg @ref I2C_IT_NACKI NACK received interrupt enable
<> 153:fa9ff456f731 427 * @arg @ref I2C_IT_ADDRI Address match interrupt enable
<> 153:fa9ff456f731 428 * @arg @ref I2C_IT_RXI RX interrupt enable
<> 153:fa9ff456f731 429 * @arg @ref I2C_IT_TXI TX interrupt enable
<> 153:fa9ff456f731 430 *
<> 144:ef7eb2e8f9f7 431 * @retval None
<> 144:ef7eb2e8f9f7 432 */
<> 153:fa9ff456f731 433 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 434
<> 153:fa9ff456f731 435 /** @brief Check whether the specified I2C interrupt source is enabled or not.
<> 153:fa9ff456f731 436 * @param __HANDLE__ specifies the I2C Handle.
<> 153:fa9ff456f731 437 * @param __INTERRUPT__ specifies the I2C interrupt source to check.
<> 144:ef7eb2e8f9f7 438 * This parameter can be one of the following values:
<> 153:fa9ff456f731 439 * @arg @ref I2C_IT_ERRI Errors interrupt enable
<> 153:fa9ff456f731 440 * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
<> 153:fa9ff456f731 441 * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
<> 153:fa9ff456f731 442 * @arg @ref I2C_IT_NACKI NACK received interrupt enable
<> 153:fa9ff456f731 443 * @arg @ref I2C_IT_ADDRI Address match interrupt enable
<> 153:fa9ff456f731 444 * @arg @ref I2C_IT_RXI RX interrupt enable
<> 153:fa9ff456f731 445 * @arg @ref I2C_IT_TXI TX interrupt enable
<> 153:fa9ff456f731 446 *
<> 153:fa9ff456f731 447 * @retval The new state of __INTERRUPT__ (SET or RESET).
<> 144:ef7eb2e8f9f7 448 */
<> 153:fa9ff456f731 449 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 450
<> 153:fa9ff456f731 451 /** @brief Check whether the specified I2C flag is set or not.
<> 153:fa9ff456f731 452 * @param __HANDLE__ specifies the I2C Handle.
<> 153:fa9ff456f731 453 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 454 * This parameter can be one of the following values:
<> 153:fa9ff456f731 455 * @arg @ref I2C_FLAG_TXE Transmit data register empty
<> 153:fa9ff456f731 456 * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
<> 153:fa9ff456f731 457 * @arg @ref I2C_FLAG_RXNE Receive data register not empty
<> 153:fa9ff456f731 458 * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
<> 153:fa9ff456f731 459 * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
<> 153:fa9ff456f731 460 * @arg @ref I2C_FLAG_STOPF STOP detection flag
<> 153:fa9ff456f731 461 * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
<> 153:fa9ff456f731 462 * @arg @ref I2C_FLAG_TCR Transfer complete reload
<> 153:fa9ff456f731 463 * @arg @ref I2C_FLAG_BERR Bus error
<> 153:fa9ff456f731 464 * @arg @ref I2C_FLAG_ARLO Arbitration lost
<> 153:fa9ff456f731 465 * @arg @ref I2C_FLAG_OVR Overrun/Underrun
<> 153:fa9ff456f731 466 * @arg @ref I2C_FLAG_PECERR PEC error in reception
<> 153:fa9ff456f731 467 * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 153:fa9ff456f731 468 * @arg @ref I2C_FLAG_ALERT SMBus alert
<> 153:fa9ff456f731 469 * @arg @ref I2C_FLAG_BUSY Bus busy
<> 153:fa9ff456f731 470 * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
<> 144:ef7eb2e8f9f7 471 *
<> 153:fa9ff456f731 472 * @retval The new state of __FLAG__ (SET or RESET).
<> 144:ef7eb2e8f9f7 473 */
<> 153:fa9ff456f731 474 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 475
<> 153:fa9ff456f731 476 /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
<> 153:fa9ff456f731 477 * @param __HANDLE__ specifies the I2C Handle.
<> 153:fa9ff456f731 478 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 479 * This parameter can be any combination of the following values:
<> 153:fa9ff456f731 480 * @arg @ref I2C_FLAG_TXE Transmit data register empty
<> 153:fa9ff456f731 481 * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
<> 153:fa9ff456f731 482 * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
<> 153:fa9ff456f731 483 * @arg @ref I2C_FLAG_STOPF STOP detection flag
<> 153:fa9ff456f731 484 * @arg @ref I2C_FLAG_BERR Bus error
<> 153:fa9ff456f731 485 * @arg @ref I2C_FLAG_ARLO Arbitration lost
<> 153:fa9ff456f731 486 * @arg @ref I2C_FLAG_OVR Overrun/Underrun
<> 153:fa9ff456f731 487 * @arg @ref I2C_FLAG_PECERR PEC error in reception
<> 153:fa9ff456f731 488 * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 153:fa9ff456f731 489 * @arg @ref I2C_FLAG_ALERT SMBus alert
<> 153:fa9ff456f731 490 *
<> 144:ef7eb2e8f9f7 491 * @retval None
<> 144:ef7eb2e8f9f7 492 */
<> 153:fa9ff456f731 493 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
<> 153:fa9ff456f731 494 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
<> 153:fa9ff456f731 495
<> 144:ef7eb2e8f9f7 496 /** @brief Enable the specified I2C peripheral.
<> 153:fa9ff456f731 497 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 498 * @retval None
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /** @brief Disable the specified I2C peripheral.
<> 153:fa9ff456f731 503 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 504 * @retval None
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 507
<> 153:fa9ff456f731 508 /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
<> 153:fa9ff456f731 509 * @param __HANDLE__: specifies the I2C Handle.
<> 153:fa9ff456f731 510 * @retval None
<> 153:fa9ff456f731 511 */
<> 153:fa9ff456f731 512 #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @}
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516
<> 153:fa9ff456f731 517 /* Include I2C HAL Extended module */
<> 144:ef7eb2e8f9f7 518 #include "stm32l0xx_hal_i2c_ex.h"
<> 144:ef7eb2e8f9f7 519
<> 153:fa9ff456f731 520 /* Exported functions --------------------------------------------------------*/
<> 153:fa9ff456f731 521 /** @addtogroup I2C_Exported_Functions
<> 144:ef7eb2e8f9f7 522 * @{
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524
<> 153:fa9ff456f731 525 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 526 * @{
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 /* Initialization and de-initialization functions******************************/
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 530 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 531 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 532 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @}
<> 153:fa9ff456f731 535 */
<> 144:ef7eb2e8f9f7 536
<> 153:fa9ff456f731 537 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 538 * @{
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 /* IO operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 541 /******* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 542 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 543 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 544 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 545 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 546 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 547 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 548 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /******* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 551 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 552 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 553 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 554 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 555 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 556 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 557
<> 153:fa9ff456f731 558 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 153:fa9ff456f731 559 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 153:fa9ff456f731 560 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 153:fa9ff456f731 561 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 153:fa9ff456f731 562 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
<> 153:fa9ff456f731 563 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
<> 153:fa9ff456f731 564 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
<> 153:fa9ff456f731 565
<> 144:ef7eb2e8f9f7 566 /******* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 567 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 568 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 570 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 571 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 572 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @}
<> 153:fa9ff456f731 575 */
<> 144:ef7eb2e8f9f7 576
<> 153:fa9ff456f731 577 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 578 * @{
<> 153:fa9ff456f731 579 */
<> 153:fa9ff456f731 580 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
<> 144:ef7eb2e8f9f7 581 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 582 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 583 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 584 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 585 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 586 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 153:fa9ff456f731 587 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 153:fa9ff456f731 588 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 589 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 590 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 591 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
<> 153:fa9ff456f731 592 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 593 /**
<> 144:ef7eb2e8f9f7 594 * @}
<> 153:fa9ff456f731 595 */
<> 144:ef7eb2e8f9f7 596
<> 153:fa9ff456f731 597 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
<> 144:ef7eb2e8f9f7 598 * @{
<> 144:ef7eb2e8f9f7 599 */
<> 153:fa9ff456f731 600 /* Peripheral State, Mode and Error functions *********************************/
<> 144:ef7eb2e8f9f7 601 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
<> 153:fa9ff456f731 602 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 603 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /**
<> 144:ef7eb2e8f9f7 606 * @}
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /**
<> 144:ef7eb2e8f9f7 610 * @}
<> 144:ef7eb2e8f9f7 611 */
<> 153:fa9ff456f731 612
<> 153:fa9ff456f731 613 /* Private constants ---------------------------------------------------------*/
<> 153:fa9ff456f731 614 /** @defgroup I2C_Private_Constants I2C Private Constants
<> 153:fa9ff456f731 615 * @{
<> 153:fa9ff456f731 616 */
<> 144:ef7eb2e8f9f7 617
<> 153:fa9ff456f731 618 /**
<> 153:fa9ff456f731 619 * @}
<> 153:fa9ff456f731 620 */
<> 153:fa9ff456f731 621
<> 153:fa9ff456f731 622 /* Private macros ------------------------------------------------------------*/
<> 153:fa9ff456f731 623 /** @defgroup I2C_Private_Macro I2C Private Macros
<> 144:ef7eb2e8f9f7 624 * @{
<> 144:ef7eb2e8f9f7 625 */
<> 153:fa9ff456f731 626
<> 153:fa9ff456f731 627 #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
<> 153:fa9ff456f731 628 ((MODE) == I2C_ADDRESSINGMODE_10BIT))
<> 153:fa9ff456f731 629
<> 153:fa9ff456f731 630 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
<> 153:fa9ff456f731 631 ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
<> 153:fa9ff456f731 632
<> 153:fa9ff456f731 633 #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
<> 153:fa9ff456f731 634 ((MASK) == I2C_OA2_MASK01) || \
<> 153:fa9ff456f731 635 ((MASK) == I2C_OA2_MASK02) || \
<> 153:fa9ff456f731 636 ((MASK) == I2C_OA2_MASK03) || \
<> 153:fa9ff456f731 637 ((MASK) == I2C_OA2_MASK04) || \
<> 153:fa9ff456f731 638 ((MASK) == I2C_OA2_MASK05) || \
<> 153:fa9ff456f731 639 ((MASK) == I2C_OA2_MASK06) || \
<> 153:fa9ff456f731 640 ((MASK) == I2C_OA2_MASK07))
<> 153:fa9ff456f731 641
<> 153:fa9ff456f731 642 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
<> 153:fa9ff456f731 643 ((CALL) == I2C_GENERALCALL_ENABLE))
<> 153:fa9ff456f731 644
<> 153:fa9ff456f731 645 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
<> 153:fa9ff456f731 646 ((STRETCH) == I2C_NOSTRETCH_ENABLE))
<> 153:fa9ff456f731 647
<> 153:fa9ff456f731 648 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
<> 153:fa9ff456f731 649 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
<> 153:fa9ff456f731 650
<> 153:fa9ff456f731 651 #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
<> 153:fa9ff456f731 652 ((MODE) == I2C_AUTOEND_MODE) || \
<> 153:fa9ff456f731 653 ((MODE) == I2C_SOFTEND_MODE))
<> 153:fa9ff456f731 654
<> 153:fa9ff456f731 655 #define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
<> 153:fa9ff456f731 656 ((REQUEST) == I2C_GENERATE_START_READ) || \
<> 153:fa9ff456f731 657 ((REQUEST) == I2C_GENERATE_START_WRITE) || \
<> 153:fa9ff456f731 658 ((REQUEST) == I2C_NO_STARTSTOP))
<> 153:fa9ff456f731 659
<> 153:fa9ff456f731 660 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
<> 153:fa9ff456f731 661 ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
<> 153:fa9ff456f731 662 ((REQUEST) == I2C_NEXT_FRAME) || \
<> 153:fa9ff456f731 663 ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
<> 153:fa9ff456f731 664 ((REQUEST) == I2C_LAST_FRAME))
<> 153:fa9ff456f731 665
<> 153:fa9ff456f731 666 #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
<> 153:fa9ff456f731 667
<> 153:fa9ff456f731 668 #define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
<> 153:fa9ff456f731 669 #define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
<> 153:fa9ff456f731 670 #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
<> 153:fa9ff456f731 671 #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
<> 153:fa9ff456f731 672 #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
<> 153:fa9ff456f731 673
<> 153:fa9ff456f731 674 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
<> 153:fa9ff456f731 675 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
<> 153:fa9ff456f731 676
<> 153:fa9ff456f731 677 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
<> 153:fa9ff456f731 678 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 153:fa9ff456f731 679
<> 153:fa9ff456f731 680 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
<> 153:fa9ff456f731 681 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @}
<> 153:fa9ff456f731 684 */
<> 153:fa9ff456f731 685
<> 153:fa9ff456f731 686 /* Private Functions ---------------------------------------------------------*/
<> 153:fa9ff456f731 687 /** @defgroup I2C_Private_Functions I2C Private Functions
<> 153:fa9ff456f731 688 * @{
<> 144:ef7eb2e8f9f7 689 */
<> 153:fa9ff456f731 690 /* Private functions are defined in stm32l0xx_hal_i2c.c file */
<> 153:fa9ff456f731 691 /**
<> 153:fa9ff456f731 692 * @}
<> 153:fa9ff456f731 693 */
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @}
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /**
<> 144:ef7eb2e8f9f7 700 * @}
<> 144:ef7eb2e8f9f7 701 */
<> 153:fa9ff456f731 702
<> 144:ef7eb2e8f9f7 703 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705 #endif
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 #endif /* __STM32L0xx_HAL_I2C_H */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/