mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 189:f392fc9709a3 | 1 | /* mbed Microcontroller Library |
AnnaBridge | 189:f392fc9709a3 | 2 | ******************************************************************************* |
AnnaBridge | 189:f392fc9709a3 | 3 | * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved |
AnnaBridge | 189:f392fc9709a3 | 4 | * All rights reserved. |
AnnaBridge | 189:f392fc9709a3 | 5 | * SPDX-License-Identifier: Apache-2.0 |
AnnaBridge | 189:f392fc9709a3 | 6 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 189:f392fc9709a3 | 7 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 189:f392fc9709a3 | 8 | * |
AnnaBridge | 189:f392fc9709a3 | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 189:f392fc9709a3 | 10 | * this list of conditions and the following disclaimer. |
AnnaBridge | 189:f392fc9709a3 | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 189:f392fc9709a3 | 12 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 189:f392fc9709a3 | 13 | * and/or other materials provided with the distribution. |
AnnaBridge | 189:f392fc9709a3 | 14 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 189:f392fc9709a3 | 15 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 189:f392fc9709a3 | 16 | * without specific prior written permission. |
AnnaBridge | 189:f392fc9709a3 | 17 | * |
AnnaBridge | 189:f392fc9709a3 | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 189:f392fc9709a3 | 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 189:f392fc9709a3 | 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 189:f392fc9709a3 | 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 189:f392fc9709a3 | 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 189:f392fc9709a3 | 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 189:f392fc9709a3 | 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 189:f392fc9709a3 | 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 189:f392fc9709a3 | 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 189:f392fc9709a3 | 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 189:f392fc9709a3 | 28 | ******************************************************************************* |
AnnaBridge | 189:f392fc9709a3 | 29 | */ |
AnnaBridge | 189:f392fc9709a3 | 30 | #include "spi_api.h" |
AnnaBridge | 189:f392fc9709a3 | 31 | #include "mbed_error.h" |
AnnaBridge | 189:f392fc9709a3 | 32 | #include "pinmap.h" |
AnnaBridge | 189:f392fc9709a3 | 33 | #include "gpio_include.h" |
AnnaBridge | 189:f392fc9709a3 | 34 | |
AnnaBridge | 189:f392fc9709a3 | 35 | static const PinMap PinMap_SPI_SCLK[] = { |
AnnaBridge | 189:f392fc9709a3 | 36 | {PM0, SPI_0, PIN_DATA(3, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 37 | {PB2, SPI_1, PIN_DATA(3, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 38 | {PT2, SPI_2, PIN_DATA(1, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 39 | {PP5, SPI_3, PIN_DATA(1, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 40 | {PH4, SPI_4, PIN_DATA(1, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 41 | {NC, NC, 0} |
AnnaBridge | 189:f392fc9709a3 | 42 | }; |
AnnaBridge | 189:f392fc9709a3 | 43 | |
AnnaBridge | 189:f392fc9709a3 | 44 | static const PinMap PinMap_SPI_MOSI[] = { |
AnnaBridge | 189:f392fc9709a3 | 45 | {PM1, SPI_0, PIN_DATA(3, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 46 | {PB3, SPI_1, PIN_DATA(3, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 47 | {PT3, SPI_2, PIN_DATA(1, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 48 | {PP4, SPI_3, PIN_DATA(1, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 49 | {PH5, SPI_4, PIN_DATA(1, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 50 | {NC, NC, 0} |
AnnaBridge | 189:f392fc9709a3 | 51 | }; |
AnnaBridge | 189:f392fc9709a3 | 52 | |
AnnaBridge | 189:f392fc9709a3 | 53 | static const PinMap PinMap_SPI_MISO[] = { |
AnnaBridge | 189:f392fc9709a3 | 54 | {PM2, SPI_0, PIN_DATA(3, 0)}, |
AnnaBridge | 189:f392fc9709a3 | 55 | {PB4, SPI_1, PIN_DATA(3, 0)}, |
AnnaBridge | 189:f392fc9709a3 | 56 | {PT4, SPI_2, PIN_DATA(1, 0)}, |
AnnaBridge | 189:f392fc9709a3 | 57 | {PP3, SPI_3, PIN_DATA(1, 0)}, |
AnnaBridge | 189:f392fc9709a3 | 58 | {PH6, SPI_4, PIN_DATA(1, 0)}, |
AnnaBridge | 189:f392fc9709a3 | 59 | {NC, NC, 0} |
AnnaBridge | 189:f392fc9709a3 | 60 | }; |
AnnaBridge | 189:f392fc9709a3 | 61 | |
AnnaBridge | 189:f392fc9709a3 | 62 | static const PinMap PinMap_SPI_SSEL[] = { |
AnnaBridge | 189:f392fc9709a3 | 63 | {PM3, SPI_0, PIN_DATA(3, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 64 | {PB5, SPI_1, PIN_DATA(3, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 65 | {PT1, SPI_2, PIN_DATA(2, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 66 | {PP6, SPI_3, PIN_DATA(1, 1)}, |
AnnaBridge | 189:f392fc9709a3 | 67 | {NC, NC, 0} |
AnnaBridge | 189:f392fc9709a3 | 68 | }; |
AnnaBridge | 189:f392fc9709a3 | 69 | |
AnnaBridge | 189:f392fc9709a3 | 70 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) |
AnnaBridge | 189:f392fc9709a3 | 71 | { |
AnnaBridge | 189:f392fc9709a3 | 72 | TSB_TSPI_TypeDef* spi; |
AnnaBridge | 189:f392fc9709a3 | 73 | // Check pin parameters |
AnnaBridge | 189:f392fc9709a3 | 74 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
AnnaBridge | 189:f392fc9709a3 | 75 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
AnnaBridge | 189:f392fc9709a3 | 76 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
AnnaBridge | 189:f392fc9709a3 | 77 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
AnnaBridge | 189:f392fc9709a3 | 78 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
AnnaBridge | 189:f392fc9709a3 | 79 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
AnnaBridge | 189:f392fc9709a3 | 80 | |
AnnaBridge | 189:f392fc9709a3 | 81 | obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl); |
AnnaBridge | 189:f392fc9709a3 | 82 | spi = obj->spi; |
AnnaBridge | 189:f392fc9709a3 | 83 | switch ((int)obj->module) { |
AnnaBridge | 189:f392fc9709a3 | 84 | case SPI_0: |
AnnaBridge | 189:f392fc9709a3 | 85 | TSB_CG_FSYSENA_IPENA11 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 86 | TSB_CG_FSYSENB_IPENB00 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 87 | spi = TSB_TSPI0; |
AnnaBridge | 189:f392fc9709a3 | 88 | break; |
AnnaBridge | 189:f392fc9709a3 | 89 | case SPI_1: |
AnnaBridge | 189:f392fc9709a3 | 90 | TSB_CG_FSYSENA_IPENA01 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 91 | TSB_CG_FSYSENB_IPENB01 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 92 | spi = TSB_TSPI1; |
AnnaBridge | 189:f392fc9709a3 | 93 | break; |
AnnaBridge | 189:f392fc9709a3 | 94 | case SPI_2: |
AnnaBridge | 189:f392fc9709a3 | 95 | TSB_CG_FSYSENA_IPENA15 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 96 | TSB_CG_FSYSENB_IPENB02 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 97 | spi = TSB_TSPI2; |
AnnaBridge | 189:f392fc9709a3 | 98 | break; |
AnnaBridge | 189:f392fc9709a3 | 99 | case SPI_3: |
AnnaBridge | 189:f392fc9709a3 | 100 | TSB_CG_FSYSENA_IPENA13 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 101 | TSB_CG_FSYSENB_IPENB03 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 102 | spi = TSB_TSPI3; |
AnnaBridge | 189:f392fc9709a3 | 103 | break; |
AnnaBridge | 189:f392fc9709a3 | 104 | case SPI_4: |
AnnaBridge | 189:f392fc9709a3 | 105 | TSB_CG_FSYSENA_IPENA07 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 106 | TSB_CG_FSYSENB_IPENB04 = ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 107 | spi = TSB_TSPI4; |
AnnaBridge | 189:f392fc9709a3 | 108 | break; |
AnnaBridge | 189:f392fc9709a3 | 109 | default: |
AnnaBridge | 189:f392fc9709a3 | 110 | error("Cannot found SPI module corresponding with input pins."); |
AnnaBridge | 189:f392fc9709a3 | 111 | break; |
AnnaBridge | 189:f392fc9709a3 | 112 | } |
AnnaBridge | 189:f392fc9709a3 | 113 | obj->spi = spi; |
AnnaBridge | 189:f392fc9709a3 | 114 | // pin out the SPI pins |
AnnaBridge | 189:f392fc9709a3 | 115 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
AnnaBridge | 189:f392fc9709a3 | 116 | pinmap_pinout(miso, PinMap_SPI_MISO); |
AnnaBridge | 189:f392fc9709a3 | 117 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
AnnaBridge | 189:f392fc9709a3 | 118 | |
AnnaBridge | 189:f392fc9709a3 | 119 | if (ssel != NC) { |
AnnaBridge | 189:f392fc9709a3 | 120 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
AnnaBridge | 189:f392fc9709a3 | 121 | } |
AnnaBridge | 189:f392fc9709a3 | 122 | |
AnnaBridge | 189:f392fc9709a3 | 123 | // TTSPI Software Reset |
AnnaBridge | 189:f392fc9709a3 | 124 | spi->CR0 = TSPI_RESET10; |
AnnaBridge | 189:f392fc9709a3 | 125 | spi->CR0 = TSPI_RESET01; |
AnnaBridge | 189:f392fc9709a3 | 126 | |
AnnaBridge | 189:f392fc9709a3 | 127 | // Wait for 2 clocks of reset completion |
AnnaBridge | 189:f392fc9709a3 | 128 | __NOP(); |
AnnaBridge | 189:f392fc9709a3 | 129 | __NOP(); |
AnnaBridge | 189:f392fc9709a3 | 130 | |
AnnaBridge | 189:f392fc9709a3 | 131 | // Enable the selected TSPI peripheral (TTSPIE) |
AnnaBridge | 189:f392fc9709a3 | 132 | spi->CR0 = TSPI_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 133 | spi->CR1 = 0; |
AnnaBridge | 189:f392fc9709a3 | 134 | spi->CR1 = TSPI_MASTER_OPEARTION; |
AnnaBridge | 189:f392fc9709a3 | 135 | spi->CR2 = 0; |
AnnaBridge | 189:f392fc9709a3 | 136 | spi->CR2 = (TSPI_TIDLE_LOW | TSPI_TXDEMP_HI); |
AnnaBridge | 189:f392fc9709a3 | 137 | // Format control0 Register Set |
AnnaBridge | 189:f392fc9709a3 | 138 | spi->FMTR0 = (TSPI_DATA_DIRECTION_MSB | TSPI_DATA_LENGTH_8 | |
AnnaBridge | 189:f392fc9709a3 | 139 | TSPI_MIN_IDLE_TIME_1); |
AnnaBridge | 189:f392fc9709a3 | 140 | // Format control1 Register Set |
AnnaBridge | 189:f392fc9709a3 | 141 | spi->FMTR1 = 0; |
AnnaBridge | 189:f392fc9709a3 | 142 | // Enable the selected TSPI peripheral |
AnnaBridge | 189:f392fc9709a3 | 143 | spi->CR0 |= TSPI_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 144 | spi_frequency(obj, 1000000); |
AnnaBridge | 189:f392fc9709a3 | 145 | } |
AnnaBridge | 189:f392fc9709a3 | 146 | |
AnnaBridge | 189:f392fc9709a3 | 147 | void spi_free(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 148 | { |
AnnaBridge | 189:f392fc9709a3 | 149 | TSB_TSPI_TypeDef* spi; |
AnnaBridge | 189:f392fc9709a3 | 150 | |
AnnaBridge | 189:f392fc9709a3 | 151 | spi = obj->spi; |
AnnaBridge | 189:f392fc9709a3 | 152 | spi->CR0 |= TSPI_DISABLE; |
AnnaBridge | 189:f392fc9709a3 | 153 | spi->CR2 = TSPI_INT_ALL; // Disable all interrupt |
AnnaBridge | 189:f392fc9709a3 | 154 | } |
AnnaBridge | 189:f392fc9709a3 | 155 | |
AnnaBridge | 189:f392fc9709a3 | 156 | void spi_format(spi_t *obj, int bits, int mode, int slave) |
AnnaBridge | 189:f392fc9709a3 | 157 | { |
AnnaBridge | 189:f392fc9709a3 | 158 | TSB_TSPI_TypeDef* spi; |
AnnaBridge | 189:f392fc9709a3 | 159 | |
AnnaBridge | 189:f392fc9709a3 | 160 | obj->bits = bits; |
AnnaBridge | 189:f392fc9709a3 | 161 | spi = obj->spi; |
AnnaBridge | 189:f392fc9709a3 | 162 | obj->bits = bits; |
AnnaBridge | 189:f392fc9709a3 | 163 | spi->CR0 |= TSPI_DISABLE; |
AnnaBridge | 189:f392fc9709a3 | 164 | |
AnnaBridge | 189:f392fc9709a3 | 165 | if (bits >= 8 || bits <= 32) { |
AnnaBridge | 189:f392fc9709a3 | 166 | spi->FMTR0 |= (bits << 24); |
AnnaBridge | 189:f392fc9709a3 | 167 | } else { |
AnnaBridge | 189:f392fc9709a3 | 168 | // Do nothing |
AnnaBridge | 189:f392fc9709a3 | 169 | } |
AnnaBridge | 189:f392fc9709a3 | 170 | spi->FMTR0 |= (((mode >> 1) & 0x1) << 14); |
AnnaBridge | 189:f392fc9709a3 | 171 | spi->FMTR0 |= ((mode & 0x01) << 15); |
AnnaBridge | 189:f392fc9709a3 | 172 | spi->CR0 |= TSPI_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 173 | } |
AnnaBridge | 189:f392fc9709a3 | 174 | |
AnnaBridge | 189:f392fc9709a3 | 175 | void spi_frequency(spi_t *obj, int hz) |
AnnaBridge | 189:f392fc9709a3 | 176 | { |
AnnaBridge | 189:f392fc9709a3 | 177 | TSB_TSPI_TypeDef* spi; |
AnnaBridge | 189:f392fc9709a3 | 178 | int clk_div = 1; |
AnnaBridge | 189:f392fc9709a3 | 179 | uint32_t clocks = ((SystemCoreClock / 2) / hz); |
AnnaBridge | 189:f392fc9709a3 | 180 | obj->spi->CR0 |= TSPI_DISABLE; |
AnnaBridge | 189:f392fc9709a3 | 181 | |
AnnaBridge | 189:f392fc9709a3 | 182 | while (clk_div < 10) { |
AnnaBridge | 189:f392fc9709a3 | 183 | if (clocks < 16) { |
AnnaBridge | 189:f392fc9709a3 | 184 | break; |
AnnaBridge | 189:f392fc9709a3 | 185 | } |
AnnaBridge | 189:f392fc9709a3 | 186 | clk_div++; |
AnnaBridge | 189:f392fc9709a3 | 187 | clocks >>= 1; |
AnnaBridge | 189:f392fc9709a3 | 188 | } |
AnnaBridge | 189:f392fc9709a3 | 189 | clk_div--; |
AnnaBridge | 189:f392fc9709a3 | 190 | if (clk_div == 0) { |
AnnaBridge | 189:f392fc9709a3 | 191 | clocks++; |
AnnaBridge | 189:f392fc9709a3 | 192 | } |
AnnaBridge | 189:f392fc9709a3 | 193 | spi = obj->spi; |
AnnaBridge | 189:f392fc9709a3 | 194 | spi->CR0 |= TSPI_DISABLE; |
AnnaBridge | 189:f392fc9709a3 | 195 | spi->BR = ((clk_div << 4) | clocks); |
AnnaBridge | 189:f392fc9709a3 | 196 | spi->CR0 |= TSPI_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 197 | } |
AnnaBridge | 189:f392fc9709a3 | 198 | |
AnnaBridge | 189:f392fc9709a3 | 199 | int spi_master_write(spi_t *obj, int value) |
AnnaBridge | 189:f392fc9709a3 | 200 | { |
AnnaBridge | 189:f392fc9709a3 | 201 | TSB_TSPI_TypeDef* spi; |
AnnaBridge | 189:f392fc9709a3 | 202 | MBED_ASSERT(obj != NULL); |
AnnaBridge | 189:f392fc9709a3 | 203 | spi = obj->spi; |
AnnaBridge | 189:f392fc9709a3 | 204 | spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; // FIFO Cear |
AnnaBridge | 189:f392fc9709a3 | 205 | // Check if the TSPI is already enabled |
AnnaBridge | 189:f392fc9709a3 | 206 | if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { |
AnnaBridge | 189:f392fc9709a3 | 207 | spi->CR0 |= TSPI_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 208 | } |
AnnaBridge | 189:f392fc9709a3 | 209 | // Enable TSPI Transmission Control |
AnnaBridge | 189:f392fc9709a3 | 210 | spi->CR1 |= TSPI_TRXE_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 211 | // Check the current fill level |
AnnaBridge | 189:f392fc9709a3 | 212 | if(((spi->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { |
AnnaBridge | 189:f392fc9709a3 | 213 | do { |
AnnaBridge | 189:f392fc9709a3 | 214 | spi->DR = (value & TSPI_DR_8BIT_MASK); |
AnnaBridge | 189:f392fc9709a3 | 215 | // check complete transmit |
AnnaBridge | 189:f392fc9709a3 | 216 | } while ((spi->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE); |
AnnaBridge | 189:f392fc9709a3 | 217 | spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; |
AnnaBridge | 189:f392fc9709a3 | 218 | spi->CR1 &= TSPI_TRXE_DISABLE_MASK; |
AnnaBridge | 189:f392fc9709a3 | 219 | } |
AnnaBridge | 189:f392fc9709a3 | 220 | if((spi->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { |
AnnaBridge | 189:f392fc9709a3 | 221 | // Enable TSPI Transmission Control |
AnnaBridge | 189:f392fc9709a3 | 222 | spi->CR1 |= TSPI_TRXE_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 223 | } |
AnnaBridge | 189:f392fc9709a3 | 224 | // Check if the TSPI is already enabled |
AnnaBridge | 189:f392fc9709a3 | 225 | if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { |
AnnaBridge | 189:f392fc9709a3 | 226 | // Enable TSPI Transmission Control |
AnnaBridge | 189:f392fc9709a3 | 227 | spi->CR0 |= TSPI_ENABLE; |
AnnaBridge | 189:f392fc9709a3 | 228 | } |
AnnaBridge | 189:f392fc9709a3 | 229 | value = 0; |
AnnaBridge | 189:f392fc9709a3 | 230 | // Wait until Receive Complete Flag is set to receive data |
AnnaBridge | 189:f392fc9709a3 | 231 | if((spi->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { |
AnnaBridge | 189:f392fc9709a3 | 232 | // Check the remain data exist |
AnnaBridge | 189:f392fc9709a3 | 233 | if((spi->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { |
AnnaBridge | 189:f392fc9709a3 | 234 | value = (spi->DR & TSPI_DR_8BIT_MASK); |
AnnaBridge | 189:f392fc9709a3 | 235 | } |
AnnaBridge | 189:f392fc9709a3 | 236 | spi->SR |= TSPI_RX_DONE_CLR; // Receive Complete Flag is clear |
AnnaBridge | 189:f392fc9709a3 | 237 | spi->CR2 |= TSPI_RX_BUFF_CLR_DONE; // FIFO Clear |
AnnaBridge | 189:f392fc9709a3 | 238 | spi->CR1 &= TSPI_TRXE_DISABLE_MASK; |
AnnaBridge | 189:f392fc9709a3 | 239 | } |
AnnaBridge | 189:f392fc9709a3 | 240 | return value; |
AnnaBridge | 189:f392fc9709a3 | 241 | } |
AnnaBridge | 189:f392fc9709a3 | 242 | |
AnnaBridge | 189:f392fc9709a3 | 243 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, |
AnnaBridge | 189:f392fc9709a3 | 244 | char *rx_buffer, int rx_length, char write_fill) |
AnnaBridge | 189:f392fc9709a3 | 245 | { |
AnnaBridge | 189:f392fc9709a3 | 246 | int total = (tx_length > rx_length) ? tx_length : rx_length; |
AnnaBridge | 189:f392fc9709a3 | 247 | |
AnnaBridge | 189:f392fc9709a3 | 248 | for (int i = 0; i < total; i++) { |
AnnaBridge | 189:f392fc9709a3 | 249 | char out = (i < tx_length) ? tx_buffer[i] : write_fill; |
AnnaBridge | 189:f392fc9709a3 | 250 | char in = spi_master_write(obj, out); |
AnnaBridge | 189:f392fc9709a3 | 251 | if (i < rx_length) { |
AnnaBridge | 189:f392fc9709a3 | 252 | rx_buffer[i] = in; |
AnnaBridge | 189:f392fc9709a3 | 253 | } |
AnnaBridge | 189:f392fc9709a3 | 254 | } |
AnnaBridge | 189:f392fc9709a3 | 255 | |
AnnaBridge | 189:f392fc9709a3 | 256 | return total; |
AnnaBridge | 189:f392fc9709a3 | 257 | } |
AnnaBridge | 189:f392fc9709a3 | 258 | |
AnnaBridge | 189:f392fc9709a3 | 259 | int spi_busy(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 260 | { |
AnnaBridge | 189:f392fc9709a3 | 261 | TSB_TSPI_TypeDef* spi; |
AnnaBridge | 189:f392fc9709a3 | 262 | uint8_t result = 0; |
AnnaBridge | 189:f392fc9709a3 | 263 | |
AnnaBridge | 189:f392fc9709a3 | 264 | spi = obj->spi; |
AnnaBridge | 189:f392fc9709a3 | 265 | if( (spi->SR & (1<<7)) || (spi->SR & (1<<23))) { |
AnnaBridge | 189:f392fc9709a3 | 266 | result = 1; |
AnnaBridge | 189:f392fc9709a3 | 267 | } else { |
AnnaBridge | 189:f392fc9709a3 | 268 | result = 0; |
AnnaBridge | 189:f392fc9709a3 | 269 | } |
AnnaBridge | 189:f392fc9709a3 | 270 | return result; |
AnnaBridge | 189:f392fc9709a3 | 271 | } |
AnnaBridge | 189:f392fc9709a3 | 272 | |
AnnaBridge | 189:f392fc9709a3 | 273 | uint8_t spi_get_module(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 274 | { |
AnnaBridge | 189:f392fc9709a3 | 275 | return (uint8_t)(obj->module); |
AnnaBridge | 189:f392fc9709a3 | 276 | } |