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mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /* mbed Microcontroller Library |
| AnnaBridge | 189:f392fc9709a3 | 2 | * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved |
| AnnaBridge | 189:f392fc9709a3 | 3 | * |
| AnnaBridge | 189:f392fc9709a3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| AnnaBridge | 189:f392fc9709a3 | 5 | * you may not use this file except in compliance with the License. |
| AnnaBridge | 189:f392fc9709a3 | 6 | * You may obtain a copy of the License at |
| AnnaBridge | 189:f392fc9709a3 | 7 | * |
| AnnaBridge | 189:f392fc9709a3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 9 | * |
| AnnaBridge | 189:f392fc9709a3 | 10 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 189:f392fc9709a3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 189:f392fc9709a3 | 13 | * See the License for the specific language governing permissions and |
| AnnaBridge | 189:f392fc9709a3 | 14 | * limitations under the License. |
| AnnaBridge | 189:f392fc9709a3 | 15 | */ |
| AnnaBridge | 189:f392fc9709a3 | 16 | #include "gpio_irq_api.h" |
| AnnaBridge | 189:f392fc9709a3 | 17 | #include "mbed_error.h" |
| AnnaBridge | 189:f392fc9709a3 | 18 | #include "PeripheralNames.h" |
| AnnaBridge | 189:f392fc9709a3 | 19 | #include "pinmap.h" |
| AnnaBridge | 189:f392fc9709a3 | 20 | #include "gpio_include.h" |
| AnnaBridge | 189:f392fc9709a3 | 21 | #include "mbed_critical.h" |
| AnnaBridge | 189:f392fc9709a3 | 22 | |
| AnnaBridge | 189:f392fc9709a3 | 23 | #define CHANNEL_NUM 32 |
| AnnaBridge | 189:f392fc9709a3 | 24 | |
| AnnaBridge | 189:f392fc9709a3 | 25 | const PinMap PinMap_GPIO_IRQ[] = { |
| AnnaBridge | 189:f392fc9709a3 | 26 | {PC0, GPIO_IRQ_00, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 27 | {PC1, GPIO_IRQ_01, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 28 | {PC2, GPIO_IRQ_02, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 29 | {PB1, GPIO_IRQ_03, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 30 | {PJ4, GPIO_IRQ_04, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 31 | {PK1, GPIO_IRQ_05, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 32 | {PH3, GPIO_IRQ_06, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 33 | {PA6, GPIO_IRQ_07, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 34 | {PL3, GPIO_IRQ_08, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 35 | {PM2, GPIO_IRQ_09, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 36 | {PN3, GPIO_IRQ_10, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 37 | {PA7, GPIO_IRQ_11, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 38 | {PL4, GPIO_IRQ_12, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 39 | {PK7, GPIO_IRQ_13, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 40 | {PP3, GPIO_IRQ_14, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 41 | {PM6, GPIO_IRQ_15, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 42 | {PB7, GPIO_IRQ_16, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 43 | {PV2, GPIO_IRQ_17_18, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 44 | {PH4, GPIO_IRQ_19_22, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 45 | {PT0, GPIO_IRQ_23_26, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 46 | {PG2, GPIO_IRQ_27_28, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 47 | {PT7, GPIO_IRQ_29, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 48 | {PU0, GPIO_IRQ_30_31, PIN_DATA(0, 0)}, |
| AnnaBridge | 189:f392fc9709a3 | 49 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 50 | }; |
| AnnaBridge | 189:f392fc9709a3 | 51 | |
| AnnaBridge | 189:f392fc9709a3 | 52 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
| AnnaBridge | 189:f392fc9709a3 | 53 | static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; |
| AnnaBridge | 189:f392fc9709a3 | 54 | static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState ); |
| AnnaBridge | 189:f392fc9709a3 | 55 | cg_intactivestate CurrentState; |
| AnnaBridge | 189:f392fc9709a3 | 56 | static void INT_IRQHandler(PinName pin, uint32_t index); |
| AnnaBridge | 189:f392fc9709a3 | 57 | |
| AnnaBridge | 189:f392fc9709a3 | 58 | // Initialize gpio IRQ pin |
| AnnaBridge | 189:f392fc9709a3 | 59 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) |
| AnnaBridge | 189:f392fc9709a3 | 60 | { |
| AnnaBridge | 189:f392fc9709a3 | 61 | uint8_t bit = 0; |
| AnnaBridge | 189:f392fc9709a3 | 62 | uint32_t port_base = 0; |
| AnnaBridge | 189:f392fc9709a3 | 63 | |
| AnnaBridge | 189:f392fc9709a3 | 64 | // Get gpio interrupt ID |
| AnnaBridge | 189:f392fc9709a3 | 65 | obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); |
| AnnaBridge | 189:f392fc9709a3 | 66 | |
| AnnaBridge | 189:f392fc9709a3 | 67 | // Disable interrupt by CPU |
| AnnaBridge | 189:f392fc9709a3 | 68 | core_util_critical_section_enter(); |
| AnnaBridge | 189:f392fc9709a3 | 69 | |
| AnnaBridge | 189:f392fc9709a3 | 70 | // Calculate port and pin position |
| AnnaBridge | 189:f392fc9709a3 | 71 | obj->port = (PortName)PIN_PORT(pin); |
| AnnaBridge | 189:f392fc9709a3 | 72 | obj->pin = pin; |
| AnnaBridge | 189:f392fc9709a3 | 73 | bit = PIN_POS(pin); |
| AnnaBridge | 189:f392fc9709a3 | 74 | |
| AnnaBridge | 189:f392fc9709a3 | 75 | port_base = BITBAND_PORT_BASE(obj->port); |
| AnnaBridge | 189:f392fc9709a3 | 76 | port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); |
| AnnaBridge | 189:f392fc9709a3 | 77 | BITBAND_PORT_CLR(port_base, bit); |
| AnnaBridge | 189:f392fc9709a3 | 78 | // Enable gpio interrupt function |
| AnnaBridge | 189:f392fc9709a3 | 79 | pinmap_pinout(pin, PinMap_GPIO_IRQ); |
| AnnaBridge | 189:f392fc9709a3 | 80 | |
| AnnaBridge | 189:f392fc9709a3 | 81 | // Get GPIO irq source |
| AnnaBridge | 189:f392fc9709a3 | 82 | switch (obj->irq_id) { |
| AnnaBridge | 189:f392fc9709a3 | 83 | case GPIO_IRQ_00: |
| AnnaBridge | 189:f392fc9709a3 | 84 | obj->irq_src = CG_INT_SRC_01; |
| AnnaBridge | 189:f392fc9709a3 | 85 | break; |
| AnnaBridge | 189:f392fc9709a3 | 86 | case GPIO_IRQ_01: |
| AnnaBridge | 189:f392fc9709a3 | 87 | obj->irq_src = CG_INT_SRC_02; |
| AnnaBridge | 189:f392fc9709a3 | 88 | break; |
| AnnaBridge | 189:f392fc9709a3 | 89 | case GPIO_IRQ_02: |
| AnnaBridge | 189:f392fc9709a3 | 90 | obj->irq_src = CG_INT_SRC_03; |
| AnnaBridge | 189:f392fc9709a3 | 91 | break; |
| AnnaBridge | 189:f392fc9709a3 | 92 | case GPIO_IRQ_03: |
| AnnaBridge | 189:f392fc9709a3 | 93 | obj->irq_src = CG_INT_SRC_04; |
| AnnaBridge | 189:f392fc9709a3 | 94 | break; |
| AnnaBridge | 189:f392fc9709a3 | 95 | case GPIO_IRQ_04: |
| AnnaBridge | 189:f392fc9709a3 | 96 | obj->irq_src = CG_INT_SRC_05; |
| AnnaBridge | 189:f392fc9709a3 | 97 | break; |
| AnnaBridge | 189:f392fc9709a3 | 98 | case GPIO_IRQ_05: |
| AnnaBridge | 189:f392fc9709a3 | 99 | obj->irq_src = CG_INT_SRC_06; |
| AnnaBridge | 189:f392fc9709a3 | 100 | break; |
| AnnaBridge | 189:f392fc9709a3 | 101 | case GPIO_IRQ_06: |
| AnnaBridge | 189:f392fc9709a3 | 102 | obj->irq_src = CG_INT_SRC_07; |
| AnnaBridge | 189:f392fc9709a3 | 103 | break; |
| AnnaBridge | 189:f392fc9709a3 | 104 | case GPIO_IRQ_07: |
| AnnaBridge | 189:f392fc9709a3 | 105 | obj->irq_src = CG_INT_SRC_08; |
| AnnaBridge | 189:f392fc9709a3 | 106 | break; |
| AnnaBridge | 189:f392fc9709a3 | 107 | case GPIO_IRQ_08: |
| AnnaBridge | 189:f392fc9709a3 | 108 | obj->irq_src = CG_INT_SRC_09; |
| AnnaBridge | 189:f392fc9709a3 | 109 | break; |
| AnnaBridge | 189:f392fc9709a3 | 110 | case GPIO_IRQ_09: |
| AnnaBridge | 189:f392fc9709a3 | 111 | obj->irq_src = CG_INT_SRC_0A; |
| AnnaBridge | 189:f392fc9709a3 | 112 | break; |
| AnnaBridge | 189:f392fc9709a3 | 113 | case GPIO_IRQ_10: |
| AnnaBridge | 189:f392fc9709a3 | 114 | obj->irq_src = CG_INT_SRC_0B; |
| AnnaBridge | 189:f392fc9709a3 | 115 | break; |
| AnnaBridge | 189:f392fc9709a3 | 116 | case GPIO_IRQ_11: |
| AnnaBridge | 189:f392fc9709a3 | 117 | obj->irq_src = CG_INT_SRC_0C; |
| AnnaBridge | 189:f392fc9709a3 | 118 | break; |
| AnnaBridge | 189:f392fc9709a3 | 119 | case GPIO_IRQ_12: |
| AnnaBridge | 189:f392fc9709a3 | 120 | obj->irq_src = CG_INT_SRC_0D; |
| AnnaBridge | 189:f392fc9709a3 | 121 | break; |
| AnnaBridge | 189:f392fc9709a3 | 122 | case GPIO_IRQ_13: |
| AnnaBridge | 189:f392fc9709a3 | 123 | obj->irq_src = CG_INT_SRC_0E; |
| AnnaBridge | 189:f392fc9709a3 | 124 | break; |
| AnnaBridge | 189:f392fc9709a3 | 125 | case GPIO_IRQ_14: |
| AnnaBridge | 189:f392fc9709a3 | 126 | obj->irq_src = CG_INT_SRC_0F; |
| AnnaBridge | 189:f392fc9709a3 | 127 | break; |
| AnnaBridge | 189:f392fc9709a3 | 128 | case GPIO_IRQ_15: |
| AnnaBridge | 189:f392fc9709a3 | 129 | obj->irq_src = CG_INT_SRC_10; |
| AnnaBridge | 189:f392fc9709a3 | 130 | break; |
| AnnaBridge | 189:f392fc9709a3 | 131 | case GPIO_IRQ_16: |
| AnnaBridge | 189:f392fc9709a3 | 132 | obj->irq_src = CG_INT_SRC_11; |
| AnnaBridge | 189:f392fc9709a3 | 133 | break; |
| AnnaBridge | 189:f392fc9709a3 | 134 | case GPIO_IRQ_17_18: |
| AnnaBridge | 189:f392fc9709a3 | 135 | obj->irq_src = CG_INT_SRC_12; |
| AnnaBridge | 189:f392fc9709a3 | 136 | break; |
| AnnaBridge | 189:f392fc9709a3 | 137 | case GPIO_IRQ_19_22: |
| AnnaBridge | 189:f392fc9709a3 | 138 | obj->irq_src = CG_INT_SRC_14; |
| AnnaBridge | 189:f392fc9709a3 | 139 | break; |
| AnnaBridge | 189:f392fc9709a3 | 140 | case GPIO_IRQ_23_26: |
| AnnaBridge | 189:f392fc9709a3 | 141 | obj->irq_src = CG_INT_SRC_18; |
| AnnaBridge | 189:f392fc9709a3 | 142 | break; |
| AnnaBridge | 189:f392fc9709a3 | 143 | case GPIO_IRQ_27_28: |
| AnnaBridge | 189:f392fc9709a3 | 144 | obj->irq_src = CG_INT_SRC_1C; |
| AnnaBridge | 189:f392fc9709a3 | 145 | break; |
| AnnaBridge | 189:f392fc9709a3 | 146 | case GPIO_IRQ_29: |
| AnnaBridge | 189:f392fc9709a3 | 147 | obj->irq_src = CG_INT_SRC_1E; |
| AnnaBridge | 189:f392fc9709a3 | 148 | break; |
| AnnaBridge | 189:f392fc9709a3 | 149 | case GPIO_IRQ_30_31: |
| AnnaBridge | 189:f392fc9709a3 | 150 | obj->irq_src = CG_INT_SRC_1F; |
| AnnaBridge | 189:f392fc9709a3 | 151 | break; |
| AnnaBridge | 189:f392fc9709a3 | 152 | default: |
| AnnaBridge | 189:f392fc9709a3 | 153 | break; |
| AnnaBridge | 189:f392fc9709a3 | 154 | } |
| AnnaBridge | 189:f392fc9709a3 | 155 | |
| AnnaBridge | 189:f392fc9709a3 | 156 | // Save irq handler |
| AnnaBridge | 189:f392fc9709a3 | 157 | hal_irq_handler[obj->irq_src] = handler; |
| AnnaBridge | 189:f392fc9709a3 | 158 | |
| AnnaBridge | 189:f392fc9709a3 | 159 | // Save irq id |
| AnnaBridge | 189:f392fc9709a3 | 160 | channel_ids[obj->irq_src] = id; |
| AnnaBridge | 189:f392fc9709a3 | 161 | |
| AnnaBridge | 189:f392fc9709a3 | 162 | // Initialize interrupt event as both edges detection |
| AnnaBridge | 189:f392fc9709a3 | 163 | obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; |
| AnnaBridge | 189:f392fc9709a3 | 164 | CurrentState = CG_INT_ACTIVE_STATE_BOTH_EDGES; |
| AnnaBridge | 189:f392fc9709a3 | 165 | // Set interrupt event and enable INTx clear |
| AnnaBridge | 189:f392fc9709a3 | 166 | SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE); |
| AnnaBridge | 189:f392fc9709a3 | 167 | |
| AnnaBridge | 189:f392fc9709a3 | 168 | // Clear gpio pending interrupt |
| AnnaBridge | 189:f392fc9709a3 | 169 | NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id); |
| AnnaBridge | 189:f392fc9709a3 | 170 | |
| AnnaBridge | 189:f392fc9709a3 | 171 | core_util_critical_section_exit(); |
| AnnaBridge | 189:f392fc9709a3 | 172 | |
| AnnaBridge | 189:f392fc9709a3 | 173 | return 0; |
| AnnaBridge | 189:f392fc9709a3 | 174 | } |
| AnnaBridge | 189:f392fc9709a3 | 175 | |
| AnnaBridge | 189:f392fc9709a3 | 176 | void gpio_irq_free(gpio_irq_t *obj) |
| AnnaBridge | 189:f392fc9709a3 | 177 | { |
| AnnaBridge | 189:f392fc9709a3 | 178 | // Clear gpio_irq |
| AnnaBridge | 189:f392fc9709a3 | 179 | NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); |
| AnnaBridge | 189:f392fc9709a3 | 180 | // Reset interrupt handler |
| AnnaBridge | 189:f392fc9709a3 | 181 | hal_irq_handler[obj->irq_src] = NULL; |
| AnnaBridge | 189:f392fc9709a3 | 182 | // Reset interrupt id |
| AnnaBridge | 189:f392fc9709a3 | 183 | channel_ids[obj->irq_src] = 0; |
| AnnaBridge | 189:f392fc9709a3 | 184 | } |
| AnnaBridge | 189:f392fc9709a3 | 185 | |
| AnnaBridge | 189:f392fc9709a3 | 186 | // Set interrupt event of gpio_irq object |
| AnnaBridge | 189:f392fc9709a3 | 187 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) |
| AnnaBridge | 189:f392fc9709a3 | 188 | { |
| AnnaBridge | 189:f392fc9709a3 | 189 | uint8_t bit = 0; |
| AnnaBridge | 189:f392fc9709a3 | 190 | uint32_t port_base = 0; |
| AnnaBridge | 189:f392fc9709a3 | 191 | |
| AnnaBridge | 189:f392fc9709a3 | 192 | //Disable GPIO interrupt on obj |
| AnnaBridge | 189:f392fc9709a3 | 193 | gpio_irq_disable(obj); |
| AnnaBridge | 189:f392fc9709a3 | 194 | if (enable) { |
| AnnaBridge | 189:f392fc9709a3 | 195 | // Get gpio interrupt event |
| AnnaBridge | 189:f392fc9709a3 | 196 | if (event == IRQ_RISE) { |
| AnnaBridge | 189:f392fc9709a3 | 197 | if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { |
| AnnaBridge | 189:f392fc9709a3 | 198 | obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; |
| AnnaBridge | 189:f392fc9709a3 | 199 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 200 | obj->event = CG_INT_ACTIVE_STATE_RISING; |
| AnnaBridge | 189:f392fc9709a3 | 201 | } |
| AnnaBridge | 189:f392fc9709a3 | 202 | } else if (event == IRQ_FALL) { |
| AnnaBridge | 189:f392fc9709a3 | 203 | if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { |
| AnnaBridge | 189:f392fc9709a3 | 204 | obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; |
| AnnaBridge | 189:f392fc9709a3 | 205 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 206 | obj->event = CG_INT_ACTIVE_STATE_FALLING; |
| AnnaBridge | 189:f392fc9709a3 | 207 | } |
| AnnaBridge | 189:f392fc9709a3 | 208 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 209 | error("Not supported event\n"); |
| AnnaBridge | 189:f392fc9709a3 | 210 | } |
| AnnaBridge | 189:f392fc9709a3 | 211 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 212 | // Get gpio interrupt event |
| AnnaBridge | 189:f392fc9709a3 | 213 | if (event == IRQ_RISE) { |
| AnnaBridge | 189:f392fc9709a3 | 214 | if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { |
| AnnaBridge | 189:f392fc9709a3 | 215 | obj->event = CG_INT_ACTIVE_STATE_INVALID; |
| AnnaBridge | 189:f392fc9709a3 | 216 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 217 | obj->event = CG_INT_ACTIVE_STATE_FALLING; |
| AnnaBridge | 189:f392fc9709a3 | 218 | } |
| AnnaBridge | 189:f392fc9709a3 | 219 | } else if (event == IRQ_FALL) { |
| AnnaBridge | 189:f392fc9709a3 | 220 | if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { |
| AnnaBridge | 189:f392fc9709a3 | 221 | obj->event = CG_INT_ACTIVE_STATE_INVALID; |
| AnnaBridge | 189:f392fc9709a3 | 222 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 223 | obj->event = CG_INT_ACTIVE_STATE_RISING; |
| AnnaBridge | 189:f392fc9709a3 | 224 | } |
| AnnaBridge | 189:f392fc9709a3 | 225 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 226 | error("Not supported event\n"); |
| AnnaBridge | 189:f392fc9709a3 | 227 | } |
| AnnaBridge | 189:f392fc9709a3 | 228 | } |
| AnnaBridge | 189:f392fc9709a3 | 229 | CurrentState = obj->event; |
| AnnaBridge | 189:f392fc9709a3 | 230 | // Calculate port and pin position |
| AnnaBridge | 189:f392fc9709a3 | 231 | bit = PIN_POS(obj->pin); |
| AnnaBridge | 189:f392fc9709a3 | 232 | |
| AnnaBridge | 189:f392fc9709a3 | 233 | port_base = BITBAND_PORT_BASE(obj->port); |
| AnnaBridge | 189:f392fc9709a3 | 234 | port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); |
| AnnaBridge | 189:f392fc9709a3 | 235 | |
| AnnaBridge | 189:f392fc9709a3 | 236 | if(obj->event != CG_INT_ACTIVE_STATE_INVALID ) { |
| AnnaBridge | 189:f392fc9709a3 | 237 | // Set interrupt event and enable INTx clear |
| AnnaBridge | 189:f392fc9709a3 | 238 | SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE); |
| AnnaBridge | 189:f392fc9709a3 | 239 | BITBAND_PORT_CLR(port_base, bit); |
| AnnaBridge | 189:f392fc9709a3 | 240 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 241 | BITBAND_PORT_SET(port_base, bit); |
| AnnaBridge | 189:f392fc9709a3 | 242 | } |
| AnnaBridge | 189:f392fc9709a3 | 243 | //Enable GPIO interrupt on obj |
| AnnaBridge | 189:f392fc9709a3 | 244 | gpio_irq_enable(obj); |
| AnnaBridge | 189:f392fc9709a3 | 245 | } |
| AnnaBridge | 189:f392fc9709a3 | 246 | |
| AnnaBridge | 189:f392fc9709a3 | 247 | // Enable gpio_irq object |
| AnnaBridge | 189:f392fc9709a3 | 248 | void gpio_irq_enable(gpio_irq_t *obj) |
| AnnaBridge | 189:f392fc9709a3 | 249 | { |
| AnnaBridge | 189:f392fc9709a3 | 250 | // Clear and Enable gpio_irq object |
| AnnaBridge | 189:f392fc9709a3 | 251 | NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); |
| AnnaBridge | 189:f392fc9709a3 | 252 | NVIC_EnableIRQ((IRQn_Type)obj->irq_id); |
| AnnaBridge | 189:f392fc9709a3 | 253 | } |
| AnnaBridge | 189:f392fc9709a3 | 254 | |
| AnnaBridge | 189:f392fc9709a3 | 255 | // Disable gpio_irq object |
| AnnaBridge | 189:f392fc9709a3 | 256 | void gpio_irq_disable(gpio_irq_t *obj) |
| AnnaBridge | 189:f392fc9709a3 | 257 | { |
| AnnaBridge | 189:f392fc9709a3 | 258 | // Disable gpio_irq object |
| AnnaBridge | 189:f392fc9709a3 | 259 | NVIC_DisableIRQ((IRQn_Type)obj->irq_id); |
| AnnaBridge | 189:f392fc9709a3 | 260 | } |
| AnnaBridge | 189:f392fc9709a3 | 261 | |
| AnnaBridge | 189:f392fc9709a3 | 262 | static void INT_IRQHandler(PinName pin, uint32_t index) |
| AnnaBridge | 189:f392fc9709a3 | 263 | { |
| AnnaBridge | 189:f392fc9709a3 | 264 | int port = 0; |
| AnnaBridge | 189:f392fc9709a3 | 265 | uint8_t bit = 0; |
| AnnaBridge | 189:f392fc9709a3 | 266 | uint32_t data = 0; |
| AnnaBridge | 189:f392fc9709a3 | 267 | uint32_t port_base = 0; |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | // Calculate port and pin position |
| AnnaBridge | 189:f392fc9709a3 | 270 | port = PIN_PORT(pin); |
| AnnaBridge | 189:f392fc9709a3 | 271 | bit = PIN_POS(pin); |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | // Clear interrupt request |
| AnnaBridge | 189:f392fc9709a3 | 274 | SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, DISABLE); |
| AnnaBridge | 189:f392fc9709a3 | 275 | |
| AnnaBridge | 189:f392fc9709a3 | 276 | port_base = BITBAND_PORT_BASE(port); |
| AnnaBridge | 189:f392fc9709a3 | 277 | port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); |
| AnnaBridge | 189:f392fc9709a3 | 278 | BITBAND_PORT_READ(data, port_base, bit); |
| AnnaBridge | 189:f392fc9709a3 | 279 | |
| AnnaBridge | 189:f392fc9709a3 | 280 | switch (data) { |
| AnnaBridge | 189:f392fc9709a3 | 281 | // Falling edge detection |
| AnnaBridge | 189:f392fc9709a3 | 282 | case 0: |
| AnnaBridge | 189:f392fc9709a3 | 283 | hal_irq_handler[index](channel_ids[index], IRQ_FALL); |
| AnnaBridge | 189:f392fc9709a3 | 284 | break; |
| AnnaBridge | 189:f392fc9709a3 | 285 | // Rising edge detection |
| AnnaBridge | 189:f392fc9709a3 | 286 | case 1: |
| AnnaBridge | 189:f392fc9709a3 | 287 | hal_irq_handler[index](channel_ids[index], IRQ_RISE); |
| AnnaBridge | 189:f392fc9709a3 | 288 | break; |
| AnnaBridge | 189:f392fc9709a3 | 289 | default: |
| AnnaBridge | 189:f392fc9709a3 | 290 | break; |
| AnnaBridge | 189:f392fc9709a3 | 291 | } |
| AnnaBridge | 189:f392fc9709a3 | 292 | // Clear gpio pending interrupt |
| AnnaBridge | 189:f392fc9709a3 | 293 | NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_01 + index)); |
| AnnaBridge | 189:f392fc9709a3 | 294 | |
| AnnaBridge | 189:f392fc9709a3 | 295 | // Enable interrupt request |
| AnnaBridge | 189:f392fc9709a3 | 296 | SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, ENABLE); |
| AnnaBridge | 189:f392fc9709a3 | 297 | } |
| AnnaBridge | 189:f392fc9709a3 | 298 | |
| AnnaBridge | 189:f392fc9709a3 | 299 | void INT00_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 300 | { |
| AnnaBridge | 189:f392fc9709a3 | 301 | INT_IRQHandler(PC0, 0); |
| AnnaBridge | 189:f392fc9709a3 | 302 | } |
| AnnaBridge | 189:f392fc9709a3 | 303 | |
| AnnaBridge | 189:f392fc9709a3 | 304 | void INT01_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 305 | { |
| AnnaBridge | 189:f392fc9709a3 | 306 | INT_IRQHandler(PC1, 1); |
| AnnaBridge | 189:f392fc9709a3 | 307 | } |
| AnnaBridge | 189:f392fc9709a3 | 308 | |
| AnnaBridge | 189:f392fc9709a3 | 309 | void INT02_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 310 | { |
| AnnaBridge | 189:f392fc9709a3 | 311 | INT_IRQHandler(PC2, 2); |
| AnnaBridge | 189:f392fc9709a3 | 312 | } |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | void INT03_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 315 | { |
| AnnaBridge | 189:f392fc9709a3 | 316 | INT_IRQHandler(PB1, 3); |
| AnnaBridge | 189:f392fc9709a3 | 317 | } |
| AnnaBridge | 189:f392fc9709a3 | 318 | |
| AnnaBridge | 189:f392fc9709a3 | 319 | void INT04_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 320 | { |
| AnnaBridge | 189:f392fc9709a3 | 321 | INT_IRQHandler(PJ4, 4); |
| AnnaBridge | 189:f392fc9709a3 | 322 | } |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | void INT05_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 325 | { |
| AnnaBridge | 189:f392fc9709a3 | 326 | INT_IRQHandler(PK1, 5); |
| AnnaBridge | 189:f392fc9709a3 | 327 | } |
| AnnaBridge | 189:f392fc9709a3 | 328 | |
| AnnaBridge | 189:f392fc9709a3 | 329 | void INT06_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 330 | { |
| AnnaBridge | 189:f392fc9709a3 | 331 | INT_IRQHandler(PH3, 6); |
| AnnaBridge | 189:f392fc9709a3 | 332 | } |
| AnnaBridge | 189:f392fc9709a3 | 333 | |
| AnnaBridge | 189:f392fc9709a3 | 334 | void INT07_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 335 | { |
| AnnaBridge | 189:f392fc9709a3 | 336 | INT_IRQHandler(PA6, 7); |
| AnnaBridge | 189:f392fc9709a3 | 337 | } |
| AnnaBridge | 189:f392fc9709a3 | 338 | |
| AnnaBridge | 189:f392fc9709a3 | 339 | void INT08_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 340 | { |
| AnnaBridge | 189:f392fc9709a3 | 341 | INT_IRQHandler(PL3, 8); |
| AnnaBridge | 189:f392fc9709a3 | 342 | } |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | void INT09_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 345 | { |
| AnnaBridge | 189:f392fc9709a3 | 346 | INT_IRQHandler(PM2, 9); |
| AnnaBridge | 189:f392fc9709a3 | 347 | } |
| AnnaBridge | 189:f392fc9709a3 | 348 | |
| AnnaBridge | 189:f392fc9709a3 | 349 | void INT10_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 350 | { |
| AnnaBridge | 189:f392fc9709a3 | 351 | INT_IRQHandler(PN3, 10); |
| AnnaBridge | 189:f392fc9709a3 | 352 | } |
| AnnaBridge | 189:f392fc9709a3 | 353 | |
| AnnaBridge | 189:f392fc9709a3 | 354 | void INT11_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 355 | { |
| AnnaBridge | 189:f392fc9709a3 | 356 | INT_IRQHandler(PA7, 11); |
| AnnaBridge | 189:f392fc9709a3 | 357 | } |
| AnnaBridge | 189:f392fc9709a3 | 358 | |
| AnnaBridge | 189:f392fc9709a3 | 359 | void INT12_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 360 | { |
| AnnaBridge | 189:f392fc9709a3 | 361 | INT_IRQHandler(PL4, 12); |
| AnnaBridge | 189:f392fc9709a3 | 362 | } |
| AnnaBridge | 189:f392fc9709a3 | 363 | |
| AnnaBridge | 189:f392fc9709a3 | 364 | void INT13_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 365 | { |
| AnnaBridge | 189:f392fc9709a3 | 366 | INT_IRQHandler(PK7, 13); |
| AnnaBridge | 189:f392fc9709a3 | 367 | } |
| AnnaBridge | 189:f392fc9709a3 | 368 | |
| AnnaBridge | 189:f392fc9709a3 | 369 | void INT14_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 370 | { |
| AnnaBridge | 189:f392fc9709a3 | 371 | INT_IRQHandler(PP3, 14); |
| AnnaBridge | 189:f392fc9709a3 | 372 | } |
| AnnaBridge | 189:f392fc9709a3 | 373 | |
| AnnaBridge | 189:f392fc9709a3 | 374 | void INT15_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 375 | { |
| AnnaBridge | 189:f392fc9709a3 | 376 | INT_IRQHandler(PM6, 15); |
| AnnaBridge | 189:f392fc9709a3 | 377 | } |
| AnnaBridge | 189:f392fc9709a3 | 378 | |
| AnnaBridge | 189:f392fc9709a3 | 379 | void INT16_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 380 | { |
| AnnaBridge | 189:f392fc9709a3 | 381 | INT_IRQHandler(PB7, 16); |
| AnnaBridge | 189:f392fc9709a3 | 382 | } |
| AnnaBridge | 189:f392fc9709a3 | 383 | |
| AnnaBridge | 189:f392fc9709a3 | 384 | void INT17_18_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 385 | { |
| AnnaBridge | 189:f392fc9709a3 | 386 | INT_IRQHandler(PV2, 17); |
| AnnaBridge | 189:f392fc9709a3 | 387 | } |
| AnnaBridge | 189:f392fc9709a3 | 388 | |
| AnnaBridge | 189:f392fc9709a3 | 389 | void INT19_22_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 390 | { |
| AnnaBridge | 189:f392fc9709a3 | 391 | INT_IRQHandler(PH4, 19); |
| AnnaBridge | 189:f392fc9709a3 | 392 | } |
| AnnaBridge | 189:f392fc9709a3 | 393 | |
| AnnaBridge | 189:f392fc9709a3 | 394 | void INT23_26_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 395 | { |
| AnnaBridge | 189:f392fc9709a3 | 396 | INT_IRQHandler(PT0, 23); |
| AnnaBridge | 189:f392fc9709a3 | 397 | } |
| AnnaBridge | 189:f392fc9709a3 | 398 | |
| AnnaBridge | 189:f392fc9709a3 | 399 | void INT27_28_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 400 | { |
| AnnaBridge | 189:f392fc9709a3 | 401 | INT_IRQHandler(PG2, 27); |
| AnnaBridge | 189:f392fc9709a3 | 402 | } |
| AnnaBridge | 189:f392fc9709a3 | 403 | |
| AnnaBridge | 189:f392fc9709a3 | 404 | void INT29_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 405 | { |
| AnnaBridge | 189:f392fc9709a3 | 406 | INT_IRQHandler(PT7, 29); |
| AnnaBridge | 189:f392fc9709a3 | 407 | } |
| AnnaBridge | 189:f392fc9709a3 | 408 | |
| AnnaBridge | 189:f392fc9709a3 | 409 | void INT30_31_IRQHandler(void) |
| AnnaBridge | 189:f392fc9709a3 | 410 | { |
| AnnaBridge | 189:f392fc9709a3 | 411 | INT_IRQHandler(PU0, 30); |
| AnnaBridge | 189:f392fc9709a3 | 412 | } |
| AnnaBridge | 189:f392fc9709a3 | 413 | |
| AnnaBridge | 189:f392fc9709a3 | 414 | static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState) |
| AnnaBridge | 189:f392fc9709a3 | 415 | { |
| AnnaBridge | 189:f392fc9709a3 | 416 | __IO uint8_t *p_imc; |
| AnnaBridge | 189:f392fc9709a3 | 417 | |
| AnnaBridge | 189:f392fc9709a3 | 418 | if(intsource < 3U || intsource == 13U) { |
| AnnaBridge | 189:f392fc9709a3 | 419 | if(intsource == 13U) { |
| AnnaBridge | 189:f392fc9709a3 | 420 | intsource = (cg_intsrc)3U; |
| AnnaBridge | 189:f392fc9709a3 | 421 | } |
| AnnaBridge | 189:f392fc9709a3 | 422 | p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource)); |
| AnnaBridge | 189:f392fc9709a3 | 423 | *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); |
| AnnaBridge | 189:f392fc9709a3 | 424 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 425 | if(intsource > 13U) { |
| AnnaBridge | 189:f392fc9709a3 | 426 | intsource -= 4; |
| AnnaBridge | 189:f392fc9709a3 | 427 | } else { |
| AnnaBridge | 189:f392fc9709a3 | 428 | intsource -= 3; |
| AnnaBridge | 189:f392fc9709a3 | 429 | } |
| AnnaBridge | 189:f392fc9709a3 | 430 | p_imc = (__IO uint8_t *)(&TSB_IB->IMC066 + (intsource)); |
| AnnaBridge | 189:f392fc9709a3 | 431 | *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); |
| AnnaBridge | 189:f392fc9709a3 | 432 | } |
| AnnaBridge | 189:f392fc9709a3 | 433 | // Dummy read is need |
| AnnaBridge | 189:f392fc9709a3 | 434 | { |
| AnnaBridge | 189:f392fc9709a3 | 435 | __IO uint8_t imc = *p_imc; |
| AnnaBridge | 189:f392fc9709a3 | 436 | } |
| AnnaBridge | 189:f392fc9709a3 | 437 | } |
