mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /* mbed Microcontroller Library |
| AnnaBridge | 189:f392fc9709a3 | 2 | * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved |
| AnnaBridge | 189:f392fc9709a3 | 3 | * |
| AnnaBridge | 189:f392fc9709a3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| AnnaBridge | 189:f392fc9709a3 | 5 | * you may not use this file except in compliance with the License. |
| AnnaBridge | 189:f392fc9709a3 | 6 | * You may obtain a copy of the License at |
| AnnaBridge | 189:f392fc9709a3 | 7 | * |
| AnnaBridge | 189:f392fc9709a3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 9 | * |
| AnnaBridge | 189:f392fc9709a3 | 10 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 189:f392fc9709a3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 189:f392fc9709a3 | 13 | * See the License for the specific language governing permissions and |
| AnnaBridge | 189:f392fc9709a3 | 14 | * limitations under the License. |
| AnnaBridge | 189:f392fc9709a3 | 15 | */ |
| AnnaBridge | 189:f392fc9709a3 | 16 | #ifndef __GPIO_INCLUDE_H |
| AnnaBridge | 189:f392fc9709a3 | 17 | #define __GPIO_INCLUDE_H |
| AnnaBridge | 189:f392fc9709a3 | 18 | |
| AnnaBridge | 189:f392fc9709a3 | 19 | #include <stdint.h> |
| AnnaBridge | 189:f392fc9709a3 | 20 | #include "TMPM3HQ.h" |
| AnnaBridge | 189:f392fc9709a3 | 21 | #include "objects.h" |
| AnnaBridge | 189:f392fc9709a3 | 22 | #include "serial_api.h" |
| AnnaBridge | 189:f392fc9709a3 | 23 | |
| AnnaBridge | 189:f392fc9709a3 | 24 | enum BitMode { |
| AnnaBridge | 189:f392fc9709a3 | 25 | GPIO_PIN_RESET = 0, /* 0: Clear */ |
| AnnaBridge | 189:f392fc9709a3 | 26 | GPIO_PIN_SET, /* 1: Set */ |
| AnnaBridge | 189:f392fc9709a3 | 27 | }; |
| AnnaBridge | 189:f392fc9709a3 | 28 | |
| AnnaBridge | 189:f392fc9709a3 | 29 | enum PortFunction { |
| AnnaBridge | 189:f392fc9709a3 | 30 | GPIO_Mode_DATA = 0x0, /* 0x0: PxDATA */ |
| AnnaBridge | 189:f392fc9709a3 | 31 | GPIO_Mode_CR = 0x04, /* 0x4: PxCR */ |
| AnnaBridge | 189:f392fc9709a3 | 32 | GPIO_Mode_FR1 = 0x08, /* 0x8: PxFR1 */ |
| AnnaBridge | 189:f392fc9709a3 | 33 | GPIO_Mode_FR2 = 0x0C, /* 0xC: PxFR2 */ |
| AnnaBridge | 189:f392fc9709a3 | 34 | GPIO_Mode_FR3 = 0x10, /* 0x10: PxFR3 */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | GPIO_Mode_FR4 = 0x14, /* 0x14: PxFR4 */ |
| AnnaBridge | 189:f392fc9709a3 | 36 | GPIO_Mode_FR5 = 0x18, /* 0x18: PxFR5 */ |
| AnnaBridge | 189:f392fc9709a3 | 37 | GPIO_Mode_FR6 = 0x1C, /* 0x1C: PxFR6 */ |
| AnnaBridge | 189:f392fc9709a3 | 38 | GPIO_Mode_FR7 = 0x20, /* 0x20: PxFR7 */ |
| AnnaBridge | 189:f392fc9709a3 | 39 | GPIO_Mode_OD = 0x28, /* 0x28: PxOD */ |
| AnnaBridge | 189:f392fc9709a3 | 40 | GPIO_Mode_PUP = 0x2C, /* 0x2C: PxPUP */ |
| AnnaBridge | 189:f392fc9709a3 | 41 | GPIO_Mode_PDN = 0x30, /* 0x30: PxPDN */ |
| AnnaBridge | 189:f392fc9709a3 | 42 | GPIO_Mode_IE = 0x38 /* 0x38: PxIE */ |
| AnnaBridge | 189:f392fc9709a3 | 43 | }; |
| AnnaBridge | 189:f392fc9709a3 | 44 | |
| AnnaBridge | 189:f392fc9709a3 | 45 | #define PORT_BASE (0x400C0000UL) /* Port Register Base Adress */ |
| AnnaBridge | 189:f392fc9709a3 | 46 | #define BITBAND_PORT_OFFSET (0x0000100UL) /* Port Register Offset Value */ |
| AnnaBridge | 189:f392fc9709a3 | 47 | #define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) /* Operational target Port Adress */ |
| AnnaBridge | 189:f392fc9709a3 | 48 | #define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /* Operational target Control Register Adress */ |
| AnnaBridge | 189:f392fc9709a3 | 49 | #define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) /* Target Pin Bit set */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | #define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) /* Target Pin Bit clear */ |
| AnnaBridge | 189:f392fc9709a3 | 51 | #define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) /* Target Pin Bit read */ |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /* PWM Macros */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | #define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) |
| AnnaBridge | 189:f392fc9709a3 | 55 | #define T32A_COUNT_DONT_START ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 56 | #define T32A_RUN_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 57 | #define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) |
| AnnaBridge | 189:f392fc9709a3 | 58 | #define T32A_OCR_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 59 | #define T32A_MODE_16 ((uint32_t)0x00000000) /* 16bit Mode */ |
| AnnaBridge | 189:f392fc9709a3 | 60 | #define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /* prescaler */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | #define T32A_WBF_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 62 | #define T32A_WBF_ENABLE ((uint32_t)0x00100000) /* Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 63 | #define T32A_COUNT_UP ((uint32_t)0x00000000) /* count up */ |
| AnnaBridge | 189:f392fc9709a3 | 64 | #define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /* match up Timer Register */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | #define T32A_STOP_NON ((uint32_t)0x00000000) /* No use trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 66 | #define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /* external trigger rising edge */ |
| AnnaBridge | 189:f392fc9709a3 | 67 | #define T32A_OCR_SET ((uint32_t)0x00000001) /* Hi */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | #define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /* Hi */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | #define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /* Hi */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | #define T32A_IMx0_MASK_ALL ((uint32_t)0x0000000F) /* request */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | #define T32A_COUNT_DOWN ((uint32_t)0x00010000) |
| AnnaBridge | 189:f392fc9709a3 | 72 | #define MAX_COUNTER_16B 0xFFFF |
| AnnaBridge | 189:f392fc9709a3 | 73 | #define DEFAULT_CLOCK_DIVISION 32 |
| AnnaBridge | 189:f392fc9709a3 | 74 | #define DEFAULT_PERIOD 0.02f |
| AnnaBridge | 189:f392fc9709a3 | 75 | |
| AnnaBridge | 189:f392fc9709a3 | 76 | /* RTC Configuration Macro */ |
| AnnaBridge | 189:f392fc9709a3 | 77 | #define RTC_24_HOUR_MODE ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 78 | #define PAGER_PAGE_ONE ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 79 | #define PAGER_PAGE_ZERO ((uint8_t)0xEE) |
| AnnaBridge | 189:f392fc9709a3 | 80 | #define RTC_CLK_ENABLE ((uint8_t)0x08) |
| AnnaBridge | 189:f392fc9709a3 | 81 | #define RTC_CLK_DISABLE ((uint8_t)0xE7) |
| AnnaBridge | 189:f392fc9709a3 | 82 | #define RTC_INT_ENABLE ((uint8_t)0x80) |
| AnnaBridge | 189:f392fc9709a3 | 83 | #define RTC_CLEAR_ALL ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 84 | #define RTC_RESET ((uint8_t)0xF7) |
| AnnaBridge | 189:f392fc9709a3 | 85 | #define RTC_INT_SET ((uint8_t)0xFB) |
| AnnaBridge | 189:f392fc9709a3 | 86 | #define RTC_INT_CLR ((uint8_t)0x04) |
| AnnaBridge | 189:f392fc9709a3 | 87 | #define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) |
| AnnaBridge | 189:f392fc9709a3 | 88 | #define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) |
| AnnaBridge | 189:f392fc9709a3 | 89 | #define ELOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define ELOSC_CFG_CLOCK ((uint32_t)(32768)) /* Clock(hz) */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | #define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) /* WUPTL :High Bit Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | #define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) /* WULEF :Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | #define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) /* WULEF :[R] :Done */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) /* WULON :[W] :Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | #define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) /* XTEN :[R/W] :Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | #define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro |
| AnnaBridge | 189:f392fc9709a3 | 97 | #define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro |
| AnnaBridge | 189:f392fc9709a3 | 98 | |
| AnnaBridge | 189:f392fc9709a3 | 99 | /* Serial Macros */ |
| AnnaBridge | 189:f392fc9709a3 | 100 | #define UART0 TSB_UART0 |
| AnnaBridge | 189:f392fc9709a3 | 101 | #define UART1 TSB_UART1 |
| AnnaBridge | 189:f392fc9709a3 | 102 | #define UART2 TSB_UART2 |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define UART3 TSB_UART3 |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define UART4 TSB_UART4 |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define UART5 TSB_UART5 |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define UART_ENABLE_RX ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 107 | #define UART_ENABLE_TX ((uint32_t)0x00000002) |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /* SWRSTF :Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /* SWRSTF :During "Software Reset */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /* SWRST :"10" */ |
| AnnaBridge | 189:f392fc9709a3 | 111 | #define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /* SWRST :"01" */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | #define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /* TFCLR :Clear the transmit buff */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | #define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /* RFCLR :Clear the receive buff */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define UART_PLESCALER_1 ((uint32_t)0x00000000) /* Boudrate Generator prescale 1/1 */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | #define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /* Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | #define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /* Available */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | #define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /* Available */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | #define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) /* 1 stage */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | #define UART_RANGE_K_MIN ((uint32_t)0x00000000) /* Minimum Value :K=0 */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | #define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /* Maximum Value :K=63 */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | #define UART_RANGE_N_MIN ((uint32_t)0x00000001) /* Minimum Value :N=1 */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | #define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /* Maximum Value :N=65535 */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 124 | uint32_t ken; /* Enable/Disable Division Definition */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | uint32_t brk; /* Division Value K */ |
| AnnaBridge | 189:f392fc9709a3 | 126 | uint32_t brn; /* Division Value N */ |
| AnnaBridge | 189:f392fc9709a3 | 127 | } uart_boudrate_t; |
| AnnaBridge | 189:f392fc9709a3 | 128 | /* Sleep Macros */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | #define CG_STBY_MODE_IDLE 0x00 |
| AnnaBridge | 189:f392fc9709a3 | 130 | #define CG_STBY_MODE_STOP1 0x01 |
| AnnaBridge | 189:f392fc9709a3 | 131 | #define EXTERNEL_OSC_MASK 0xFFFFFFF9 |
| AnnaBridge | 189:f392fc9709a3 | 132 | #define IHOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | #define IHOSC_CFG_CLOCK ((uint32_t)(10000000)) /* Clock(hz) */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000) /* WUPT :High Bit Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | #define CGWUPHCR_WUCLK_MASK ((uint32_t)0x00000100) /* WUCLK :Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | #define CGWUPHCR_WUCLK_RW_IHOSC ((uint32_t)0x00000000) /* WUCLK :[R/W] :IHOSC */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | /* SPI macros */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | typedef enum { |
| AnnaBridge | 189:f392fc9709a3 | 140 | SPI_MASTER, |
| AnnaBridge | 189:f392fc9709a3 | 141 | SPI_SLAVE |
| AnnaBridge | 189:f392fc9709a3 | 142 | } spi_mode; |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define IS_SPI_MODULE(param) (((param) == SPI_0) || ((param) == SPI_1)) |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define TSPI_INT_ALL (uint32_t)0xF4 /* All above interrupt control */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /* DR :Mask for 8bit */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | /* TSPI_SW_Reset SW Reset */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define TSPI_RESET10 ((uint32_t)0x00000010) /* RESET Pattarn 10 */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define TSPI_RESET01 ((uint32_t)0x00000001) /* RESET Pattarn 01 */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | /* TSPI_Enable TSPI Enable/Disable Control */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | #define TSPI_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 151 | #define TSPI_ENABLE ((uint32_t)0x00000001) /* Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | /* TSPI_Triger_Control Triger Control */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /* Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define TSPI_SPI_MODE ((uint32_t)0x00000000) /* TSPI MODE */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | #define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /* MASTER MODE */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define TSPI_TWO_WAY ((uint32_t)0x00000C00) /* TWO WAY */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | #define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /* Single Transfer Frame :0 */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | #define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /* Low */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /* Hi */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | #define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 8 */ |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | #define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 166 | #define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | #define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | #define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | /* TSPI_Baudrate_Clock */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /* T16 */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /* 1/3 */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | #define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /* MSB first */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | #define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /* 8 bit */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /* 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /* 1st Edge Sampling */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /* IDLE Term TSPII??SCK LOW */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /* 1 x TSPIIxSCK */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | #define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | #define TSPI_NEGATE_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | /* Format control1 Register */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /* Odd Parity */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /* Clear */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | #define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /* Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 189 | #define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /* TX_REACH_FILL_LEVEL_MASK */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /* Send Data Complete Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | #define TSPI_TX_DONE ((uint32_t)0x00400000) /* Send Data Complete */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | #define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /* Disable MASK */ |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /* Transfer Mode bit MASK */ |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define TSPI_RX_ONLY ((uint32_t)0x00000800) /* RECEIVE ONLY */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /* Receive Data Complete Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define TSPI_RX_DONE ((uint32_t)0x00000040) /* Send Data Complete */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /* TX_REACH_FILL_LEVEL_MASK */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /* Receive Data Complete Flag Clear */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /* Clear */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | /* Ticker Macros */ |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define T32A_MODE_32 ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 203 | #define T32A_PRSCLx_32 ((uint32_t)0x30000000) |
| AnnaBridge | 189:f392fc9709a3 | 204 | #define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) |
| AnnaBridge | 189:f392fc9709a3 | 205 | #define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define T32A_COUNT_STOP ((uint32_t)0x00000004) |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define T32A_COUNT_START ((uint32_t)0x00000002) |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define T32A_RUN_ENABLE ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 209 | |
| AnnaBridge | 189:f392fc9709a3 | 210 | /* I2C Macros */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080) |
| AnnaBridge | 189:f392fc9709a3 | 213 | #define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define I2CxCR2_INIT ((uint32_t)0x00000008) |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) |
| AnnaBridge | 189:f392fc9709a3 | 219 | #define I2CxCR2_TRX ((uint32_t)0x00000040) |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define I2CxST_I2C ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 221 | #define I2CxST_CLEAR ((uint32_t)0x0000000F) |
| AnnaBridge | 189:f392fc9709a3 | 222 | #define I2CxCR1_ACK ((uint32_t)0x00000010) |
| AnnaBridge | 189:f392fc9709a3 | 223 | #define I2CxSR_BB ((uint32_t)0x00000020) |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define I2CxSR_LRB ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define I2CxOP_RSTA ((uint32_t)0x00000008) |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define I2CxOP_SREN ((uint32_t)0x00000002) |
| AnnaBridge | 189:f392fc9709a3 | 227 | #define I2CxOP_MFACK ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 228 | #define I2CxOP_INIT ((uint32_t)0x00000084) |
| AnnaBridge | 189:f392fc9709a3 | 229 | #define I2CxIE_CLEAR ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 230 | #define I2CxPRS_PRCK ((uint32_t)0x0000000F) |
| AnnaBridge | 189:f392fc9709a3 | 231 | #define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) |
| AnnaBridge | 189:f392fc9709a3 | 232 | // Slave Initial Settings. |
| AnnaBridge | 189:f392fc9709a3 | 233 | #define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define I2CAR_SA_MASK ((uint32_t)0x000000FE) |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define I2CxSR_TRX ((uint32_t)0x00000040) |
| AnnaBridge | 189:f392fc9709a3 | 236 | #define I2CxOP_SAST ((uint32_t)0x00000020) |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define I2CxIE_INTI2C ((uint32_t)0x00000001) |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define I2C_NO_DATA (0) |
| AnnaBridge | 189:f392fc9709a3 | 239 | #define I2C_READ_ADDRESSED (1) |
| AnnaBridge | 189:f392fc9709a3 | 240 | #define I2C_WRITE_GENERAL (2) |
| AnnaBridge | 189:f392fc9709a3 | 241 | #define I2C_WRITE_ADDRESSED (3) |
| AnnaBridge | 189:f392fc9709a3 | 242 | #define I2C_ACK (1) |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define I2C_TIMEOUT (100000) |
| AnnaBridge | 189:f392fc9709a3 | 244 | |
| AnnaBridge | 189:f392fc9709a3 | 245 | /* ADC macros */ |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define ADC_12BIT_RANGE 0xFFF |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define ADC_SCLK_1 ((uint32_t)0x00000000) /* SCLK : ADCLK/1 */ |
| AnnaBridge | 189:f392fc9709a3 | 248 | #define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /* RCUT : Normal */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /* DACON : DAC on */ |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /* ENINT :Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 251 | #define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) /* TRGS :Single */ |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /* CNTDMEN :Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /* SGLDMEN :Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 254 | #define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /* TRGDMEN :Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 255 | #define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /* TRGEN :Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 256 | #define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /* ADEN :Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 257 | #define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /* ADEN :Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /* SGL :Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | #define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /* CNT :Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 260 | #define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /* SNGF :Idle */ |
| AnnaBridge | 189:f392fc9709a3 | 261 | #define ADxST_SNGF_RUN ((uint32_t)0x00000004) /* SNGF :Running */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /* ADRFn :Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 263 | #define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /* ADRFn :Flag on */ |
| AnnaBridge | 189:f392fc9709a3 | 264 | #define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /* ADRn :Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define ADC_SAMPLING_PERIOD_3V ((uint32_t)0x00000008) |
| AnnaBridge | 189:f392fc9709a3 | 266 | #define ADC_MOD2_TMPM3Hx ((uint32_t)0x00000300) |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define ADC_MOD1_AVDD5_3V ((uint32_t)0x0000B001) |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | /* RMC Include */ |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define RMC_LI_ENABLE ((uint32_t)0x80000000) /* Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define RMC_EDI_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 272 | #define RMC_LD_DISABLE ((uint32_t)0x00000000) /* Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define RMC_PHM_DISABLE ((uint32_t)0x00000000) /* A remote control signal of the phase system isn't received */ |
| AnnaBridge | 189:f392fc9709a3 | 274 | #define RMC_LL_MAX ((uint32_t)0x00000FF) /* Maximum Value(Disable Receiving End Interrupt) */ |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define RMC_THRESH_HIGH_MIN ((uint32_t)0x0000000) /* Minimum Value */ |
| AnnaBridge | 189:f392fc9709a3 | 276 | #define RMC_POLARITY_POSITIVE ((uint32_t)0x0000000) /* Positive side */ |
| AnnaBridge | 189:f392fc9709a3 | 277 | #define RMC_NOISE_REDUCTION_MIN ((uint32_t)0x0000000) /* Minimum Value */ |
| AnnaBridge | 189:f392fc9709a3 | 278 | #define RMC_RX_DATA_BITS_MIN ((uint32_t)0x0000000) /* Minimum Value */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | #define RMC_CLK_LOW_SPEED ((uint32_t)0x00000000) /* Low speed clock(32.768kHz) */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define RMC_CYCLE_MAX_INT_OCCUR ((uint32_t)0x00002000) /* It occurs */ |
| AnnaBridge | 189:f392fc9709a3 | 281 | #define RMC_LEADER_DETECT ((uint32_t)0x00000080) /* It detests */ |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define RMC_RX_BIT_NUM_MASK ((uint32_t)0x0000007F) /* Mask */ |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define RMCxEN_RMCEN_ENABLE ((uint32_t)0x00000001) /* RMCEN : Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 284 | |
| AnnaBridge | 189:f392fc9709a3 | 285 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 286 | uint32_t lcMax; /* Upper limit in a cycle period of leader detection */ |
| AnnaBridge | 189:f392fc9709a3 | 287 | uint32_t lcMin; /* Lower limit in a cycle period of leader detection */ |
| AnnaBridge | 189:f392fc9709a3 | 288 | uint32_t llMax; /* Upper limit in a low period of leader detection */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | uint32_t llMin; /* Lower limit in a low period of leader detection */ |
| AnnaBridge | 189:f392fc9709a3 | 290 | } rmc_control1_t; |
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 293 | uint32_t lien; /* Enable a leader detection interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | uint32_t edien; /* Enable a remote control input falling edge interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 295 | uint32_t cld; /* Enable a receive mode, that receives both remote control signals without leaders and with leaders */ |
| AnnaBridge | 189:f392fc9709a3 | 296 | uint32_t phim; /* Setting of a remote control reception mode of the phase system */ |
| AnnaBridge | 189:f392fc9709a3 | 297 | uint32_t ll; /* Setting at the timing of a "Receiving End Interrupt" by detection Low */ |
| AnnaBridge | 189:f392fc9709a3 | 298 | uint32_t dmax; /* Setting at the timing of a "Receiving End Interrupt" by the cycle of the data bit */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | } rmc_control2_t; |
| AnnaBridge | 189:f392fc9709a3 | 300 | |
| AnnaBridge | 189:f392fc9709a3 | 301 | /* Receive Control Setting "3" */ |
| AnnaBridge | 189:f392fc9709a3 | 302 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 303 | uint32_t dath; /* Threshold value high setting of 3 price judgement of a Data bit */ |
| AnnaBridge | 189:f392fc9709a3 | 304 | uint32_t datl; /* Threshold value low setting of 3 price judgement of a Data bit */ |
| AnnaBridge | 189:f392fc9709a3 | 305 | } rmc_control3_t; |
| AnnaBridge | 189:f392fc9709a3 | 306 | |
| AnnaBridge | 189:f392fc9709a3 | 307 | /* Receive Control Setting "4" */ |
| AnnaBridge | 189:f392fc9709a3 | 308 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 309 | uint32_t po; /* Polarity choice of a remote control input signal */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | uint32_t nc; /* Setting of noise reduction time */ |
| AnnaBridge | 189:f392fc9709a3 | 311 | } rmc_control4_t; |
| AnnaBridge | 189:f392fc9709a3 | 312 | |
| AnnaBridge | 189:f392fc9709a3 | 313 | /* Num of received end bit "1" */ |
| AnnaBridge | 189:f392fc9709a3 | 314 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 315 | uint32_t end1; /* Num of received data bits */ |
| AnnaBridge | 189:f392fc9709a3 | 316 | } rmc_end1_t; |
| AnnaBridge | 189:f392fc9709a3 | 317 | |
| AnnaBridge | 189:f392fc9709a3 | 318 | /* Num of received end bit "2" */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 320 | uint32_t end2; /* Num of received data bits */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | } rmc_end2_t; |
| AnnaBridge | 189:f392fc9709a3 | 322 | |
| AnnaBridge | 189:f392fc9709a3 | 323 | /* Num of received end bit "3" */ |
| AnnaBridge | 189:f392fc9709a3 | 324 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 325 | uint32_t end3; /* Num of received data bits */ |
| AnnaBridge | 189:f392fc9709a3 | 326 | } rmc_end3_t; |
| AnnaBridge | 189:f392fc9709a3 | 327 | |
| AnnaBridge | 189:f392fc9709a3 | 328 | /* Select source clock */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 330 | uint32_t clk; /* Select RMC sampling clock */ |
| AnnaBridge | 189:f392fc9709a3 | 331 | } rmc_fssel_t; |
| AnnaBridge | 189:f392fc9709a3 | 332 | |
| AnnaBridge | 189:f392fc9709a3 | 333 | /* Initial setting structure definition */ |
| AnnaBridge | 189:f392fc9709a3 | 334 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 335 | rmc_control1_t cnt1; /* Receive Control Setting "1" */ |
| AnnaBridge | 189:f392fc9709a3 | 336 | rmc_control2_t cnt2; /* Receive Control Setting "2" */ |
| AnnaBridge | 189:f392fc9709a3 | 337 | rmc_control3_t cnt3; /* Receive Control Setting "3" */ |
| AnnaBridge | 189:f392fc9709a3 | 338 | rmc_control4_t cnt4; /* Control4 setting */ |
| AnnaBridge | 189:f392fc9709a3 | 339 | rmc_end1_t end1; /* Receive End Bit1 setting */ |
| AnnaBridge | 189:f392fc9709a3 | 340 | rmc_end2_t end2; /* Receive End Bit2 setting */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | rmc_end3_t end3; /* Receive End Bit3 setting */ |
| AnnaBridge | 189:f392fc9709a3 | 342 | rmc_fssel_t fssel; /* Select source clock */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | } rmc_initial_setting_t; |
| AnnaBridge | 189:f392fc9709a3 | 344 | |
| AnnaBridge | 189:f392fc9709a3 | 345 | /* RMC handle structure definition */ |
| AnnaBridge | 189:f392fc9709a3 | 346 | typedef struct uart_handle { |
| AnnaBridge | 189:f392fc9709a3 | 347 | TSB_RMC_TypeDef *p_instance; /* Registers base address */ |
| AnnaBridge | 189:f392fc9709a3 | 348 | rmc_initial_setting_t init; /* Initial setting */ |
| AnnaBridge | 189:f392fc9709a3 | 349 | } rmc_t; |
| AnnaBridge | 189:f392fc9709a3 | 350 | |
| AnnaBridge | 189:f392fc9709a3 | 351 | void rmc_init(rmc_t *p_obj); |
| AnnaBridge | 189:f392fc9709a3 | 352 | void rmc_get_data(rmc_t *p_obj, uint32_t data[]); |
| AnnaBridge | 189:f392fc9709a3 | 353 | |
| AnnaBridge | 189:f392fc9709a3 | 354 | |
| AnnaBridge | 189:f392fc9709a3 | 355 | #endif /* __GPIO_INCLUDE_H */ |
