mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_TOSHIBA/TARGET_TMPM4G9/spi_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 188:bcfe06ba3d64 1 /* mbed Microcontroller Library
AnnaBridge 188:bcfe06ba3d64 2 * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
AnnaBridge 188:bcfe06ba3d64 3 *
AnnaBridge 188:bcfe06ba3d64 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 188:bcfe06ba3d64 5 * you may not use this file except in compliance with the License.
AnnaBridge 188:bcfe06ba3d64 6 * You may obtain a copy of the License at
AnnaBridge 188:bcfe06ba3d64 7 *
AnnaBridge 188:bcfe06ba3d64 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 188:bcfe06ba3d64 9 *
AnnaBridge 188:bcfe06ba3d64 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 188:bcfe06ba3d64 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 188:bcfe06ba3d64 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 188:bcfe06ba3d64 13 * See the License for the specific language governing permissions and
AnnaBridge 188:bcfe06ba3d64 14 * limitations under the License.
AnnaBridge 188:bcfe06ba3d64 15 */
AnnaBridge 188:bcfe06ba3d64 16 #include "spi_api.h"
AnnaBridge 188:bcfe06ba3d64 17 #include "mbed_error.h"
AnnaBridge 188:bcfe06ba3d64 18 #include "txz_tspi.h"
AnnaBridge 188:bcfe06ba3d64 19 #include "pinmap.h"
AnnaBridge 188:bcfe06ba3d64 20
AnnaBridge 188:bcfe06ba3d64 21 #define TIMEOUT (5000)
AnnaBridge 188:bcfe06ba3d64 22 #define BAUDRATE_1MHZ_BRS (0x0A)
AnnaBridge 188:bcfe06ba3d64 23 #define BAUDRATE_1MHZ_BRCK (0x30)
AnnaBridge 188:bcfe06ba3d64 24
AnnaBridge 188:bcfe06ba3d64 25 static const PinMap PinMap_SPI_SCLK[] = {
AnnaBridge 188:bcfe06ba3d64 26 {PA1, SPI_0, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 27 {PL1, SPI_1, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 28 {PA6, SPI_2, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 29 {PK6, SPI_3, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 30 {PD1, SPI_4, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 31 {PV6, SPI_5, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 32 {PM2, SPI_6, PIN_DATA(6, 1)},
AnnaBridge 188:bcfe06ba3d64 33 {PM5, SPI_7, PIN_DATA(6, 1)},
AnnaBridge 188:bcfe06ba3d64 34 {PW1, SPI_8, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 35 {NC, NC, 0}
AnnaBridge 188:bcfe06ba3d64 36 };
AnnaBridge 188:bcfe06ba3d64 37
AnnaBridge 188:bcfe06ba3d64 38 static const PinMap PinMap_SPI_MOSI[] = {
AnnaBridge 188:bcfe06ba3d64 39 {PA3, SPI_0, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 40 {PL3, SPI_1, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 41 {PA4, SPI_2, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 42 {PK4, SPI_3, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 43 {PD3, SPI_4, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 44 {PV5, SPI_5, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 45 {PM0, SPI_6, PIN_DATA(6, 1)},
AnnaBridge 188:bcfe06ba3d64 46 {PM7, SPI_7, PIN_DATA(6, 1)},
AnnaBridge 188:bcfe06ba3d64 47 {PW3, SPI_8, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 48 {NC, NC, 0}
AnnaBridge 188:bcfe06ba3d64 49 };
AnnaBridge 188:bcfe06ba3d64 50
AnnaBridge 188:bcfe06ba3d64 51 static const PinMap PinMap_SPI_MISO[] = {
AnnaBridge 188:bcfe06ba3d64 52 {PA2, SPI_0, PIN_DATA(7, 0)},
AnnaBridge 188:bcfe06ba3d64 53 {PL2, SPI_1, PIN_DATA(7, 0)},
AnnaBridge 188:bcfe06ba3d64 54 {PA5, SPI_2, PIN_DATA(7, 0)},
AnnaBridge 188:bcfe06ba3d64 55 {PK5, SPI_3, PIN_DATA(4, 0)},
AnnaBridge 188:bcfe06ba3d64 56 {PD2, SPI_4, PIN_DATA(4, 0)},
AnnaBridge 188:bcfe06ba3d64 57 {PV4, SPI_5, PIN_DATA(4, 0)},
AnnaBridge 188:bcfe06ba3d64 58 {PM1, SPI_6, PIN_DATA(6, 0)},
AnnaBridge 188:bcfe06ba3d64 59 {PM6, SPI_7, PIN_DATA(6, 0)},
AnnaBridge 188:bcfe06ba3d64 60 {PW2, SPI_8, PIN_DATA(4, 0)},
AnnaBridge 188:bcfe06ba3d64 61 {NC, NC, 0}
AnnaBridge 188:bcfe06ba3d64 62 };
AnnaBridge 188:bcfe06ba3d64 63
AnnaBridge 188:bcfe06ba3d64 64 static const PinMap PinMap_SPI_SSEL[] = {
AnnaBridge 188:bcfe06ba3d64 65 {PA0, SPI_0, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 66 {PL0, SPI_1, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 67 {PA7, SPI_2, PIN_DATA(7, 1)},
AnnaBridge 188:bcfe06ba3d64 68 {PK7, SPI_3, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 69 {PD0, SPI_4, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 70 {PV7, SPI_5, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 71 {PM3, SPI_6, PIN_DATA(6, 1)},
AnnaBridge 188:bcfe06ba3d64 72 {PM4, SPI_7, PIN_DATA(6, 1)},
AnnaBridge 188:bcfe06ba3d64 73 {PW0, SPI_8, PIN_DATA(4, 1)},
AnnaBridge 188:bcfe06ba3d64 74 {NC, NC, 0}
AnnaBridge 188:bcfe06ba3d64 75 };
AnnaBridge 188:bcfe06ba3d64 76 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
AnnaBridge 188:bcfe06ba3d64 77 {
AnnaBridge 188:bcfe06ba3d64 78 // Check pin parameters
AnnaBridge 188:bcfe06ba3d64 79 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
AnnaBridge 188:bcfe06ba3d64 80 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
AnnaBridge 188:bcfe06ba3d64 81 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
AnnaBridge 188:bcfe06ba3d64 82 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
AnnaBridge 188:bcfe06ba3d64 83 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
AnnaBridge 188:bcfe06ba3d64 84 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
AnnaBridge 188:bcfe06ba3d64 85
AnnaBridge 188:bcfe06ba3d64 86 obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk);
AnnaBridge 188:bcfe06ba3d64 87 obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl);
AnnaBridge 188:bcfe06ba3d64 88 MBED_ASSERT((int)obj->module!= NC);
AnnaBridge 188:bcfe06ba3d64 89
AnnaBridge 188:bcfe06ba3d64 90 // Identify SPI module to use
AnnaBridge 188:bcfe06ba3d64 91 switch ((int)obj->module) {
AnnaBridge 188:bcfe06ba3d64 92 case SPI_0:
AnnaBridge 188:bcfe06ba3d64 93 obj->p_obj.p_instance = TSB_TSPI0;
AnnaBridge 188:bcfe06ba3d64 94 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 95 TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 96 TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 97 break;
AnnaBridge 188:bcfe06ba3d64 98 case SPI_1:
AnnaBridge 188:bcfe06ba3d64 99 obj->p_obj.p_instance = TSB_TSPI1;
AnnaBridge 188:bcfe06ba3d64 100 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 101 TSB_CG_FSYSENA_IPENA05 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 102 TSB_CG_FSYSMENB_IPMENB12 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 103 break;
AnnaBridge 188:bcfe06ba3d64 104 case SPI_2:
AnnaBridge 188:bcfe06ba3d64 105 obj->p_obj.p_instance = TSB_TSPI2;
AnnaBridge 188:bcfe06ba3d64 106 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 107 TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 108 TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 109 break;
AnnaBridge 188:bcfe06ba3d64 110 case SPI_3:
AnnaBridge 188:bcfe06ba3d64 111 obj->p_obj.p_instance = TSB_TSPI3;
AnnaBridge 188:bcfe06ba3d64 112 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 113 TSB_CG_FSYSENA_IPENA07 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 114 TSB_CG_FSYSMENB_IPMENB11 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 115 break;
AnnaBridge 188:bcfe06ba3d64 116 case SPI_4:
AnnaBridge 188:bcfe06ba3d64 117 obj->p_obj.p_instance = TSB_TSPI4;
AnnaBridge 188:bcfe06ba3d64 118 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 119 TSB_CG_FSYSENA_IPENA08 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 120 TSB_CG_FSYSMENB_IPMENB05 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 121 break;
AnnaBridge 188:bcfe06ba3d64 122 case SPI_5:
AnnaBridge 188:bcfe06ba3d64 123 obj->p_obj.p_instance = TSB_TSPI5;
AnnaBridge 188:bcfe06ba3d64 124 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 125 TSB_CG_FSYSENA_IPENA09 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 126 TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 127 break;
AnnaBridge 188:bcfe06ba3d64 128 case SPI_6:
AnnaBridge 188:bcfe06ba3d64 129 obj->p_obj.p_instance = TSB_TSPI6;
AnnaBridge 188:bcfe06ba3d64 130 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 131 TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 132 TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 133 break;
AnnaBridge 188:bcfe06ba3d64 134 case SPI_7:
AnnaBridge 188:bcfe06ba3d64 135 obj->p_obj.p_instance = TSB_TSPI7;
AnnaBridge 188:bcfe06ba3d64 136 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 137 TSB_CG_FSYSMENA_IPMENA21 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 138 TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 139 break;
AnnaBridge 188:bcfe06ba3d64 140 case SPI_8:
AnnaBridge 188:bcfe06ba3d64 141 obj->p_obj.p_instance = TSB_TSPI8;
AnnaBridge 188:bcfe06ba3d64 142 // Enable clock for particular Port and SPI
AnnaBridge 188:bcfe06ba3d64 143 TSB_CG_FSYSMENA_IPMENA22 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 144 TSB_CG_FSYSMENB_IPMENB20 = TXZ_ENABLE;
AnnaBridge 188:bcfe06ba3d64 145 break;
AnnaBridge 188:bcfe06ba3d64 146 default:
AnnaBridge 188:bcfe06ba3d64 147 obj->p_obj.p_instance = NULL;
AnnaBridge 188:bcfe06ba3d64 148 obj->module = (SPIName)NC;
AnnaBridge 188:bcfe06ba3d64 149 error("Cannot found SPI module corresponding with input pins.");
AnnaBridge 188:bcfe06ba3d64 150 break;
AnnaBridge 188:bcfe06ba3d64 151 }
AnnaBridge 188:bcfe06ba3d64 152
AnnaBridge 188:bcfe06ba3d64 153 // Pin out the spi pins
AnnaBridge 188:bcfe06ba3d64 154 pinmap_pinout(mosi, PinMap_SPI_MOSI);
AnnaBridge 188:bcfe06ba3d64 155 pinmap_pinout(miso, PinMap_SPI_MISO);
AnnaBridge 188:bcfe06ba3d64 156 pinmap_pinout(sclk, PinMap_SPI_SCLK);
AnnaBridge 188:bcfe06ba3d64 157
AnnaBridge 188:bcfe06ba3d64 158 if (ssel != NC) {
AnnaBridge 188:bcfe06ba3d64 159 pinmap_pinout(ssel, PinMap_SPI_SSEL);
AnnaBridge 188:bcfe06ba3d64 160 }
AnnaBridge 188:bcfe06ba3d64 161
AnnaBridge 188:bcfe06ba3d64 162 // Default configurations 8 bit, 1Mhz frequency
AnnaBridge 188:bcfe06ba3d64 163 // Control 1 configurations
AnnaBridge 188:bcfe06ba3d64 164 obj->p_obj.init.id = (uint32_t)obj->module;
AnnaBridge 188:bcfe06ba3d64 165 obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled
AnnaBridge 188:bcfe06ba3d64 166 obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication
AnnaBridge 188:bcfe06ba3d64 167 obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode
AnnaBridge 188:bcfe06ba3d64 168 obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // Master mode operation
AnnaBridge 188:bcfe06ba3d64 169 obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive)
AnnaBridge 188:bcfe06ba3d64 170 obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid
AnnaBridge 188:bcfe06ba3d64 171 obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // Transfer single frame at a time contineously
AnnaBridge 188:bcfe06ba3d64 172
AnnaBridge 188:bcfe06ba3d64 173 // Control 2 configurations
AnnaBridge 188:bcfe06ba3d64 174 obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI;
AnnaBridge 188:bcfe06ba3d64 175 obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // When slave underruns TxD fixed to low
AnnaBridge 188:bcfe06ba3d64 176 obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_SET;
AnnaBridge 188:bcfe06ba3d64 177 obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // Transmit FIFO Level
AnnaBridge 188:bcfe06ba3d64 178 obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // Receive FIFO Level
AnnaBridge 188:bcfe06ba3d64 179 obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE;
AnnaBridge 188:bcfe06ba3d64 180 obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE;
AnnaBridge 188:bcfe06ba3d64 181 obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE;
AnnaBridge 188:bcfe06ba3d64 182 obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE;
AnnaBridge 188:bcfe06ba3d64 183 obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE;
AnnaBridge 188:bcfe06ba3d64 184 obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE;
AnnaBridge 188:bcfe06ba3d64 185 obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE;
AnnaBridge 188:bcfe06ba3d64 186
AnnaBridge 188:bcfe06ba3d64 187 // Control 3 configurations
AnnaBridge 188:bcfe06ba3d64 188 obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // Transmit buffer clear
AnnaBridge 188:bcfe06ba3d64 189 obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // Receive buffer clear
AnnaBridge 188:bcfe06ba3d64 190
AnnaBridge 188:bcfe06ba3d64 191 // Baudrate settings - 1 Mhz default
AnnaBridge 188:bcfe06ba3d64 192 obj->p_obj.init.brd.brck = BAUDRATE_1MHZ_BRCK;
AnnaBridge 188:bcfe06ba3d64 193 obj->p_obj.init.brd.brs = BAUDRATE_1MHZ_BRS;
AnnaBridge 188:bcfe06ba3d64 194
AnnaBridge 188:bcfe06ba3d64 195 // Format Control 0 settings
AnnaBridge 188:bcfe06ba3d64 196 obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first
AnnaBridge 188:bcfe06ba3d64 197 obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8;
AnnaBridge 188:bcfe06ba3d64 198 obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0;
AnnaBridge 188:bcfe06ba3d64 199
AnnaBridge 188:bcfe06ba3d64 200 // Special control on polarity of signal and generation timing
AnnaBridge 188:bcfe06ba3d64 201 obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE;
AnnaBridge 188:bcfe06ba3d64 202 obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE;
AnnaBridge 188:bcfe06ba3d64 203 obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE;
AnnaBridge 188:bcfe06ba3d64 204 obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE;
AnnaBridge 188:bcfe06ba3d64 205 obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
AnnaBridge 188:bcfe06ba3d64 206 obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
AnnaBridge 188:bcfe06ba3d64 207 obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1;
AnnaBridge 188:bcfe06ba3d64 208
AnnaBridge 188:bcfe06ba3d64 209 obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1;
AnnaBridge 188:bcfe06ba3d64 210 obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1;
AnnaBridge 188:bcfe06ba3d64 211
AnnaBridge 188:bcfe06ba3d64 212 // Format Control 1 settings tspi_fmtr1_t
AnnaBridge 188:bcfe06ba3d64 213 obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE;
AnnaBridge 188:bcfe06ba3d64 214 obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD;
AnnaBridge 188:bcfe06ba3d64 215
AnnaBridge 188:bcfe06ba3d64 216 obj->bits = (uint8_t)TSPI_DATA_LENGTH_8;
AnnaBridge 188:bcfe06ba3d64 217
AnnaBridge 188:bcfe06ba3d64 218 // Initialize SPI
AnnaBridge 188:bcfe06ba3d64 219 tspi_init(&obj->p_obj);
AnnaBridge 188:bcfe06ba3d64 220 }
AnnaBridge 188:bcfe06ba3d64 221
AnnaBridge 188:bcfe06ba3d64 222 void spi_free(spi_t *obj)
AnnaBridge 188:bcfe06ba3d64 223 {
AnnaBridge 188:bcfe06ba3d64 224 tspi_deinit(&obj->p_obj);
AnnaBridge 188:bcfe06ba3d64 225 obj->module = (SPIName)NC;
AnnaBridge 188:bcfe06ba3d64 226 }
AnnaBridge 188:bcfe06ba3d64 227
AnnaBridge 188:bcfe06ba3d64 228 void spi_format(spi_t *obj, int bits, int mode, int slave)
AnnaBridge 188:bcfe06ba3d64 229 {
AnnaBridge 188:bcfe06ba3d64 230 MBED_ASSERT((slave == 0U)); // 0: master mode, 1: slave mode
AnnaBridge 188:bcfe06ba3d64 231 MBED_ASSERT((bits >= 8) && (bits <= 32));
AnnaBridge 188:bcfe06ba3d64 232
AnnaBridge 188:bcfe06ba3d64 233 obj->bits = bits;
AnnaBridge 188:bcfe06ba3d64 234 obj->p_obj.init.fmr0.fl = (bits << 24);
AnnaBridge 188:bcfe06ba3d64 235
AnnaBridge 188:bcfe06ba3d64 236 if ((mode >> 1) & 0x1) {
AnnaBridge 188:bcfe06ba3d64 237 obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI;
AnnaBridge 188:bcfe06ba3d64 238 } else {
AnnaBridge 188:bcfe06ba3d64 239 obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
AnnaBridge 188:bcfe06ba3d64 240 }
AnnaBridge 188:bcfe06ba3d64 241
AnnaBridge 188:bcfe06ba3d64 242 if (mode & 0x1) {
AnnaBridge 188:bcfe06ba3d64 243 obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE;
AnnaBridge 188:bcfe06ba3d64 244 } else {
AnnaBridge 188:bcfe06ba3d64 245 obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
AnnaBridge 188:bcfe06ba3d64 246 }
AnnaBridge 188:bcfe06ba3d64 247
AnnaBridge 188:bcfe06ba3d64 248 tspi_init(&obj->p_obj);
AnnaBridge 188:bcfe06ba3d64 249 }
AnnaBridge 188:bcfe06ba3d64 250
AnnaBridge 188:bcfe06ba3d64 251 void spi_frequency(spi_t *obj, int hz)
AnnaBridge 188:bcfe06ba3d64 252 {
AnnaBridge 188:bcfe06ba3d64 253 SystemCoreClockUpdate();
AnnaBridge 188:bcfe06ba3d64 254 uint8_t brs = 0;
AnnaBridge 188:bcfe06ba3d64 255 uint8_t brck = 0;
AnnaBridge 188:bcfe06ba3d64 256 uint16_t prsck = 1;
AnnaBridge 188:bcfe06ba3d64 257 uint64_t fscl = 0;
AnnaBridge 188:bcfe06ba3d64 258 uint64_t tmp_fscl = 0;
AnnaBridge 188:bcfe06ba3d64 259 uint64_t fx = 0;
AnnaBridge 188:bcfe06ba3d64 260 uint64_t tmpvar = SystemCoreClock / 2;
AnnaBridge 188:bcfe06ba3d64 261
AnnaBridge 188:bcfe06ba3d64 262 for (prsck = 1; prsck <= 512; prsck *= 2) {
AnnaBridge 188:bcfe06ba3d64 263 fx = ((uint64_t)tmpvar / prsck);
AnnaBridge 188:bcfe06ba3d64 264 for (brs = 1; brs <= 16; brs++) {
AnnaBridge 188:bcfe06ba3d64 265 fscl = fx /brs;
AnnaBridge 188:bcfe06ba3d64 266 if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
AnnaBridge 188:bcfe06ba3d64 267 tmp_fscl = fscl;
AnnaBridge 188:bcfe06ba3d64 268 obj->p_obj.init.brd.brck = (brck << 4);
AnnaBridge 188:bcfe06ba3d64 269 if (brs == 16) {
AnnaBridge 188:bcfe06ba3d64 270 obj->p_obj.init.brd.brs = 0;
AnnaBridge 188:bcfe06ba3d64 271 } else {
AnnaBridge 188:bcfe06ba3d64 272 obj->p_obj.init.brd.brs = brs;
AnnaBridge 188:bcfe06ba3d64 273 }
AnnaBridge 188:bcfe06ba3d64 274 }
AnnaBridge 188:bcfe06ba3d64 275 }
AnnaBridge 188:bcfe06ba3d64 276 brck ++;
AnnaBridge 188:bcfe06ba3d64 277 }
AnnaBridge 188:bcfe06ba3d64 278
AnnaBridge 188:bcfe06ba3d64 279 tspi_init(&obj->p_obj);
AnnaBridge 188:bcfe06ba3d64 280 }
AnnaBridge 188:bcfe06ba3d64 281
AnnaBridge 188:bcfe06ba3d64 282 int spi_master_write(spi_t *obj, int value)
AnnaBridge 188:bcfe06ba3d64 283 {
AnnaBridge 188:bcfe06ba3d64 284 uint8_t ret_value = 0;
AnnaBridge 188:bcfe06ba3d64 285
AnnaBridge 188:bcfe06ba3d64 286 tspi_transmit_t send_obj;
AnnaBridge 188:bcfe06ba3d64 287 tspi_receive_t rec_obj;
AnnaBridge 188:bcfe06ba3d64 288
AnnaBridge 188:bcfe06ba3d64 289 // Transmit data
AnnaBridge 188:bcfe06ba3d64 290 send_obj.tx8.p_data = (uint8_t *)&value;
AnnaBridge 188:bcfe06ba3d64 291 send_obj.tx8.num = 1;
AnnaBridge 188:bcfe06ba3d64 292 tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT);
AnnaBridge 188:bcfe06ba3d64 293
AnnaBridge 188:bcfe06ba3d64 294 // Read received data
AnnaBridge 188:bcfe06ba3d64 295 rec_obj.rx8.p_data = &ret_value;
AnnaBridge 188:bcfe06ba3d64 296 rec_obj.rx8.num = 1;
AnnaBridge 188:bcfe06ba3d64 297 tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT);
AnnaBridge 188:bcfe06ba3d64 298
AnnaBridge 188:bcfe06ba3d64 299 return ret_value;
AnnaBridge 188:bcfe06ba3d64 300 }
AnnaBridge 188:bcfe06ba3d64 301
AnnaBridge 188:bcfe06ba3d64 302 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
AnnaBridge 188:bcfe06ba3d64 303 char *rx_buffer, int rx_length, char write_fill)
AnnaBridge 188:bcfe06ba3d64 304 {
AnnaBridge 188:bcfe06ba3d64 305 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 188:bcfe06ba3d64 306
AnnaBridge 188:bcfe06ba3d64 307 for (int i = 0; i < total; i++) {
AnnaBridge 188:bcfe06ba3d64 308 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 188:bcfe06ba3d64 309 char in = spi_master_write(obj, out);
AnnaBridge 188:bcfe06ba3d64 310 if (i < rx_length) {
AnnaBridge 188:bcfe06ba3d64 311 rx_buffer[i] = in;
AnnaBridge 188:bcfe06ba3d64 312 }
AnnaBridge 188:bcfe06ba3d64 313 }
AnnaBridge 188:bcfe06ba3d64 314
AnnaBridge 188:bcfe06ba3d64 315 return total;
AnnaBridge 188:bcfe06ba3d64 316 }
AnnaBridge 188:bcfe06ba3d64 317
AnnaBridge 188:bcfe06ba3d64 318 int spi_busy(spi_t *obj)
AnnaBridge 188:bcfe06ba3d64 319 {
AnnaBridge 188:bcfe06ba3d64 320 int ret = 1;
AnnaBridge 188:bcfe06ba3d64 321 uint32_t status = 0;
AnnaBridge 188:bcfe06ba3d64 322
AnnaBridge 188:bcfe06ba3d64 323 tspi_get_status(&obj->p_obj, &status);
AnnaBridge 188:bcfe06ba3d64 324
AnnaBridge 188:bcfe06ba3d64 325 if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) {
AnnaBridge 188:bcfe06ba3d64 326 ret = 0;
AnnaBridge 188:bcfe06ba3d64 327 }
AnnaBridge 188:bcfe06ba3d64 328
AnnaBridge 188:bcfe06ba3d64 329 return ret;
AnnaBridge 188:bcfe06ba3d64 330 }
AnnaBridge 188:bcfe06ba3d64 331
AnnaBridge 188:bcfe06ba3d64 332 uint8_t spi_get_module(spi_t *obj)
AnnaBridge 188:bcfe06ba3d64 333 {
AnnaBridge 188:bcfe06ba3d64 334 return (uint8_t)(obj->module);
AnnaBridge 188:bcfe06ba3d64 335 }