mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
172:7d866c31b3c5 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /* mbed Microcontroller Library
AnnaBridge 172:7d866c31b3c5 2 * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
AnnaBridge 172:7d866c31b3c5 3 *
AnnaBridge 172:7d866c31b3c5 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 172:7d866c31b3c5 5 * you may not use this file except in compliance with the License.
AnnaBridge 172:7d866c31b3c5 6 * You may obtain a copy of the License at
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:7d866c31b3c5 9 *
AnnaBridge 172:7d866c31b3c5 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:7d866c31b3c5 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 172:7d866c31b3c5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:7d866c31b3c5 13 * See the License for the specific language governing permissions and
AnnaBridge 172:7d866c31b3c5 14 * limitations under the License.
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16 #include "gpio_irq_api.h"
AnnaBridge 172:7d866c31b3c5 17 #include "mbed_error.h"
AnnaBridge 172:7d866c31b3c5 18 #include "PeripheralNames.h"
AnnaBridge 172:7d866c31b3c5 19 #include "pinmap.h"
AnnaBridge 172:7d866c31b3c5 20 #include "mbed_critical.h"
AnnaBridge 172:7d866c31b3c5 21
AnnaBridge 172:7d866c31b3c5 22 #define CHANNEL_NUM 6
AnnaBridge 172:7d866c31b3c5 23
AnnaBridge 172:7d866c31b3c5 24 const PinMap PinMap_GPIO_IRQ[] = {
AnnaBridge 172:7d866c31b3c5 25 {PD5, GPIO_IRQ_0, PIN_DATA(0, 0)},
AnnaBridge 172:7d866c31b3c5 26 {PA5, GPIO_IRQ_1, PIN_DATA(0, 0)},
AnnaBridge 172:7d866c31b3c5 27 {PA6, GPIO_IRQ_2, PIN_DATA(0, 0)},
AnnaBridge 172:7d866c31b3c5 28 {PF1, GPIO_IRQ_3, PIN_DATA(0, 0)},
AnnaBridge 172:7d866c31b3c5 29 {PC5, GPIO_IRQ_4, PIN_DATA(0, 0)},
AnnaBridge 172:7d866c31b3c5 30 {PF0, GPIO_IRQ_5, PIN_DATA(0, 0)},
AnnaBridge 172:7d866c31b3c5 31 {NC, NC, 0}
AnnaBridge 172:7d866c31b3c5 32 };
AnnaBridge 172:7d866c31b3c5 33
AnnaBridge 172:7d866c31b3c5 34 static uint32_t channel_ids[CHANNEL_NUM] = {0};
AnnaBridge 172:7d866c31b3c5 35 static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
AnnaBridge 172:7d866c31b3c5 36
AnnaBridge 172:7d866c31b3c5 37 static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index)
AnnaBridge 172:7d866c31b3c5 38 {
AnnaBridge 172:7d866c31b3c5 39 uint32_t val;
AnnaBridge 172:7d866c31b3c5 40 GPIO_Port port;
AnnaBridge 172:7d866c31b3c5 41 uint32_t mask;
AnnaBridge 172:7d866c31b3c5 42 INTIFAO_INTActiveState ActiveState;
AnnaBridge 172:7d866c31b3c5 43 port = (GPIO_Port)(pin >> 3);
AnnaBridge 172:7d866c31b3c5 44 mask = 0x01 << (pin & 0x07);
AnnaBridge 172:7d866c31b3c5 45 // Clear interrupt request
AnnaBridge 172:7d866c31b3c5 46 INTIFAO_ClearINTReq((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index));
AnnaBridge 172:7d866c31b3c5 47 // Clear gpio pending interrupt
AnnaBridge 172:7d866c31b3c5 48 NVIC_ClearPendingIRQ((IRQn_Type)irq_id);
AnnaBridge 172:7d866c31b3c5 49 ActiveState = INTIFAO_GetSTBYReleaseINTState((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index));
AnnaBridge 172:7d866c31b3c5 50 INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index),
AnnaBridge 172:7d866c31b3c5 51 ActiveState, DISABLE);
AnnaBridge 172:7d866c31b3c5 52 // Get pin value
AnnaBridge 172:7d866c31b3c5 53 val = GPIO_ReadDataBit(port, mask);
AnnaBridge 172:7d866c31b3c5 54 switch (val) {
AnnaBridge 172:7d866c31b3c5 55 // Falling edge detection
AnnaBridge 172:7d866c31b3c5 56 case 0:
AnnaBridge 172:7d866c31b3c5 57 hal_irq_handler[index](channel_ids[index], IRQ_FALL);
AnnaBridge 172:7d866c31b3c5 58 break;
AnnaBridge 172:7d866c31b3c5 59 // Rising edge detection
AnnaBridge 172:7d866c31b3c5 60 case 1:
AnnaBridge 172:7d866c31b3c5 61 hal_irq_handler[index](channel_ids[index], IRQ_RISE);
AnnaBridge 172:7d866c31b3c5 62 break;
AnnaBridge 172:7d866c31b3c5 63 default:
AnnaBridge 172:7d866c31b3c5 64 break;
AnnaBridge 172:7d866c31b3c5 65 }
AnnaBridge 172:7d866c31b3c5 66
AnnaBridge 172:7d866c31b3c5 67 // Enable interrupt request
AnnaBridge 172:7d866c31b3c5 68 INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index),
AnnaBridge 172:7d866c31b3c5 69 ActiveState, ENABLE);
AnnaBridge 172:7d866c31b3c5 70 }
AnnaBridge 172:7d866c31b3c5 71
AnnaBridge 172:7d866c31b3c5 72 void INT0_IRQHandler(void)
AnnaBridge 172:7d866c31b3c5 73 {
AnnaBridge 172:7d866c31b3c5 74 INT_IRQHandler(PD5, GPIO_IRQ_0, 0);
AnnaBridge 172:7d866c31b3c5 75 }
AnnaBridge 172:7d866c31b3c5 76
AnnaBridge 172:7d866c31b3c5 77 void INT1_IRQHandler(void)
AnnaBridge 172:7d866c31b3c5 78 {
AnnaBridge 172:7d866c31b3c5 79 INT_IRQHandler(PA5, GPIO_IRQ_1, 1);
AnnaBridge 172:7d866c31b3c5 80 }
AnnaBridge 172:7d866c31b3c5 81
AnnaBridge 172:7d866c31b3c5 82 void INT2_IRQHandler(void)
AnnaBridge 172:7d866c31b3c5 83 {
AnnaBridge 172:7d866c31b3c5 84 INT_IRQHandler(PA6, GPIO_IRQ_2, 2);
AnnaBridge 172:7d866c31b3c5 85 }
AnnaBridge 172:7d866c31b3c5 86
AnnaBridge 172:7d866c31b3c5 87 void INT3_IRQHandler(void)
AnnaBridge 172:7d866c31b3c5 88 {
AnnaBridge 172:7d866c31b3c5 89 INT_IRQHandler(PF1, GPIO_IRQ_3, 3);
AnnaBridge 172:7d866c31b3c5 90 }
AnnaBridge 172:7d866c31b3c5 91
AnnaBridge 172:7d866c31b3c5 92 void INT4_IRQHandler(void)
AnnaBridge 172:7d866c31b3c5 93 {
AnnaBridge 172:7d866c31b3c5 94 INT_IRQHandler(PC5, GPIO_IRQ_4, 4);
AnnaBridge 172:7d866c31b3c5 95 }
AnnaBridge 172:7d866c31b3c5 96
AnnaBridge 172:7d866c31b3c5 97 void INT5_IRQHandler(void)
AnnaBridge 172:7d866c31b3c5 98 {
AnnaBridge 172:7d866c31b3c5 99 INT_IRQHandler(PF0, GPIO_IRQ_5, 5);
AnnaBridge 172:7d866c31b3c5 100 }
AnnaBridge 172:7d866c31b3c5 101
AnnaBridge 172:7d866c31b3c5 102 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
AnnaBridge 172:7d866c31b3c5 103 {
AnnaBridge 172:7d866c31b3c5 104 // Get gpio interrupt ID
AnnaBridge 172:7d866c31b3c5 105 obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
AnnaBridge 172:7d866c31b3c5 106 core_util_critical_section_enter();
AnnaBridge 172:7d866c31b3c5 107 // Get pin mask
AnnaBridge 172:7d866c31b3c5 108 obj->mask = (uint32_t)(1 << (pin & 0x07));
AnnaBridge 172:7d866c31b3c5 109 // Get GPIO port
AnnaBridge 172:7d866c31b3c5 110 obj->port = (GPIO_Port)(pin >> 3);
AnnaBridge 172:7d866c31b3c5 111 // Set pin level as LOW
AnnaBridge 172:7d866c31b3c5 112 GPIO_WriteDataBit(obj->port, obj->mask, 0);
AnnaBridge 172:7d866c31b3c5 113 // Enable gpio interrupt function
AnnaBridge 172:7d866c31b3c5 114 pinmap_pinout(pin, PinMap_GPIO_IRQ);
AnnaBridge 172:7d866c31b3c5 115
AnnaBridge 172:7d866c31b3c5 116 // Get GPIO irq source
AnnaBridge 172:7d866c31b3c5 117 switch (obj->irq_id) {
AnnaBridge 172:7d866c31b3c5 118 case GPIO_IRQ_0:
AnnaBridge 172:7d866c31b3c5 119 obj->irq_src = INTIFAO_INT_SRC_0;
AnnaBridge 172:7d866c31b3c5 120 break;
AnnaBridge 172:7d866c31b3c5 121 case GPIO_IRQ_1:
AnnaBridge 172:7d866c31b3c5 122 obj->irq_src = INTIFAO_INT_SRC_1;
AnnaBridge 172:7d866c31b3c5 123 break;
AnnaBridge 172:7d866c31b3c5 124 case GPIO_IRQ_2:
AnnaBridge 172:7d866c31b3c5 125 obj->irq_src = INTIFAO_INT_SRC_2;
AnnaBridge 172:7d866c31b3c5 126 break;
AnnaBridge 172:7d866c31b3c5 127 case GPIO_IRQ_3:
AnnaBridge 172:7d866c31b3c5 128 obj->irq_src = INTIFAO_INT_SRC_3;
AnnaBridge 172:7d866c31b3c5 129 break;
AnnaBridge 172:7d866c31b3c5 130 case GPIO_IRQ_4:
AnnaBridge 172:7d866c31b3c5 131 obj->irq_src = INTIFAO_INT_SRC_4;
AnnaBridge 172:7d866c31b3c5 132 break;
AnnaBridge 172:7d866c31b3c5 133 case GPIO_IRQ_5:
AnnaBridge 172:7d866c31b3c5 134 obj->irq_src = INTIFAO_INT_SRC_5;
AnnaBridge 172:7d866c31b3c5 135 break;
AnnaBridge 172:7d866c31b3c5 136 default:
AnnaBridge 172:7d866c31b3c5 137 break;
AnnaBridge 172:7d866c31b3c5 138 }
AnnaBridge 172:7d866c31b3c5 139
AnnaBridge 172:7d866c31b3c5 140 // Save irq handler
AnnaBridge 172:7d866c31b3c5 141 hal_irq_handler[obj->irq_src] = handler;
AnnaBridge 172:7d866c31b3c5 142 // Save irq id
AnnaBridge 172:7d866c31b3c5 143 channel_ids[obj->irq_src] = id;
AnnaBridge 172:7d866c31b3c5 144 // Initialize interrupt event as both edges detection
AnnaBridge 172:7d866c31b3c5 145 obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
AnnaBridge 172:7d866c31b3c5 146 // Set interrupt event and enable INTx clear
AnnaBridge 172:7d866c31b3c5 147 INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE);
AnnaBridge 172:7d866c31b3c5 148 // Clear gpio pending interrupt
AnnaBridge 172:7d866c31b3c5 149 NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
AnnaBridge 172:7d866c31b3c5 150 core_util_critical_section_exit();;
AnnaBridge 172:7d866c31b3c5 151
AnnaBridge 172:7d866c31b3c5 152 return 0;
AnnaBridge 172:7d866c31b3c5 153 }
AnnaBridge 172:7d866c31b3c5 154
AnnaBridge 172:7d866c31b3c5 155 void gpio_irq_free(gpio_irq_t *obj)
AnnaBridge 172:7d866c31b3c5 156 {
AnnaBridge 172:7d866c31b3c5 157 // Clear gpio_irq
AnnaBridge 172:7d866c31b3c5 158 NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
AnnaBridge 172:7d866c31b3c5 159 // Reset interrupt handler
AnnaBridge 172:7d866c31b3c5 160 hal_irq_handler[obj->irq_src] = NULL;
AnnaBridge 172:7d866c31b3c5 161 // Reset interrupt id
AnnaBridge 172:7d866c31b3c5 162 channel_ids[obj->irq_src] = 0;
AnnaBridge 172:7d866c31b3c5 163 }
AnnaBridge 172:7d866c31b3c5 164
AnnaBridge 172:7d866c31b3c5 165 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
AnnaBridge 172:7d866c31b3c5 166 {
AnnaBridge 172:7d866c31b3c5 167 //Disable GPIO interrupt on obj
AnnaBridge 172:7d866c31b3c5 168 gpio_irq_disable(obj);
AnnaBridge 172:7d866c31b3c5 169 if (enable) {
AnnaBridge 172:7d866c31b3c5 170 // Get gpio interrupt event
AnnaBridge 172:7d866c31b3c5 171 if (event == IRQ_RISE) {
AnnaBridge 172:7d866c31b3c5 172 if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) ||
AnnaBridge 172:7d866c31b3c5 173 (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) {
AnnaBridge 172:7d866c31b3c5 174 obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
AnnaBridge 172:7d866c31b3c5 175 } else {
AnnaBridge 172:7d866c31b3c5 176 obj->event = INTIFAO_INT_ACTIVE_STATE_RISING;
AnnaBridge 172:7d866c31b3c5 177 }
AnnaBridge 172:7d866c31b3c5 178 } else if (event == IRQ_FALL) {
AnnaBridge 172:7d866c31b3c5 179 if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) ||
AnnaBridge 172:7d866c31b3c5 180 (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) {
AnnaBridge 172:7d866c31b3c5 181 obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
AnnaBridge 172:7d866c31b3c5 182 } else {
AnnaBridge 172:7d866c31b3c5 183 obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING;
AnnaBridge 172:7d866c31b3c5 184 }
AnnaBridge 172:7d866c31b3c5 185 } else {
AnnaBridge 172:7d866c31b3c5 186 error("Not supported event\n");
AnnaBridge 172:7d866c31b3c5 187 }
AnnaBridge 172:7d866c31b3c5 188 } else {
AnnaBridge 172:7d866c31b3c5 189 // Get gpio interrupt event
AnnaBridge 172:7d866c31b3c5 190 if (event == IRQ_RISE) {
AnnaBridge 172:7d866c31b3c5 191 if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) ||
AnnaBridge 172:7d866c31b3c5 192 (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) {
AnnaBridge 172:7d866c31b3c5 193 obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
AnnaBridge 172:7d866c31b3c5 194 } else {
AnnaBridge 172:7d866c31b3c5 195 obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING;
AnnaBridge 172:7d866c31b3c5 196 }
AnnaBridge 172:7d866c31b3c5 197 } else if (event == IRQ_FALL) {
AnnaBridge 172:7d866c31b3c5 198 if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) ||
AnnaBridge 172:7d866c31b3c5 199 (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) {
AnnaBridge 172:7d866c31b3c5 200 obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
AnnaBridge 172:7d866c31b3c5 201 } else {
AnnaBridge 172:7d866c31b3c5 202 obj->event = INTIFAO_INT_ACTIVE_STATE_RISING;
AnnaBridge 172:7d866c31b3c5 203 }
AnnaBridge 172:7d866c31b3c5 204 } else {
AnnaBridge 172:7d866c31b3c5 205 error("Not supported event\n");
AnnaBridge 172:7d866c31b3c5 206 }
AnnaBridge 172:7d866c31b3c5 207 }
AnnaBridge 172:7d866c31b3c5 208
AnnaBridge 172:7d866c31b3c5 209 if (obj->event != INTIFAO_INT_ACTIVE_STATE_INVALID) {
AnnaBridge 172:7d866c31b3c5 210 // Set interrupt event and enable INTx clear
AnnaBridge 172:7d866c31b3c5 211 INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE);
AnnaBridge 172:7d866c31b3c5 212 GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE);
AnnaBridge 172:7d866c31b3c5 213 } else {
AnnaBridge 172:7d866c31b3c5 214 GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
AnnaBridge 172:7d866c31b3c5 215 }
AnnaBridge 172:7d866c31b3c5 216
AnnaBridge 172:7d866c31b3c5 217 // Clear interrupt request
AnnaBridge 172:7d866c31b3c5 218 INTIFAO_ClearINTReq(obj->irq_src);
AnnaBridge 172:7d866c31b3c5 219 // Enable GPIO interrupt on obj
AnnaBridge 172:7d866c31b3c5 220 gpio_irq_enable(obj);
AnnaBridge 172:7d866c31b3c5 221 }
AnnaBridge 172:7d866c31b3c5 222
AnnaBridge 172:7d866c31b3c5 223 void gpio_irq_enable(gpio_irq_t *obj)
AnnaBridge 172:7d866c31b3c5 224 {
AnnaBridge 172:7d866c31b3c5 225 // Clear and Enable gpio_irq object
AnnaBridge 172:7d866c31b3c5 226 NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
AnnaBridge 172:7d866c31b3c5 227 NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
AnnaBridge 172:7d866c31b3c5 228 }
AnnaBridge 172:7d866c31b3c5 229
AnnaBridge 172:7d866c31b3c5 230 void gpio_irq_disable(gpio_irq_t *obj)
AnnaBridge 172:7d866c31b3c5 231 {
AnnaBridge 172:7d866c31b3c5 232 // Disable gpio_irq object
AnnaBridge 172:7d866c31b3c5 233 NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
AnnaBridge 172:7d866c31b3c5 234 }