mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
179:b0033dcd6934 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_ebi.c
<> 144:ef7eb2e8f9f7 3 * @brief External Bus Interface (EBI) Peripheral API
AnnaBridge 179:b0033dcd6934 4 * @version 5.3.3
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
AnnaBridge 179:b0033dcd6934 6 * # License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "em_ebi.h"
<> 144:ef7eb2e8f9f7 34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
<> 144:ef7eb2e8f9f7 35 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 36 #include "em_bus.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /***************************************************************************//**
<> 150:02e0a0aed4ec 39 * @addtogroup emlib
<> 144:ef7eb2e8f9f7 40 * @{
<> 144:ef7eb2e8f9f7 41 ******************************************************************************/
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 44 * @addtogroup EBI
<> 144:ef7eb2e8f9f7 45 * @brief EBI External Bus Interface (EBI) Peripheral API
<> 150:02e0a0aed4ec 46 * @details
<> 150:02e0a0aed4ec 47 * This module contains functions to control the EBI peripheral of Silicon
<> 150:02e0a0aed4ec 48 * Labs 32-bit MCUs and SoCs. The EBI is used for accessing external parallel
<> 150:02e0a0aed4ec 49 * devices. The devices appear as part of the internal memory map of the MCU.
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 ******************************************************************************/
<> 144:ef7eb2e8f9f7 52
AnnaBridge 179:b0033dcd6934 53 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 179:b0033dcd6934 54
AnnaBridge 179:b0033dcd6934 55 /* The ROUTE register has been renamed in the newest platform so these register
AnnaBridge 179:b0033dcd6934 56 * field names have been created in order to make it easier to work with both
AnnaBridge 179:b0033dcd6934 57 * the new and the old names in a generic way. */
AnnaBridge 179:b0033dcd6934 58 #if defined(_EBI_ROUTE_MASK)
AnnaBridge 179:b0033dcd6934 59 #define _EBI_GENERIC_ALEPEN_SHIFT _EBI_ROUTE_ALEPEN_SHIFT
AnnaBridge 179:b0033dcd6934 60 #define _EBI_GENERIC_BLPEN_SHIFT _EBI_ROUTE_BLPEN_SHIFT
AnnaBridge 179:b0033dcd6934 61 #define _EBI_GENERIC_EBIPEN_SHIFT _EBI_ROUTE_EBIPEN_SHIFT
AnnaBridge 179:b0033dcd6934 62 #define _EBI_GENERIC_CS0PEN_SHIFT _EBI_ROUTE_CS0PEN_SHIFT
AnnaBridge 179:b0033dcd6934 63 #define _EBI_GENERIC_CS1PEN_SHIFT _EBI_ROUTE_CS1PEN_SHIFT
AnnaBridge 179:b0033dcd6934 64 #define _EBI_GENERIC_CS2PEN_SHIFT _EBI_ROUTE_CS2PEN_SHIFT
AnnaBridge 179:b0033dcd6934 65 #define _EBI_GENERIC_CS3PEN_SHIFT _EBI_ROUTE_CS3PEN_SHIFT
AnnaBridge 179:b0033dcd6934 66 #define _EBI_GENERIC_RESETVALUE _EBI_ROUTE_RESETVALUE
AnnaBridge 179:b0033dcd6934 67 #define EBI_GENERIC_ROUTE_REG EBI->ROUTE
AnnaBridge 179:b0033dcd6934 68 #define _EBI_GENERIC_ALB_MASK _EBI_ROUTE_ALB_MASK
AnnaBridge 179:b0033dcd6934 69 #define _EBI_GENERIC_APEN_MASK _EBI_ROUTE_APEN_MASK
AnnaBridge 179:b0033dcd6934 70 #define EBI_GENERIC_TFTPEN EBI_ROUTE_TFTPEN
AnnaBridge 179:b0033dcd6934 71 #else
AnnaBridge 179:b0033dcd6934 72 #define _EBI_GENERIC_ALEPEN_SHIFT _EBI_ROUTEPEN_ALEPEN_SHIFT
AnnaBridge 179:b0033dcd6934 73 #define _EBI_GENERIC_BLPEN_SHIFT _EBI_ROUTEPEN_BLPEN_SHIFT
AnnaBridge 179:b0033dcd6934 74 #define _EBI_GENERIC_EBIPEN_SHIFT _EBI_ROUTEPEN_EBIPEN_SHIFT
AnnaBridge 179:b0033dcd6934 75 #define _EBI_GENERIC_CS0PEN_SHIFT _EBI_ROUTEPEN_CS0PEN_SHIFT
AnnaBridge 179:b0033dcd6934 76 #define _EBI_GENERIC_CS1PEN_SHIFT _EBI_ROUTEPEN_CS1PEN_SHIFT
AnnaBridge 179:b0033dcd6934 77 #define _EBI_GENERIC_CS2PEN_SHIFT _EBI_ROUTEPEN_CS2PEN_SHIFT
AnnaBridge 179:b0033dcd6934 78 #define _EBI_GENERIC_CS3PEN_SHIFT _EBI_ROUTEPEN_CS3PEN_SHIFT
AnnaBridge 179:b0033dcd6934 79 #define _EBI_GENERIC_RESETVALUE _EBI_ROUTEPEN_RESETVALUE
AnnaBridge 179:b0033dcd6934 80 #define EBI_GENERIC_ROUTE_REG EBI->ROUTEPEN
AnnaBridge 179:b0033dcd6934 81 #define _EBI_GENERIC_ALB_MASK _EBI_ROUTEPEN_ALB_MASK
AnnaBridge 179:b0033dcd6934 82 #define _EBI_GENERIC_APEN_MASK _EBI_ROUTEPEN_APEN_MASK
AnnaBridge 179:b0033dcd6934 83 #define EBI_GENERIC_TFTPEN EBI_ROUTEPEN_TFTPEN
AnnaBridge 179:b0033dcd6934 84 #endif
AnnaBridge 179:b0033dcd6934 85
AnnaBridge 179:b0033dcd6934 86 /***************************************************************************//**
AnnaBridge 179:b0033dcd6934 87 * @brief
AnnaBridge 179:b0033dcd6934 88 * Perform a single-bit write operation on a EBI route register
AnnaBridge 179:b0033dcd6934 89 *
AnnaBridge 179:b0033dcd6934 90 * @param[in] bit
AnnaBridge 179:b0033dcd6934 91 * bit Bit position to write, 0-31
AnnaBridge 179:b0033dcd6934 92 *
AnnaBridge 179:b0033dcd6934 93 * @param[in] val
AnnaBridge 179:b0033dcd6934 94 * 0 to clear bit and 1 to set bit
AnnaBridge 179:b0033dcd6934 95 ******************************************************************************/
AnnaBridge 179:b0033dcd6934 96 __STATIC_INLINE void EBI_RouteBitWrite(uint32_t bit, uint32_t val)
AnnaBridge 179:b0033dcd6934 97 {
AnnaBridge 179:b0033dcd6934 98 BUS_RegBitWrite(&(EBI_GENERIC_ROUTE_REG), bit, val);
AnnaBridge 179:b0033dcd6934 99 }
AnnaBridge 179:b0033dcd6934 100 /** @endcond */
AnnaBridge 179:b0033dcd6934 101
<> 144:ef7eb2e8f9f7 102 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 103 * @brief
<> 144:ef7eb2e8f9f7 104 * Configure and enable External Bus Interface
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * @param[in] ebiInit
<> 144:ef7eb2e8f9f7 107 * EBI configuration structure
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * @note
<> 144:ef7eb2e8f9f7 110 * GPIO lines must be configured as PUSH_PULL for correct operation
<> 144:ef7eb2e8f9f7 111 * GPIO and EBI clocks must be enabled in the CMU
<> 144:ef7eb2e8f9f7 112 ******************************************************************************/
<> 144:ef7eb2e8f9f7 113 void EBI_Init(const EBI_Init_TypeDef *ebiInit)
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 uint32_t ctrl = EBI->CTRL;
<> 144:ef7eb2e8f9f7 116
AnnaBridge 179:b0033dcd6934 117 #if defined(_EFM32_GECKO_FAMILY)
AnnaBridge 179:b0033dcd6934 118 /* Set polarity of address ready */
AnnaBridge 179:b0033dcd6934 119 EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
AnnaBridge 179:b0033dcd6934 120 /* Set polarity of address latch enable */
AnnaBridge 179:b0033dcd6934 121 EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
AnnaBridge 179:b0033dcd6934 122 /* Set polarity of write enable */
AnnaBridge 179:b0033dcd6934 123 EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
AnnaBridge 179:b0033dcd6934 124 /* Set polarity of read enable */
AnnaBridge 179:b0033dcd6934 125 EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
AnnaBridge 179:b0033dcd6934 126 /* Set polarity of chip select lines */
AnnaBridge 179:b0033dcd6934 127 EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
AnnaBridge 179:b0033dcd6934 128 #else
<> 144:ef7eb2e8f9f7 129 /* Enable Independent Timing for devices that supports it */
<> 144:ef7eb2e8f9f7 130 ctrl |= EBI_CTRL_ITS;
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Set polarity of address ready */
<> 144:ef7eb2e8f9f7 133 EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
<> 144:ef7eb2e8f9f7 134 /* Set polarity of address latch enable */
<> 144:ef7eb2e8f9f7 135 EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
<> 144:ef7eb2e8f9f7 136 /* Set polarity of write enable */
<> 144:ef7eb2e8f9f7 137 EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
<> 144:ef7eb2e8f9f7 138 /* Set polarity of read enable */
<> 144:ef7eb2e8f9f7 139 EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
<> 144:ef7eb2e8f9f7 140 /* Set polarity of chip select lines */
<> 144:ef7eb2e8f9f7 141 EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
<> 144:ef7eb2e8f9f7 142 /* Set polarity of byte lane line */
<> 144:ef7eb2e8f9f7 143 EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
<> 144:ef7eb2e8f9f7 144 #endif
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Configure EBI mode and control settings */
AnnaBridge 179:b0033dcd6934 147 #if defined(_EFM32_GECKO_FAMILY)
AnnaBridge 179:b0033dcd6934 148 ctrl &= ~(_EBI_CTRL_MODE_MASK
AnnaBridge 179:b0033dcd6934 149 | _EBI_CTRL_ARDYEN_MASK
AnnaBridge 179:b0033dcd6934 150 | _EBI_CTRL_ARDYTODIS_MASK
AnnaBridge 179:b0033dcd6934 151 | _EBI_CTRL_BANK0EN_MASK
AnnaBridge 179:b0033dcd6934 152 | _EBI_CTRL_BANK1EN_MASK
AnnaBridge 179:b0033dcd6934 153 | _EBI_CTRL_BANK2EN_MASK
AnnaBridge 179:b0033dcd6934 154 | _EBI_CTRL_BANK3EN_MASK);
AnnaBridge 179:b0033dcd6934 155 if ( ebiInit->enable) {
AnnaBridge 179:b0033dcd6934 156 if ( ebiInit->banks & EBI_BANK0 ) {
AnnaBridge 179:b0033dcd6934 157 ctrl |= EBI_CTRL_BANK0EN;
AnnaBridge 179:b0033dcd6934 158 }
AnnaBridge 179:b0033dcd6934 159 if ( ebiInit->banks & EBI_BANK1 ) {
AnnaBridge 179:b0033dcd6934 160 ctrl |= EBI_CTRL_BANK1EN;
AnnaBridge 179:b0033dcd6934 161 }
AnnaBridge 179:b0033dcd6934 162 if ( ebiInit->banks & EBI_BANK2 ) {
AnnaBridge 179:b0033dcd6934 163 ctrl |= EBI_CTRL_BANK2EN;
AnnaBridge 179:b0033dcd6934 164 }
AnnaBridge 179:b0033dcd6934 165 if ( ebiInit->banks & EBI_BANK3 ) {
AnnaBridge 179:b0033dcd6934 166 ctrl |= EBI_CTRL_BANK3EN;
AnnaBridge 179:b0033dcd6934 167 }
AnnaBridge 179:b0033dcd6934 168 }
AnnaBridge 179:b0033dcd6934 169 ctrl |= ebiInit->mode;
AnnaBridge 179:b0033dcd6934 170 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
AnnaBridge 179:b0033dcd6934 171 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
AnnaBridge 179:b0033dcd6934 172 #else
AnnaBridge 179:b0033dcd6934 173 if (ebiInit->banks & EBI_BANK0) {
<> 144:ef7eb2e8f9f7 174 ctrl &= ~(_EBI_CTRL_MODE_MASK
<> 144:ef7eb2e8f9f7 175 | _EBI_CTRL_ARDYEN_MASK
<> 144:ef7eb2e8f9f7 176 | _EBI_CTRL_ARDYTODIS_MASK
<> 144:ef7eb2e8f9f7 177 | _EBI_CTRL_BL_MASK
<> 144:ef7eb2e8f9f7 178 | _EBI_CTRL_NOIDLE_MASK
<> 144:ef7eb2e8f9f7 179 | _EBI_CTRL_BANK0EN_MASK);
<> 144:ef7eb2e8f9f7 180 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
<> 144:ef7eb2e8f9f7 181 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
<> 144:ef7eb2e8f9f7 182 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
<> 144:ef7eb2e8f9f7 183 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
<> 144:ef7eb2e8f9f7 184 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
AnnaBridge 179:b0033dcd6934 185 if ( ebiInit->enable) {
<> 144:ef7eb2e8f9f7 186 ctrl |= EBI_CTRL_BANK0EN;
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188 }
AnnaBridge 179:b0033dcd6934 189 if (ebiInit->banks & EBI_BANK1) {
<> 144:ef7eb2e8f9f7 190 ctrl &= ~(_EBI_CTRL_BL1_MASK
<> 144:ef7eb2e8f9f7 191 | _EBI_CTRL_MODE1_MASK
<> 144:ef7eb2e8f9f7 192 | _EBI_CTRL_ARDY1EN_MASK
<> 144:ef7eb2e8f9f7 193 | _EBI_CTRL_ARDYTO1DIS_MASK
<> 144:ef7eb2e8f9f7 194 | _EBI_CTRL_NOIDLE1_MASK
<> 144:ef7eb2e8f9f7 195 | _EBI_CTRL_BANK1EN_MASK);
<> 144:ef7eb2e8f9f7 196 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
<> 144:ef7eb2e8f9f7 197 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
<> 144:ef7eb2e8f9f7 198 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
<> 144:ef7eb2e8f9f7 199 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
<> 144:ef7eb2e8f9f7 200 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
AnnaBridge 179:b0033dcd6934 201 if ( ebiInit->enable) {
<> 144:ef7eb2e8f9f7 202 ctrl |= EBI_CTRL_BANK1EN;
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 }
AnnaBridge 179:b0033dcd6934 205 if (ebiInit->banks & EBI_BANK2) {
<> 144:ef7eb2e8f9f7 206 ctrl &= ~(_EBI_CTRL_BL2_MASK
<> 144:ef7eb2e8f9f7 207 | _EBI_CTRL_MODE2_MASK
<> 144:ef7eb2e8f9f7 208 | _EBI_CTRL_ARDY2EN_MASK
<> 144:ef7eb2e8f9f7 209 | _EBI_CTRL_ARDYTO2DIS_MASK
<> 144:ef7eb2e8f9f7 210 | _EBI_CTRL_NOIDLE2_MASK
<> 144:ef7eb2e8f9f7 211 | _EBI_CTRL_BANK2EN_MASK);
<> 144:ef7eb2e8f9f7 212 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
<> 144:ef7eb2e8f9f7 213 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
<> 144:ef7eb2e8f9f7 214 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
<> 144:ef7eb2e8f9f7 215 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
<> 144:ef7eb2e8f9f7 216 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
AnnaBridge 179:b0033dcd6934 217 if ( ebiInit->enable) {
<> 144:ef7eb2e8f9f7 218 ctrl |= EBI_CTRL_BANK2EN;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220 }
AnnaBridge 179:b0033dcd6934 221 if (ebiInit->banks & EBI_BANK3) {
<> 144:ef7eb2e8f9f7 222 ctrl &= ~(_EBI_CTRL_BL3_MASK
<> 144:ef7eb2e8f9f7 223 | _EBI_CTRL_MODE3_MASK
<> 144:ef7eb2e8f9f7 224 | _EBI_CTRL_ARDY3EN_MASK
<> 144:ef7eb2e8f9f7 225 | _EBI_CTRL_ARDYTO3DIS_MASK
<> 144:ef7eb2e8f9f7 226 | _EBI_CTRL_NOIDLE3_MASK
<> 144:ef7eb2e8f9f7 227 | _EBI_CTRL_BANK3EN_MASK);
<> 144:ef7eb2e8f9f7 228 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
<> 144:ef7eb2e8f9f7 229 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
<> 144:ef7eb2e8f9f7 230 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
<> 144:ef7eb2e8f9f7 231 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
<> 144:ef7eb2e8f9f7 232 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
AnnaBridge 179:b0033dcd6934 233 if ( ebiInit->enable) {
<> 144:ef7eb2e8f9f7 234 ctrl |= EBI_CTRL_BANK3EN;
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237 #endif
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Configure timing */
AnnaBridge 179:b0033dcd6934 240 #if defined(_EFM32_GECKO_FAMILY)
AnnaBridge 179:b0033dcd6934 241 EBI_ReadTimingSet(ebiInit->readSetupCycles,
AnnaBridge 179:b0033dcd6934 242 ebiInit->readStrobeCycles,
AnnaBridge 179:b0033dcd6934 243 ebiInit->readHoldCycles);
AnnaBridge 179:b0033dcd6934 244 EBI_WriteTimingSet(ebiInit->writeSetupCycles,
AnnaBridge 179:b0033dcd6934 245 ebiInit->writeStrobeCycles,
AnnaBridge 179:b0033dcd6934 246 ebiInit->writeHoldCycles);
AnnaBridge 179:b0033dcd6934 247 EBI_AddressTimingSet(ebiInit->addrSetupCycles,
AnnaBridge 179:b0033dcd6934 248 ebiInit->addrHoldCycles);
AnnaBridge 179:b0033dcd6934 249 #else
<> 144:ef7eb2e8f9f7 250 EBI_BankReadTimingSet(ebiInit->banks,
<> 144:ef7eb2e8f9f7 251 ebiInit->readSetupCycles,
<> 144:ef7eb2e8f9f7 252 ebiInit->readStrobeCycles,
<> 144:ef7eb2e8f9f7 253 ebiInit->readHoldCycles);
<> 144:ef7eb2e8f9f7 254 EBI_BankReadTimingConfig(ebiInit->banks,
<> 144:ef7eb2e8f9f7 255 ebiInit->readPageMode,
<> 144:ef7eb2e8f9f7 256 ebiInit->readPrefetch,
<> 144:ef7eb2e8f9f7 257 ebiInit->readHalfRE);
<> 144:ef7eb2e8f9f7 258 EBI_BankWriteTimingSet(ebiInit->banks,
<> 144:ef7eb2e8f9f7 259 ebiInit->writeSetupCycles,
<> 144:ef7eb2e8f9f7 260 ebiInit->writeStrobeCycles,
<> 144:ef7eb2e8f9f7 261 ebiInit->writeHoldCycles);
<> 144:ef7eb2e8f9f7 262 EBI_BankWriteTimingConfig(ebiInit->banks,
<> 144:ef7eb2e8f9f7 263 ebiInit->writeBufferDisable,
<> 144:ef7eb2e8f9f7 264 ebiInit->writeHalfWE);
<> 144:ef7eb2e8f9f7 265 EBI_BankAddressTimingSet(ebiInit->banks,
<> 144:ef7eb2e8f9f7 266 ebiInit->addrSetupCycles,
<> 144:ef7eb2e8f9f7 267 ebiInit->addrHoldCycles);
<> 144:ef7eb2e8f9f7 268 EBI_BankAddressTimingConfig(ebiInit->banks,
<> 144:ef7eb2e8f9f7 269 ebiInit->addrHalfALE);
<> 144:ef7eb2e8f9f7 270 #endif
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Activate new configuration */
<> 144:ef7eb2e8f9f7 273 EBI->CTRL = ctrl;
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Configure Adress Latch Enable */
AnnaBridge 179:b0033dcd6934 276 switch (ebiInit->mode) {
<> 144:ef7eb2e8f9f7 277 case ebiModeD16A16ALE:
<> 144:ef7eb2e8f9f7 278 case ebiModeD8A24ALE:
<> 144:ef7eb2e8f9f7 279 /* Address Latch Enable */
AnnaBridge 179:b0033dcd6934 280 EBI_RouteBitWrite(_EBI_GENERIC_ALEPEN_SHIFT, 1);
<> 144:ef7eb2e8f9f7 281 break;
AnnaBridge 179:b0033dcd6934 282 #if defined(EBI_CTRL_MODE_D16)
<> 144:ef7eb2e8f9f7 283 case ebiModeD16:
<> 144:ef7eb2e8f9f7 284 #endif
<> 144:ef7eb2e8f9f7 285 case ebiModeD8A8:
<> 144:ef7eb2e8f9f7 286 /* Make sure Address Latch is disabled */
AnnaBridge 179:b0033dcd6934 287 EBI_RouteBitWrite(_EBI_GENERIC_ALEPEN_SHIFT, 0);
<> 144:ef7eb2e8f9f7 288 break;
<> 144:ef7eb2e8f9f7 289 }
AnnaBridge 179:b0033dcd6934 290
AnnaBridge 179:b0033dcd6934 291 #if !defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 292 /* Limit pin enable */
AnnaBridge 179:b0033dcd6934 293 EBI_GENERIC_ROUTE_REG = (EBI_GENERIC_ROUTE_REG & ~_EBI_GENERIC_ALB_MASK) | ebiInit->aLow;
AnnaBridge 179:b0033dcd6934 294 EBI_GENERIC_ROUTE_REG = (EBI_GENERIC_ROUTE_REG & ~_EBI_GENERIC_APEN_MASK) | ebiInit->aHigh;
AnnaBridge 179:b0033dcd6934 295 #if defined(_EBI_ROUTE_LOCATION_MASK)
<> 144:ef7eb2e8f9f7 296 /* Location */
<> 144:ef7eb2e8f9f7 297 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
AnnaBridge 179:b0033dcd6934 298 #endif
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Enable EBI BL pin if necessary */
AnnaBridge 179:b0033dcd6934 301 if (ctrl & (_EBI_CTRL_BL_MASK | _EBI_CTRL_BL1_MASK | _EBI_CTRL_BL2_MASK | _EBI_CTRL_BL3_MASK)) {
AnnaBridge 179:b0033dcd6934 302 EBI_RouteBitWrite(_EBI_GENERIC_BLPEN_SHIFT, ebiInit->blEnable);
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304 #endif
AnnaBridge 179:b0033dcd6934 305
<> 144:ef7eb2e8f9f7 306 /* Enable EBI pins EBI_WEn and EBI_REn */
AnnaBridge 179:b0033dcd6934 307 EBI_RouteBitWrite(_EBI_GENERIC_EBIPEN_SHIFT, 1);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Enable chip select lines */
<> 144:ef7eb2e8f9f7 310 EBI_ChipSelectEnable(ebiInit->csLines, true);
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 314 * @brief
<> 144:ef7eb2e8f9f7 315 * Disable External Bus Interface
<> 144:ef7eb2e8f9f7 316 ******************************************************************************/
<> 144:ef7eb2e8f9f7 317 void EBI_Disable(void)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /* Disable pins */
AnnaBridge 179:b0033dcd6934 320 EBI_GENERIC_ROUTE_REG = _EBI_GENERIC_RESETVALUE;
<> 144:ef7eb2e8f9f7 321 /* Disable banks */
<> 144:ef7eb2e8f9f7 322 EBI->CTRL = _EBI_CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 326 * @brief
<> 144:ef7eb2e8f9f7 327 * Enable or disable EBI Bank
<> 144:ef7eb2e8f9f7 328 *
<> 144:ef7eb2e8f9f7 329 * @param[in] banks
<> 144:ef7eb2e8f9f7 330 * Banks to reconfigure, mask of EBI_BANK<n> flags
<> 144:ef7eb2e8f9f7 331 *
<> 144:ef7eb2e8f9f7 332 * @param[in] enable
<> 144:ef7eb2e8f9f7 333 * True to enable, false to disable
<> 144:ef7eb2e8f9f7 334 ******************************************************************************/
<> 144:ef7eb2e8f9f7 335 void EBI_BankEnable(uint32_t banks, bool enable)
<> 144:ef7eb2e8f9f7 336 {
AnnaBridge 179:b0033dcd6934 337 if (banks & EBI_BANK0) {
<> 144:ef7eb2e8f9f7 338 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 339 }
AnnaBridge 179:b0033dcd6934 340 if (banks & EBI_BANK1) {
<> 144:ef7eb2e8f9f7 341 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 342 }
AnnaBridge 179:b0033dcd6934 343 if (banks & EBI_BANK2) {
<> 144:ef7eb2e8f9f7 344 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 345 }
AnnaBridge 179:b0033dcd6934 346 if (banks & EBI_BANK3) {
<> 144:ef7eb2e8f9f7 347 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 352 * @brief
<> 144:ef7eb2e8f9f7 353 * Return base address of EBI bank
<> 144:ef7eb2e8f9f7 354 *
<> 144:ef7eb2e8f9f7 355 * @param[in] bank
<> 144:ef7eb2e8f9f7 356 * Bank to return start address for
<> 144:ef7eb2e8f9f7 357 *
<> 144:ef7eb2e8f9f7 358 * @return
<> 144:ef7eb2e8f9f7 359 * Absolute address of bank
<> 144:ef7eb2e8f9f7 360 ******************************************************************************/
<> 144:ef7eb2e8f9f7 361 uint32_t EBI_BankAddress(uint32_t bank)
<> 144:ef7eb2e8f9f7 362 {
AnnaBridge 179:b0033dcd6934 363 #if defined (EBI_CTRL_ALTMAP)
AnnaBridge 179:b0033dcd6934 364 if (EBI->CTRL & EBI_CTRL_ALTMAP) {
AnnaBridge 179:b0033dcd6934 365 switch (bank) {
<> 144:ef7eb2e8f9f7 366 case EBI_BANK0:
AnnaBridge 179:b0033dcd6934 367 return EBI_MEM_BASE;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 case EBI_BANK1:
AnnaBridge 179:b0033dcd6934 370 return EBI_MEM_BASE + 0x10000000UL;
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 case EBI_BANK2:
AnnaBridge 179:b0033dcd6934 373 return EBI_MEM_BASE + 0x20000000UL;
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 case EBI_BANK3:
AnnaBridge 179:b0033dcd6934 376 return EBI_MEM_BASE + 0x30000000UL;
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 default:
<> 144:ef7eb2e8f9f7 379 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 380 break;
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383 #endif
AnnaBridge 179:b0033dcd6934 384 switch (bank) {
<> 144:ef7eb2e8f9f7 385 case EBI_BANK0:
AnnaBridge 179:b0033dcd6934 386 return EBI_MEM_BASE;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 case EBI_BANK1:
AnnaBridge 179:b0033dcd6934 389 return EBI_MEM_BASE + 0x04000000UL;
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 case EBI_BANK2:
AnnaBridge 179:b0033dcd6934 392 return EBI_MEM_BASE + 0x08000000UL;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 case EBI_BANK3:
AnnaBridge 179:b0033dcd6934 395 return EBI_MEM_BASE + 0x0C000000UL;
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 default:
<> 144:ef7eb2e8f9f7 398 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 399 break;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 return 0;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 405 * @brief
<> 144:ef7eb2e8f9f7 406 * Enable or disable EBI Chip Select
<> 144:ef7eb2e8f9f7 407 *
<> 144:ef7eb2e8f9f7 408 * @param[in] cs
<> 144:ef7eb2e8f9f7 409 * ChipSelect lines to reconfigure, mask of EBI_CS<n> flags
<> 144:ef7eb2e8f9f7 410 *
<> 144:ef7eb2e8f9f7 411 * @param[in] enable
<> 144:ef7eb2e8f9f7 412 * True to enable, false to disable
<> 144:ef7eb2e8f9f7 413 ******************************************************************************/
<> 144:ef7eb2e8f9f7 414 void EBI_ChipSelectEnable(uint32_t cs, bool enable)
<> 144:ef7eb2e8f9f7 415 {
AnnaBridge 179:b0033dcd6934 416 if (cs & EBI_CS0) {
AnnaBridge 179:b0033dcd6934 417 EBI_RouteBitWrite(_EBI_GENERIC_CS0PEN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 418 }
AnnaBridge 179:b0033dcd6934 419 if (cs & EBI_CS1) {
AnnaBridge 179:b0033dcd6934 420 EBI_RouteBitWrite(_EBI_GENERIC_CS1PEN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 421 }
AnnaBridge 179:b0033dcd6934 422 if (cs & EBI_CS2) {
AnnaBridge 179:b0033dcd6934 423 EBI_RouteBitWrite(_EBI_GENERIC_CS2PEN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 424 }
AnnaBridge 179:b0033dcd6934 425 if (cs & EBI_CS3) {
AnnaBridge 179:b0033dcd6934 426 EBI_RouteBitWrite(_EBI_GENERIC_CS3PEN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 431 * @brief
<> 144:ef7eb2e8f9f7 432 * Configure EBI pin polarity
<> 144:ef7eb2e8f9f7 433 *
<> 144:ef7eb2e8f9f7 434 * @param[in] line
<> 144:ef7eb2e8f9f7 435 * Which pin/line to configure
<> 144:ef7eb2e8f9f7 436 *
<> 144:ef7eb2e8f9f7 437 * @param[in] polarity
<> 144:ef7eb2e8f9f7 438 * Active high, or active low
<> 144:ef7eb2e8f9f7 439 ******************************************************************************/
<> 144:ef7eb2e8f9f7 440 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
<> 144:ef7eb2e8f9f7 441 {
AnnaBridge 179:b0033dcd6934 442 switch (line) {
<> 144:ef7eb2e8f9f7 443 case ebiLineARDY:
AnnaBridge 179:b0033dcd6934 444 BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 445 break;
<> 144:ef7eb2e8f9f7 446 case ebiLineALE:
AnnaBridge 179:b0033dcd6934 447 BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 448 break;
<> 144:ef7eb2e8f9f7 449 case ebiLineWE:
AnnaBridge 179:b0033dcd6934 450 BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_WEPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 451 break;
<> 144:ef7eb2e8f9f7 452 case ebiLineRE:
AnnaBridge 179:b0033dcd6934 453 BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_REPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 454 break;
<> 144:ef7eb2e8f9f7 455 case ebiLineCS:
AnnaBridge 179:b0033dcd6934 456 BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_CSPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 457 break;
AnnaBridge 179:b0033dcd6934 458 #if defined(_EBI_POLARITY_BLPOL_MASK)
<> 144:ef7eb2e8f9f7 459 case ebiLineBL:
AnnaBridge 179:b0033dcd6934 460 BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_BLPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 461 break;
AnnaBridge 179:b0033dcd6934 462 #endif
AnnaBridge 179:b0033dcd6934 463 #if defined (_EBI_TFTPOLARITY_MASK)
<> 144:ef7eb2e8f9f7 464 case ebiLineTFTVSync:
AnnaBridge 179:b0033dcd6934 465 BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 466 break;
<> 144:ef7eb2e8f9f7 467 case ebiLineTFTHSync:
AnnaBridge 179:b0033dcd6934 468 BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 469 break;
<> 144:ef7eb2e8f9f7 470 case ebiLineTFTDataEn:
AnnaBridge 179:b0033dcd6934 471 BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 472 break;
<> 144:ef7eb2e8f9f7 473 case ebiLineTFTDClk:
AnnaBridge 179:b0033dcd6934 474 BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 475 break;
<> 144:ef7eb2e8f9f7 476 case ebiLineTFTCS:
AnnaBridge 179:b0033dcd6934 477 BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 478 break;
<> 144:ef7eb2e8f9f7 479 #endif
<> 144:ef7eb2e8f9f7 480 default:
<> 144:ef7eb2e8f9f7 481 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 482 break;
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 487 * @brief
<> 144:ef7eb2e8f9f7 488 * Configure timing values of read bus accesses
<> 144:ef7eb2e8f9f7 489 *
<> 144:ef7eb2e8f9f7 490 * @param[in] setupCycles
<> 144:ef7eb2e8f9f7 491 * Number of clock cycles for address setup before REn is asserted
<> 144:ef7eb2e8f9f7 492 *
<> 144:ef7eb2e8f9f7 493 * @param[in] strobeCycles
<> 144:ef7eb2e8f9f7 494 * The number of cycles the REn is held active. After the specified number of
<> 144:ef7eb2e8f9f7 495 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
<> 144:ef7eb2e8f9f7 496 *
<> 144:ef7eb2e8f9f7 497 * @param[in] holdCycles
<> 144:ef7eb2e8f9f7 498 * The number of cycles CSn is held active after the REn is dessarted
<> 144:ef7eb2e8f9f7 499 ******************************************************************************/
<> 144:ef7eb2e8f9f7 500 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 uint32_t readTiming;
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Check that timings are within limits */
<> 144:ef7eb2e8f9f7 505 EFM_ASSERT(setupCycles < 4);
<> 144:ef7eb2e8f9f7 506 EFM_ASSERT(strobeCycles < 16);
<> 144:ef7eb2e8f9f7 507 EFM_ASSERT(holdCycles < 4);
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Configure timing values */
<> 144:ef7eb2e8f9f7 510 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
<> 144:ef7eb2e8f9f7 511 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
<> 144:ef7eb2e8f9f7 512 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 EBI->RDTIMING = (EBI->RDTIMING
<> 144:ef7eb2e8f9f7 515 & ~(_EBI_RDTIMING_RDSETUP_MASK
<> 144:ef7eb2e8f9f7 516 | _EBI_RDTIMING_RDSTRB_MASK
<> 144:ef7eb2e8f9f7 517 | _EBI_RDTIMING_RDHOLD_MASK))
<> 144:ef7eb2e8f9f7 518 | readTiming;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 522 * @brief
<> 144:ef7eb2e8f9f7 523 * Configure timing values of write bus accesses
<> 144:ef7eb2e8f9f7 524 *
<> 144:ef7eb2e8f9f7 525 * @param[in] setupCycles
<> 144:ef7eb2e8f9f7 526 * Number of clock cycles for address setup before WEn is asserted
<> 144:ef7eb2e8f9f7 527 *
<> 144:ef7eb2e8f9f7 528 * @param[in] strobeCycles
<> 144:ef7eb2e8f9f7 529 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
<> 144:ef7eb2e8f9f7 530 *
<> 144:ef7eb2e8f9f7 531 * @param[in] holdCycles
<> 144:ef7eb2e8f9f7 532 * Number of cycles CSn is held active after the WEn is deasserted
<> 144:ef7eb2e8f9f7 533 ******************************************************************************/
<> 144:ef7eb2e8f9f7 534 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 uint32_t writeTiming;
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Check that timings are within limits */
<> 144:ef7eb2e8f9f7 539 EFM_ASSERT(setupCycles < 4);
<> 144:ef7eb2e8f9f7 540 EFM_ASSERT(strobeCycles < 16);
<> 144:ef7eb2e8f9f7 541 EFM_ASSERT(holdCycles < 4);
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Configure timing values */
<> 144:ef7eb2e8f9f7 544 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
<> 144:ef7eb2e8f9f7 545 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
<> 144:ef7eb2e8f9f7 546 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 EBI->WRTIMING = (EBI->WRTIMING
<> 144:ef7eb2e8f9f7 549 & ~(_EBI_WRTIMING_WRSETUP_MASK
<> 144:ef7eb2e8f9f7 550 | _EBI_WRTIMING_WRSTRB_MASK
<> 144:ef7eb2e8f9f7 551 | _EBI_WRTIMING_WRHOLD_MASK))
<> 144:ef7eb2e8f9f7 552 | writeTiming;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 556 * @brief
<> 144:ef7eb2e8f9f7 557 * Configure timing values of address latch bus accesses
<> 144:ef7eb2e8f9f7 558 *
<> 144:ef7eb2e8f9f7 559 * @param[in] setupCycles
<> 144:ef7eb2e8f9f7 560 * Sets the number of cycles the address is held after ALE is asserted
<> 144:ef7eb2e8f9f7 561 *
<> 144:ef7eb2e8f9f7 562 * @param[in] holdCycles
<> 144:ef7eb2e8f9f7 563 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
<> 144:ef7eb2e8f9f7 564 * ALE is asserted. If set 0, 1 cycle is inserted by HW
<> 144:ef7eb2e8f9f7 565 ******************************************************************************/
<> 144:ef7eb2e8f9f7 566 void EBI_AddressTimingSet(int setupCycles, int holdCycles)
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 uint32_t addressLatchTiming;
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Check that timing values are within limits */
<> 144:ef7eb2e8f9f7 571 EFM_ASSERT(setupCycles < 4);
<> 144:ef7eb2e8f9f7 572 EFM_ASSERT(holdCycles < 4);
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Configure address latch timing values */
<> 144:ef7eb2e8f9f7 575 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
<> 144:ef7eb2e8f9f7 576 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 EBI->ADDRTIMING = (EBI->ADDRTIMING
<> 144:ef7eb2e8f9f7 579 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
<> 144:ef7eb2e8f9f7 580 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
<> 144:ef7eb2e8f9f7 581 | addressLatchTiming;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583
AnnaBridge 179:b0033dcd6934 584 #if defined(_EBI_TFTCTRL_MASK)
<> 144:ef7eb2e8f9f7 585 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 586 * @brief
<> 144:ef7eb2e8f9f7 587 * Configure and initialize TFT Direct Drive
<> 144:ef7eb2e8f9f7 588 *
<> 144:ef7eb2e8f9f7 589 * @param[in] ebiTFTInit
<> 144:ef7eb2e8f9f7 590 * TFT Initialization structure
<> 144:ef7eb2e8f9f7 591 ******************************************************************************/
<> 144:ef7eb2e8f9f7 592 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 uint32_t ctrl;
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Configure base address for frame buffer offset to EBI bank */
<> 144:ef7eb2e8f9f7 597 EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Configure display size and porch areas */
<> 144:ef7eb2e8f9f7 600 EBI_TFTSizeSet(ebiTFTInit->hsize,
<> 144:ef7eb2e8f9f7 601 ebiTFTInit->vsize);
<> 144:ef7eb2e8f9f7 602 EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
<> 144:ef7eb2e8f9f7 603 ebiTFTInit->hPorchBack,
<> 144:ef7eb2e8f9f7 604 ebiTFTInit->hPulseWidth);
<> 144:ef7eb2e8f9f7 605 EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
<> 144:ef7eb2e8f9f7 606 ebiTFTInit->vPorchBack,
<> 144:ef7eb2e8f9f7 607 ebiTFTInit->vPulseWidth);
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Configure timing settings */
<> 144:ef7eb2e8f9f7 610 EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
<> 144:ef7eb2e8f9f7 611 ebiTFTInit->startPosition,
<> 144:ef7eb2e8f9f7 612 ebiTFTInit->setupCycles,
<> 144:ef7eb2e8f9f7 613 ebiTFTInit->holdCycles);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Configure line polarity settings */
<> 144:ef7eb2e8f9f7 616 EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
<> 144:ef7eb2e8f9f7 617 EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
<> 144:ef7eb2e8f9f7 618 EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
<> 144:ef7eb2e8f9f7 619 EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
<> 144:ef7eb2e8f9f7 620 EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Main control, EBI bank select, mask and blending configuration */
<> 144:ef7eb2e8f9f7 623 ctrl = (uint32_t)ebiTFTInit->bank
<> 144:ef7eb2e8f9f7 624 | (uint32_t)ebiTFTInit->width
<> 144:ef7eb2e8f9f7 625 | (uint32_t)ebiTFTInit->colSrc
<> 144:ef7eb2e8f9f7 626 | (uint32_t)ebiTFTInit->interleave
<> 144:ef7eb2e8f9f7 627 | (uint32_t)ebiTFTInit->fbTrigger
<> 144:ef7eb2e8f9f7 628 | (uint32_t)(ebiTFTInit->shiftDClk == true
<> 144:ef7eb2e8f9f7 629 ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
<> 144:ef7eb2e8f9f7 630 | (uint32_t)ebiTFTInit->maskBlend
<> 144:ef7eb2e8f9f7 631 | (uint32_t)ebiTFTInit->driveMode;
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 EBI->TFTCTRL = ctrl;
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Enable TFT pins */
AnnaBridge 179:b0033dcd6934 636 if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled) {
AnnaBridge 179:b0033dcd6934 637 EBI_GENERIC_ROUTE_REG |= EBI_GENERIC_TFTPEN;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 642 * @brief
<> 144:ef7eb2e8f9f7 643 * Configure and initialize TFT size settings
<> 144:ef7eb2e8f9f7 644 *
<> 144:ef7eb2e8f9f7 645 * @param[in] horizontal
<> 144:ef7eb2e8f9f7 646 * TFT display horizontal size in pixels
<> 144:ef7eb2e8f9f7 647 * @param[in] vertical
<> 144:ef7eb2e8f9f7 648 * TFT display vertical size in pixels
<> 144:ef7eb2e8f9f7 649 ******************************************************************************/
<> 144:ef7eb2e8f9f7 650 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
<> 144:ef7eb2e8f9f7 651 {
AnnaBridge 179:b0033dcd6934 652 EFM_ASSERT((horizontal - 1) < 1024);
AnnaBridge 179:b0033dcd6934 653 EFM_ASSERT((vertical - 1) < 1024);
<> 144:ef7eb2e8f9f7 654
AnnaBridge 179:b0033dcd6934 655 EBI->TFTSIZE = ((horizontal - 1) << _EBI_TFTSIZE_HSZ_SHIFT)
AnnaBridge 179:b0033dcd6934 656 | ((vertical - 1) << _EBI_TFTSIZE_VSZ_SHIFT);
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 660 * @brief
<> 144:ef7eb2e8f9f7 661 * Configure and initialize Horizontal Porch Settings
<> 144:ef7eb2e8f9f7 662 *
<> 144:ef7eb2e8f9f7 663 * @param[in] front
<> 144:ef7eb2e8f9f7 664 * Horizontal front porch size in pixels
<> 144:ef7eb2e8f9f7 665 * @param[in] back
<> 144:ef7eb2e8f9f7 666 * Horizontal back porch size in pixels
<> 144:ef7eb2e8f9f7 667 * @param[in] pulseWidth
<> 144:ef7eb2e8f9f7 668 * Horizontal synchronization pulse width. Set to required -1.
<> 144:ef7eb2e8f9f7 669 ******************************************************************************/
<> 144:ef7eb2e8f9f7 670 void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 EFM_ASSERT(front < 256);
<> 144:ef7eb2e8f9f7 673 EFM_ASSERT(back < 256);
AnnaBridge 179:b0033dcd6934 674 EFM_ASSERT((pulseWidth - 1) < 128);
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
<> 144:ef7eb2e8f9f7 677 | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
AnnaBridge 179:b0033dcd6934 678 | ((pulseWidth - 1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 682 * @brief
<> 144:ef7eb2e8f9f7 683 * Configure Vertical Porch Settings
<> 144:ef7eb2e8f9f7 684 *
<> 144:ef7eb2e8f9f7 685 * @param[in] front
<> 144:ef7eb2e8f9f7 686 * Vertical front porch size in pixels
<> 144:ef7eb2e8f9f7 687 * @param[in] back
<> 144:ef7eb2e8f9f7 688 * Vertical back porch size in pixels
<> 144:ef7eb2e8f9f7 689 * @param[in] pulseWidth
<> 144:ef7eb2e8f9f7 690 * Vertical synchronization pulse width. Set to required -1.
<> 144:ef7eb2e8f9f7 691 ******************************************************************************/
<> 144:ef7eb2e8f9f7 692 void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 EFM_ASSERT(front < 256);
<> 144:ef7eb2e8f9f7 695 EFM_ASSERT(back < 256);
AnnaBridge 179:b0033dcd6934 696 EFM_ASSERT((pulseWidth - 1) < 128);
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
<> 144:ef7eb2e8f9f7 699 | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
AnnaBridge 179:b0033dcd6934 700 | ((pulseWidth - 1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 704 * @brief
<> 144:ef7eb2e8f9f7 705 * Configure TFT Direct Drive Timing Settings
<> 144:ef7eb2e8f9f7 706 *
<> 144:ef7eb2e8f9f7 707 * @param[in] dclkPeriod
<> 144:ef7eb2e8f9f7 708 * DCLK period in internal cycles
<> 144:ef7eb2e8f9f7 709 *
<> 144:ef7eb2e8f9f7 710 * @param[in] start
<> 144:ef7eb2e8f9f7 711 * Starting position of external direct drive, relative to DCLK inactive edge
<> 144:ef7eb2e8f9f7 712 *
<> 144:ef7eb2e8f9f7 713 * @param[in] setup
<> 144:ef7eb2e8f9f7 714 * Number of cycles RGB data is driven before active edge of DCLK
<> 144:ef7eb2e8f9f7 715 *
<> 144:ef7eb2e8f9f7 716 * @param[in] hold
<> 144:ef7eb2e8f9f7 717 * Number of cycles RGB data is held after active edge of DCLK
<> 144:ef7eb2e8f9f7 718 ******************************************************************************/
<> 144:ef7eb2e8f9f7 719 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
<> 144:ef7eb2e8f9f7 720 {
<> 144:ef7eb2e8f9f7 721 EFM_ASSERT(dclkPeriod < 2048);
<> 144:ef7eb2e8f9f7 722 EFM_ASSERT(start < 2048);
<> 144:ef7eb2e8f9f7 723 EFM_ASSERT(setup < 4);
<> 144:ef7eb2e8f9f7 724 EFM_ASSERT(hold < 4);
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
<> 144:ef7eb2e8f9f7 727 | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
<> 144:ef7eb2e8f9f7 728 | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
<> 144:ef7eb2e8f9f7 729 | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
<> 144:ef7eb2e8f9f7 730 }
<> 144:ef7eb2e8f9f7 731 #endif
<> 144:ef7eb2e8f9f7 732
AnnaBridge 179:b0033dcd6934 733 #if !defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 734 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 735 * @brief
<> 144:ef7eb2e8f9f7 736 * Configure read operation parameters for selected bank
<> 144:ef7eb2e8f9f7 737 *
<> 144:ef7eb2e8f9f7 738 * @param[in] banks
<> 144:ef7eb2e8f9f7 739 * Mask of memory bank(s) to configure write timing for
<> 144:ef7eb2e8f9f7 740 *
<> 144:ef7eb2e8f9f7 741 * @param[in] pageMode
<> 144:ef7eb2e8f9f7 742 * Enables or disables half cycle WE strobe in last strobe cycle
<> 144:ef7eb2e8f9f7 743 *
<> 144:ef7eb2e8f9f7 744 * @param[in] prefetch
<> 144:ef7eb2e8f9f7 745 * Enables or disables half cycle WE strobe in last strobe cycle
<> 144:ef7eb2e8f9f7 746 *
<> 144:ef7eb2e8f9f7 747 * @param[in] halfRE
<> 144:ef7eb2e8f9f7 748 * Enables or disables half cycle WE strobe in last strobe cycle
<> 144:ef7eb2e8f9f7 749 ******************************************************************************/
<> 144:ef7eb2e8f9f7 750 void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
<> 144:ef7eb2e8f9f7 751 {
AnnaBridge 179:b0033dcd6934 752 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 753 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Configure read operation parameters */
AnnaBridge 179:b0033dcd6934 756 if ( banks & EBI_BANK0 ) {
<> 144:ef7eb2e8f9f7 757 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
<> 144:ef7eb2e8f9f7 758 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
<> 144:ef7eb2e8f9f7 759 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
<> 144:ef7eb2e8f9f7 760 }
AnnaBridge 179:b0033dcd6934 761 if ( banks & EBI_BANK1 ) {
<> 144:ef7eb2e8f9f7 762 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
<> 144:ef7eb2e8f9f7 763 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
<> 144:ef7eb2e8f9f7 764 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
<> 144:ef7eb2e8f9f7 765 }
AnnaBridge 179:b0033dcd6934 766 if ( banks & EBI_BANK2 ) {
<> 144:ef7eb2e8f9f7 767 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
<> 144:ef7eb2e8f9f7 768 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
<> 144:ef7eb2e8f9f7 769 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
<> 144:ef7eb2e8f9f7 770 }
AnnaBridge 179:b0033dcd6934 771 if ( banks & EBI_BANK3 ) {
<> 144:ef7eb2e8f9f7 772 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
<> 144:ef7eb2e8f9f7 773 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
<> 144:ef7eb2e8f9f7 774 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
<> 144:ef7eb2e8f9f7 775 }
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 779 * @brief
<> 144:ef7eb2e8f9f7 780 * Configure timing values of read bus accesses
<> 144:ef7eb2e8f9f7 781 *
<> 144:ef7eb2e8f9f7 782 * @param[in] banks
<> 144:ef7eb2e8f9f7 783 * Mask of memory bank(s) to configure timing for
<> 144:ef7eb2e8f9f7 784 *
<> 144:ef7eb2e8f9f7 785 * @param[in] setupCycles
<> 144:ef7eb2e8f9f7 786 * Number of clock cycles for address setup before REn is asserted
<> 144:ef7eb2e8f9f7 787 *
<> 144:ef7eb2e8f9f7 788 * @param[in] strobeCycles
<> 144:ef7eb2e8f9f7 789 * The number of cycles the REn is held active. After the specified number of
<> 144:ef7eb2e8f9f7 790 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
<> 144:ef7eb2e8f9f7 791 *
<> 144:ef7eb2e8f9f7 792 * @param[in] holdCycles
<> 144:ef7eb2e8f9f7 793 * The number of cycles CSn is held active after the REn is dessarted
<> 144:ef7eb2e8f9f7 794 ******************************************************************************/
<> 144:ef7eb2e8f9f7 795 void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 uint32_t readTiming;
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 800 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Check that timings are within limits */
<> 144:ef7eb2e8f9f7 803 EFM_ASSERT(setupCycles < 4);
<> 144:ef7eb2e8f9f7 804 EFM_ASSERT(strobeCycles < 64);
<> 144:ef7eb2e8f9f7 805 EFM_ASSERT(holdCycles < 4);
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Configure timing values */
<> 144:ef7eb2e8f9f7 808 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
<> 144:ef7eb2e8f9f7 809 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
<> 144:ef7eb2e8f9f7 810 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
<> 144:ef7eb2e8f9f7 811
AnnaBridge 179:b0033dcd6934 812 if (banks & EBI_BANK0) {
<> 144:ef7eb2e8f9f7 813 EBI->RDTIMING = (EBI->RDTIMING
<> 144:ef7eb2e8f9f7 814 & ~(_EBI_RDTIMING_RDSETUP_MASK
<> 144:ef7eb2e8f9f7 815 | _EBI_RDTIMING_RDSTRB_MASK
<> 144:ef7eb2e8f9f7 816 | _EBI_RDTIMING_RDHOLD_MASK))
<> 144:ef7eb2e8f9f7 817 | readTiming;
<> 144:ef7eb2e8f9f7 818 }
AnnaBridge 179:b0033dcd6934 819 if (banks & EBI_BANK1) {
<> 144:ef7eb2e8f9f7 820 EBI->RDTIMING1 = (EBI->RDTIMING1
<> 144:ef7eb2e8f9f7 821 & ~(_EBI_RDTIMING1_RDSETUP_MASK
AnnaBridge 179:b0033dcd6934 822 | _EBI_RDTIMING1_RDSTRB_MASK
AnnaBridge 179:b0033dcd6934 823 | _EBI_RDTIMING1_RDHOLD_MASK))
<> 144:ef7eb2e8f9f7 824 | readTiming;
<> 144:ef7eb2e8f9f7 825 }
AnnaBridge 179:b0033dcd6934 826 if (banks & EBI_BANK2) {
<> 144:ef7eb2e8f9f7 827 EBI->RDTIMING2 = (EBI->RDTIMING2
<> 144:ef7eb2e8f9f7 828 & ~(_EBI_RDTIMING2_RDSETUP_MASK
<> 144:ef7eb2e8f9f7 829 | _EBI_RDTIMING2_RDSTRB_MASK
<> 144:ef7eb2e8f9f7 830 | _EBI_RDTIMING2_RDHOLD_MASK))
<> 144:ef7eb2e8f9f7 831 | readTiming;
<> 144:ef7eb2e8f9f7 832 }
AnnaBridge 179:b0033dcd6934 833 if (banks & EBI_BANK3) {
<> 144:ef7eb2e8f9f7 834 EBI->RDTIMING3 = (EBI->RDTIMING3
<> 144:ef7eb2e8f9f7 835 & ~(_EBI_RDTIMING3_RDSETUP_MASK
<> 144:ef7eb2e8f9f7 836 | _EBI_RDTIMING3_RDSTRB_MASK
<> 144:ef7eb2e8f9f7 837 | _EBI_RDTIMING3_RDHOLD_MASK))
<> 144:ef7eb2e8f9f7 838 | readTiming;
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 843 * @brief
<> 144:ef7eb2e8f9f7 844 * Configure write operation parameters for selected bank
<> 144:ef7eb2e8f9f7 845 *
<> 144:ef7eb2e8f9f7 846 * @param[in] banks
<> 144:ef7eb2e8f9f7 847 * Mask of memory bank(s) to configure write timing for
<> 144:ef7eb2e8f9f7 848 *
<> 144:ef7eb2e8f9f7 849 * @param[in] writeBufDisable
<> 144:ef7eb2e8f9f7 850 * If true, disable the write buffer
<> 144:ef7eb2e8f9f7 851 *
<> 144:ef7eb2e8f9f7 852 * @param[in] halfWE
<> 144:ef7eb2e8f9f7 853 * Enables or disables half cycle WE strobe in last strobe cycle
<> 144:ef7eb2e8f9f7 854 ******************************************************************************/
<> 144:ef7eb2e8f9f7 855 void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 858 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /* Configure write operation parameters */
AnnaBridge 179:b0033dcd6934 861 if ( banks & EBI_BANK0 ) {
<> 144:ef7eb2e8f9f7 862 BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
<> 144:ef7eb2e8f9f7 863 BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
<> 144:ef7eb2e8f9f7 864 }
AnnaBridge 179:b0033dcd6934 865 if ( banks & EBI_BANK1 ) {
<> 144:ef7eb2e8f9f7 866 BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
<> 144:ef7eb2e8f9f7 867 BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
<> 144:ef7eb2e8f9f7 868 }
AnnaBridge 179:b0033dcd6934 869 if ( banks & EBI_BANK2 ) {
<> 144:ef7eb2e8f9f7 870 BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
<> 144:ef7eb2e8f9f7 871 BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
<> 144:ef7eb2e8f9f7 872 }
AnnaBridge 179:b0033dcd6934 873 if ( banks & EBI_BANK3 ) {
<> 144:ef7eb2e8f9f7 874 BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
<> 144:ef7eb2e8f9f7 875 BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 880 * @brief
<> 144:ef7eb2e8f9f7 881 * Configure timing values of write bus accesses
<> 144:ef7eb2e8f9f7 882 *
<> 144:ef7eb2e8f9f7 883 * @param[in] banks
<> 144:ef7eb2e8f9f7 884 * Mask of memory bank(s) to configure write timing for
<> 144:ef7eb2e8f9f7 885 *
<> 144:ef7eb2e8f9f7 886 * @param[in] setupCycles
<> 144:ef7eb2e8f9f7 887 * Number of clock cycles for address setup before WEn is asserted
<> 144:ef7eb2e8f9f7 888 *
<> 144:ef7eb2e8f9f7 889 * @param[in] strobeCycles
<> 144:ef7eb2e8f9f7 890 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
<> 144:ef7eb2e8f9f7 891 *
<> 144:ef7eb2e8f9f7 892 * @param[in] holdCycles
<> 144:ef7eb2e8f9f7 893 * Number of cycles CSn is held active after the WEn is deasserted
<> 144:ef7eb2e8f9f7 894 ******************************************************************************/
<> 144:ef7eb2e8f9f7 895 void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
<> 144:ef7eb2e8f9f7 896 {
<> 144:ef7eb2e8f9f7 897 uint32_t writeTiming;
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 900 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* Check that timings are within limits */
<> 144:ef7eb2e8f9f7 903 EFM_ASSERT(setupCycles < 4);
<> 144:ef7eb2e8f9f7 904 EFM_ASSERT(strobeCycles < 64);
<> 144:ef7eb2e8f9f7 905 EFM_ASSERT(holdCycles < 4);
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Configure timing values */
<> 144:ef7eb2e8f9f7 908 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
<> 144:ef7eb2e8f9f7 909 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
<> 144:ef7eb2e8f9f7 910 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
<> 144:ef7eb2e8f9f7 911
AnnaBridge 179:b0033dcd6934 912 if (banks & EBI_BANK0) {
<> 144:ef7eb2e8f9f7 913 EBI->WRTIMING = (EBI->WRTIMING
<> 144:ef7eb2e8f9f7 914 & ~(_EBI_WRTIMING_WRSETUP_MASK
<> 144:ef7eb2e8f9f7 915 | _EBI_WRTIMING_WRSTRB_MASK
<> 144:ef7eb2e8f9f7 916 | _EBI_WRTIMING_WRHOLD_MASK))
<> 144:ef7eb2e8f9f7 917 | writeTiming;
<> 144:ef7eb2e8f9f7 918 }
AnnaBridge 179:b0033dcd6934 919 if (banks & EBI_BANK1) {
<> 144:ef7eb2e8f9f7 920 EBI->WRTIMING1 = (EBI->WRTIMING1
<> 144:ef7eb2e8f9f7 921 & ~(_EBI_WRTIMING1_WRSETUP_MASK
<> 144:ef7eb2e8f9f7 922 | _EBI_WRTIMING1_WRSTRB_MASK
<> 144:ef7eb2e8f9f7 923 | _EBI_WRTIMING1_WRHOLD_MASK))
<> 144:ef7eb2e8f9f7 924 | writeTiming;
<> 144:ef7eb2e8f9f7 925 }
AnnaBridge 179:b0033dcd6934 926 if (banks & EBI_BANK2) {
<> 144:ef7eb2e8f9f7 927 EBI->WRTIMING2 = (EBI->WRTIMING2
<> 144:ef7eb2e8f9f7 928 & ~(_EBI_WRTIMING2_WRSETUP_MASK
<> 144:ef7eb2e8f9f7 929 | _EBI_WRTIMING2_WRSTRB_MASK
<> 144:ef7eb2e8f9f7 930 | _EBI_WRTIMING2_WRHOLD_MASK))
<> 144:ef7eb2e8f9f7 931 | writeTiming;
<> 144:ef7eb2e8f9f7 932 }
AnnaBridge 179:b0033dcd6934 933 if (banks & EBI_BANK3) {
<> 144:ef7eb2e8f9f7 934 EBI->WRTIMING3 = (EBI->WRTIMING3
<> 144:ef7eb2e8f9f7 935 & ~(_EBI_WRTIMING3_WRSETUP_MASK
<> 144:ef7eb2e8f9f7 936 | _EBI_WRTIMING3_WRSTRB_MASK
<> 144:ef7eb2e8f9f7 937 | _EBI_WRTIMING3_WRHOLD_MASK))
<> 144:ef7eb2e8f9f7 938 | writeTiming;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940 }
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 943 * @brief
<> 144:ef7eb2e8f9f7 944 * Configure address operation parameters for selected bank
<> 144:ef7eb2e8f9f7 945 *
<> 144:ef7eb2e8f9f7 946 * @param[in] banks
<> 144:ef7eb2e8f9f7 947 * Mask of memory bank(s) to configure write timing for
<> 144:ef7eb2e8f9f7 948 *
<> 144:ef7eb2e8f9f7 949 * @param[in] halfALE
<> 144:ef7eb2e8f9f7 950 * Enables or disables half cycle ALE strobe in last strobe cycle
<> 144:ef7eb2e8f9f7 951 ******************************************************************************/
<> 144:ef7eb2e8f9f7 952 void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
<> 144:ef7eb2e8f9f7 953 {
<> 144:ef7eb2e8f9f7 954 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 955 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 956
AnnaBridge 179:b0033dcd6934 957 if ( banks & EBI_BANK0 ) {
<> 144:ef7eb2e8f9f7 958 BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
<> 144:ef7eb2e8f9f7 959 }
AnnaBridge 179:b0033dcd6934 960 if ( banks & EBI_BANK1 ) {
<> 144:ef7eb2e8f9f7 961 BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
<> 144:ef7eb2e8f9f7 962 }
AnnaBridge 179:b0033dcd6934 963 if ( banks & EBI_BANK2 ) {
<> 144:ef7eb2e8f9f7 964 BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
<> 144:ef7eb2e8f9f7 965 }
AnnaBridge 179:b0033dcd6934 966 if ( banks & EBI_BANK3 ) {
<> 144:ef7eb2e8f9f7 967 BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 972 * @brief
<> 144:ef7eb2e8f9f7 973 * Configure timing values of address latch bus accesses
<> 144:ef7eb2e8f9f7 974 *
<> 144:ef7eb2e8f9f7 975 * @param[in] banks
<> 144:ef7eb2e8f9f7 976 * Mask of memory bank(s) to configure address timing for
<> 144:ef7eb2e8f9f7 977 *
<> 144:ef7eb2e8f9f7 978 * @param[in] setupCycles
<> 144:ef7eb2e8f9f7 979 * Sets the number of cycles the address is held after ALE is asserted
<> 144:ef7eb2e8f9f7 980 *
<> 144:ef7eb2e8f9f7 981 * @param[in] holdCycles
<> 144:ef7eb2e8f9f7 982 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
<> 144:ef7eb2e8f9f7 983 * ALE is asserted. If set 0, 1 cycle is inserted by HW
<> 144:ef7eb2e8f9f7 984 ******************************************************************************/
<> 144:ef7eb2e8f9f7 985 void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 uint32_t addressLatchTiming;
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 990 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /* Check that timing values are within limits */
<> 144:ef7eb2e8f9f7 993 EFM_ASSERT(setupCycles < 4);
<> 144:ef7eb2e8f9f7 994 EFM_ASSERT(holdCycles < 4);
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Configure address latch timing values */
<> 144:ef7eb2e8f9f7 997 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
<> 144:ef7eb2e8f9f7 998 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
<> 144:ef7eb2e8f9f7 999
AnnaBridge 179:b0033dcd6934 1000 if (banks & EBI_BANK0) {
<> 144:ef7eb2e8f9f7 1001 EBI->ADDRTIMING = (EBI->ADDRTIMING
<> 144:ef7eb2e8f9f7 1002 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
<> 144:ef7eb2e8f9f7 1003 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
<> 144:ef7eb2e8f9f7 1004 | addressLatchTiming;
<> 144:ef7eb2e8f9f7 1005 }
AnnaBridge 179:b0033dcd6934 1006 if (banks & EBI_BANK1) {
<> 144:ef7eb2e8f9f7 1007 EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
<> 144:ef7eb2e8f9f7 1008 & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
<> 144:ef7eb2e8f9f7 1009 | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
<> 144:ef7eb2e8f9f7 1010 | addressLatchTiming;
<> 144:ef7eb2e8f9f7 1011 }
AnnaBridge 179:b0033dcd6934 1012 if (banks & EBI_BANK2) {
<> 144:ef7eb2e8f9f7 1013 EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
<> 144:ef7eb2e8f9f7 1014 & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
<> 144:ef7eb2e8f9f7 1015 | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
<> 144:ef7eb2e8f9f7 1016 | addressLatchTiming;
<> 144:ef7eb2e8f9f7 1017 }
AnnaBridge 179:b0033dcd6934 1018 if (banks & EBI_BANK3) {
<> 144:ef7eb2e8f9f7 1019 EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
<> 144:ef7eb2e8f9f7 1020 & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
<> 144:ef7eb2e8f9f7 1021 | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
<> 144:ef7eb2e8f9f7 1022 | addressLatchTiming;
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1027 * @brief
<> 144:ef7eb2e8f9f7 1028 * Configure EBI pin polarity for selected bank(s) for devices with individual
<> 144:ef7eb2e8f9f7 1029 * timing support
<> 144:ef7eb2e8f9f7 1030 *
<> 144:ef7eb2e8f9f7 1031 * @param[in] banks
<> 144:ef7eb2e8f9f7 1032 * Mask of memory bank(s) to configure polarity for
<> 144:ef7eb2e8f9f7 1033 *
<> 144:ef7eb2e8f9f7 1034 * @param[in] line
<> 144:ef7eb2e8f9f7 1035 * Which pin/line to configure
<> 144:ef7eb2e8f9f7 1036 *
<> 144:ef7eb2e8f9f7 1037 * @param[in] polarity
<> 144:ef7eb2e8f9f7 1038 * Active high, or active low
<> 144:ef7eb2e8f9f7 1039 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1040 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 uint32_t bankSet = 0;
<> 144:ef7eb2e8f9f7 1043 volatile uint32_t *polRegister = 0;
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 1046 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 1047
AnnaBridge 179:b0033dcd6934 1048 while (banks) {
AnnaBridge 179:b0033dcd6934 1049 if (banks & EBI_BANK0) {
<> 144:ef7eb2e8f9f7 1050 polRegister = &EBI->POLARITY;
<> 144:ef7eb2e8f9f7 1051 bankSet = EBI_BANK0;
<> 144:ef7eb2e8f9f7 1052 }
AnnaBridge 179:b0033dcd6934 1053 if (banks & EBI_BANK1) {
<> 144:ef7eb2e8f9f7 1054 polRegister = &EBI->POLARITY1;
<> 144:ef7eb2e8f9f7 1055 bankSet = EBI_BANK1;
<> 144:ef7eb2e8f9f7 1056 }
AnnaBridge 179:b0033dcd6934 1057 if (banks & EBI_BANK2) {
<> 144:ef7eb2e8f9f7 1058 polRegister = &EBI->POLARITY2;
<> 144:ef7eb2e8f9f7 1059 bankSet = EBI_BANK2;
<> 144:ef7eb2e8f9f7 1060 }
AnnaBridge 179:b0033dcd6934 1061 if (banks & EBI_BANK3) {
<> 144:ef7eb2e8f9f7 1062 polRegister = &EBI->POLARITY3;
<> 144:ef7eb2e8f9f7 1063 bankSet = EBI_BANK3;
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* What line to configure */
AnnaBridge 179:b0033dcd6934 1067 switch (line) {
<> 144:ef7eb2e8f9f7 1068 case ebiLineARDY:
<> 144:ef7eb2e8f9f7 1069 BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1070 break;
<> 144:ef7eb2e8f9f7 1071 case ebiLineALE:
<> 144:ef7eb2e8f9f7 1072 BUS_RegBitWrite(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1073 break;
<> 144:ef7eb2e8f9f7 1074 case ebiLineWE:
<> 144:ef7eb2e8f9f7 1075 BUS_RegBitWrite(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1076 break;
<> 144:ef7eb2e8f9f7 1077 case ebiLineRE:
<> 144:ef7eb2e8f9f7 1078 BUS_RegBitWrite(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1079 break;
<> 144:ef7eb2e8f9f7 1080 case ebiLineCS:
<> 144:ef7eb2e8f9f7 1081 BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1082 break;
<> 144:ef7eb2e8f9f7 1083 case ebiLineBL:
<> 144:ef7eb2e8f9f7 1084 BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1085 break;
<> 144:ef7eb2e8f9f7 1086 case ebiLineTFTVSync:
<> 144:ef7eb2e8f9f7 1087 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1088 break;
<> 144:ef7eb2e8f9f7 1089 case ebiLineTFTHSync:
<> 144:ef7eb2e8f9f7 1090 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1091 break;
<> 144:ef7eb2e8f9f7 1092 case ebiLineTFTDataEn:
<> 144:ef7eb2e8f9f7 1093 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1094 break;
<> 144:ef7eb2e8f9f7 1095 case ebiLineTFTDClk:
<> 144:ef7eb2e8f9f7 1096 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1097 break;
<> 144:ef7eb2e8f9f7 1098 case ebiLineTFTCS:
<> 144:ef7eb2e8f9f7 1099 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
<> 144:ef7eb2e8f9f7 1100 break;
<> 144:ef7eb2e8f9f7 1101 default:
<> 144:ef7eb2e8f9f7 1102 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1103 break;
<> 144:ef7eb2e8f9f7 1104 }
<> 144:ef7eb2e8f9f7 1105 banks = banks & ~bankSet;
<> 144:ef7eb2e8f9f7 1106 }
<> 144:ef7eb2e8f9f7 1107 }
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1110 * @brief
<> 144:ef7eb2e8f9f7 1111 * Configure Byte Lane Enable for select banks
<> 144:ef7eb2e8f9f7 1112 * timing support
<> 144:ef7eb2e8f9f7 1113 *
<> 144:ef7eb2e8f9f7 1114 * @param[in] banks
<> 144:ef7eb2e8f9f7 1115 * Mask of memory bank(s) to configure polarity for
<> 144:ef7eb2e8f9f7 1116 *
<> 144:ef7eb2e8f9f7 1117 * @param[in] enable
<> 144:ef7eb2e8f9f7 1118 * Flag
<> 144:ef7eb2e8f9f7 1119 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1120 void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
<> 144:ef7eb2e8f9f7 1121 {
<> 144:ef7eb2e8f9f7 1122 /* Verify only valid banks are used */
<> 144:ef7eb2e8f9f7 1123 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /* Configure byte lane support for each selected bank */
AnnaBridge 179:b0033dcd6934 1126 if (banks & EBI_BANK0) {
<> 144:ef7eb2e8f9f7 1127 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
<> 144:ef7eb2e8f9f7 1128 }
AnnaBridge 179:b0033dcd6934 1129 if (banks & EBI_BANK1) {
<> 144:ef7eb2e8f9f7 1130 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
<> 144:ef7eb2e8f9f7 1131 }
AnnaBridge 179:b0033dcd6934 1132 if (banks & EBI_BANK2) {
<> 144:ef7eb2e8f9f7 1133 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
<> 144:ef7eb2e8f9f7 1134 }
AnnaBridge 179:b0033dcd6934 1135 if (banks & EBI_BANK3) {
<> 144:ef7eb2e8f9f7 1136 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
<> 144:ef7eb2e8f9f7 1137 }
<> 144:ef7eb2e8f9f7 1138 }
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1141 * @brief
<> 144:ef7eb2e8f9f7 1142 * Configure Alternate Address Map support
<> 144:ef7eb2e8f9f7 1143 * Enables or disables 256MB address range for all banks
<> 144:ef7eb2e8f9f7 1144 *
<> 144:ef7eb2e8f9f7 1145 * @param[in] enable
<> 144:ef7eb2e8f9f7 1146 * Set or clear address map extension
<> 144:ef7eb2e8f9f7 1147 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1148 void EBI_AltMapEnable(bool enable)
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
<> 144:ef7eb2e8f9f7 1151 }
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 #endif
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /** @} (end addtogroup EBI) */
<> 150:02e0a0aed4ec 1156 /** @} (end addtogroup emlib) */
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */