mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
179:b0033dcd6934 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_dac.c
<> 150:02e0a0aed4ec 3 * @brief Digital to Analog Converter (DAC) Peripheral API
AnnaBridge 179:b0033dcd6934 4 * @version 5.3.3
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
AnnaBridge 179:b0033dcd6934 6 * # License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "em_dac.h"
<> 144:ef7eb2e8f9f7 34 #if defined(DAC_COUNT) && (DAC_COUNT > 0)
<> 144:ef7eb2e8f9f7 35 #include "em_cmu.h"
<> 144:ef7eb2e8f9f7 36 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 37 #include "em_bus.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /***************************************************************************//**
<> 150:02e0a0aed4ec 40 * @addtogroup emlib
<> 144:ef7eb2e8f9f7 41 * @{
<> 144:ef7eb2e8f9f7 42 ******************************************************************************/
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 45 * @addtogroup DAC
<> 150:02e0a0aed4ec 46 * @brief Digital to Analog Converter (DAC) Peripheral API
<> 150:02e0a0aed4ec 47 * @details
<> 150:02e0a0aed4ec 48 * This module contains functions to control the DAC peripheral of Silicon
<> 150:02e0a0aed4ec 49 * Labs 32-bit MCUs and SoCs. The DAC converts digital values to analog signals
<> 150:02e0a0aed4ec 50 * at up to 500 ksps with 12-bit accuracy. The DAC is designed for low energy
<> 150:02e0a0aed4ec 51 * consumption, but can also provide very good performance.
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 ******************************************************************************/
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*******************************************************************************
<> 144:ef7eb2e8f9f7 56 ******************************* DEFINES ***********************************
<> 144:ef7eb2e8f9f7 57 ******************************************************************************/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** Validation of DAC channel for assert statements. */
<> 144:ef7eb2e8f9f7 62 #define DAC_CH_VALID(ch) ((ch) <= 1)
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /** Max DAC clock */
<> 144:ef7eb2e8f9f7 65 #define DAC_MAX_CLOCK 1000000
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /** @endcond */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /*******************************************************************************
<> 144:ef7eb2e8f9f7 70 ************************** GLOBAL FUNCTIONS *******************************
<> 144:ef7eb2e8f9f7 71 ******************************************************************************/
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 74 * @brief
<> 144:ef7eb2e8f9f7 75 * Enable/disable DAC channel.
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * @param[in] dac
<> 144:ef7eb2e8f9f7 78 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * @param[in] ch
<> 144:ef7eb2e8f9f7 81 * Channel to enable/disable.
<> 144:ef7eb2e8f9f7 82 *
<> 144:ef7eb2e8f9f7 83 * @param[in] enable
<> 144:ef7eb2e8f9f7 84 * true to enable DAC channel, false to disable.
<> 144:ef7eb2e8f9f7 85 ******************************************************************************/
<> 144:ef7eb2e8f9f7 86 void DAC_Enable(DAC_TypeDef *dac, unsigned int ch, bool enable)
<> 144:ef7eb2e8f9f7 87 {
<> 144:ef7eb2e8f9f7 88 volatile uint32_t *reg;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 EFM_ASSERT(DAC_REF_VALID(dac));
<> 144:ef7eb2e8f9f7 91 EFM_ASSERT(DAC_CH_VALID(ch));
<> 144:ef7eb2e8f9f7 92
AnnaBridge 179:b0033dcd6934 93 if (!ch) {
<> 144:ef7eb2e8f9f7 94 reg = &(dac->CH0CTRL);
AnnaBridge 179:b0033dcd6934 95 } else {
<> 144:ef7eb2e8f9f7 96 reg = &(dac->CH1CTRL);
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 BUS_RegBitWrite(reg, _DAC_CH0CTRL_EN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 103 * @brief
<> 144:ef7eb2e8f9f7 104 * Initialize DAC.
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * @details
<> 144:ef7eb2e8f9f7 107 * Initializes common parts for both channels. In addition, channel control
<> 144:ef7eb2e8f9f7 108 * configuration must be done, please refer to DAC_InitChannel().
<> 144:ef7eb2e8f9f7 109 *
<> 144:ef7eb2e8f9f7 110 * @note
<> 144:ef7eb2e8f9f7 111 * This function will disable both channels prior to configuration.
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * @param[in] dac
<> 144:ef7eb2e8f9f7 114 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 115 *
<> 144:ef7eb2e8f9f7 116 * @param[in] init
<> 144:ef7eb2e8f9f7 117 * Pointer to DAC initialization structure.
<> 144:ef7eb2e8f9f7 118 ******************************************************************************/
<> 144:ef7eb2e8f9f7 119 void DAC_Init(DAC_TypeDef *dac, const DAC_Init_TypeDef *init)
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 uint32_t tmp;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 EFM_ASSERT(DAC_REF_VALID(dac));
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Make sure both channels are disabled. */
<> 144:ef7eb2e8f9f7 126 BUS_RegBitWrite(&(dac->CH0CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
<> 144:ef7eb2e8f9f7 127 BUS_RegBitWrite(&(dac->CH1CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Load proper calibration data depending on selected reference */
AnnaBridge 179:b0033dcd6934 130 switch (init->reference) {
<> 144:ef7eb2e8f9f7 131 case dacRef2V5:
<> 144:ef7eb2e8f9f7 132 dac->CAL = DEVINFO->DAC0CAL1;
<> 144:ef7eb2e8f9f7 133 break;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 case dacRefVDD:
<> 144:ef7eb2e8f9f7 136 dac->CAL = DEVINFO->DAC0CAL2;
<> 144:ef7eb2e8f9f7 137 break;
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 default: /* 1.25V */
<> 144:ef7eb2e8f9f7 140 dac->CAL = DEVINFO->DAC0CAL0;
<> 144:ef7eb2e8f9f7 141 break;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 tmp = ((uint32_t)(init->refresh) << _DAC_CTRL_REFRSEL_SHIFT)
<> 144:ef7eb2e8f9f7 145 | (((uint32_t)(init->prescale) << _DAC_CTRL_PRESC_SHIFT)
<> 144:ef7eb2e8f9f7 146 & _DAC_CTRL_PRESC_MASK)
<> 144:ef7eb2e8f9f7 147 | ((uint32_t)(init->reference) << _DAC_CTRL_REFSEL_SHIFT)
<> 144:ef7eb2e8f9f7 148 | ((uint32_t)(init->outMode) << _DAC_CTRL_OUTMODE_SHIFT)
<> 144:ef7eb2e8f9f7 149 | ((uint32_t)(init->convMode) << _DAC_CTRL_CONVMODE_SHIFT);
<> 144:ef7eb2e8f9f7 150
AnnaBridge 179:b0033dcd6934 151 if (init->ch0ResetPre) {
<> 144:ef7eb2e8f9f7 152 tmp |= DAC_CTRL_CH0PRESCRST;
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154
AnnaBridge 179:b0033dcd6934 155 if (init->outEnablePRS) {
<> 144:ef7eb2e8f9f7 156 tmp |= DAC_CTRL_OUTENPRS;
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
AnnaBridge 179:b0033dcd6934 159 if (init->sineEnable) {
<> 144:ef7eb2e8f9f7 160 tmp |= DAC_CTRL_SINEMODE;
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
AnnaBridge 179:b0033dcd6934 163 if (init->diff) {
<> 144:ef7eb2e8f9f7 164 tmp |= DAC_CTRL_DIFF;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 dac->CTRL = tmp;
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 171 * @brief
<> 144:ef7eb2e8f9f7 172 * Initialize DAC channel.
<> 144:ef7eb2e8f9f7 173 *
<> 144:ef7eb2e8f9f7 174 * @param[in] dac
<> 144:ef7eb2e8f9f7 175 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 176 *
<> 144:ef7eb2e8f9f7 177 * @param[in] init
<> 144:ef7eb2e8f9f7 178 * Pointer to DAC initialization structure.
<> 144:ef7eb2e8f9f7 179 *
<> 144:ef7eb2e8f9f7 180 * @param[in] ch
<> 144:ef7eb2e8f9f7 181 * Channel number to initialize.
<> 144:ef7eb2e8f9f7 182 ******************************************************************************/
<> 144:ef7eb2e8f9f7 183 void DAC_InitChannel(DAC_TypeDef *dac,
<> 144:ef7eb2e8f9f7 184 const DAC_InitChannel_TypeDef *init,
<> 144:ef7eb2e8f9f7 185 unsigned int ch)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 uint32_t tmp;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 EFM_ASSERT(DAC_REF_VALID(dac));
<> 144:ef7eb2e8f9f7 190 EFM_ASSERT(DAC_CH_VALID(ch));
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 tmp = (uint32_t)(init->prsSel) << _DAC_CH0CTRL_PRSSEL_SHIFT;
<> 144:ef7eb2e8f9f7 193
AnnaBridge 179:b0033dcd6934 194 if (init->enable) {
<> 144:ef7eb2e8f9f7 195 tmp |= DAC_CH0CTRL_EN;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
AnnaBridge 179:b0033dcd6934 198 if (init->prsEnable) {
<> 144:ef7eb2e8f9f7 199 tmp |= DAC_CH0CTRL_PRSEN;
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201
AnnaBridge 179:b0033dcd6934 202 if (init->refreshEnable) {
<> 144:ef7eb2e8f9f7 203 tmp |= DAC_CH0CTRL_REFREN;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
AnnaBridge 179:b0033dcd6934 206 if (ch) {
<> 144:ef7eb2e8f9f7 207 dac->CH1CTRL = tmp;
AnnaBridge 179:b0033dcd6934 208 } else {
<> 144:ef7eb2e8f9f7 209 dac->CH0CTRL = tmp;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 214 * @brief
<> 144:ef7eb2e8f9f7 215 * Set the output signal of a DAC channel to a given value.
<> 144:ef7eb2e8f9f7 216 *
<> 144:ef7eb2e8f9f7 217 * @details
<> 144:ef7eb2e8f9f7 218 * This function sets the output signal of a DAC channel by writing @p value
<> 144:ef7eb2e8f9f7 219 * to the corresponding CHnDATA register.
<> 144:ef7eb2e8f9f7 220 *
<> 144:ef7eb2e8f9f7 221 * @param[in] dac
<> 144:ef7eb2e8f9f7 222 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 223 *
<> 144:ef7eb2e8f9f7 224 * @param[in] channel
<> 144:ef7eb2e8f9f7 225 * Channel number to set output of.
<> 144:ef7eb2e8f9f7 226 *
<> 144:ef7eb2e8f9f7 227 * @param[in] value
<> 144:ef7eb2e8f9f7 228 * Value to write to the channel output register CHnDATA.
<> 144:ef7eb2e8f9f7 229 ******************************************************************************/
AnnaBridge 179:b0033dcd6934 230 void DAC_ChannelOutputSet(DAC_TypeDef *dac,
AnnaBridge 179:b0033dcd6934 231 unsigned int channel,
AnnaBridge 179:b0033dcd6934 232 uint32_t value)
<> 144:ef7eb2e8f9f7 233 {
AnnaBridge 179:b0033dcd6934 234 switch (channel) {
<> 144:ef7eb2e8f9f7 235 case 0:
<> 144:ef7eb2e8f9f7 236 DAC_Channel0OutputSet(dac, value);
<> 144:ef7eb2e8f9f7 237 break;
<> 144:ef7eb2e8f9f7 238 case 1:
<> 144:ef7eb2e8f9f7 239 DAC_Channel1OutputSet(dac, value);
<> 144:ef7eb2e8f9f7 240 break;
<> 144:ef7eb2e8f9f7 241 default:
<> 144:ef7eb2e8f9f7 242 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 243 break;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 248 * @brief
<> 144:ef7eb2e8f9f7 249 * Calculate prescaler value used to determine DAC clock.
<> 144:ef7eb2e8f9f7 250 *
<> 144:ef7eb2e8f9f7 251 * @details
<> 144:ef7eb2e8f9f7 252 * The DAC clock is given by: HFPERCLK / (prescale ^ 2). If the requested
<> 144:ef7eb2e8f9f7 253 * DAC frequency is low and the max prescaler value can not adjust the
<> 144:ef7eb2e8f9f7 254 * actual DAC frequency lower than the requested DAC frequency, then the
<> 144:ef7eb2e8f9f7 255 * max prescaler value is returned, resulting in a higher DAC frequency
<> 144:ef7eb2e8f9f7 256 * than requested.
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 * @param[in] dacFreq DAC frequency wanted. The frequency will automatically
<> 144:ef7eb2e8f9f7 259 * be adjusted to be below max allowed DAC clock.
<> 144:ef7eb2e8f9f7 260 *
<> 144:ef7eb2e8f9f7 261 * @param[in] hfperFreq Frequency in Hz of reference HFPER clock. Set to 0 to
<> 144:ef7eb2e8f9f7 262 * use currently defined HFPER clock setting.
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * @return
<> 144:ef7eb2e8f9f7 265 * Prescaler value to use for DAC in order to achieve a clock value
<> 144:ef7eb2e8f9f7 266 * <= @p dacFreq.
<> 144:ef7eb2e8f9f7 267 ******************************************************************************/
<> 144:ef7eb2e8f9f7 268 uint8_t DAC_PrescaleCalc(uint32_t dacFreq, uint32_t hfperFreq)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 uint32_t ret;
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Make sure selected DAC clock is below max value */
AnnaBridge 179:b0033dcd6934 273 if (dacFreq > DAC_MAX_CLOCK) {
<> 144:ef7eb2e8f9f7 274 dacFreq = DAC_MAX_CLOCK;
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Use current HFPER frequency? */
AnnaBridge 179:b0033dcd6934 278 if (!hfperFreq) {
<> 144:ef7eb2e8f9f7 279 hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Iterate in order to determine best prescale value. Only a few possible */
<> 144:ef7eb2e8f9f7 283 /* values. We start with lowest prescaler value in order to get first */
<> 144:ef7eb2e8f9f7 284 /* equal or below wanted DAC frequency value. */
AnnaBridge 179:b0033dcd6934 285 for (ret = 0; ret <= (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT); ret++) {
AnnaBridge 179:b0033dcd6934 286 if ((hfperFreq >> ret) <= dacFreq) {
<> 144:ef7eb2e8f9f7 287 break;
AnnaBridge 179:b0033dcd6934 288 }
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* If ret is higher than the max prescaler value, make sure to return
<> 144:ef7eb2e8f9f7 292 the max value. */
AnnaBridge 179:b0033dcd6934 293 if (ret > (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT)) {
<> 144:ef7eb2e8f9f7 294 ret = _DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT;
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 return (uint8_t)ret;
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 301 * @brief
<> 144:ef7eb2e8f9f7 302 * Reset DAC to same state as after a HW reset.
<> 144:ef7eb2e8f9f7 303 *
<> 144:ef7eb2e8f9f7 304 * @param[in] dac
<> 144:ef7eb2e8f9f7 305 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 306 ******************************************************************************/
<> 144:ef7eb2e8f9f7 307 void DAC_Reset(DAC_TypeDef *dac)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 /* Disable channels, before resetting other registers. */
<> 144:ef7eb2e8f9f7 310 dac->CH0CTRL = _DAC_CH0CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 311 dac->CH1CTRL = _DAC_CH1CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 312 dac->CTRL = _DAC_CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 313 dac->IEN = _DAC_IEN_RESETVALUE;
<> 144:ef7eb2e8f9f7 314 dac->IFC = _DAC_IFC_MASK;
<> 144:ef7eb2e8f9f7 315 dac->CAL = DEVINFO->DAC0CAL0;
<> 144:ef7eb2e8f9f7 316 dac->BIASPROG = _DAC_BIASPROG_RESETVALUE;
<> 144:ef7eb2e8f9f7 317 /* Do not reset route register, setting should be done independently */
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /** @} (end addtogroup DAC) */
<> 150:02e0a0aed4ec 321 /** @} (end addtogroup emlib) */
<> 144:ef7eb2e8f9f7 322 #endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */