mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
179:b0033dcd6934 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ================ Revision history ============================================
AnnaBridge 179:b0033dcd6934 2 5.3.3
AnnaBridge 179:b0033dcd6934 3 - em_cmu: 48 MHz HFRCO band selectable for devices that support it.
AnnaBridge 179:b0033dcd6934 4 - em_emu: Added macro guards for BU mode functionality for series 0 devices.
AnnaBridge 179:b0033dcd6934 5
AnnaBridge 179:b0033dcd6934 6 5.3.2
AnnaBridge 179:b0033dcd6934 7 - No changes.
AnnaBridge 179:b0033dcd6934 8
AnnaBridge 179:b0033dcd6934 9 5.3.1
AnnaBridge 179:b0033dcd6934 10 - em_opamp: Corrected reload of default calibration trims in OPAMP_Enable()
AnnaBridge 179:b0033dcd6934 11 for Series 0.
AnnaBridge 179:b0033dcd6934 12 - em_core: Fixed invalid parameter in CORE_YIELD_CRITICAL and
AnnaBridge 179:b0033dcd6934 13 CORE_YIELD_ATOMIC macros.
AnnaBridge 179:b0033dcd6934 14
AnnaBridge 179:b0033dcd6934 15 5.3.0
AnnaBridge 179:b0033dcd6934 16 - em_chip: Updated PLFRCO tuning values.
AnnaBridge 179:b0033dcd6934 17 - em_can: Fixed ID filter mask bug.
AnnaBridge 179:b0033dcd6934 18 - em_gpio: Doc updates.
AnnaBridge 179:b0033dcd6934 19 - em_gpio: Fixed bug in GPIO pin validation to enable PD9 on BGM121 modules.
AnnaBridge 179:b0033dcd6934 20 - em_ldma: Added missing signals for EFM32GG11.
AnnaBridge 179:b0033dcd6934 21
AnnaBridge 179:b0033dcd6934 22 5.2.2:
AnnaBridge 179:b0033dcd6934 23 - em_emu: Fixed bug in EMU_EM4Init(), The BUBODRSTDIS field was not initialized
AnnaBridge 179:b0033dcd6934 24 as specified in function input parameters.
AnnaBridge 179:b0033dcd6934 25
AnnaBridge 179:b0033dcd6934 26 5.2.1:
AnnaBridge 179:b0033dcd6934 27 - em_emu: Fixed a problem with handling of DCDC bypass current limiter
AnnaBridge 179:b0033dcd6934 28 that may cause brownout reset.
AnnaBridge 179:b0033dcd6934 29 - em_chip: Added workaround for errata DCDC-E206 for EFR32xG1x devices.
AnnaBridge 179:b0033dcd6934 30 - em_cmu: Fixed handling of HFCLKLE prescaling at frequencies above 64 MHz.
AnnaBridge 179:b0033dcd6934 31
AnnaBridge 179:b0033dcd6934 32 5.2.0:
AnnaBridge 179:b0033dcd6934 33 - em_cmu: Added flash wait state handling for all devices that can scale down
AnnaBridge 179:b0033dcd6934 34 the voltage.
AnnaBridge 179:b0033dcd6934 35 - em_adc: Fixed bug where ADC SINGLECTRLX register fields VREFSEL, PRSSEL and
AnnaBridge 179:b0033dcd6934 36 FIFOOFACT was not cleared when calling ADC_InitSingle().
AnnaBridge 179:b0033dcd6934 37 - em_msc: Removed call to SystemCoreClockGet() in MSC_Init.
AnnaBridge 179:b0033dcd6934 38 - em_msc: MSC_WriteWordFast() can now only be used when executing code from
AnnaBridge 179:b0033dcd6934 39 RAM on parts that include a flash write buffer.
AnnaBridge 179:b0033dcd6934 40 - em_emu: Using VMON calibration values to set voltage thresholds when
AnnaBridge 179:b0033dcd6934 41 calling EMU_VmonInit() and EMU_VmonHystInit(). The DI page contains
AnnaBridge 179:b0033dcd6934 42 calibration values for 1.86 V and 2.98 V for each VMON channel. Updated
AnnaBridge 179:b0033dcd6934 43 VMON supported voltage range to 1.62V-3.4V.
AnnaBridge 179:b0033dcd6934 44 - em_emu: Added EMU_Save() and changed EMU_EnterEM2() and EMU_EnterEM3()
AnnaBridge 179:b0033dcd6934 45 to only save the state if the restore parameter is true.
AnnaBridge 179:b0033dcd6934 46 - em_usart: Fixed USART async baudrate calculation for EFM32HG devices.
AnnaBridge 179:b0033dcd6934 47 The extra fractional bits in the CLKDIV register was not used.
AnnaBridge 179:b0033dcd6934 48 - Added support for EFM32GG11B devices. This includes new modules for
AnnaBridge 179:b0033dcd6934 49 Quad SPI (em_qspi) and CAN (em_can). This also includes
AnnaBridge 179:b0033dcd6934 50 changes to other emlib modules in order to support the changes in the
AnnaBridge 179:b0033dcd6934 51 register interface of the new device.
AnnaBridge 179:b0033dcd6934 52 - em_cmu: Added DPLL support. Added support for asynchronous clocks for
AnnaBridge 179:b0033dcd6934 53 ADC, reference clocks for QSPI and SDIO and USB rate clock. Added
AnnaBridge 179:b0033dcd6934 54 functions to support the USHFRCO and clock select for HFXOX2.
AnnaBridge 179:b0033dcd6934 55 - em_gpio: Using single cycle set and clear of DOUT on platforms
AnnaBridge 179:b0033dcd6934 56 where this is supported.
AnnaBridge 179:b0033dcd6934 57 - em_lesense: Added configuration of DACCHnEN and DACSTARTUP bits in
AnnaBridge 179:b0033dcd6934 58 LESENSE->PERCTRL in LESENSE_Init() and init struct. Also changed
AnnaBridge 179:b0033dcd6934 59 default values for LESENSE_AltExDesc_TypeDef and
AnnaBridge 179:b0033dcd6934 60 LESENSE_ChDesc_TypeDef to be disabled by default.
AnnaBridge 179:b0033dcd6934 61
AnnaBridge 179:b0033dcd6934 62 5.1.3:
AnnaBridge 179:b0033dcd6934 63 - No changes.
AnnaBridge 179:b0033dcd6934 64
<> 161:2cc1468da177 65 5.1.2:
<> 161:2cc1468da177 66 Misc. bugfixes and improvements.
<> 161:2cc1468da177 67
<> 161:2cc1468da177 68 5.1.1:
<> 161:2cc1468da177 69 - Enabled errata CMU_E113 workaround for EFM32GG revE.
<> 161:2cc1468da177 70
<> 161:2cc1468da177 71 5.1.0:
<> 161:2cc1468da177 72 - em_timer: Added support for WTIMER0 and WTIMER1. Added EFM_ASSERT in
<> 161:2cc1468da177 73 em_timer to check that operations on a 16 bit timer is always <= 0xFFFF.
<> 161:2cc1468da177 74 - em_usart: Updated the baudrate sync calculation in USART_BaudrateSyncSet().
<> 161:2cc1468da177 75 The calculated baudrate is not using any fractional bits and it is always
<> 161:2cc1468da177 76 lower than or equal to the specified frequency.
<> 161:2cc1468da177 77 - em_emu: added function EMU_DCDCConductionModeSet() to allow switching
<> 161:2cc1468da177 78 between DCDC Low-Noise Continuous Conduction Mode (CCM) and
<> 161:2cc1468da177 79 Discontinuous Conduction Mode (DCM).
<> 161:2cc1468da177 80 - SYSTEM_GetSRAMSize() updated to return size of SRAM excluding RAMH for EFR32xG1.
<> 161:2cc1468da177 81 - em_csen: Added support for CSEN (Capacitive Sense Module).
<> 161:2cc1468da177 82 - em_adc: updated ADC_PosSel_TypeDef enum names.
<> 161:2cc1468da177 83 - em_vdac: Added support for VDAC (voltage DAC).
<> 161:2cc1468da177 84 - em_smu: Added support for SMU (Security Management Unit) module.
<> 161:2cc1468da177 85 SMU is used to restrict access to device peripherals.
<> 161:2cc1468da177 86 - Updated emlib to use the _SILICON_LABS_32B_SERIES_x,
<> 161:2cc1468da177 87 _SILICON_LABS_32B_SERIES_x_CONFIG and _SILICON_LABS_GECKO_INTERNAL_SDID_x
<> 161:2cc1468da177 88 macros instead of the _SILICON_LABS_32B_PLATFORM_x and
<> 161:2cc1468da177 89 _SILICON_LABS_32B_PLATFORM_x_GEN_x macros.
<> 161:2cc1468da177 90 - em_rtcc: added workarounds for errata RTCC_E203 and RTCC_E204 for
<> 161:2cc1468da177 91 EFR32xG12, EFM32xG12, EFR32xG13 and EFM32xG13 devices.
<> 161:2cc1468da177 92 - em_lesense: added LESENSE_DecoderPrsOut() for configuring PRS output
<> 161:2cc1468da177 93 from the LESENSE decoder on EFM32xG12 and EFR32xG12.
<> 161:2cc1468da177 94 - em_lesense: added support for the new evaluation modes for EFM32xG12 and
<> 161:2cc1468da177 95 EFR32xG12.
<> 161:2cc1468da177 96 - em_emu: added EMU_RamPowerDown() function for powering down a memory range
<> 161:2cc1468da177 97 and deprecating EMU_MemPwrDown().
<> 161:2cc1468da177 98 - em_emu: added support for voltage scaling.
<> 161:2cc1468da177 99 - em_emu: added support for EM2 and 3 peripheral retention control.
<> 161:2cc1468da177 100 - em_chip: added current consumption fixes for EFM32xG12 and EFR32xG12.
<> 161:2cc1468da177 101 - em_emu: added support for DCDC EM01-LP mode.
<> 161:2cc1468da177 102 - em_lesense: Support for Series 1 devices
<> 161:2cc1468da177 103 - em_acmp: Added ACMP_ExternalInputSelect() which is used when the ACMP is
<> 161:2cc1468da177 104 controlled by an external module like LESENSE.
<> 161:2cc1468da177 105
<> 150:02e0a0aed4ec 106 5.0.0:
<> 150:02e0a0aed4ec 107 - em_core: New module, contains API for enabling/disabling interrupts
<> 150:02e0a0aed4ec 108 and implementing critical regions.
<> 150:02e0a0aed4ec 109 em_core replaces em_int which is deprecated and marked for removal in a
<> 150:02e0a0aed4ec 110 later release.
<> 150:02e0a0aed4ec 111 - em_emu: Added EMU_SetBiasMode() for Series 1 Configuration 1 devices.
<> 150:02e0a0aed4ec 112 - em_chip: Adding EMU_E210 errata fix in CHIP_Init().
<> 150:02e0a0aed4ec 113 - em_adc: Changed default value of negSel in ADC_INITSINGLE_DEFAULT
<> 150:02e0a0aed4ec 114 from adcNegSelAPORT0XCH1 to adcNegSelVSS.
<> 150:02e0a0aed4ec 115 - em_emu, em_cmu, em_chip, em_system: Added support for Series 1,
<> 150:02e0a0aed4ec 116 Configuration 2 parts (eg. EFR32MG12)
<> 150:02e0a0aed4ec 117 - em_gpio: Fixed GPIO_ExtIntConfig() to enable correct interrupt number on
<> 150:02e0a0aed4ec 118 Series 1 devices.
<> 150:02e0a0aed4ec 119 - em_ldma: Updated LDMA_Init() and LDMA_StartTransfer() to support pointers
<> 150:02e0a0aed4ec 120 to const memory.
<> 150:02e0a0aed4ec 121 - em_ldma: Adding LDMA_DESCRIPTOR_SINGLE_P2P_BYTE which can be used when
<> 150:02e0a0aed4ec 122 transfering bytes from one peripheral to another peripheral.
<> 150:02e0a0aed4ec 123 - em_i2c: Fixed bug that may clear IEN bits set by the user.
<> 150:02e0a0aed4ec 124 - em_emu: DCDC LN mode RCOBAND is now set based on LNFORCECCM.
<> 150:02e0a0aed4ec 125 - em_emu: Member dcdcLnCompCtrl added to EMU_DCDCInit_TypeDef. This parameter
<> 150:02e0a0aed4ec 126 allows configuraiton of 1uF or 4.7uF DCDC capacitor. 1uF is default for
<> 150:02e0a0aed4ec 127 Series 1 Device Configuration 1 while 4.7 is default for Series 1
<> 150:02e0a0aed4ec 128 Device Configuration 2 and later.
<> 150:02e0a0aed4ec 129 - Updated documentation with more code examples for em_assert, em_common,
<> 150:02e0a0aed4ec 130 em_cryotimer, em_gpcrc, em_ldma, em_msc, em_ramfunc, em_system, em_usart.
<> 150:02e0a0aed4ec 131
<> 150:02e0a0aed4ec 132 4.4.0:
<> 150:02e0a0aed4ec 133 - em_emu: Putting DCDC in bypass mode before entering EM4S.
<> 150:02e0a0aed4ec 134 - em_cmu: In the CMU_HFXOInit_TypeDef struct the following members have been
<> 150:02e0a0aed4ec 135 deprecated and are no longer in use: autoStartEm01, autoSelEm01, and
<> 150:02e0a0aed4ec 136 autoStartSelOnRacWakeup. Any application using the HFXO autostart feature
<> 150:02e0a0aed4ec 137 must use the CMU_HFXOAutostartEnable() function instead.
<> 150:02e0a0aed4ec 138 - em_emu: Updating DCDC LP comparator bias thresholds for EM2/3/4 according to
<> 150:02e0a0aed4ec 139 updated reference manual. The thresholds are compared to the
<> 150:02e0a0aed4ec 140 em234LoadCurrent_uA value of the EMU_DCDCInit_TypeDef struct.
<> 150:02e0a0aed4ec 141 - em_msc: Fix for errata FLASH_E201 - Potential program failure after power on
<> 150:02e0a0aed4ec 142 After a flash write the first word is checked to verify write operation. On
<> 150:02e0a0aed4ec 143 a verification failure the first word is re-programmed.
<> 150:02e0a0aed4ec 144 - em_adc: Enforcing at least 8 cycle aquisition time when reading ADC internal
<> 150:02e0a0aed4ec 145 temp sensor using a 1.25V reference on platform 2 generation 1 devices.
<> 150:02e0a0aed4ec 146 - em_adc: Setting GPBIASACC when initializing measurement of the ADC internal
<> 150:02e0a0aed4ec 147 temp sensor as documented in the reference manual.
<> 150:02e0a0aed4ec 148 - em_emu: Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H
<> 150:02e0a0aed4ec 149 - em_cmu: Added the possibility to configure external clock as HFXO
<> 150:02e0a0aed4ec 150 and LFXO source via the CMU_HFXOInit() and CMU_LFXOInit() functions.
<> 150:02e0a0aed4ec 151 - em_emu: Added EMU_EnterEM4H and EMU_EnterEM4S functions.
<> 150:02e0a0aed4ec 152 - Fixed shift bug in ADC_EM2ClockConfig_TypeDef.
<> 150:02e0a0aed4ec 153 - Added bounds check on ADC prescaler.
<> 150:02e0a0aed4ec 154 - Updated ADC_INITSCAN_DEFAULT to match ADC_ScanInputClear().
<> 150:02e0a0aed4ec 155
<> 150:02e0a0aed4ec 156 4.3.1:
<> 150:02e0a0aed4ec 157 - EFR32 and EFM32PG/JG em_cmu: Added automatic switching to HFXO
<> 150:02e0a0aed4ec 158 PEAKDETSHUNTOPTMODE=CMD mode after the first enable. This means automatic
<> 150:02e0a0aed4ec 159 peak detection and shunt current optimization runs at the first call to
<> 150:02e0a0aed4ec 160 CMU_OscillatorEnable(cmuOsc_HFXO, true, true) or
<> 150:02e0a0aed4ec 161 CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO) only.
<> 150:02e0a0aed4ec 162 Optimization can be restarted by calling CMU_OscillatorTuningOptimize(). This is
<> 150:02e0a0aed4ec 163 required if the temperature changes by more than 100degC.
<> 150:02e0a0aed4ec 164 - Added CMU_HFXOAutostartEnable() function to support automatic HFXO start and
<> 150:02e0a0aed4ec 165 select.
<> 150:02e0a0aed4ec 166 - Updated default timeouts for CMU_HFXOInit() to optimize HFXO startup
<> 150:02e0a0aed4ec 167 time. The startup time reduction depends on the oscillator specification.
<> 150:02e0a0aed4ec 168 The new defaults are safe for typical oscillator specifications.
<> 150:02e0a0aed4ec 169 - em_ldma: LDMA_StartTransfer() now only enable a DMA channel once.
<> 150:02e0a0aed4ec 170 - em_cmu: Fixed condtitional compilation bug in CMU_ClockSelectGet().
<> 150:02e0a0aed4ec 171 - em_usart: Fixed bug in USART_BaudrateCalc() function.
<> 150:02e0a0aed4ec 172 - em_usart: Improved corner cases in synchrounous baudrate calculation math.
<> 150:02e0a0aed4ec 173 - em_emu.c: EMU_DCDCLnRcoBandSet() calls EMU_DCDCOptimizeSlice() as the slice
<> 150:02e0a0aed4ec 174 configuration depends on RCO band.
<> 150:02e0a0aed4ec 175
<> 150:02e0a0aed4ec 176 4.3.0:
<> 150:02e0a0aed4ec 177 - em_cmu: Removed unused fields from CMU_HFXOInit_TypeDef. The removed fields
<> 150:02e0a0aed4ec 178 are regIshStartup and timeoutWarmSteady.
<> 150:02e0a0aed4ec 179 - em_rtc.h: Added RTC_CounterSet function for modifying the RTC Counter.
<> 150:02e0a0aed4ec 180 - em_burtc.c: Fixed bug when doing low frequency domain synchronization.
<> 150:02e0a0aed4ec 181 - em_gpio.c: Deprecated GPIO_IntConfig(), use new function GPIO_ExtIntConfig()
<> 150:02e0a0aed4ec 182 instead.
<> 150:02e0a0aed4ec 183 - Removed deprecated file em_part.h.
<> 150:02e0a0aed4ec 184 - em_dma.c: Replaced infinite loop on bus errors in default irq handler with
<> 150:02e0a0aed4ec 185 an assert.
<> 150:02e0a0aed4ec 186 - em_gpio.c: Use direct register write instead of BUS API in GPIO_PinModeSet
<> 150:02e0a0aed4ec 187 to prevent glitches.
<> 150:02e0a0aed4ec 188 - Fixed incorrect handling of CMU_CTRL_WSHFLE and CMU_HFPRESC_HFCLKLEPRESC in
<> 150:02e0a0aed4ec 189 em_cmu.c for EFM32 Pearl and Jade Gecko.
<> 150:02e0a0aed4ec 190 - Type enumerations cmuClock_HFLE and cmuSelect_HFCLKLE can now be used for
<> 150:02e0a0aed4ec 191 all families to select or reference the divided down HF clock for LE peripherals.
<> 150:02e0a0aed4ec 192 - Code size optimization in em_cmu.c.
<> 150:02e0a0aed4ec 193 - Added GPCRC support.
<> 150:02e0a0aed4ec 194 - Added support for WARNSEL, WINSEL and WDOGRSTDIS to em_wdog. Added interrupt
<> 150:02e0a0aed4ec 195 functions. Added support for multiple WDOG instances. Deprecated functions
<> 150:02e0a0aed4ec 196 WDOG_Enable(), WDOG_Feed(), WDOG_Init() and WDOG_Lock().
<> 150:02e0a0aed4ec 197 - GPIO_EM4GetPinWakeupCause() now returns the content of the EM4WU field from
<> 150:02e0a0aed4ec 198 the GPIO_IF register for platform 2 devices.
<> 150:02e0a0aed4ec 199 - Added function GPIO_SlewrateSet() to set slewrate for GPIO ports.
<> 150:02e0a0aed4ec 200 - Added fix for GPIO_E201 in CHIP_Init().
<> 150:02e0a0aed4ec 201 - Added function CMU_HFRCOBandGet() and CMU_HFRCOBandSet() for platform 2.
<> 150:02e0a0aed4ec 202 Functions with the same names are present for platform 1, but the parameter
<> 150:02e0a0aed4ec 203 and return types are different. Platform 1 and 2 also do not support the same
<> 150:02e0a0aed4ec 204 HFRCO/AUXHFRCO frequencies.
<> 150:02e0a0aed4ec 205 - Added HFLE wait-state control to CMU_HFRCOBandSet(). This is a bug on
<> 150:02e0a0aed4ec 206 EFM32 Wonder Gecko only as HFLE DIV4 is required at 24MHz, in between the 28HMz
<> 150:02e0a0aed4ec 207 and 21MHz HFRCO bands.
<> 150:02e0a0aed4ec 208 - Fixed reset-cause XMASKs for platform 2, gen 1 parts. Improved
<> 150:02e0a0aed4ec 209 documentation in em_rmu.c.
<> 150:02e0a0aed4ec 210 - Added support for configuring IrDA on USART1 for EFM32 Happy Gecko. The
<> 150:02e0a0aed4ec 211 function USART_InitIrDA() is deprecated, and replaced by USARTn_InitIrDA().
<> 150:02e0a0aed4ec 212 - Added module em_ramfunc. Fixed issue with calls from em_msc RAM code to Flash.
<> 150:02e0a0aed4ec 213 - Updated current limiter threshold equations for LNCLIMILIMSEL, LPCLIMILIMSEL
<> 150:02e0a0aed4ec 214 and DCDCZDETCTRL.
<> 150:02e0a0aed4ec 215 - Member type EMU_DcdcLnTransientMode_TypeDef in EMU_DCDCInit_TypeDef changed to
<> 150:02e0a0aed4ec 216 EMU_DcdcLnReverseCurrentControl_TypeDef to enable support for reverse current
<> 150:02e0a0aed4ec 217 limiter.
<> 150:02e0a0aed4ec 218 - EM2/3 current consumption optimization: Default value
<> 150:02e0a0aed4ec 219 emuDcdcAnaPeripheralPower_AVDD in EMU_DCDCINIT_DEFAULT for EFR32
<> 150:02e0a0aed4ec 220 changed to emuDcdcAnaPeripheralPower_DCDC.
<> 150:02e0a0aed4ec 221 - EM2/3 current consumption optimization: DCDC_LP_NFET_CNT updated to 7
<> 150:02e0a0aed4ec 222
<> 150:02e0a0aed4ec 223 4.2.3:
<> 150:02e0a0aed4ec 224 - Added DMA and LDMA functions to enable/disable channel requests.
<> 150:02e0a0aed4ec 225
<> 150:02e0a0aed4ec 226 4.2.2:
<> 150:02e0a0aed4ec 227 - em_gpio.c: Use direct register write instead of BUS API in GPIO_PinModeSet
<> 150:02e0a0aed4ec 228 to prevent glitches.
<> 150:02e0a0aed4ec 229
<> 144:ef7eb2e8f9f7 230 4.2.1:
<> 144:ef7eb2e8f9f7 231 - Added errata fix for an issue that may cause BOD resets in EM2 when using
<> 144:ef7eb2e8f9f7 232 DCDC-to-DVDD mode. The fix is implemented in EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 233 - Added function EMU_DCDCPowerOff() for boards with physically disconnected DCDC.
<> 144:ef7eb2e8f9f7 234 - Current consumption is optimized for DCDC bypass mode. This update is
<> 144:ef7eb2e8f9f7 235 implemented in EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 4.2.0:
<> 144:ef7eb2e8f9f7 238 - Updated I2C clock divider equation for platform 2 parts. Added constraints
<> 144:ef7eb2e8f9f7 239 to HFPER clock frequency in I2C_BusFreqSet().
<> 144:ef7eb2e8f9f7 240 - EMU EMU_EM23VregMode_TypeDef replaced with a bool.
<> 144:ef7eb2e8f9f7 241 - Added support for GPIO alternate drive strength and alternate control modes.
<> 144:ef7eb2e8f9f7 242 - DCDC setup is simplified. More tuning and optimization settings added to
<> 144:ef7eb2e8f9f7 243 EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 244 - Added member pinRetentionMode to EMU_EM4Init_TypeDef.
<> 144:ef7eb2e8f9f7 245 - Added function EMU_UnlatchPinRetention() to support unlatching of pin
<> 144:ef7eb2e8f9f7 246 retention in EM4H/S.
<> 144:ef7eb2e8f9f7 247 - Fixed bug in ADC_InitScan() which caused a overwrite of single conversion
<> 144:ef7eb2e8f9f7 248 mode calibration values.
<> 150:02e0a0aed4ec 249 - Added support for CRYPTO module on EFM32 Pearl and Jade Gecko (em_crypto.c/h).
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 4.1.1:
<> 144:ef7eb2e8f9f7 252 - EMU_DCDCInit() updated with new parameters for EM2 and 3. Current consumption
<> 150:02e0a0aed4ec 253 with DCDC at expected levels for EFR32 and EFM32 Pearl and Jade Gecko.
<> 144:ef7eb2e8f9f7 254 - EMU_DCDCInit_TypeDef updated with more parameters. EMU_DcdcLpcmpBiasMode_TypeDef
<> 144:ef7eb2e8f9f7 255 is removed.
<> 144:ef7eb2e8f9f7 256 - More assertions added to EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 257 - HFXO default parameters updated.
<> 144:ef7eb2e8f9f7 258 - ADC defaults updated.
<> 144:ef7eb2e8f9f7 259 - RMU pin mode set fixed.
<> 144:ef7eb2e8f9f7 260 - Added missing define for cmuSelect_ULFRCO.
<> 144:ef7eb2e8f9f7 261 - Added missing functions for handling peripheral interrupts.
<> 144:ef7eb2e8f9f7 262 - Added support for VMON.
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 4.1.0:
<> 150:02e0a0aed4ec 265 - New signature for RMU_ResetControl() function.
<> 144:ef7eb2e8f9f7 266 - The typedef EMU_EM23Init_TypeDef which is a parameter to EMU_EM23Init()
<> 144:ef7eb2e8f9f7 267 has got a new definition.
<> 150:02e0a0aed4ec 268 - Initial support _SILICON_LABS_32B_PLATFORM_2 devices added.
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 4.0.0:
<> 144:ef7eb2e8f9f7 271 - Use ARM CMSIS version 4.2.0.
<> 144:ef7eb2e8f9f7 272 - New style version macros in em_version.h.
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 3.20.14:
<> 144:ef7eb2e8f9f7 275 - USB release only.
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 3.20.13:
<> 144:ef7eb2e8f9f7 278 - Added new style family #defines in em_system.h, including EZR32 families.
<> 144:ef7eb2e8f9f7 279 - Fixed I2C_FREQ_STANDARD_MAX macros.
<> 144:ef7eb2e8f9f7 280 - Fixed bug in MSC_WriteWord which called internal functions that were linked
<> 144:ef7eb2e8f9f7 281 to flash for armgcc. All subsequent calls of MSC_WriteWord should now be
<> 150:02e0a0aed4ec 282 linked to RAM for all supported compilers. The internals of MSC_WriteWord()
<> 144:ef7eb2e8f9f7 283 will check the global variable SystemCoreClock in order to make sure the
<> 144:ef7eb2e8f9f7 284 frequency is high enough for flash operations. If the core clock frequency
<> 144:ef7eb2e8f9f7 285 is changed, software is responsible for calling MSC_Init or
<> 144:ef7eb2e8f9f7 286 SystemCoreClockGet in order to set the SystemCoreClock variable to the
<> 144:ef7eb2e8f9f7 287 correct value.
<> 144:ef7eb2e8f9f7 288 - Added errata fix IDAC_101.
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 3.20.12:
<> 144:ef7eb2e8f9f7 291 - Added errata fix EMU_108.
<> 144:ef7eb2e8f9f7 292 - #ifdef's now use register defines instead of a mix of register and family defines.
<> 144:ef7eb2e8f9f7 293 - Added a case for when there are only 4 DMA channels available:
<> 144:ef7eb2e8f9f7 294 Alignment was (correctly) defined at 7 bit, but got asserted for 8 bit, leading
<> 144:ef7eb2e8f9f7 295 to unpredictable tripped asserts.
<> 144:ef7eb2e8f9f7 296 - Added USART_INITPRSTRIGGER_DEFAULT defined structure to support HWCONF.
<> 144:ef7eb2e8f9f7 297 - Added support for LFC clock tree.
<> 144:ef7eb2e8f9f7 298 - Added CMU_USHFRCOBandSet() and CMU_USHFRCOBandGet().
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 3.20.10:
<> 144:ef7eb2e8f9f7 301 - Maintenance release, no changes.
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 3.20.9:
<> 144:ef7eb2e8f9f7 304 - Added support for Happy Gecko including support for the new oscillator USHFRCO.
<> 144:ef7eb2e8f9f7 305 - Added MSC_WriteWordFast() function. This flash write function has a similar
<> 144:ef7eb2e8f9f7 306 performance as the old MSC_WriteWord(), but it disables interrupts and
<> 144:ef7eb2e8f9f7 307 requires a core clock frequency of at least 14MHz. The new MSC_WriteWord()
<> 144:ef7eb2e8f9f7 308 is slower, but it does not disable interrupts and may be called with core
<> 144:ef7eb2e8f9f7 309 clock frequencies down to 1MHz.
<> 144:ef7eb2e8f9f7 310 - Fixed a bug in EMU_EnterEM4() that set other EM4 configuration bits to 0
<> 144:ef7eb2e8f9f7 311 on EM4 entry.
<> 144:ef7eb2e8f9f7 312 - Added EMU_EM23Init().
<> 144:ef7eb2e8f9f7 313 - Fixed a bug in CMU_FlashWaitStateControl() where it failed to set the
<> 144:ef7eb2e8f9f7 314 required wait-state configuration if the MSC is locked.
<> 144:ef7eb2e8f9f7 315 - Added EMU interrupt handling functions.
<> 144:ef7eb2e8f9f7 316 - BURTC_Reset() changed to use async reset RMU_CTRL_BURSTEN instead of
<> 144:ef7eb2e8f9f7 317 reset value writeback. This makes the function independent of a selected
<> 144:ef7eb2e8f9f7 318 and enabled clock.
<> 144:ef7eb2e8f9f7 319 - BURTC_Sync() now returns without waiting for BURTC->SYNCBUSY to clear
<> 144:ef7eb2e8f9f7 320 when no clock is selected in BURTC_CTRL_CLKSEL.
<> 144:ef7eb2e8f9f7 321 - Fixed assertion bug in ACMP_ChannelSet() that checked the negSel parameter
<> 144:ef7eb2e8f9f7 322 against the wrong upper bound.
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 3.20.7:
<> 144:ef7eb2e8f9f7 325 - Fixed CMU_MAX_FREQ_HFLE macro for Wonder family.
<> 144:ef7eb2e8f9f7 326 - Fixed MSC_WriteWord() bug.
<> 144:ef7eb2e8f9f7 327 - Added syncbusy wait in RTC_Reset() for Gecko family.
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 3.20.6:
<> 144:ef7eb2e8f9f7 330 - Corrected fix for Errata EMU_E107.
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 3.20.5:
<> 144:ef7eb2e8f9f7 333 - Updated license texts.
<> 144:ef7eb2e8f9f7 334 - Removed unnecessary fix for Wonder Gecko.
<> 144:ef7eb2e8f9f7 335 - Updated LFXO temperature compensation in CHIP_Init().
<> 144:ef7eb2e8f9f7 336 - Changed LESENSE_ScanStart, LESENSE_ScanStop, LESENSE_DecoderStart,
<> 144:ef7eb2e8f9f7 337 LESENSE_ResultBufferClear() and LESENSE_Reset() functions to wait until
<> 144:ef7eb2e8f9f7 338 CMD register writes complete in order to make sure CMD register writes do
<> 144:ef7eb2e8f9f7 339 not break each other, and for register values to be consistent when
<> 144:ef7eb2e8f9f7 340 returning from functions that write to the CMD register.
<> 144:ef7eb2e8f9f7 341 - Added fix for Errata EMU_E107.
<> 144:ef7eb2e8f9f7 342 - Added family to SYSTEM_ChipRevision_TypeDef.
<> 144:ef7eb2e8f9f7 343 - Fixed bug in function AES_OFB128 which failed on Zero Gecko.
<> 144:ef7eb2e8f9f7 344 - Fixed RMU_ResetCauseGet() to return correct reset causes.
<> 144:ef7eb2e8f9f7 345 - Fixed bug in RTC_CounterReset() which failed to reset counter immediately
<> 144:ef7eb2e8f9f7 346 after return on Gecko devices.
<> 144:ef7eb2e8f9f7 347 - Added static inline non-blocking USART receive functions (USART_Rx...).
<> 144:ef7eb2e8f9f7 348 - Added function SYSTEM_GetFamily().
<> 144:ef7eb2e8f9f7 349 - Added function DAC_ChannelOutputSet().
<> 144:ef7eb2e8f9f7 350 - Fixed MSC_WriteWord() to not use WDOUBLE if LPWRITE is set.
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 3.20.2:
<> 144:ef7eb2e8f9f7 353 - Fixed bug regarding when MEMINFO in DEVINFO was introduced.
<> 144:ef7eb2e8f9f7 354 The correct crossover is production revision 18.
<> 144:ef7eb2e8f9f7 355 - Fixed bug in WDOG_Feed() which does not feed the watchdog if the watchdog
<> 144:ef7eb2e8f9f7 356 is disabled. Previously, the watchdog was broken after WDOG_Feed() fed it
<> 144:ef7eb2e8f9f7 357 when it was disabled.
<> 144:ef7eb2e8f9f7 358 - Fixed issue in em_i2c.c, which should set the NACK bit in the I2C CMD
<> 144:ef7eb2e8f9f7 359 register for the next to last byte received. The exception is when only
<> 144:ef7eb2e8f9f7 360 one byte is to be received. Then the NACK bit must be set like the
<> 144:ef7eb2e8f9f7 361 previous code was doing.
<> 144:ef7eb2e8f9f7 362 - Added function BURTC_ClockFreqGet() in order to determine clock frequency
<> 144:ef7eb2e8f9f7 363 of BURTC.
<> 144:ef7eb2e8f9f7 364 - Fixed bug in BURTC_Reset() which made a subsequent call to BURTC_Init hang.
<> 144:ef7eb2e8f9f7 365 - Added support for the IDAC module on the Zero Gecko family, em_idac.c/h.
<> 144:ef7eb2e8f9f7 366 - Fixed bug in DAC_PrescaleCalc() which could return higher values than
<> 144:ef7eb2e8f9f7 367 the maximum prescaler value. The fix makes sure to return the max prescaler
<> 144:ef7eb2e8f9f7 368 value resulting in possible higher DAC frequency than requested.
<> 144:ef7eb2e8f9f7 369 - Fixed I2C_BusFreqSet to use documented values for Nlow and Nhigh values,
<> 144:ef7eb2e8f9f7 370 and do not decrement the div(isor) by one according to the formula because
<> 144:ef7eb2e8f9f7 371 this resulted in higher I2C bus frequencies than desired.
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 3.20.0:
<> 144:ef7eb2e8f9f7 374 - LEUART: Added LEUART_TxDmaInEM2Enable() and LEUART_RxDmaInEM2Enable() for
<> 144:ef7eb2e8f9f7 375 enabling and disabling DMA LEUART RX and Tx in EM2 support.
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 3.0.3:
<> 144:ef7eb2e8f9f7 378 - Internal release for testing Wonder Gecko support.
<> 144:ef7eb2e8f9f7 379 - SYSTEM: Added function to enable/disable FPU access on Wonder parts,
<> 144:ef7eb2e8f9f7 380 SYSTEM_FpuAccessModeSet().
<> 144:ef7eb2e8f9f7 381 - USART: Added USART_SpiTransfer() function.
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 3.0.2:
<> 144:ef7eb2e8f9f7 384 - MSC: In MSC_WriteWord(), added support for double word write cycle support
<> 144:ef7eb2e8f9f7 385 (WDOUBLE) on devices with more than 512KiBytes of Flash memory. This can
<> 144:ef7eb2e8f9f7 386 almost double the speed of the MSC_WriteWord function for large data sizes.
<> 144:ef7eb2e8f9f7 387 - MSC: In MSC_ErasePage(), added support for devices with Flash page size
<> 144:ef7eb2e8f9f7 388 larger than 512 bytes, like Giant and Leopard Gecko.
<> 144:ef7eb2e8f9f7 389 - CMU: Fixed bug in CMU_ClockDivSet(). Clear HFLE and HFCORECLKLEDIV flags when
<> 144:ef7eb2e8f9f7 390 the core runs at frequencies up to 32MHz.
<> 144:ef7eb2e8f9f7 391 - CMU: Fixed bug in CMU_ClockEnable(): Set the HFLE and HFCORECLKLEDIV flags
<> 144:ef7eb2e8f9f7 392 when the CORE clock runs at frequencies higher than 32MHz.
<> 144:ef7eb2e8f9f7 393 - CMU: Fixed bug in CMU_ClockSelectSet(): Set HFLE and DIV4 factor for peripheral
<> 144:ef7eb2e8f9f7 394 clock if HFCORE clock for LE is enabled and the CORE clock runs at
<> 144:ef7eb2e8f9f7 395 frequencies higher than 32MHz.
<> 144:ef7eb2e8f9f7 396 - BITBAND: Added BITBAND_PeripheralRead() and BITBAND_SRAMRead() functions.
<> 144:ef7eb2e8f9f7 397 - DMA: Added #ifndef EXCLUDE_DEFAULT_DMA_IRQ_HANDLER around DMA_IRQHandler in
<> 144:ef7eb2e8f9f7 398 order for the user to implement a custom IRQ handler or run without a DMA
<> 144:ef7eb2e8f9f7 399 IRQ handler by defining EXCLUDE_DEFAULT_DMA_IRQ_HANDLER with the -D compiler
<> 144:ef7eb2e8f9f7 400 option.
<> 144:ef7eb2e8f9f7 401 - BURTC: In functions BURTC_Init() and BURTC_CompareSet(), moved SYNCBUSY
<> 144:ef7eb2e8f9f7 402 loops in front of modifications of registers COMP0 and LPMODE.
<> 144:ef7eb2e8f9f7 403 - MSC: Fixed ram_code section error on Keil toolchain.
<> 144:ef7eb2e8f9f7 404 - MSC: Removed uneeded code from MSC init and deinit which would have no
<> 144:ef7eb2e8f9f7 405 effect (Big thanks to Martin Schreiber for reporting this bug!).
<> 144:ef7eb2e8f9f7 406 - System: Added access functions for reading some values out of the Device
<> 144:ef7eb2e8f9f7 407 Information page.
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 3.0.1:
<> 144:ef7eb2e8f9f7 410 - LFXO fix for Giant family.
<> 144:ef7eb2e8f9f7 411 - USART: Fix for EFM32TG108Fxx which does not have USART0.
<> 144:ef7eb2e8f9f7 412 - EBI: The write to the CTRL register now happens before the ROUTE registers
<> 144:ef7eb2e8f9f7 413 are set. This avoids potential glitches.
<> 144:ef7eb2e8f9f7 414 - LESENSE: Fix issue when using lesenseAltExMapACMP.
<> 144:ef7eb2e8f9f7 415 - TIMER: Fix compilation on devices where ADC is not available.
<> 144:ef7eb2e8f9f7 416 - LCD: Fix bug where Aloc field would not be set to 0.
<> 144:ef7eb2e8f9f7 417 - BURTC: Fix Reset function by adding reset of COMP0 register and removing
<> 144:ef7eb2e8f9f7 418 reset of POWERDOWN register. The POWERDOWN register cannot be used to
<> 144:ef7eb2e8f9f7 419 power up the blocks after it has been powered down.
<> 144:ef7eb2e8f9f7 420 - CMU: Fixed bug where ClockDivSet, ClockDivGet and ClockFreqGet didn't work for
<> 144:ef7eb2e8f9f7 421 cmuClock_LCDpre clock. Also corrected 3 wrongly typed constants.
<> 144:ef7eb2e8f9f7 422 - CMU: Fixed bug where LFBE field in LFCLKSEL was not cleared before setting
<> 144:ef7eb2e8f9f7 423 bit-value.
<> 144:ef7eb2e8f9f7 424 - CMU: Fixed bug with CMU_ClockSelectGet. Did not give correct return value
<> 144:ef7eb2e8f9f7 425 for cmuClock_LFB.
<> 144:ef7eb2e8f9f7 426 - I2C: Fixed bug where I2C_Init would set divisor depending on the previous
<> 144:ef7eb2e8f9f7 427 master/slave configuration, not the one set in the initialization.
<> 144:ef7eb2e8f9f7 428 - I2C: Fixed issue in the function I2C_BusFreqSet (called by I2C_Init). The
<> 144:ef7eb2e8f9f7 429 input parameter 'I2C_ClockHLR_TypeDef type' was not in use. The fix enables
<> 144:ef7eb2e8f9f7 430 the parameter to add support for 'i2cClockHLRAsymetric' and 'i2cClockHLRFast'
<> 144:ef7eb2e8f9f7 431 modes. In order to use 'i2cClockHLRAsymetric' and 'i2cClockHLRFast' the
<> 144:ef7eb2e8f9f7 432 frequency of the HFPER clock may need to be increased.
<> 144:ef7eb2e8f9f7 433 - OPAMP: Fixed bug in the function OPAMP_Enable where an incorrect register
<> 144:ef7eb2e8f9f7 434 was used when setting the OPA2 calibration value.
<> 144:ef7eb2e8f9f7 435 - LEUART: Fixed issue in LEUART_BaudrateSet when a high clock frequency and a
<> 144:ef7eb2e8f9f7 436 low baudrate can overflow the clock divisor register (CLKDIV). The fix uses
<> 144:ef7eb2e8f9f7 437 an assert statement to check whether the calculated clock divisor is out of
<> 144:ef7eb2e8f9f7 438 range.
<> 144:ef7eb2e8f9f7 439 - USART: Fixed issue in USART_BaudrateAsyncSet when a high clock frequency and
<> 144:ef7eb2e8f9f7 440 a low baudrate can overflow the clock divisor register (CLKDIV). The fix uses
<> 144:ef7eb2e8f9f7 441 an assert statement to check whether the calculated clock divisor is out of
<> 144:ef7eb2e8f9f7 442 range.
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 3.0.0:
<> 144:ef7eb2e8f9f7 445 - efm32lib renamed emlib, as it will include support for non-EFM32 devices
<> 144:ef7eb2e8f9f7 446 in the future
<> 144:ef7eb2e8f9f7 447 - Added CMSIS_V3 compatibility fixes, and use of CMSIS_V3 definitions
<> 144:ef7eb2e8f9f7 448 - See Device/Changes-EnergyMicro.txt for detailed path changes
<> 144:ef7eb2e8f9f7 449 - New prefixes of all files, efm32_<peripherqal>.c/h to em_<peripheral>.c/h
<> 144:ef7eb2e8f9f7 450 - New names for readme and changes files
<> 144:ef7eb2e8f9f7 451 - RMU - BUMODERST not masked away when EM4 bits has been set
<> 144:ef7eb2e8f9f7 452 - CMU - CMU_LFClkGet now accounts for ULFRCO bit for Tiny Gecko
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 2.4.1:
<> 144:ef7eb2e8f9f7 455 - New, open source friendly license
<> 144:ef7eb2e8f9f7 456 - Fixed BURTC initialization hang if init->enable was false
<> 144:ef7eb2e8f9f7 457 - Fixed CMU issue with USBC and USB checks not being used correctly
<> 144:ef7eb2e8f9f7 458 - Added CMU feature, missing TIMER3 support
<> 144:ef7eb2e8f9f7 459 - Improved accuracy of SPI mode for USART baudrate calculation
<> 144:ef7eb2e8f9f7 460 - Corrected USBC HFCLKNODIV setting to comply with new header file defines
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 2.4.0:
<> 144:ef7eb2e8f9f7 463 - Added efm32_version.h defining software version number
<> 144:ef7eb2e8f9f7 464 - Added BURTC support for Giant and Leopard Gecko
<> 144:ef7eb2e8f9f7 465 - Added RMU_ResetControl for BU reset flag
<> 144:ef7eb2e8f9f7 466 - Added some missing features to EMU for back up domain and EM4 support
<> 144:ef7eb2e8f9f7 467 - ADC TimebaseCalc(), Giant/Leopard Gecko have max 5 bits in TIMEBASE field
<> 144:ef7eb2e8f9f7 468 - Removed EMU Backup Power Domain threshold setings from EMU_BUPDInit, added
<> 144:ef7eb2e8f9f7 469 EMU_BUThresRangeSet() and EMU_BUThresholdSet() API calls. Threshold values
<> 144:ef7eb2e8f9f7 470 are factory calibrated and should not usually be overridden by the user.
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 2.3.2:
<> 144:ef7eb2e8f9f7 473 - Added Tiny Gecko and Giant Gecko support in RMU for new reset causes
<> 144:ef7eb2e8f9f7 474 - CMU_ClockFreqGet will now report correct clock rates if HFLE is set (/4)
<> 144:ef7eb2e8f9f7 475 - Added Giant Gecko specific MSC_MassErase(), erase entire flash
<> 144:ef7eb2e8f9f7 476 - Added Giant Gecko specific MSC_BusStrategy (inline) function
<> 144:ef7eb2e8f9f7 477 - MSC_Init() will now configure TIMEBASE correctly according to AUXHFRCO clock
<> 144:ef7eb2e8f9f7 478 rate for Tiny Gecko and Giant Gecko
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 2.3.0:
<> 144:ef7eb2e8f9f7 481 - USART - Added USART_InitPrsTrigger to initialize USART PRS triggered
<> 144:ef7eb2e8f9f7 482 transmissions.
<> 144:ef7eb2e8f9f7 483 - CMU - numerous updates, now supports full clock tree of Giant/Tiny Gecko
<> 144:ef7eb2e8f9f7 484 - CMU_ClockDivSet/Get will now use real dividend and not logarithmic values
<> 144:ef7eb2e8f9f7 485 as earlier. Prior enumerated values have been kept for backward compatibility.
<> 144:ef7eb2e8f9f7 486 - Added support for CMU HFLE and DIV4 factor for core clock for LE
<> 144:ef7eb2e8f9f7 487 peripherals
<> 144:ef7eb2e8f9f7 488 - Added support for alternate LCD segment animation range for Giant Gecko
<> 144:ef7eb2e8f9f7 489 - Fixed bug: Don't enable VCMP low power reference until after warm up,
<> 144:ef7eb2e8f9f7 490 allow biasprog value of 0 in VCMP_Init()
<> 144:ef7eb2e8f9f7 491 - Added support for ALTMAP (256MB address map) in EBI_BankAddress()
<> 144:ef7eb2e8f9f7 492 - TIMER_Init() will now reset CNT value
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 2.2.2:
<> 144:ef7eb2e8f9f7 495 - Added DAC0 channel 0 and 1 to ACMP for Tiny and Giant devices
<> 144:ef7eb2e8f9f7 496 - Fixed bug in CMU for MSC WAITSTATE configuration, leading to too high wait
<> 144:ef7eb2e8f9f7 497 states depending on clock rate
<> 144:ef7eb2e8f9f7 498 - Fixed bug in CMU for UART1 clock enable
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 2.2.1:
<> 144:ef7eb2e8f9f7 501 - UART_Reset() and LEUART_Reset() will now reset ROUTE register as well, this
<> 144:ef7eb2e8f9f7 502 will mean GPIO pins will not be driven after this call. Take care to ensure
<> 144:ef7eb2e8f9f7 503 that GPIO ROUTE register is configured after calls to *UART_Init*Sync
<> 144:ef7eb2e8f9f7 504 - Fixed problems with EFM_ASSERT when using UART in USART API
<> 144:ef7eb2e8f9f7 505 - Added Giant Gecko support for EBI (new modes and TFT direct drive)
<> 144:ef7eb2e8f9f7 506 - Added Giant Gecko support for CMU 2 WAIT STATES, and I2C1
<> 144:ef7eb2e8f9f7 507 - Added Giant Gecko support for UART1 in CMU
<> 144:ef7eb2e8f9f7 508 - Added Giant Gecko support for DMA LOOP and 2D Copy operations
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 2.1.0:
<> 144:ef7eb2e8f9f7 511 - EMU_Restore will now disable HFRCO if it was not enabled when entering
<> 144:ef7eb2e8f9f7 512 an Energy Mode
<> 144:ef7eb2e8f9f7 513 - Run time changes only applies to Gecko devices, filter out Tiny and Giant
<> 144:ef7eb2e8f9f7 514 for CHIP_Init();
<> 144:ef7eb2e8f9f7 515 - Added const specificers to various initialization structures, to ensure
<> 144:ef7eb2e8f9f7 516 they can reside in flash instead of SRAM
<> 144:ef7eb2e8f9f7 517 - Bugfix in efm32_i2c.c, keep returning i2cTransferInProgress until done
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 2.0.1:
<> 144:ef7eb2e8f9f7 520 - Changed enum OPAMP_PosSel_TypeDef. Enum value opaPosSelOpaIn changed from
<> 144:ef7eb2e8f9f7 521 DAC_OPA0MUX_POSSEL_OPA1IN to DAC_OPA0MUX_POSSEL_OPA0INP.
<> 144:ef7eb2e8f9f7 522 - Bugfix in efm32_lesense.h, LESENSE_ChClk_TypeDef now contains unshifted
<> 144:ef7eb2e8f9f7 523 values, fixed the implementation in efm32_lesense.c where the bug prevented
<> 144:ef7eb2e8f9f7 524 the sampleClk to be set to AUXHFRCO.
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 2.0.0:
<> 144:ef7eb2e8f9f7 527 - USART_Init-functions now calls USART_Reset() which will also disable/reset
<> 144:ef7eb2e8f9f7 528 interrupt
<> 144:ef7eb2e8f9f7 529 - USART_BaudrateSyncSet() now asserts on invalid oversample configuration
<> 144:ef7eb2e8f9f7 530 - Added initialization of parity bit in LEUART_Init()
<> 144:ef7eb2e8f9f7 531 - Added Tiny Gecko support for CMU, ULFRCO, LESENSE clocks and continuous
<> 144:ef7eb2e8f9f7 532 calibration
<> 144:ef7eb2e8f9f7 533 - Added Tiny Gecko support for GPIO, EM4 pin retention and wake up support
<> 144:ef7eb2e8f9f7 534 - Added Tiny Gecko support for I2S, SPI auto TX mode on USART
<> 144:ef7eb2e8f9f7 535 - Added Tiny Gecko support for CACHE mesasurements for MSC module
<> 144:ef7eb2e8f9f7 536 - Added Tiny Gecko support for LCD module (with no HIGH segment registers)
<> 144:ef7eb2e8f9f7 537 - Added Tiny Gecko support for TIMER, PWM 2x, (DT lock not supported)
<> 144:ef7eb2e8f9f7 538 - Added Tiny Gecko support for LESENSE module
<> 144:ef7eb2e8f9f7 539 - Added Tiny Gecko support for PRS input in PCNT
<> 144:ef7eb2e8f9f7 540 - Added Tiny Gecko support for async signals in PRS, PRS_SourceAsyncSignalSet()
<> 144:ef7eb2e8f9f7 541 - Initial support for some Giant Gecko features, where overlapping with Tiny
<> 144:ef7eb2e8f9f7 542 - Removed LPFEN / LPFREQ support from DAC
<> 144:ef7eb2e8f9f7 543 - Fixed comments around interrupt functions, making it clear it is bitwise
<> 144:ef7eb2e8f9f7 544 logical or interrupt flags
<> 144:ef7eb2e8f9f7 545 - Fixed PCNT initialization for external clock configurations, making sure
<> 144:ef7eb2e8f9f7 546 config is synchronized at startup to 3 clocks. Note fix only works for
<> 144:ef7eb2e8f9f7 547 >revC EFM32G devices.
<> 144:ef7eb2e8f9f7 548 - Fixed efm32_cmu.c, EFM_ASSERT statement for LEUART clock div logic was
<> 144:ef7eb2e8f9f7 549 inverted
<> 144:ef7eb2e8f9f7 550 - Fixed ADC_InitScan, PRSSEL shift value corrected
<> 144:ef7eb2e8f9f7 551 - Fixed CMU_ClockFreqGet for devices that do not have I2C
<> 144:ef7eb2e8f9f7 552 - Fixed I2C_TransferInit for devices with more than one I2C-bus (Giant Gecko)
<> 144:ef7eb2e8f9f7 553 - Changed ACMP_Disable() implementation, now only disables the ACMP instance
<> 144:ef7eb2e8f9f7 554 by clearing the EN bit in the CTRL register
<> 144:ef7eb2e8f9f7 555 - Removed ACMP_DisableNoReset() function
<> 144:ef7eb2e8f9f7 556 - Fixed ACMP_Init(), removed automatic enabling, added new structure member
<> 144:ef7eb2e8f9f7 557 "enaReq" for ACMP_Init_TypeDef to control, fixed the EFM_ASSERT of the
<> 144:ef7eb2e8f9f7 558 biasprog parameter
<> 144:ef7eb2e8f9f7 559 - Added default configuration macro ACMP_INIT_DEFAULT for ACMP_Init_TypeDef
<> 144:ef7eb2e8f9f7 560 - Fixed ACMP_CapsenseInit(), removed automatic enabling, added new structure member
<> 144:ef7eb2e8f9f7 561 "enaReq" for ACMP_CapsenseInit_TypeDef to control, fixed the EFM_ASSERT of
<> 144:ef7eb2e8f9f7 562 the biasprog parameter
<> 144:ef7eb2e8f9f7 563 - Changed the name of the default configuration macro for
<> 144:ef7eb2e8f9f7 564 ACMP_CapsenseInit_TypeDef to ACMP_CAPSENSE_INIT_DEFAULT
<> 144:ef7eb2e8f9f7 565 - Added RTC_Reset and RTC_CounterReset functions for RTC
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 1.3.0:
<> 144:ef7eb2e8f9f7 568 - MSC is automatically enabled/disabled when using the MSC API. This saves
<> 144:ef7eb2e8f9f7 569 power, and reduces errors due to not calling MSC_Init().
<> 144:ef7eb2e8f9f7 570 - Added API for controlling Cortex-M3 MPU (memory protection unit)
<> 144:ef7eb2e8f9f7 571 - Adjusted bit fields to comply with latest CMSIS release, see EFM_CMSIS
<> 144:ef7eb2e8f9f7 572 changes file for details
<> 144:ef7eb2e8f9f7 573 - Fixed issue with bit mask clearing in ACMP
<> 144:ef7eb2e8f9f7 574 - Functions ACMP_Enable and ACMP_DisableNoReset added
<> 144:ef7eb2e8f9f7 575 - Added comment about rev.C chips in PCNT, CMD_LTOPBIM not neccessary any more
<> 144:ef7eb2e8f9f7 576 - Added missing instance validity asserts to peripherals (ACMP, LEUART, USART)
<> 144:ef7eb2e8f9f7 577 - Fixed UART0 check in CMU_ClockFreqGet()
<> 144:ef7eb2e8f9f7 578 - Fixed command sync for PCNT before setting TOPB value during init
<> 144:ef7eb2e8f9f7 579 - Fixed instance validity check macro in PCNT
<> 144:ef7eb2e8f9f7 580 - Fixed TIMER_Reset() removed write to unimplemented timer channel registers
<> 144:ef7eb2e8f9f7 581 - Fixed EFM_ASSERT statements in ACMP, VCMP
<> 144:ef7eb2e8f9f7 582 - General code style update: added missing curly braces, default cases, etc.
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 1.2.1:
<> 144:ef7eb2e8f9f7 585 - Feature complete efm32lib, now also includes peripheral API for modules
<> 144:ef7eb2e8f9f7 586 AES,PCNT,MSC,ACMP,VCMP,LCD,EBI
<> 144:ef7eb2e8f9f7 587 - Fixed _TIMER_CC_CTRL_ICEDGE flags for correct timer configuration
<> 144:ef7eb2e8f9f7 588 - Fixed ADC calibration of Single and Scan mode of operation
<> 144:ef7eb2e8f9f7 589 - Added PCNT (ChipRev A/B PCNT0 errata NOT supported) and AES support
<> 144:ef7eb2e8f9f7 590 - Fixed conditional inclusion in efm32_emu.h
<> 144:ef7eb2e8f9f7 591 - Fixed code for LEUART0 for devices with multiple LEUARTs.
<> 144:ef7eb2e8f9f7 592 - Fixed incorrect setting of DOUT for GPIO configuration
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 1.1.4
<> 144:ef7eb2e8f9f7 595 - Fix for TIMER_INIT_DEFAULT
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 1.1.3:
<> 144:ef7eb2e8f9f7 598 - Added ADC, DAC, LETIMER, PRS, TIMER (except DTI) support
<> 144:ef7eb2e8f9f7 599 - Added utility for fetching chip revision (efm32_system.c/h)
<> 144:ef7eb2e8f9f7 600 - Removed RTC instance ref in API, only one RTC will be supported
<> 144:ef7eb2e8f9f7 601 (Affects also define in efm32_cmu.h)
<> 144:ef7eb2e8f9f7 602 - Added default init struct macros for LEUART, USART
<> 144:ef7eb2e8f9f7 603 - Added msbf parameter in USART synchronous init struct, USART_InitSync_TypeDef.
<> 144:ef7eb2e8f9f7 604 - Updated reset for I2C, USART, LEUART to also reset IEN register.
<> 144:ef7eb2e8f9f7 605 - Corrected fault in GPIO_PortOutSet()
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 1.1.2:
<> 144:ef7eb2e8f9f7 608 - Corrected minor issues in EMU, EM3 mode when restoring clocks
<> 144:ef7eb2e8f9f7 609 - Corrected RMU reset cause checking
<> 144:ef7eb2e8f9f7 610 - Changed GPIO enumerator symbols to start with gpio (from GPIO_)
<> 144:ef7eb2e8f9f7 611 - Changed CMU and WDOG enum typedefs to start with CMU_/WDOG_ (from cmu/wdog)
<> 144:ef7eb2e8f9f7 612 - Added USART/UART, LEUART, DMA, I2C support
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 1.1.1:
<> 144:ef7eb2e8f9f7 615 - First version including support for CMU, DBG, EMU, GPIO, RTC, WDOG