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mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
161:2cc1468da177 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**************************************************************************//**
<> 161:2cc1468da177 2 * @file efr32mg12p_smu.h
<> 161:2cc1468da177 3 * @brief EFR32MG12P_SMU register and bit field definitions
<> 161:2cc1468da177 4 * @version 5.1.2
<> 161:2cc1468da177 5 ******************************************************************************
<> 161:2cc1468da177 6 * @section License
<> 161:2cc1468da177 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 161:2cc1468da177 8 ******************************************************************************
<> 161:2cc1468da177 9 *
<> 161:2cc1468da177 10 * Permission is granted to anyone to use this software for any purpose,
<> 161:2cc1468da177 11 * including commercial applications, and to alter it and redistribute it
<> 161:2cc1468da177 12 * freely, subject to the following restrictions:
<> 161:2cc1468da177 13 *
<> 161:2cc1468da177 14 * 1. The origin of this software must not be misrepresented; you must not
<> 161:2cc1468da177 15 * claim that you wrote the original software.@n
<> 161:2cc1468da177 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 161:2cc1468da177 17 * misrepresented as being the original software.@n
<> 161:2cc1468da177 18 * 3. This notice may not be removed or altered from any source distribution.
<> 161:2cc1468da177 19 *
<> 161:2cc1468da177 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 161:2cc1468da177 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 161:2cc1468da177 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 161:2cc1468da177 23 * kind, including, but not limited to, any implied warranties of
<> 161:2cc1468da177 24 * merchantability or fitness for any particular purpose or warranties against
<> 161:2cc1468da177 25 * infringement of any proprietary rights of a third party.
<> 161:2cc1468da177 26 *
<> 161:2cc1468da177 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 161:2cc1468da177 28 * incidental, or special damages, or any other relief, or for any claim by
<> 161:2cc1468da177 29 * any third party, arising from your use of this Software.
<> 161:2cc1468da177 30 *
<> 161:2cc1468da177 31 *****************************************************************************/
<> 161:2cc1468da177 32 /**************************************************************************//**
<> 161:2cc1468da177 33 * @addtogroup Parts
<> 161:2cc1468da177 34 * @{
<> 161:2cc1468da177 35 ******************************************************************************/
<> 161:2cc1468da177 36 /**************************************************************************//**
<> 161:2cc1468da177 37 * @defgroup EFR32MG12P_SMU
<> 161:2cc1468da177 38 * @{
<> 161:2cc1468da177 39 * @brief EFR32MG12P_SMU Register Declaration
<> 161:2cc1468da177 40 *****************************************************************************/
<> 161:2cc1468da177 41 typedef struct
<> 161:2cc1468da177 42 {
<> 161:2cc1468da177 43 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 161:2cc1468da177 44 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 161:2cc1468da177 45 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 161:2cc1468da177 46 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 161:2cc1468da177 47 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 161:2cc1468da177 48
<> 161:2cc1468da177 49 uint32_t RESERVED1[9]; /**< Reserved for future use **/
<> 161:2cc1468da177 50 __IOM uint32_t PPUCTRL; /**< PPU Control Register */
<> 161:2cc1468da177 51 uint32_t RESERVED2[3]; /**< Reserved for future use **/
<> 161:2cc1468da177 52 __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */
<> 161:2cc1468da177 53 __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */
<> 161:2cc1468da177 54
<> 161:2cc1468da177 55 uint32_t RESERVED3[14]; /**< Reserved for future use **/
<> 161:2cc1468da177 56 __IM uint32_t PPUFS; /**< PPU Fault Status */
<> 161:2cc1468da177 57 } SMU_TypeDef; /** @} */
<> 161:2cc1468da177 58
<> 161:2cc1468da177 59 /**************************************************************************//**
<> 161:2cc1468da177 60 * @defgroup EFR32MG12P_SMU_BitFields
<> 161:2cc1468da177 61 * @{
<> 161:2cc1468da177 62 *****************************************************************************/
<> 161:2cc1468da177 63
<> 161:2cc1468da177 64 /* Bit fields for SMU IF */
<> 161:2cc1468da177 65 #define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */
<> 161:2cc1468da177 66 #define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */
<> 161:2cc1468da177 67 #define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */
<> 161:2cc1468da177 68 #define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
<> 161:2cc1468da177 69 #define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
<> 161:2cc1468da177 70 #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */
<> 161:2cc1468da177 71 #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */
<> 161:2cc1468da177 72
<> 161:2cc1468da177 73 /* Bit fields for SMU IFS */
<> 161:2cc1468da177 74 #define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */
<> 161:2cc1468da177 75 #define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */
<> 161:2cc1468da177 76 #define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */
<> 161:2cc1468da177 77 #define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
<> 161:2cc1468da177 78 #define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
<> 161:2cc1468da177 79 #define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */
<> 161:2cc1468da177 80 #define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */
<> 161:2cc1468da177 81
<> 161:2cc1468da177 82 /* Bit fields for SMU IFC */
<> 161:2cc1468da177 83 #define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */
<> 161:2cc1468da177 84 #define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */
<> 161:2cc1468da177 85 #define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */
<> 161:2cc1468da177 86 #define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
<> 161:2cc1468da177 87 #define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
<> 161:2cc1468da177 88 #define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */
<> 161:2cc1468da177 89 #define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */
<> 161:2cc1468da177 90
<> 161:2cc1468da177 91 /* Bit fields for SMU IEN */
<> 161:2cc1468da177 92 #define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */
<> 161:2cc1468da177 93 #define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */
<> 161:2cc1468da177 94 #define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */
<> 161:2cc1468da177 95 #define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
<> 161:2cc1468da177 96 #define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
<> 161:2cc1468da177 97 #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */
<> 161:2cc1468da177 98 #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */
<> 161:2cc1468da177 99
<> 161:2cc1468da177 100 /* Bit fields for SMU PPUCTRL */
<> 161:2cc1468da177 101 #define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */
<> 161:2cc1468da177 102 #define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */
<> 161:2cc1468da177 103 #define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */
<> 161:2cc1468da177 104 #define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */
<> 161:2cc1468da177 105 #define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */
<> 161:2cc1468da177 106 #define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */
<> 161:2cc1468da177 107 #define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */
<> 161:2cc1468da177 108
<> 161:2cc1468da177 109 /* Bit fields for SMU PPUPATD0 */
<> 161:2cc1468da177 110 #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */
<> 161:2cc1468da177 111 #define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL /**< Mask for SMU_PPUPATD0 */
<> 161:2cc1468da177 112 #define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */
<> 161:2cc1468da177 113 #define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */
<> 161:2cc1468da177 114 #define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */
<> 161:2cc1468da177 115 #define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 116 #define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 117 #define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */
<> 161:2cc1468da177 118 #define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */
<> 161:2cc1468da177 119 #define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */
<> 161:2cc1468da177 120 #define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 121 #define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 122 #define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */
<> 161:2cc1468da177 123 #define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */
<> 161:2cc1468da177 124 #define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */
<> 161:2cc1468da177 125 #define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 126 #define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 127 #define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */
<> 161:2cc1468da177 128 #define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */
<> 161:2cc1468da177 129 #define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */
<> 161:2cc1468da177 130 #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 131 #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 132 #define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */
<> 161:2cc1468da177 133 #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */
<> 161:2cc1468da177 134 #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */
<> 161:2cc1468da177 135 #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 136 #define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 137 #define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */
<> 161:2cc1468da177 138 #define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */
<> 161:2cc1468da177 139 #define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */
<> 161:2cc1468da177 140 #define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 141 #define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 142 #define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */
<> 161:2cc1468da177 143 #define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */
<> 161:2cc1468da177 144 #define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */
<> 161:2cc1468da177 145 #define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 146 #define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 147 #define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */
<> 161:2cc1468da177 148 #define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */
<> 161:2cc1468da177 149 #define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */
<> 161:2cc1468da177 150 #define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 151 #define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 152 #define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */
<> 161:2cc1468da177 153 #define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */
<> 161:2cc1468da177 154 #define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */
<> 161:2cc1468da177 155 #define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 156 #define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 157 #define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */
<> 161:2cc1468da177 158 #define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */
<> 161:2cc1468da177 159 #define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */
<> 161:2cc1468da177 160 #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 161 #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 162 #define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */
<> 161:2cc1468da177 163 #define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */
<> 161:2cc1468da177 164 #define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */
<> 161:2cc1468da177 165 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 166 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 167 #define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */
<> 161:2cc1468da177 168 #define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */
<> 161:2cc1468da177 169 #define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */
<> 161:2cc1468da177 170 #define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 171 #define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 172 #define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */
<> 161:2cc1468da177 173 #define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */
<> 161:2cc1468da177 174 #define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */
<> 161:2cc1468da177 175 #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 176 #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 177 #define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */
<> 161:2cc1468da177 178 #define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */
<> 161:2cc1468da177 179 #define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */
<> 161:2cc1468da177 180 #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 181 #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 182 #define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */
<> 161:2cc1468da177 183 #define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */
<> 161:2cc1468da177 184 #define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */
<> 161:2cc1468da177 185 #define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 186 #define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 187 #define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */
<> 161:2cc1468da177 188 #define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */
<> 161:2cc1468da177 189 #define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */
<> 161:2cc1468da177 190 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 191 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 192 #define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */
<> 161:2cc1468da177 193 #define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */
<> 161:2cc1468da177 194 #define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */
<> 161:2cc1468da177 195 #define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 196 #define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 197 #define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */
<> 161:2cc1468da177 198 #define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */
<> 161:2cc1468da177 199 #define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */
<> 161:2cc1468da177 200 #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 201 #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 202 #define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */
<> 161:2cc1468da177 203 #define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */
<> 161:2cc1468da177 204 #define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */
<> 161:2cc1468da177 205 #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 206 #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 207 #define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */
<> 161:2cc1468da177 208 #define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */
<> 161:2cc1468da177 209 #define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */
<> 161:2cc1468da177 210 #define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 211 #define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 212 #define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */
<> 161:2cc1468da177 213 #define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */
<> 161:2cc1468da177 214 #define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */
<> 161:2cc1468da177 215 #define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 216 #define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 217 #define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */
<> 161:2cc1468da177 218 #define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */
<> 161:2cc1468da177 219 #define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */
<> 161:2cc1468da177 220 #define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 221 #define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 222 #define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */
<> 161:2cc1468da177 223 #define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */
<> 161:2cc1468da177 224 #define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */
<> 161:2cc1468da177 225 #define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 226 #define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 227 #define SMU_PPUPATD0_PCNT1 (0x1UL << 28) /**< Pulse Counter 1 access control bit */
<> 161:2cc1468da177 228 #define _SMU_PPUPATD0_PCNT1_SHIFT 28 /**< Shift value for SMU_PCNT1 */
<> 161:2cc1468da177 229 #define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL /**< Bit mask for SMU_PCNT1 */
<> 161:2cc1468da177 230 #define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 231 #define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 232 #define SMU_PPUPATD0_PCNT2 (0x1UL << 29) /**< Pulse Counter 2 access control bit */
<> 161:2cc1468da177 233 #define _SMU_PPUPATD0_PCNT2_SHIFT 29 /**< Shift value for SMU_PCNT2 */
<> 161:2cc1468da177 234 #define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL /**< Bit mask for SMU_PCNT2 */
<> 161:2cc1468da177 235 #define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 236 #define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
<> 161:2cc1468da177 237
<> 161:2cc1468da177 238 /* Bit fields for SMU PPUPATD1 */
<> 161:2cc1468da177 239 #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */
<> 161:2cc1468da177 240 #define _SMU_PPUPATD1_MASK 0x0000FFEEUL /**< Mask for SMU_PPUPATD1 */
<> 161:2cc1468da177 241 #define SMU_PPUPATD1_RMU (0x1UL << 1) /**< Reset Management Unit access control bit */
<> 161:2cc1468da177 242 #define _SMU_PPUPATD1_RMU_SHIFT 1 /**< Shift value for SMU_RMU */
<> 161:2cc1468da177 243 #define _SMU_PPUPATD1_RMU_MASK 0x2UL /**< Bit mask for SMU_RMU */
<> 161:2cc1468da177 244 #define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 245 #define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 246 #define SMU_PPUPATD1_RTCC (0x1UL << 2) /**< Real-Time Counter and Calendar access control bit */
<> 161:2cc1468da177 247 #define _SMU_PPUPATD1_RTCC_SHIFT 2 /**< Shift value for SMU_RTCC */
<> 161:2cc1468da177 248 #define _SMU_PPUPATD1_RTCC_MASK 0x4UL /**< Bit mask for SMU_RTCC */
<> 161:2cc1468da177 249 #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 250 #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 251 #define SMU_PPUPATD1_SMU (0x1UL << 3) /**< Security Management Unit access control bit */
<> 161:2cc1468da177 252 #define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */
<> 161:2cc1468da177 253 #define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */
<> 161:2cc1468da177 254 #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 255 #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 256 #define SMU_PPUPATD1_TIMER0 (0x1UL << 5) /**< Timer 0 access control bit */
<> 161:2cc1468da177 257 #define _SMU_PPUPATD1_TIMER0_SHIFT 5 /**< Shift value for SMU_TIMER0 */
<> 161:2cc1468da177 258 #define _SMU_PPUPATD1_TIMER0_MASK 0x20UL /**< Bit mask for SMU_TIMER0 */
<> 161:2cc1468da177 259 #define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 260 #define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 261 #define SMU_PPUPATD1_TIMER1 (0x1UL << 6) /**< Timer 1 access control bit */
<> 161:2cc1468da177 262 #define _SMU_PPUPATD1_TIMER1_SHIFT 6 /**< Shift value for SMU_TIMER1 */
<> 161:2cc1468da177 263 #define _SMU_PPUPATD1_TIMER1_MASK 0x40UL /**< Bit mask for SMU_TIMER1 */
<> 161:2cc1468da177 264 #define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 265 #define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 266 #define SMU_PPUPATD1_TRNG0 (0x1UL << 7) /**< True Random Number Generator 0 access control bit */
<> 161:2cc1468da177 267 #define _SMU_PPUPATD1_TRNG0_SHIFT 7 /**< Shift value for SMU_TRNG0 */
<> 161:2cc1468da177 268 #define _SMU_PPUPATD1_TRNG0_MASK 0x80UL /**< Bit mask for SMU_TRNG0 */
<> 161:2cc1468da177 269 #define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 270 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 271 #define SMU_PPUPATD1_USART0 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */
<> 161:2cc1468da177 272 #define _SMU_PPUPATD1_USART0_SHIFT 8 /**< Shift value for SMU_USART0 */
<> 161:2cc1468da177 273 #define _SMU_PPUPATD1_USART0_MASK 0x100UL /**< Bit mask for SMU_USART0 */
<> 161:2cc1468da177 274 #define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 275 #define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 276 #define SMU_PPUPATD1_USART1 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */
<> 161:2cc1468da177 277 #define _SMU_PPUPATD1_USART1_SHIFT 9 /**< Shift value for SMU_USART1 */
<> 161:2cc1468da177 278 #define _SMU_PPUPATD1_USART1_MASK 0x200UL /**< Bit mask for SMU_USART1 */
<> 161:2cc1468da177 279 #define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 280 #define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 281 #define SMU_PPUPATD1_USART2 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */
<> 161:2cc1468da177 282 #define _SMU_PPUPATD1_USART2_SHIFT 10 /**< Shift value for SMU_USART2 */
<> 161:2cc1468da177 283 #define _SMU_PPUPATD1_USART2_MASK 0x400UL /**< Bit mask for SMU_USART2 */
<> 161:2cc1468da177 284 #define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 285 #define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 286 #define SMU_PPUPATD1_USART3 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */
<> 161:2cc1468da177 287 #define _SMU_PPUPATD1_USART3_SHIFT 11 /**< Shift value for SMU_USART3 */
<> 161:2cc1468da177 288 #define _SMU_PPUPATD1_USART3_MASK 0x800UL /**< Bit mask for SMU_USART3 */
<> 161:2cc1468da177 289 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 290 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 291 #define SMU_PPUPATD1_WDOG0 (0x1UL << 12) /**< Watchdog 0 access control bit */
<> 161:2cc1468da177 292 #define _SMU_PPUPATD1_WDOG0_SHIFT 12 /**< Shift value for SMU_WDOG0 */
<> 161:2cc1468da177 293 #define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL /**< Bit mask for SMU_WDOG0 */
<> 161:2cc1468da177 294 #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 295 #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 296 #define SMU_PPUPATD1_WDOG1 (0x1UL << 13) /**< Watchdog 1 access control bit */
<> 161:2cc1468da177 297 #define _SMU_PPUPATD1_WDOG1_SHIFT 13 /**< Shift value for SMU_WDOG1 */
<> 161:2cc1468da177 298 #define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL /**< Bit mask for SMU_WDOG1 */
<> 161:2cc1468da177 299 #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 300 #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 301 #define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) /**< Wide Timer 0 access control bit */
<> 161:2cc1468da177 302 #define _SMU_PPUPATD1_WTIMER0_SHIFT 14 /**< Shift value for SMU_WTIMER0 */
<> 161:2cc1468da177 303 #define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL /**< Bit mask for SMU_WTIMER0 */
<> 161:2cc1468da177 304 #define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 305 #define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 306 #define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) /**< Wide Timer 1 access control bit */
<> 161:2cc1468da177 307 #define _SMU_PPUPATD1_WTIMER1_SHIFT 15 /**< Shift value for SMU_WTIMER1 */
<> 161:2cc1468da177 308 #define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL /**< Bit mask for SMU_WTIMER1 */
<> 161:2cc1468da177 309 #define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 310 #define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
<> 161:2cc1468da177 311
<> 161:2cc1468da177 312 /* Bit fields for SMU PPUFS */
<> 161:2cc1468da177 313 #define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */
<> 161:2cc1468da177 314 #define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */
<> 161:2cc1468da177 315 #define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */
<> 161:2cc1468da177 316 #define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */
<> 161:2cc1468da177 317 #define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */
<> 161:2cc1468da177 318 #define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */
<> 161:2cc1468da177 319 #define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */
<> 161:2cc1468da177 320 #define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */
<> 161:2cc1468da177 321 #define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */
<> 161:2cc1468da177 322 #define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */
<> 161:2cc1468da177 323 #define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */
<> 161:2cc1468da177 324 #define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */
<> 161:2cc1468da177 325 #define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */
<> 161:2cc1468da177 326 #define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */
<> 161:2cc1468da177 327 #define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */
<> 161:2cc1468da177 328 #define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */
<> 161:2cc1468da177 329 #define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */
<> 161:2cc1468da177 330 #define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */
<> 161:2cc1468da177 331 #define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */
<> 161:2cc1468da177 332 #define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */
<> 161:2cc1468da177 333 #define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */
<> 161:2cc1468da177 334 #define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */
<> 161:2cc1468da177 335 #define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */
<> 161:2cc1468da177 336 #define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */
<> 161:2cc1468da177 337 #define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */
<> 161:2cc1468da177 338 #define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */
<> 161:2cc1468da177 339 #define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */
<> 161:2cc1468da177 340 #define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */
<> 161:2cc1468da177 341 #define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL /**< Mode PCNT1 for SMU_PPUFS */
<> 161:2cc1468da177 342 #define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL /**< Mode PCNT2 for SMU_PPUFS */
<> 161:2cc1468da177 343 #define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL /**< Mode RMU for SMU_PPUFS */
<> 161:2cc1468da177 344 #define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL /**< Mode RTCC for SMU_PPUFS */
<> 161:2cc1468da177 345 #define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL /**< Mode SMU for SMU_PPUFS */
<> 161:2cc1468da177 346 #define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL /**< Mode TIMER0 for SMU_PPUFS */
<> 161:2cc1468da177 347 #define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL /**< Mode TIMER1 for SMU_PPUFS */
<> 161:2cc1468da177 348 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for SMU_PPUFS */
<> 161:2cc1468da177 349 #define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL /**< Mode USART0 for SMU_PPUFS */
<> 161:2cc1468da177 350 #define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL /**< Mode USART1 for SMU_PPUFS */
<> 161:2cc1468da177 351 #define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL /**< Mode USART2 for SMU_PPUFS */
<> 161:2cc1468da177 352 #define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL /**< Mode USART3 for SMU_PPUFS */
<> 161:2cc1468da177 353 #define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL /**< Mode WDOG0 for SMU_PPUFS */
<> 161:2cc1468da177 354 #define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL /**< Mode WDOG1 for SMU_PPUFS */
<> 161:2cc1468da177 355 #define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL /**< Mode WTIMER0 for SMU_PPUFS */
<> 161:2cc1468da177 356 #define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL /**< Mode WTIMER1 for SMU_PPUFS */
<> 161:2cc1468da177 357 #define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */
<> 161:2cc1468da177 358 #define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */
<> 161:2cc1468da177 359 #define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */
<> 161:2cc1468da177 360 #define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */
<> 161:2cc1468da177 361 #define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */
<> 161:2cc1468da177 362 #define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */
<> 161:2cc1468da177 363 #define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */
<> 161:2cc1468da177 364 #define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */
<> 161:2cc1468da177 365 #define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */
<> 161:2cc1468da177 366 #define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */
<> 161:2cc1468da177 367 #define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */
<> 161:2cc1468da177 368 #define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */
<> 161:2cc1468da177 369 #define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */
<> 161:2cc1468da177 370 #define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */
<> 161:2cc1468da177 371 #define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */
<> 161:2cc1468da177 372 #define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */
<> 161:2cc1468da177 373 #define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */
<> 161:2cc1468da177 374 #define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */
<> 161:2cc1468da177 375 #define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */
<> 161:2cc1468da177 376 #define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */
<> 161:2cc1468da177 377 #define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */
<> 161:2cc1468da177 378 #define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */
<> 161:2cc1468da177 379 #define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */
<> 161:2cc1468da177 380 #define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */
<> 161:2cc1468da177 381 #define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */
<> 161:2cc1468da177 382 #define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */
<> 161:2cc1468da177 383 #define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */
<> 161:2cc1468da177 384 #define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */
<> 161:2cc1468da177 385 #define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */
<> 161:2cc1468da177 386 #define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */
<> 161:2cc1468da177 387 #define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */
<> 161:2cc1468da177 388 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */
<> 161:2cc1468da177 389 #define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */
<> 161:2cc1468da177 390 #define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */
<> 161:2cc1468da177 391 #define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */
<> 161:2cc1468da177 392 #define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */
<> 161:2cc1468da177 393 #define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */
<> 161:2cc1468da177 394 #define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */
<> 161:2cc1468da177 395 #define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */
<> 161:2cc1468da177 396 #define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */
<> 161:2cc1468da177 397
<> 161:2cc1468da177 398 /** @} End of group EFR32MG12P_SMU */
<> 161:2cc1468da177 399 /** @} End of group Parts */
<> 161:2cc1468da177 400