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mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
161:2cc1468da177 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**************************************************************************//**
<> 161:2cc1468da177 2 * @file efr32mg12p432f1024gm48.h
<> 161:2cc1468da177 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 161:2cc1468da177 4 * for EFR32MG12P432F1024GM48
<> 161:2cc1468da177 5 * @version 5.1.2
<> 161:2cc1468da177 6 ******************************************************************************
<> 161:2cc1468da177 7 * @section License
<> 161:2cc1468da177 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 161:2cc1468da177 9 ******************************************************************************
<> 161:2cc1468da177 10 *
<> 161:2cc1468da177 11 * Permission is granted to anyone to use this software for any purpose,
<> 161:2cc1468da177 12 * including commercial applications, and to alter it and redistribute it
<> 161:2cc1468da177 13 * freely, subject to the following restrictions:
<> 161:2cc1468da177 14 *
<> 161:2cc1468da177 15 * 1. The origin of this software must not be misrepresented; you must not
<> 161:2cc1468da177 16 * claim that you wrote the original software.@n
<> 161:2cc1468da177 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 161:2cc1468da177 18 * misrepresented as being the original software.@n
<> 161:2cc1468da177 19 * 3. This notice may not be removed or altered from any source distribution.
<> 161:2cc1468da177 20 *
<> 161:2cc1468da177 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 161:2cc1468da177 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 161:2cc1468da177 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 161:2cc1468da177 24 * kind, including, but not limited to, any implied warranties of
<> 161:2cc1468da177 25 * merchantability or fitness for any particular purpose or warranties against
<> 161:2cc1468da177 26 * infringement of any proprietary rights of a third party.
<> 161:2cc1468da177 27 *
<> 161:2cc1468da177 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 161:2cc1468da177 29 * incidental, or special damages, or any other relief, or for any claim by
<> 161:2cc1468da177 30 * any third party, arising from your use of this Software.
<> 161:2cc1468da177 31 *
<> 161:2cc1468da177 32 *****************************************************************************/
<> 161:2cc1468da177 33
<> 161:2cc1468da177 34 #ifndef EFR32MG12P432F1024GM48_H
<> 161:2cc1468da177 35 #define EFR32MG12P432F1024GM48_H
<> 161:2cc1468da177 36
<> 161:2cc1468da177 37 #ifdef __cplusplus
<> 161:2cc1468da177 38 extern "C" {
<> 161:2cc1468da177 39 #endif
<> 161:2cc1468da177 40
<> 161:2cc1468da177 41 /**************************************************************************//**
<> 161:2cc1468da177 42 * @addtogroup Parts
<> 161:2cc1468da177 43 * @{
<> 161:2cc1468da177 44 *****************************************************************************/
<> 161:2cc1468da177 45
<> 161:2cc1468da177 46 /**************************************************************************//**
<> 161:2cc1468da177 47 * @defgroup EFR32MG12P432F1024GM48 EFR32MG12P432F1024GM48
<> 161:2cc1468da177 48 * @{
<> 161:2cc1468da177 49 *****************************************************************************/
<> 161:2cc1468da177 50
<> 161:2cc1468da177 51 /** Interrupt Number Definition */
<> 161:2cc1468da177 52 typedef enum IRQn
<> 161:2cc1468da177 53 {
<> 161:2cc1468da177 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
<> 161:2cc1468da177 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
<> 161:2cc1468da177 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
<> 161:2cc1468da177 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
<> 161:2cc1468da177 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
<> 161:2cc1468da177 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
<> 161:2cc1468da177 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
<> 161:2cc1468da177 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
<> 161:2cc1468da177 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
<> 161:2cc1468da177 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
<> 161:2cc1468da177 64
<> 161:2cc1468da177 65 /****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/
<> 161:2cc1468da177 66
<> 161:2cc1468da177 67 EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
<> 161:2cc1468da177 68 WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
<> 161:2cc1468da177 69 WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
<> 161:2cc1468da177 70 LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
<> 161:2cc1468da177 71 GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
<> 161:2cc1468da177 72 TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
<> 161:2cc1468da177 73 USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
<> 161:2cc1468da177 74 USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
<> 161:2cc1468da177 75 ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
<> 161:2cc1468da177 76 ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
<> 161:2cc1468da177 77 IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
<> 161:2cc1468da177 78 I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
<> 161:2cc1468da177 79 GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
<> 161:2cc1468da177 80 TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
<> 161:2cc1468da177 81 USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
<> 161:2cc1468da177 82 USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
<> 161:2cc1468da177 83 LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
<> 161:2cc1468da177 84 PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
<> 161:2cc1468da177 85 CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
<> 161:2cc1468da177 86 MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
<> 161:2cc1468da177 87 CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
<> 161:2cc1468da177 88 LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
<> 161:2cc1468da177 89 RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
<> 161:2cc1468da177 90 CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
<> 161:2cc1468da177 91 FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
<> 161:2cc1468da177 92 SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
<> 161:2cc1468da177 93 WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
<> 161:2cc1468da177 94 WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
<> 161:2cc1468da177 95 PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
<> 161:2cc1468da177 96 PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
<> 161:2cc1468da177 97 USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
<> 161:2cc1468da177 98 USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
<> 161:2cc1468da177 99 I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
<> 161:2cc1468da177 100 USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
<> 161:2cc1468da177 101 USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
<> 161:2cc1468da177 102 VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
<> 161:2cc1468da177 103 CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
<> 161:2cc1468da177 104 LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
<> 161:2cc1468da177 105 CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
<> 161:2cc1468da177 106 TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
<> 161:2cc1468da177 107 } IRQn_Type;
<> 161:2cc1468da177 108
<> 161:2cc1468da177 109 #define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
<> 161:2cc1468da177 110
<> 161:2cc1468da177 111 /**************************************************************************//**
<> 161:2cc1468da177 112 * @defgroup EFR32MG12P432F1024GM48_Core EFR32MG12P432F1024GM48 Core
<> 161:2cc1468da177 113 * @{
<> 161:2cc1468da177 114 * @brief Processor and Core Peripheral Section
<> 161:2cc1468da177 115 *****************************************************************************/
<> 161:2cc1468da177 116 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 161:2cc1468da177 117 #define __FPU_PRESENT 1 /**< Presence of FPU */
<> 161:2cc1468da177 118 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 161:2cc1468da177 119 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 161:2cc1468da177 120 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 161:2cc1468da177 121
<> 161:2cc1468da177 122 /** @} End of group EFR32MG12P432F1024GM48_Core */
<> 161:2cc1468da177 123
<> 161:2cc1468da177 124 /**************************************************************************//**
<> 161:2cc1468da177 125 * @defgroup EFR32MG12P432F1024GM48_Part EFR32MG12P432F1024GM48 Part
<> 161:2cc1468da177 126 * @{
<> 161:2cc1468da177 127 ******************************************************************************/
<> 161:2cc1468da177 128
<> 161:2cc1468da177 129 /** Part family */
<> 161:2cc1468da177 130 #define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
<> 161:2cc1468da177 131 #define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
<> 161:2cc1468da177 132 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
<> 161:2cc1468da177 133 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
<> 161:2cc1468da177 134 #define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
<> 161:2cc1468da177 135 #define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
<> 161:2cc1468da177 136 #define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
<> 161:2cc1468da177 137 #define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
<> 161:2cc1468da177 138 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
<> 161:2cc1468da177 139 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
<> 161:2cc1468da177 140 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
<> 161:2cc1468da177 141 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ
<> 161:2cc1468da177 142 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
<> 161:2cc1468da177 143 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
<> 161:2cc1468da177 144 #define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
<> 161:2cc1468da177 145 #define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
<> 161:2cc1468da177 146
<> 161:2cc1468da177 147 /* If part number is not defined as compiler option, define it */
<> 161:2cc1468da177 148 #if !defined(EFR32MG12P432F1024GM48)
<> 161:2cc1468da177 149 #define EFR32MG12P432F1024GM48 1 /**< MIGHTY Gecko Part */
<> 161:2cc1468da177 150 #endif
<> 161:2cc1468da177 151
<> 161:2cc1468da177 152 /** Configure part number */
<> 161:2cc1468da177 153 #define PART_NUMBER "EFR32MG12P432F1024GM48" /**< Part Number */
<> 161:2cc1468da177 154
<> 161:2cc1468da177 155 /** Memory Base addresses and limits */
<> 161:2cc1468da177 156 #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
<> 161:2cc1468da177 157 #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
<> 161:2cc1468da177 158 #define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
<> 161:2cc1468da177 159 #define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
<> 161:2cc1468da177 160 #define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
<> 161:2cc1468da177 161 #define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
<> 161:2cc1468da177 162 #define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
<> 161:2cc1468da177 163 #define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
<> 161:2cc1468da177 164 #define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
<> 161:2cc1468da177 165 #define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
<> 161:2cc1468da177 166 #define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
<> 161:2cc1468da177 167 #define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
<> 161:2cc1468da177 168 #define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
<> 161:2cc1468da177 169 #define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
<> 161:2cc1468da177 170 #define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
<> 161:2cc1468da177 171 #define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
<> 161:2cc1468da177 172 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 161:2cc1468da177 173 #define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
<> 161:2cc1468da177 174 #define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
<> 161:2cc1468da177 175 #define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
<> 161:2cc1468da177 176 #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
<> 161:2cc1468da177 177 #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
<> 161:2cc1468da177 178 #define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
<> 161:2cc1468da177 179 #define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
<> 161:2cc1468da177 180 #define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
<> 161:2cc1468da177 181 #define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
<> 161:2cc1468da177 182 #define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
<> 161:2cc1468da177 183 #define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
<> 161:2cc1468da177 184 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
<> 161:2cc1468da177 185 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 161:2cc1468da177 186 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
<> 161:2cc1468da177 187 #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
<> 161:2cc1468da177 188 #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
<> 161:2cc1468da177 189 #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
<> 161:2cc1468da177 190 #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
<> 161:2cc1468da177 191 #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
<> 161:2cc1468da177 192 #define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
<> 161:2cc1468da177 193 #define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
<> 161:2cc1468da177 194 #define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
<> 161:2cc1468da177 195 #define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
<> 161:2cc1468da177 196 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
<> 161:2cc1468da177 197 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
<> 161:2cc1468da177 198 #define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
<> 161:2cc1468da177 199 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
<> 161:2cc1468da177 200 #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
<> 161:2cc1468da177 201 #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
<> 161:2cc1468da177 202 #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
<> 161:2cc1468da177 203 #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
<> 161:2cc1468da177 204 #define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
<> 161:2cc1468da177 205 #define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
<> 161:2cc1468da177 206 #define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
<> 161:2cc1468da177 207 #define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
<> 161:2cc1468da177 208 #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
<> 161:2cc1468da177 209 #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
<> 161:2cc1468da177 210 #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
<> 161:2cc1468da177 211 #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
<> 161:2cc1468da177 212 #define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
<> 161:2cc1468da177 213 #define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
<> 161:2cc1468da177 214 #define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
<> 161:2cc1468da177 215 #define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
<> 161:2cc1468da177 216 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
<> 161:2cc1468da177 217 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
<> 161:2cc1468da177 218 #define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
<> 161:2cc1468da177 219 #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
<> 161:2cc1468da177 220 #define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
<> 161:2cc1468da177 221 #define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
<> 161:2cc1468da177 222 #define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
<> 161:2cc1468da177 223 #define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
<> 161:2cc1468da177 224 #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
<> 161:2cc1468da177 225 #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
<> 161:2cc1468da177 226 #define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
<> 161:2cc1468da177 227 #define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
<> 161:2cc1468da177 228 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 161:2cc1468da177 229 #define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
<> 161:2cc1468da177 230 #define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
<> 161:2cc1468da177 231 #define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
<> 161:2cc1468da177 232
<> 161:2cc1468da177 233 /** Bit banding area */
<> 161:2cc1468da177 234 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 161:2cc1468da177 235 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 161:2cc1468da177 236
<> 161:2cc1468da177 237 /** Flash and SRAM limits for EFR32MG12P432F1024GM48 */
<> 161:2cc1468da177 238 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 161:2cc1468da177 239 #define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
<> 161:2cc1468da177 240 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
<> 161:2cc1468da177 241 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 161:2cc1468da177 242 #define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
<> 161:2cc1468da177 243 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
<> 161:2cc1468da177 244 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 161:2cc1468da177 245 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
<> 161:2cc1468da177 246 #define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
<> 161:2cc1468da177 247
<> 161:2cc1468da177 248 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 161:2cc1468da177 249 #define AFCHAN_MAX 136
<> 161:2cc1468da177 250 #define AFCHANLOC_MAX 32
<> 161:2cc1468da177 251 /** Analog AF channels */
<> 161:2cc1468da177 252 #define AFACHAN_MAX 125
<> 161:2cc1468da177 253
<> 161:2cc1468da177 254 /* Part number capabilities */
<> 161:2cc1468da177 255
<> 161:2cc1468da177 256 #define CRYPTO_PRESENT /**< CRYPTO is available in this part */
<> 161:2cc1468da177 257 #define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
<> 161:2cc1468da177 258 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 161:2cc1468da177 259 #define TIMER_COUNT 2 /**< 2 TIMERs available */
<> 161:2cc1468da177 260 #define WTIMER_PRESENT /**< WTIMER is available in this part */
<> 161:2cc1468da177 261 #define WTIMER_COUNT 2 /**< 2 WTIMERs available */
<> 161:2cc1468da177 262 #define USART_PRESENT /**< USART is available in this part */
<> 161:2cc1468da177 263 #define USART_COUNT 4 /**< 4 USARTs available */
<> 161:2cc1468da177 264 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 161:2cc1468da177 265 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
<> 161:2cc1468da177 266 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 161:2cc1468da177 267 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 161:2cc1468da177 268 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 161:2cc1468da177 269 #define PCNT_COUNT 3 /**< 3 PCNTs available */
<> 161:2cc1468da177 270 #define I2C_PRESENT /**< I2C is available in this part */
<> 161:2cc1468da177 271 #define I2C_COUNT 2 /**< 2 I2Cs available */
<> 161:2cc1468da177 272 #define ADC_PRESENT /**< ADC is available in this part */
<> 161:2cc1468da177 273 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 161:2cc1468da177 274 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 161:2cc1468da177 275 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 161:2cc1468da177 276 #define IDAC_PRESENT /**< IDAC is available in this part */
<> 161:2cc1468da177 277 #define IDAC_COUNT 1 /**< 1 IDACs available */
<> 161:2cc1468da177 278 #define VDAC_PRESENT /**< VDAC is available in this part */
<> 161:2cc1468da177 279 #define VDAC_COUNT 1 /**< 1 VDACs available */
<> 161:2cc1468da177 280 #define WDOG_PRESENT /**< WDOG is available in this part */
<> 161:2cc1468da177 281 #define WDOG_COUNT 2 /**< 2 WDOGs available */
<> 161:2cc1468da177 282 #define TRNG_PRESENT /**< TRNG is available in this part */
<> 161:2cc1468da177 283 #define TRNG_COUNT 1 /**< 1 TRNGs available */
<> 161:2cc1468da177 284 #define SYSTICK_PRESENT
<> 161:2cc1468da177 285 #define SYSTICK_COUNT 1
<> 161:2cc1468da177 286 #define MSC_PRESENT
<> 161:2cc1468da177 287 #define MSC_COUNT 1
<> 161:2cc1468da177 288 #define EMU_PRESENT
<> 161:2cc1468da177 289 #define EMU_COUNT 1
<> 161:2cc1468da177 290 #define RMU_PRESENT
<> 161:2cc1468da177 291 #define RMU_COUNT 1
<> 161:2cc1468da177 292 #define CMU_PRESENT
<> 161:2cc1468da177 293 #define CMU_COUNT 1
<> 161:2cc1468da177 294 #define GPIO_PRESENT
<> 161:2cc1468da177 295 #define GPIO_COUNT 1
<> 161:2cc1468da177 296 #define PRS_PRESENT
<> 161:2cc1468da177 297 #define PRS_COUNT 1
<> 161:2cc1468da177 298 #define LDMA_PRESENT
<> 161:2cc1468da177 299 #define LDMA_COUNT 1
<> 161:2cc1468da177 300 #define FPUEH_PRESENT
<> 161:2cc1468da177 301 #define FPUEH_COUNT 1
<> 161:2cc1468da177 302 #define GPCRC_PRESENT
<> 161:2cc1468da177 303 #define GPCRC_COUNT 1
<> 161:2cc1468da177 304 #define CRYOTIMER_PRESENT
<> 161:2cc1468da177 305 #define CRYOTIMER_COUNT 1
<> 161:2cc1468da177 306 #define CSEN_PRESENT
<> 161:2cc1468da177 307 #define CSEN_COUNT 1
<> 161:2cc1468da177 308 #define LESENSE_PRESENT
<> 161:2cc1468da177 309 #define LESENSE_COUNT 1
<> 161:2cc1468da177 310 #define RTCC_PRESENT
<> 161:2cc1468da177 311 #define RTCC_COUNT 1
<> 161:2cc1468da177 312 #define ETM_PRESENT
<> 161:2cc1468da177 313 #define ETM_COUNT 1
<> 161:2cc1468da177 314 #define BOOTLOADER_PRESENT
<> 161:2cc1468da177 315 #define BOOTLOADER_COUNT 1
<> 161:2cc1468da177 316 #define SMU_PRESENT
<> 161:2cc1468da177 317 #define SMU_COUNT 1
<> 161:2cc1468da177 318
<> 161:2cc1468da177 319 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 161:2cc1468da177 320 #include "system_efr32mg12p.h" /* System Header File */
<> 161:2cc1468da177 321
<> 161:2cc1468da177 322 /** @} End of group EFR32MG12P432F1024GM48_Part */
<> 161:2cc1468da177 323
<> 161:2cc1468da177 324 /**************************************************************************//**
<> 161:2cc1468da177 325 * @defgroup EFR32MG12P432F1024GM48_Peripheral_TypeDefs EFR32MG12P432F1024GM48 Peripheral TypeDefs
<> 161:2cc1468da177 326 * @{
<> 161:2cc1468da177 327 * @brief Device Specific Peripheral Register Structures
<> 161:2cc1468da177 328 *****************************************************************************/
<> 161:2cc1468da177 329
<> 161:2cc1468da177 330 #include "efr32mg12p_msc.h"
<> 161:2cc1468da177 331 #include "efr32mg12p_emu.h"
<> 161:2cc1468da177 332 #include "efr32mg12p_rmu.h"
<> 161:2cc1468da177 333 #include "efr32mg12p_cmu.h"
<> 161:2cc1468da177 334 #include "efr32mg12p_crypto.h"
<> 161:2cc1468da177 335 #include "efr32mg12p_gpio_p.h"
<> 161:2cc1468da177 336 #include "efr32mg12p_gpio.h"
<> 161:2cc1468da177 337 #include "efr32mg12p_prs_ch.h"
<> 161:2cc1468da177 338 #include "efr32mg12p_prs.h"
<> 161:2cc1468da177 339 #include "efr32mg12p_ldma_ch.h"
<> 161:2cc1468da177 340 #include "efr32mg12p_ldma.h"
<> 161:2cc1468da177 341 #include "efr32mg12p_fpueh.h"
<> 161:2cc1468da177 342 #include "efr32mg12p_gpcrc.h"
<> 161:2cc1468da177 343 #include "efr32mg12p_timer_cc.h"
<> 161:2cc1468da177 344 #include "efr32mg12p_timer.h"
<> 161:2cc1468da177 345 #include "efr32mg12p_usart.h"
<> 161:2cc1468da177 346 #include "efr32mg12p_leuart.h"
<> 161:2cc1468da177 347 #include "efr32mg12p_letimer.h"
<> 161:2cc1468da177 348 #include "efr32mg12p_cryotimer.h"
<> 161:2cc1468da177 349 #include "efr32mg12p_pcnt.h"
<> 161:2cc1468da177 350 #include "efr32mg12p_i2c.h"
<> 161:2cc1468da177 351 #include "efr32mg12p_adc.h"
<> 161:2cc1468da177 352 #include "efr32mg12p_acmp.h"
<> 161:2cc1468da177 353 #include "efr32mg12p_idac.h"
<> 161:2cc1468da177 354 #include "efr32mg12p_vdac_opa.h"
<> 161:2cc1468da177 355 #include "efr32mg12p_vdac.h"
<> 161:2cc1468da177 356 #include "efr32mg12p_csen.h"
<> 161:2cc1468da177 357 #include "efr32mg12p_lesense_st.h"
<> 161:2cc1468da177 358 #include "efr32mg12p_lesense_buf.h"
<> 161:2cc1468da177 359 #include "efr32mg12p_lesense_ch.h"
<> 161:2cc1468da177 360 #include "efr32mg12p_lesense.h"
<> 161:2cc1468da177 361 #include "efr32mg12p_rtcc_cc.h"
<> 161:2cc1468da177 362 #include "efr32mg12p_rtcc_ret.h"
<> 161:2cc1468da177 363 #include "efr32mg12p_rtcc.h"
<> 161:2cc1468da177 364 #include "efr32mg12p_wdog_pch.h"
<> 161:2cc1468da177 365 #include "efr32mg12p_wdog.h"
<> 161:2cc1468da177 366 #include "efr32mg12p_etm.h"
<> 161:2cc1468da177 367 #include "efr32mg12p_smu.h"
<> 161:2cc1468da177 368 #include "efr32mg12p_trng.h"
<> 161:2cc1468da177 369 #include "efr32mg12p_dma_descriptor.h"
<> 161:2cc1468da177 370 #include "efr32mg12p_devinfo.h"
<> 161:2cc1468da177 371 #include "efr32mg12p_romtable.h"
<> 161:2cc1468da177 372
<> 161:2cc1468da177 373 /** @} End of group EFR32MG12P432F1024GM48_Peripheral_TypeDefs */
<> 161:2cc1468da177 374
<> 161:2cc1468da177 375 /**************************************************************************//**
<> 161:2cc1468da177 376 * @defgroup EFR32MG12P432F1024GM48_Peripheral_Base EFR32MG12P432F1024GM48 Peripheral Memory Map
<> 161:2cc1468da177 377 * @{
<> 161:2cc1468da177 378 *****************************************************************************/
<> 161:2cc1468da177 379
<> 161:2cc1468da177 380 #define MSC_BASE (0x400E0000UL) /**< MSC base address */
<> 161:2cc1468da177 381 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
<> 161:2cc1468da177 382 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
<> 161:2cc1468da177 383 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
<> 161:2cc1468da177 384 #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */
<> 161:2cc1468da177 385 #define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */
<> 161:2cc1468da177 386 #define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */
<> 161:2cc1468da177 387 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
<> 161:2cc1468da177 388 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
<> 161:2cc1468da177 389 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
<> 161:2cc1468da177 390 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
<> 161:2cc1468da177 391 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
<> 161:2cc1468da177 392 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
<> 161:2cc1468da177 393 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
<> 161:2cc1468da177 394 #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
<> 161:2cc1468da177 395 #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
<> 161:2cc1468da177 396 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
<> 161:2cc1468da177 397 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
<> 161:2cc1468da177 398 #define USART2_BASE (0x40010800UL) /**< USART2 base address */
<> 161:2cc1468da177 399 #define USART3_BASE (0x40010C00UL) /**< USART3 base address */
<> 161:2cc1468da177 400 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
<> 161:2cc1468da177 401 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
<> 161:2cc1468da177 402 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
<> 161:2cc1468da177 403 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
<> 161:2cc1468da177 404 #define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */
<> 161:2cc1468da177 405 #define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */
<> 161:2cc1468da177 406 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
<> 161:2cc1468da177 407 #define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
<> 161:2cc1468da177 408 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 161:2cc1468da177 409 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
<> 161:2cc1468da177 410 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
<> 161:2cc1468da177 411 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
<> 161:2cc1468da177 412 #define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
<> 161:2cc1468da177 413 #define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
<> 161:2cc1468da177 414 #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
<> 161:2cc1468da177 415 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */
<> 161:2cc1468da177 416 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
<> 161:2cc1468da177 417 #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
<> 161:2cc1468da177 418 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
<> 161:2cc1468da177 419 #define SMU_BASE (0x40022000UL) /**< SMU base address */
<> 161:2cc1468da177 420 #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
<> 161:2cc1468da177 421 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 161:2cc1468da177 422 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 161:2cc1468da177 423 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 161:2cc1468da177 424 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 161:2cc1468da177 425
<> 161:2cc1468da177 426 /** @} End of group EFR32MG12P432F1024GM48_Peripheral_Base */
<> 161:2cc1468da177 427
<> 161:2cc1468da177 428 /**************************************************************************//**
<> 161:2cc1468da177 429 * @defgroup EFR32MG12P432F1024GM48_Peripheral_Declaration EFR32MG12P432F1024GM48 Peripheral Declarations
<> 161:2cc1468da177 430 * @{
<> 161:2cc1468da177 431 *****************************************************************************/
<> 161:2cc1468da177 432
<> 161:2cc1468da177 433 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 161:2cc1468da177 434 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 161:2cc1468da177 435 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 161:2cc1468da177 436 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 161:2cc1468da177 437 #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */
<> 161:2cc1468da177 438 #define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */
<> 161:2cc1468da177 439 #define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */
<> 161:2cc1468da177 440 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 161:2cc1468da177 441 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 161:2cc1468da177 442 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
<> 161:2cc1468da177 443 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
<> 161:2cc1468da177 444 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
<> 161:2cc1468da177 445 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 161:2cc1468da177 446 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 161:2cc1468da177 447 #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
<> 161:2cc1468da177 448 #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
<> 161:2cc1468da177 449 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 161:2cc1468da177 450 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 161:2cc1468da177 451 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
<> 161:2cc1468da177 452 #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
<> 161:2cc1468da177 453 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 161:2cc1468da177 454 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 161:2cc1468da177 455 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
<> 161:2cc1468da177 456 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 161:2cc1468da177 457 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
<> 161:2cc1468da177 458 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
<> 161:2cc1468da177 459 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 161:2cc1468da177 460 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
<> 161:2cc1468da177 461 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 161:2cc1468da177 462 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 161:2cc1468da177 463 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 161:2cc1468da177 464 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
<> 161:2cc1468da177 465 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
<> 161:2cc1468da177 466 #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
<> 161:2cc1468da177 467 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
<> 161:2cc1468da177 468 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
<> 161:2cc1468da177 469 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
<> 161:2cc1468da177 470 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
<> 161:2cc1468da177 471 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
<> 161:2cc1468da177 472 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
<> 161:2cc1468da177 473 #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
<> 161:2cc1468da177 474 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 161:2cc1468da177 475 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 161:2cc1468da177 476
<> 161:2cc1468da177 477 /** @} End of group EFR32MG12P432F1024GM48_Peripheral_Declaration */
<> 161:2cc1468da177 478
<> 161:2cc1468da177 479 /**************************************************************************//**
<> 161:2cc1468da177 480 * @defgroup EFR32MG12P432F1024GM48_Peripheral_Offsets EFR32MG12P432F1024GM48 Peripheral Offsets
<> 161:2cc1468da177 481 * @{
<> 161:2cc1468da177 482 *****************************************************************************/
<> 161:2cc1468da177 483
<> 161:2cc1468da177 484 #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
<> 161:2cc1468da177 485 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
<> 161:2cc1468da177 486 #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */
<> 161:2cc1468da177 487 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
<> 161:2cc1468da177 488 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
<> 161:2cc1468da177 489 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
<> 161:2cc1468da177 490 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
<> 161:2cc1468da177 491 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
<> 161:2cc1468da177 492 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
<> 161:2cc1468da177 493 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
<> 161:2cc1468da177 494 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
<> 161:2cc1468da177 495 #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
<> 161:2cc1468da177 496 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
<> 161:2cc1468da177 497 #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
<> 161:2cc1468da177 498
<> 161:2cc1468da177 499 /** @} End of group EFR32MG12P432F1024GM48_Peripheral_Offsets */
<> 161:2cc1468da177 500
<> 161:2cc1468da177 501
<> 161:2cc1468da177 502 /**************************************************************************//**
<> 161:2cc1468da177 503 * @defgroup EFR32MG12P432F1024GM48_BitFields EFR32MG12P432F1024GM48 Bit Fields
<> 161:2cc1468da177 504 * @{
<> 161:2cc1468da177 505 *****************************************************************************/
<> 161:2cc1468da177 506
<> 161:2cc1468da177 507 #include "efr32mg12p_prs_signals.h"
<> 161:2cc1468da177 508 #include "efr32mg12p_dmareq.h"
<> 161:2cc1468da177 509
<> 161:2cc1468da177 510 /**************************************************************************//**
<> 161:2cc1468da177 511 * @defgroup EFR32MG12P432F1024GM48_WTIMER_BitFields EFR32MG12P432F1024GM48_WTIMER Bit Fields
<> 161:2cc1468da177 512 * @{
<> 161:2cc1468da177 513 *****************************************************************************/
<> 161:2cc1468da177 514
<> 161:2cc1468da177 515 /* Bit fields for WTIMER CTRL */
<> 161:2cc1468da177 516 #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
<> 161:2cc1468da177 517 #define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */
<> 161:2cc1468da177 518 #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
<> 161:2cc1468da177 519 #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
<> 161:2cc1468da177 520 #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 521 #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */
<> 161:2cc1468da177 522 #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */
<> 161:2cc1468da177 523 #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */
<> 161:2cc1468da177 524 #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */
<> 161:2cc1468da177 525 #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 526 #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */
<> 161:2cc1468da177 527 #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */
<> 161:2cc1468da177 528 #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */
<> 161:2cc1468da177 529 #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */
<> 161:2cc1468da177 530 #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
<> 161:2cc1468da177 531 #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
<> 161:2cc1468da177 532 #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
<> 161:2cc1468da177 533 #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 534 #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 535 #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
<> 161:2cc1468da177 536 #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
<> 161:2cc1468da177 537 #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
<> 161:2cc1468da177 538 #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 539 #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 540 #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
<> 161:2cc1468da177 541 #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
<> 161:2cc1468da177 542 #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
<> 161:2cc1468da177 543 #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 544 #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */
<> 161:2cc1468da177 545 #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */
<> 161:2cc1468da177 546 #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 547 #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */
<> 161:2cc1468da177 548 #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */
<> 161:2cc1468da177 549 #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
<> 161:2cc1468da177 550 #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
<> 161:2cc1468da177 551 #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
<> 161:2cc1468da177 552 #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 553 #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 554 #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
<> 161:2cc1468da177 555 #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
<> 161:2cc1468da177 556 #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
<> 161:2cc1468da177 557 #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 558 #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 559 #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
<> 161:2cc1468da177 560 #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
<> 161:2cc1468da177 561 #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 562 #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
<> 161:2cc1468da177 563 #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
<> 161:2cc1468da177 564 #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
<> 161:2cc1468da177 565 #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
<> 161:2cc1468da177 566 #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 567 #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */
<> 161:2cc1468da177 568 #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */
<> 161:2cc1468da177 569 #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */
<> 161:2cc1468da177 570 #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
<> 161:2cc1468da177 571 #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
<> 161:2cc1468da177 572 #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
<> 161:2cc1468da177 573 #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 574 #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
<> 161:2cc1468da177 575 #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
<> 161:2cc1468da177 576 #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
<> 161:2cc1468da177 577 #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
<> 161:2cc1468da177 578 #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 579 #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */
<> 161:2cc1468da177 580 #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */
<> 161:2cc1468da177 581 #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */
<> 161:2cc1468da177 582 #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
<> 161:2cc1468da177 583 #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
<> 161:2cc1468da177 584 #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
<> 161:2cc1468da177 585 #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
<> 161:2cc1468da177 586 #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 587 #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 588 #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
<> 161:2cc1468da177 589 #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
<> 161:2cc1468da177 590 #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 591 #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */
<> 161:2cc1468da177 592 #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */
<> 161:2cc1468da177 593 #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */
<> 161:2cc1468da177 594 #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 595 #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */
<> 161:2cc1468da177 596 #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */
<> 161:2cc1468da177 597 #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */
<> 161:2cc1468da177 598 #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
<> 161:2cc1468da177 599 #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
<> 161:2cc1468da177 600 #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 601 #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */
<> 161:2cc1468da177 602 #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */
<> 161:2cc1468da177 603 #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */
<> 161:2cc1468da177 604 #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */
<> 161:2cc1468da177 605 #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */
<> 161:2cc1468da177 606 #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */
<> 161:2cc1468da177 607 #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */
<> 161:2cc1468da177 608 #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */
<> 161:2cc1468da177 609 #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */
<> 161:2cc1468da177 610 #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */
<> 161:2cc1468da177 611 #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */
<> 161:2cc1468da177 612 #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 613 #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */
<> 161:2cc1468da177 614 #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */
<> 161:2cc1468da177 615 #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */
<> 161:2cc1468da177 616 #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */
<> 161:2cc1468da177 617 #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */
<> 161:2cc1468da177 618 #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */
<> 161:2cc1468da177 619 #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */
<> 161:2cc1468da177 620 #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */
<> 161:2cc1468da177 621 #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */
<> 161:2cc1468da177 622 #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */
<> 161:2cc1468da177 623 #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */
<> 161:2cc1468da177 624 #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
<> 161:2cc1468da177 625 #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
<> 161:2cc1468da177 626 #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
<> 161:2cc1468da177 627 #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 628 #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 629 #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
<> 161:2cc1468da177 630 #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
<> 161:2cc1468da177 631 #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
<> 161:2cc1468da177 632 #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 633 #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */
<> 161:2cc1468da177 634
<> 161:2cc1468da177 635 /* Bit fields for WTIMER CMD */
<> 161:2cc1468da177 636 #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */
<> 161:2cc1468da177 637 #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */
<> 161:2cc1468da177 638 #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */
<> 161:2cc1468da177 639 #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
<> 161:2cc1468da177 640 #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
<> 161:2cc1468da177 641 #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
<> 161:2cc1468da177 642 #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */
<> 161:2cc1468da177 643 #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
<> 161:2cc1468da177 644 #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
<> 161:2cc1468da177 645 #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
<> 161:2cc1468da177 646 #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
<> 161:2cc1468da177 647 #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */
<> 161:2cc1468da177 648
<> 161:2cc1468da177 649 /* Bit fields for WTIMER STATUS */
<> 161:2cc1468da177 650 #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */
<> 161:2cc1468da177 651 #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */
<> 161:2cc1468da177 652 #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
<> 161:2cc1468da177 653 #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
<> 161:2cc1468da177 654 #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
<> 161:2cc1468da177 655 #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 656 #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 657 #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
<> 161:2cc1468da177 658 #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
<> 161:2cc1468da177 659 #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
<> 161:2cc1468da177 660 #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 661 #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */
<> 161:2cc1468da177 662 #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */
<> 161:2cc1468da177 663 #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 664 #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */
<> 161:2cc1468da177 665 #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */
<> 161:2cc1468da177 666 #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
<> 161:2cc1468da177 667 #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
<> 161:2cc1468da177 668 #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
<> 161:2cc1468da177 669 #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 670 #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 671 #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
<> 161:2cc1468da177 672 #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
<> 161:2cc1468da177 673 #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
<> 161:2cc1468da177 674 #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 675 #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 676 #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
<> 161:2cc1468da177 677 #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
<> 161:2cc1468da177 678 #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
<> 161:2cc1468da177 679 #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 680 #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 681 #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
<> 161:2cc1468da177 682 #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
<> 161:2cc1468da177 683 #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
<> 161:2cc1468da177 684 #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 685 #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 686 #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
<> 161:2cc1468da177 687 #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
<> 161:2cc1468da177 688 #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
<> 161:2cc1468da177 689 #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 690 #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 691 #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
<> 161:2cc1468da177 692 #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
<> 161:2cc1468da177 693 #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
<> 161:2cc1468da177 694 #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 695 #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 696 #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
<> 161:2cc1468da177 697 #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
<> 161:2cc1468da177 698 #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
<> 161:2cc1468da177 699 #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 700 #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 701 #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
<> 161:2cc1468da177 702 #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
<> 161:2cc1468da177 703 #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
<> 161:2cc1468da177 704 #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 705 #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 706 #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
<> 161:2cc1468da177 707 #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
<> 161:2cc1468da177 708 #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
<> 161:2cc1468da177 709 #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 710 #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 711 #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
<> 161:2cc1468da177 712 #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
<> 161:2cc1468da177 713 #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
<> 161:2cc1468da177 714 #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 715 #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 716 #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 717 #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 718 #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 719 #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 720 #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
<> 161:2cc1468da177 721 #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
<> 161:2cc1468da177 722 #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
<> 161:2cc1468da177 723 #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 724 #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 725 #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 726 #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 727 #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 728 #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 729 #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
<> 161:2cc1468da177 730 #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
<> 161:2cc1468da177 731 #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
<> 161:2cc1468da177 732 #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 733 #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 734 #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 735 #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 736 #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 737 #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 738 #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
<> 161:2cc1468da177 739 #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
<> 161:2cc1468da177 740 #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
<> 161:2cc1468da177 741 #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 742 #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 743 #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 744 #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */
<> 161:2cc1468da177 745 #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */
<> 161:2cc1468da177 746 #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
<> 161:2cc1468da177 747
<> 161:2cc1468da177 748 /* Bit fields for WTIMER IF */
<> 161:2cc1468da177 749 #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */
<> 161:2cc1468da177 750 #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */
<> 161:2cc1468da177 751 #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 161:2cc1468da177 752 #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 161:2cc1468da177 753 #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 161:2cc1468da177 754 #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 755 #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 756 #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
<> 161:2cc1468da177 757 #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 161:2cc1468da177 758 #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 161:2cc1468da177 759 #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 760 #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 761 #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
<> 161:2cc1468da177 762 #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
<> 161:2cc1468da177 763 #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
<> 161:2cc1468da177 764 #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 765 #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 766 #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
<> 161:2cc1468da177 767 #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 161:2cc1468da177 768 #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 161:2cc1468da177 769 #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 770 #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 771 #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
<> 161:2cc1468da177 772 #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 161:2cc1468da177 773 #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 161:2cc1468da177 774 #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 775 #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 776 #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
<> 161:2cc1468da177 777 #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 161:2cc1468da177 778 #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 161:2cc1468da177 779 #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 780 #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 781 #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
<> 161:2cc1468da177 782 #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
<> 161:2cc1468da177 783 #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
<> 161:2cc1468da177 784 #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 785 #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 786 #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
<> 161:2cc1468da177 787 #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 161:2cc1468da177 788 #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 161:2cc1468da177 789 #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 790 #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 791 #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
<> 161:2cc1468da177 792 #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 161:2cc1468da177 793 #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 161:2cc1468da177 794 #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 795 #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 796 #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
<> 161:2cc1468da177 797 #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 161:2cc1468da177 798 #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 161:2cc1468da177 799 #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 800 #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 801 #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
<> 161:2cc1468da177 802 #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
<> 161:2cc1468da177 803 #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
<> 161:2cc1468da177 804 #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 805 #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */
<> 161:2cc1468da177 806
<> 161:2cc1468da177 807 /* Bit fields for WTIMER IFS */
<> 161:2cc1468da177 808 #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */
<> 161:2cc1468da177 809 #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */
<> 161:2cc1468da177 810 #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
<> 161:2cc1468da177 811 #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 161:2cc1468da177 812 #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 161:2cc1468da177 813 #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 814 #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 815 #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
<> 161:2cc1468da177 816 #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 161:2cc1468da177 817 #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 161:2cc1468da177 818 #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 819 #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 820 #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
<> 161:2cc1468da177 821 #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
<> 161:2cc1468da177 822 #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
<> 161:2cc1468da177 823 #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 824 #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 825 #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
<> 161:2cc1468da177 826 #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 161:2cc1468da177 827 #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 161:2cc1468da177 828 #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 829 #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 830 #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
<> 161:2cc1468da177 831 #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 161:2cc1468da177 832 #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 161:2cc1468da177 833 #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 834 #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 835 #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
<> 161:2cc1468da177 836 #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 161:2cc1468da177 837 #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 161:2cc1468da177 838 #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 839 #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 840 #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
<> 161:2cc1468da177 841 #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
<> 161:2cc1468da177 842 #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
<> 161:2cc1468da177 843 #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 844 #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 845 #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
<> 161:2cc1468da177 846 #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 161:2cc1468da177 847 #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 161:2cc1468da177 848 #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 849 #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 850 #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
<> 161:2cc1468da177 851 #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 161:2cc1468da177 852 #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 161:2cc1468da177 853 #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 854 #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 855 #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
<> 161:2cc1468da177 856 #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 161:2cc1468da177 857 #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 161:2cc1468da177 858 #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 859 #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 860 #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
<> 161:2cc1468da177 861 #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
<> 161:2cc1468da177 862 #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
<> 161:2cc1468da177 863 #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 864 #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */
<> 161:2cc1468da177 865
<> 161:2cc1468da177 866 /* Bit fields for WTIMER IFC */
<> 161:2cc1468da177 867 #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */
<> 161:2cc1468da177 868 #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */
<> 161:2cc1468da177 869 #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
<> 161:2cc1468da177 870 #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 161:2cc1468da177 871 #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 161:2cc1468da177 872 #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 873 #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 874 #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
<> 161:2cc1468da177 875 #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 161:2cc1468da177 876 #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 161:2cc1468da177 877 #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 878 #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 879 #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
<> 161:2cc1468da177 880 #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
<> 161:2cc1468da177 881 #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
<> 161:2cc1468da177 882 #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 883 #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 884 #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
<> 161:2cc1468da177 885 #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 161:2cc1468da177 886 #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 161:2cc1468da177 887 #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 888 #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 889 #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
<> 161:2cc1468da177 890 #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 161:2cc1468da177 891 #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 161:2cc1468da177 892 #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 893 #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 894 #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
<> 161:2cc1468da177 895 #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 161:2cc1468da177 896 #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 161:2cc1468da177 897 #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 898 #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 899 #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
<> 161:2cc1468da177 900 #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
<> 161:2cc1468da177 901 #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
<> 161:2cc1468da177 902 #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 903 #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 904 #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
<> 161:2cc1468da177 905 #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 161:2cc1468da177 906 #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 161:2cc1468da177 907 #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 908 #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 909 #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
<> 161:2cc1468da177 910 #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 161:2cc1468da177 911 #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 161:2cc1468da177 912 #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 913 #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 914 #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
<> 161:2cc1468da177 915 #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 161:2cc1468da177 916 #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 161:2cc1468da177 917 #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 918 #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 919 #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
<> 161:2cc1468da177 920 #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
<> 161:2cc1468da177 921 #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
<> 161:2cc1468da177 922 #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 923 #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */
<> 161:2cc1468da177 924
<> 161:2cc1468da177 925 /* Bit fields for WTIMER IEN */
<> 161:2cc1468da177 926 #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */
<> 161:2cc1468da177 927 #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */
<> 161:2cc1468da177 928 #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
<> 161:2cc1468da177 929 #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 161:2cc1468da177 930 #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 161:2cc1468da177 931 #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 932 #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 933 #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
<> 161:2cc1468da177 934 #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 161:2cc1468da177 935 #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 161:2cc1468da177 936 #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 937 #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 938 #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
<> 161:2cc1468da177 939 #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
<> 161:2cc1468da177 940 #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
<> 161:2cc1468da177 941 #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 942 #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 943 #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
<> 161:2cc1468da177 944 #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 161:2cc1468da177 945 #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 161:2cc1468da177 946 #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 947 #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 948 #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
<> 161:2cc1468da177 949 #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 161:2cc1468da177 950 #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 161:2cc1468da177 951 #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 952 #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 953 #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
<> 161:2cc1468da177 954 #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 161:2cc1468da177 955 #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 161:2cc1468da177 956 #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 957 #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 958 #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
<> 161:2cc1468da177 959 #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
<> 161:2cc1468da177 960 #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
<> 161:2cc1468da177 961 #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 962 #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 963 #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
<> 161:2cc1468da177 964 #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 161:2cc1468da177 965 #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 161:2cc1468da177 966 #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 967 #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 968 #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
<> 161:2cc1468da177 969 #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 161:2cc1468da177 970 #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 161:2cc1468da177 971 #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 972 #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 973 #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
<> 161:2cc1468da177 974 #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 161:2cc1468da177 975 #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 161:2cc1468da177 976 #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 977 #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 978 #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
<> 161:2cc1468da177 979 #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
<> 161:2cc1468da177 980 #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
<> 161:2cc1468da177 981 #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 982 #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */
<> 161:2cc1468da177 983
<> 161:2cc1468da177 984 /* Bit fields for WTIMER TOP */
<> 161:2cc1468da177 985 #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */
<> 161:2cc1468da177 986 #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */
<> 161:2cc1468da177 987 #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
<> 161:2cc1468da177 988 #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */
<> 161:2cc1468da177 989 #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */
<> 161:2cc1468da177 990 #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */
<> 161:2cc1468da177 991
<> 161:2cc1468da177 992 /* Bit fields for WTIMER TOPB */
<> 161:2cc1468da177 993 #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */
<> 161:2cc1468da177 994 #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */
<> 161:2cc1468da177 995 #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
<> 161:2cc1468da177 996 #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */
<> 161:2cc1468da177 997 #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */
<> 161:2cc1468da177 998 #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */
<> 161:2cc1468da177 999
<> 161:2cc1468da177 1000 /* Bit fields for WTIMER CNT */
<> 161:2cc1468da177 1001 #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */
<> 161:2cc1468da177 1002 #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */
<> 161:2cc1468da177 1003 #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
<> 161:2cc1468da177 1004 #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */
<> 161:2cc1468da177 1005 #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */
<> 161:2cc1468da177 1006 #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */
<> 161:2cc1468da177 1007
<> 161:2cc1468da177 1008 /* Bit fields for WTIMER LOCK */
<> 161:2cc1468da177 1009 #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */
<> 161:2cc1468da177 1010 #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */
<> 161:2cc1468da177 1011 #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
<> 161:2cc1468da177 1012 #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
<> 161:2cc1468da177 1013 #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
<> 161:2cc1468da177 1014 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
<> 161:2cc1468da177 1015 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
<> 161:2cc1468da177 1016 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
<> 161:2cc1468da177 1017 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
<> 161:2cc1468da177 1018 #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
<> 161:2cc1468da177 1019 #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
<> 161:2cc1468da177 1020 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
<> 161:2cc1468da177 1021 #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
<> 161:2cc1468da177 1022 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
<> 161:2cc1468da177 1023
<> 161:2cc1468da177 1024 /* Bit fields for WTIMER ROUTEPEN */
<> 161:2cc1468da177 1025 #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1026 #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1027 #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
<> 161:2cc1468da177 1028 #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
<> 161:2cc1468da177 1029 #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
<> 161:2cc1468da177 1030 #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1031 #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1032 #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
<> 161:2cc1468da177 1033 #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
<> 161:2cc1468da177 1034 #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
<> 161:2cc1468da177 1035 #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1036 #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1037 #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
<> 161:2cc1468da177 1038 #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
<> 161:2cc1468da177 1039 #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
<> 161:2cc1468da177 1040 #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1041 #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1042 #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
<> 161:2cc1468da177 1043 #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
<> 161:2cc1468da177 1044 #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
<> 161:2cc1468da177 1045 #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1046 #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1047 #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
<> 161:2cc1468da177 1048 #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
<> 161:2cc1468da177 1049 #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
<> 161:2cc1468da177 1050 #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1051 #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1052 #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
<> 161:2cc1468da177 1053 #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
<> 161:2cc1468da177 1054 #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
<> 161:2cc1468da177 1055 #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1056 #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1057 #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
<> 161:2cc1468da177 1058 #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
<> 161:2cc1468da177 1059 #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
<> 161:2cc1468da177 1060 #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1061 #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
<> 161:2cc1468da177 1062
<> 161:2cc1468da177 1063 /* Bit fields for WTIMER ROUTELOC0 */
<> 161:2cc1468da177 1064 #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1065 #define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1066 #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
<> 161:2cc1468da177 1067 #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */
<> 161:2cc1468da177 1068 #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1069 #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1070 #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1071 #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1072 #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1073 #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1074 #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1075 #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1076 #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1077 #define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1078 #define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1079 #define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1080 #define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1081 #define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1082 #define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1083 #define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1084 #define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1085 #define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1086 #define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1087 #define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1088 #define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1089 #define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1090 #define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1091 #define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1092 #define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1093 #define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1094 #define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1095 #define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1096 #define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1097 #define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1098 #define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1099 #define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1100 #define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1101 #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1102 #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1103 #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1104 #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1105 #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1106 #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1107 #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1108 #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1109 #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1110 #define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1111 #define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1112 #define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1113 #define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1114 #define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1115 #define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1116 #define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1117 #define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1118 #define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1119 #define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1120 #define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1121 #define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1122 #define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1123 #define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1124 #define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1125 #define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1126 #define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1127 #define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1128 #define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1129 #define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1130 #define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1131 #define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1132 #define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1133 #define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1134 #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
<> 161:2cc1468da177 1135 #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */
<> 161:2cc1468da177 1136 #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1137 #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1138 #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1139 #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1140 #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1141 #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1142 #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1143 #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1144 #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1145 #define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1146 #define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1147 #define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1148 #define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1149 #define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1150 #define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1151 #define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1152 #define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1153 #define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1154 #define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1155 #define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1156 #define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1157 #define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1158 #define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1159 #define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1160 #define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1161 #define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1162 #define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1163 #define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1164 #define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1165 #define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1166 #define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1167 #define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1168 #define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1169 #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1170 #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1171 #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1172 #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1173 #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1174 #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1175 #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1176 #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1177 #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1178 #define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1179 #define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1180 #define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1181 #define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1182 #define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1183 #define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1184 #define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1185 #define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1186 #define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1187 #define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1188 #define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1189 #define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1190 #define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1191 #define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1192 #define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1193 #define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1194 #define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1195 #define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1196 #define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1197 #define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1198 #define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1199 #define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1200 #define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1201 #define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1202 #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
<> 161:2cc1468da177 1203 #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */
<> 161:2cc1468da177 1204 #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1205 #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1206 #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1207 #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1208 #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1209 #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1210 #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1211 #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1212 #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1213 #define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1214 #define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1215 #define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1216 #define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1217 #define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1218 #define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1219 #define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1220 #define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1221 #define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1222 #define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1223 #define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1224 #define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1225 #define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1226 #define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1227 #define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1228 #define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1229 #define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1230 #define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1231 #define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1232 #define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1233 #define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1234 #define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1235 #define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1236 #define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1237 #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1238 #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1239 #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1240 #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1241 #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1242 #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1243 #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1244 #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1245 #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1246 #define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1247 #define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1248 #define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1249 #define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1250 #define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1251 #define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1252 #define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1253 #define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1254 #define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1255 #define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1256 #define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1257 #define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1258 #define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1259 #define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1260 #define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1261 #define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1262 #define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1263 #define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1264 #define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1265 #define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1266 #define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1267 #define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1268 #define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1269 #define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1270 #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
<> 161:2cc1468da177 1271 #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */
<> 161:2cc1468da177 1272 #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1273 #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1274 #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1275 #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1276 #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1277 #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1278 #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1279 #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1280 #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1281 #define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1282 #define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1283 #define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1284 #define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1285 #define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1286 #define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1287 #define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1288 #define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1289 #define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1290 #define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1291 #define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1292 #define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1293 #define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1294 #define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1295 #define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1296 #define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1297 #define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1298 #define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1299 #define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1300 #define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1301 #define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1302 #define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1303 #define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1304 #define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1305 #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1306 #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1307 #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1308 #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1309 #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1310 #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1311 #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1312 #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1313 #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1314 #define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1315 #define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1316 #define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1317 #define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1318 #define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1319 #define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1320 #define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1321 #define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1322 #define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1323 #define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1324 #define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1325 #define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1326 #define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1327 #define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1328 #define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1329 #define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1330 #define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1331 #define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1332 #define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1333 #define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1334 #define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1335 #define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1336 #define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1337 #define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
<> 161:2cc1468da177 1338
<> 161:2cc1468da177 1339 /* Bit fields for WTIMER ROUTELOC2 */
<> 161:2cc1468da177 1340 #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1341 #define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1342 #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
<> 161:2cc1468da177 1343 #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */
<> 161:2cc1468da177 1344 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1345 #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1346 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1347 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1348 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1349 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1350 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1351 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1352 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1353 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1354 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1355 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1356 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1357 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1358 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1359 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1360 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1361 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1362 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1363 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1364 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1365 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1366 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1367 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1368 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1369 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1370 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1371 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1372 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1373 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1374 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1375 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1376 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1377 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1378 #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1379 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1380 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1381 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1382 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1383 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1384 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1385 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1386 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1387 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1388 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1389 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1390 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1391 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1392 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1393 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1394 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1395 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1396 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1397 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1398 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1399 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1400 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1401 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1402 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1403 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1404 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1405 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1406 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1407 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1408 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1409 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1410 #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
<> 161:2cc1468da177 1411 #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */
<> 161:2cc1468da177 1412 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1413 #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1414 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1415 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1416 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1417 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1418 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1419 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1420 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1421 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1422 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1423 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1424 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1425 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1426 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1427 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1428 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1429 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1430 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1431 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1432 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1433 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1434 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1435 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1436 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1437 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1438 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1439 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1440 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1441 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1442 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1443 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1444 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1445 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1446 #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1447 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1448 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1449 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1450 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1451 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1452 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1453 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1454 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1455 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1456 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1457 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1458 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1459 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1460 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1461 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1462 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1463 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1464 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1465 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1466 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1467 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1468 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1469 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1470 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1471 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1472 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1473 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1474 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1475 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1476 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1477 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1478 #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
<> 161:2cc1468da177 1479 #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */
<> 161:2cc1468da177 1480 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1481 #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1482 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1483 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1484 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1485 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1486 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1487 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1488 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1489 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1490 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1491 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1492 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1493 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1494 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1495 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1496 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1497 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1498 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1499 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1500 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1501 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1502 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1503 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1504 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1505 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1506 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1507 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1508 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1509 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1510 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1511 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1512 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1513 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1514 #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1515 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1516 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1517 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1518 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1519 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1520 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1521 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1522 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1523 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1524 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1525 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1526 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1527 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1528 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1529 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1530 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1531 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1532 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1533 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1534 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1535 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1536 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1537 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1538 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1539 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1540 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1541 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1542 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1543 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1544 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1545 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
<> 161:2cc1468da177 1546
<> 161:2cc1468da177 1547 /* Bit fields for WTIMER CC_CTRL */
<> 161:2cc1468da177 1548 #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1549 #define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1550 #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
<> 161:2cc1468da177 1551 #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
<> 161:2cc1468da177 1552 #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1553 #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1554 #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1555 #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1556 #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1557 #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1558 #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1559 #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1560 #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1561 #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1562 #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
<> 161:2cc1468da177 1563 #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
<> 161:2cc1468da177 1564 #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
<> 161:2cc1468da177 1565 #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1566 #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1567 #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
<> 161:2cc1468da177 1568 #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
<> 161:2cc1468da177 1569 #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
<> 161:2cc1468da177 1570 #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1571 #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1572 #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
<> 161:2cc1468da177 1573 #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
<> 161:2cc1468da177 1574 #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1575 #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1576 #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1577 #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1578 #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1579 #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1580 #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1581 #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1582 #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1583 #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1584 #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
<> 161:2cc1468da177 1585 #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
<> 161:2cc1468da177 1586 #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1587 #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1588 #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1589 #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1590 #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1591 #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1592 #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1593 #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1594 #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1595 #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1596 #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
<> 161:2cc1468da177 1597 #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
<> 161:2cc1468da177 1598 #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1599 #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1600 #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1601 #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1602 #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1603 #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1604 #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1605 #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1606 #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1607 #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1608 #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
<> 161:2cc1468da177 1609 #define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
<> 161:2cc1468da177 1610 #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1611 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1612 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1613 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1614 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1615 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1616 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1617 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1618 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1619 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1620 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1621 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1622 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1623 #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1624 #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1625 #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1626 #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1627 #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1628 #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1629 #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1630 #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1631 #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1632 #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1633 #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1634 #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1635 #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1636 #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
<> 161:2cc1468da177 1637 #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
<> 161:2cc1468da177 1638 #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1639 #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1640 #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1641 #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1642 #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1643 #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1644 #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1645 #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1646 #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1647 #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1648 #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
<> 161:2cc1468da177 1649 #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
<> 161:2cc1468da177 1650 #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1651 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1652 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1653 #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1654 #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1655 #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1656 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1657 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1658 #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1659 #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1660 #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
<> 161:2cc1468da177 1661 #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
<> 161:2cc1468da177 1662 #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
<> 161:2cc1468da177 1663 #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1664 #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1665 #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1666 #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1667 #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1668 #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1669 #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
<> 161:2cc1468da177 1670 #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
<> 161:2cc1468da177 1671 #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
<> 161:2cc1468da177 1672 #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1673 #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1674 #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1675 #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1676 #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1677 #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1678 #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
<> 161:2cc1468da177 1679 #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
<> 161:2cc1468da177 1680 #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
<> 161:2cc1468da177 1681 #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1682 #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1683 #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1684 #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1685 #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1686 #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */
<> 161:2cc1468da177 1687
<> 161:2cc1468da177 1688 /* Bit fields for WTIMER CC_CCV */
<> 161:2cc1468da177 1689 #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */
<> 161:2cc1468da177 1690 #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */
<> 161:2cc1468da177 1691 #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
<> 161:2cc1468da177 1692 #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */
<> 161:2cc1468da177 1693 #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */
<> 161:2cc1468da177 1694 #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */
<> 161:2cc1468da177 1695
<> 161:2cc1468da177 1696 /* Bit fields for WTIMER CC_CCVP */
<> 161:2cc1468da177 1697 #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */
<> 161:2cc1468da177 1698 #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */
<> 161:2cc1468da177 1699 #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
<> 161:2cc1468da177 1700 #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */
<> 161:2cc1468da177 1701 #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */
<> 161:2cc1468da177 1702 #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */
<> 161:2cc1468da177 1703
<> 161:2cc1468da177 1704 /* Bit fields for WTIMER CC_CCVB */
<> 161:2cc1468da177 1705 #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */
<> 161:2cc1468da177 1706 #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */
<> 161:2cc1468da177 1707 #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
<> 161:2cc1468da177 1708 #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */
<> 161:2cc1468da177 1709 #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */
<> 161:2cc1468da177 1710 #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */
<> 161:2cc1468da177 1711
<> 161:2cc1468da177 1712 /* Bit fields for WTIMER DTCTRL */
<> 161:2cc1468da177 1713 #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */
<> 161:2cc1468da177 1714 #define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */
<> 161:2cc1468da177 1715 #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
<> 161:2cc1468da177 1716 #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
<> 161:2cc1468da177 1717 #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
<> 161:2cc1468da177 1718 #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1719 #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1720 #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
<> 161:2cc1468da177 1721 #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
<> 161:2cc1468da177 1722 #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
<> 161:2cc1468da177 1723 #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1724 #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */
<> 161:2cc1468da177 1725 #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */
<> 161:2cc1468da177 1726 #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1727 #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */
<> 161:2cc1468da177 1728 #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */
<> 161:2cc1468da177 1729 #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
<> 161:2cc1468da177 1730 #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
<> 161:2cc1468da177 1731 #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
<> 161:2cc1468da177 1732 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1733 #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1734 #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
<> 161:2cc1468da177 1735 #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
<> 161:2cc1468da177 1736 #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
<> 161:2cc1468da177 1737 #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1738 #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1739 #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
<> 161:2cc1468da177 1740 #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
<> 161:2cc1468da177 1741 #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1742 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1743 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1744 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1745 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1746 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1747 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1748 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1749 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1750 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1751 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1752 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1753 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1754 #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1755 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1756 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1757 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1758 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1759 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1760 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1761 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1762 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1763 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1764 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1765 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1766 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */
<> 161:2cc1468da177 1767 #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
<> 161:2cc1468da177 1768 #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
<> 161:2cc1468da177 1769 #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
<> 161:2cc1468da177 1770 #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1771 #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1772 #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
<> 161:2cc1468da177 1773 #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
<> 161:2cc1468da177 1774 #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
<> 161:2cc1468da177 1775 #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1776 #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1777 #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
<> 161:2cc1468da177 1778 #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
<> 161:2cc1468da177 1779 #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
<> 161:2cc1468da177 1780 #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1781 #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
<> 161:2cc1468da177 1782
<> 161:2cc1468da177 1783 /* Bit fields for WTIMER DTTIME */
<> 161:2cc1468da177 1784 #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */
<> 161:2cc1468da177 1785 #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */
<> 161:2cc1468da177 1786 #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
<> 161:2cc1468da177 1787 #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
<> 161:2cc1468da177 1788 #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
<> 161:2cc1468da177 1789 #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */
<> 161:2cc1468da177 1790 #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */
<> 161:2cc1468da177 1791 #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */
<> 161:2cc1468da177 1792 #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */
<> 161:2cc1468da177 1793 #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */
<> 161:2cc1468da177 1794 #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */
<> 161:2cc1468da177 1795 #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */
<> 161:2cc1468da177 1796 #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */
<> 161:2cc1468da177 1797 #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */
<> 161:2cc1468da177 1798 #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */
<> 161:2cc1468da177 1799 #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */
<> 161:2cc1468da177 1800 #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
<> 161:2cc1468da177 1801 #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */
<> 161:2cc1468da177 1802 #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */
<> 161:2cc1468da177 1803 #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */
<> 161:2cc1468da177 1804 #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */
<> 161:2cc1468da177 1805 #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */
<> 161:2cc1468da177 1806 #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */
<> 161:2cc1468da177 1807 #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */
<> 161:2cc1468da177 1808 #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */
<> 161:2cc1468da177 1809 #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */
<> 161:2cc1468da177 1810 #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */
<> 161:2cc1468da177 1811 #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */
<> 161:2cc1468da177 1812 #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
<> 161:2cc1468da177 1813 #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
<> 161:2cc1468da177 1814 #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
<> 161:2cc1468da177 1815 #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
<> 161:2cc1468da177 1816 #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
<> 161:2cc1468da177 1817 #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
<> 161:2cc1468da177 1818 #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
<> 161:2cc1468da177 1819 #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
<> 161:2cc1468da177 1820
<> 161:2cc1468da177 1821 /* Bit fields for WTIMER DTFC */
<> 161:2cc1468da177 1822 #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */
<> 161:2cc1468da177 1823 #define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */
<> 161:2cc1468da177 1824 #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
<> 161:2cc1468da177 1825 #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */
<> 161:2cc1468da177 1826 #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1827 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
<> 161:2cc1468da177 1828 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
<> 161:2cc1468da177 1829 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
<> 161:2cc1468da177 1830 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
<> 161:2cc1468da177 1831 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
<> 161:2cc1468da177 1832 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
<> 161:2cc1468da177 1833 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
<> 161:2cc1468da177 1834 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
<> 161:2cc1468da177 1835 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
<> 161:2cc1468da177 1836 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
<> 161:2cc1468da177 1837 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
<> 161:2cc1468da177 1838 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
<> 161:2cc1468da177 1839 #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1840 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
<> 161:2cc1468da177 1841 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
<> 161:2cc1468da177 1842 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
<> 161:2cc1468da177 1843 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
<> 161:2cc1468da177 1844 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
<> 161:2cc1468da177 1845 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
<> 161:2cc1468da177 1846 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
<> 161:2cc1468da177 1847 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
<> 161:2cc1468da177 1848 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
<> 161:2cc1468da177 1849 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
<> 161:2cc1468da177 1850 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
<> 161:2cc1468da177 1851 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
<> 161:2cc1468da177 1852 #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
<> 161:2cc1468da177 1853 #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */
<> 161:2cc1468da177 1854 #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1855 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
<> 161:2cc1468da177 1856 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
<> 161:2cc1468da177 1857 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
<> 161:2cc1468da177 1858 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
<> 161:2cc1468da177 1859 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
<> 161:2cc1468da177 1860 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
<> 161:2cc1468da177 1861 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
<> 161:2cc1468da177 1862 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
<> 161:2cc1468da177 1863 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
<> 161:2cc1468da177 1864 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
<> 161:2cc1468da177 1865 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
<> 161:2cc1468da177 1866 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
<> 161:2cc1468da177 1867 #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1868 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
<> 161:2cc1468da177 1869 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
<> 161:2cc1468da177 1870 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
<> 161:2cc1468da177 1871 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
<> 161:2cc1468da177 1872 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
<> 161:2cc1468da177 1873 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
<> 161:2cc1468da177 1874 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
<> 161:2cc1468da177 1875 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
<> 161:2cc1468da177 1876 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
<> 161:2cc1468da177 1877 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
<> 161:2cc1468da177 1878 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
<> 161:2cc1468da177 1879 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
<> 161:2cc1468da177 1880 #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
<> 161:2cc1468da177 1881 #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
<> 161:2cc1468da177 1882 #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1883 #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */
<> 161:2cc1468da177 1884 #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */
<> 161:2cc1468da177 1885 #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */
<> 161:2cc1468da177 1886 #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */
<> 161:2cc1468da177 1887 #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1888 #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */
<> 161:2cc1468da177 1889 #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */
<> 161:2cc1468da177 1890 #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */
<> 161:2cc1468da177 1891 #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */
<> 161:2cc1468da177 1892 #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
<> 161:2cc1468da177 1893 #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
<> 161:2cc1468da177 1894 #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
<> 161:2cc1468da177 1895 #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1896 #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1897 #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
<> 161:2cc1468da177 1898 #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
<> 161:2cc1468da177 1899 #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
<> 161:2cc1468da177 1900 #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1901 #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1902 #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
<> 161:2cc1468da177 1903 #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
<> 161:2cc1468da177 1904 #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
<> 161:2cc1468da177 1905 #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1906 #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1907 #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
<> 161:2cc1468da177 1908 #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
<> 161:2cc1468da177 1909 #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
<> 161:2cc1468da177 1910 #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1911 #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */
<> 161:2cc1468da177 1912
<> 161:2cc1468da177 1913 /* Bit fields for WTIMER DTOGEN */
<> 161:2cc1468da177 1914 #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */
<> 161:2cc1468da177 1915 #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */
<> 161:2cc1468da177 1916 #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
<> 161:2cc1468da177 1917 #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
<> 161:2cc1468da177 1918 #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
<> 161:2cc1468da177 1919 #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1920 #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1921 #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
<> 161:2cc1468da177 1922 #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
<> 161:2cc1468da177 1923 #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
<> 161:2cc1468da177 1924 #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1925 #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1926 #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
<> 161:2cc1468da177 1927 #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
<> 161:2cc1468da177 1928 #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
<> 161:2cc1468da177 1929 #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1930 #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1931 #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
<> 161:2cc1468da177 1932 #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
<> 161:2cc1468da177 1933 #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
<> 161:2cc1468da177 1934 #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1935 #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1936 #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
<> 161:2cc1468da177 1937 #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
<> 161:2cc1468da177 1938 #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
<> 161:2cc1468da177 1939 #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1940 #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1941 #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
<> 161:2cc1468da177 1942 #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
<> 161:2cc1468da177 1943 #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
<> 161:2cc1468da177 1944 #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1945 #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
<> 161:2cc1468da177 1946
<> 161:2cc1468da177 1947 /* Bit fields for WTIMER DTFAULT */
<> 161:2cc1468da177 1948 #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */
<> 161:2cc1468da177 1949 #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */
<> 161:2cc1468da177 1950 #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
<> 161:2cc1468da177 1951 #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
<> 161:2cc1468da177 1952 #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
<> 161:2cc1468da177 1953 #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1954 #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1955 #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
<> 161:2cc1468da177 1956 #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
<> 161:2cc1468da177 1957 #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
<> 161:2cc1468da177 1958 #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1959 #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1960 #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
<> 161:2cc1468da177 1961 #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
<> 161:2cc1468da177 1962 #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
<> 161:2cc1468da177 1963 #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1964 #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1965 #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
<> 161:2cc1468da177 1966 #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
<> 161:2cc1468da177 1967 #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
<> 161:2cc1468da177 1968 #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1969 #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
<> 161:2cc1468da177 1970
<> 161:2cc1468da177 1971 /* Bit fields for WTIMER DTFAULTC */
<> 161:2cc1468da177 1972 #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1973 #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1974 #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
<> 161:2cc1468da177 1975 #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
<> 161:2cc1468da177 1976 #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
<> 161:2cc1468da177 1977 #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1978 #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1979 #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
<> 161:2cc1468da177 1980 #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
<> 161:2cc1468da177 1981 #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
<> 161:2cc1468da177 1982 #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1983 #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1984 #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
<> 161:2cc1468da177 1985 #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
<> 161:2cc1468da177 1986 #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
<> 161:2cc1468da177 1987 #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1988 #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1989 #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
<> 161:2cc1468da177 1990 #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
<> 161:2cc1468da177 1991 #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
<> 161:2cc1468da177 1992 #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1993 #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
<> 161:2cc1468da177 1994
<> 161:2cc1468da177 1995 /* Bit fields for WTIMER DTLOCK */
<> 161:2cc1468da177 1996 #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */
<> 161:2cc1468da177 1997 #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */
<> 161:2cc1468da177 1998 #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
<> 161:2cc1468da177 1999 #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
<> 161:2cc1468da177 2000 #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
<> 161:2cc1468da177 2001 #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
<> 161:2cc1468da177 2002 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
<> 161:2cc1468da177 2003 #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
<> 161:2cc1468da177 2004 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
<> 161:2cc1468da177 2005 #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
<> 161:2cc1468da177 2006 #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
<> 161:2cc1468da177 2007 #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
<> 161:2cc1468da177 2008 #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
<> 161:2cc1468da177 2009 #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
<> 161:2cc1468da177 2010
<> 161:2cc1468da177 2011 /** @} End of group EFR32MG12P432F1024GM48_WTIMER */
<> 161:2cc1468da177 2012
<> 161:2cc1468da177 2013
<> 161:2cc1468da177 2014
<> 161:2cc1468da177 2015 /**************************************************************************//**
<> 161:2cc1468da177 2016 * @defgroup EFR32MG12P432F1024GM48_SYSTICK_BitFields EFR32MG12P432F1024GM48_SYSTICK Bit Fields
<> 161:2cc1468da177 2017 * @{
<> 161:2cc1468da177 2018 *****************************************************************************/
<> 161:2cc1468da177 2019
<> 161:2cc1468da177 2020 /** @} End of group EFR32MG12P432F1024GM48_SYSTICK */
<> 161:2cc1468da177 2021
<> 161:2cc1468da177 2022
<> 161:2cc1468da177 2023
<> 161:2cc1468da177 2024 /**************************************************************************//**
<> 161:2cc1468da177 2025 * @defgroup EFR32MG12P432F1024GM48_UNLOCK EFR32MG12P432F1024GM48 Unlock Codes
<> 161:2cc1468da177 2026 * @{
<> 161:2cc1468da177 2027 *****************************************************************************/
<> 161:2cc1468da177 2028 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 161:2cc1468da177 2029 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 161:2cc1468da177 2030 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
<> 161:2cc1468da177 2031 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 161:2cc1468da177 2032 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 161:2cc1468da177 2033 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 161:2cc1468da177 2034 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
<> 161:2cc1468da177 2035
<> 161:2cc1468da177 2036 /** @} End of group EFR32MG12P432F1024GM48_UNLOCK */
<> 161:2cc1468da177 2037
<> 161:2cc1468da177 2038 /** @} End of group EFR32MG12P432F1024GM48_BitFields */
<> 161:2cc1468da177 2039
<> 161:2cc1468da177 2040 /**************************************************************************//**
<> 161:2cc1468da177 2041 * @defgroup EFR32MG12P432F1024GM48_Alternate_Function EFR32MG12P432F1024GM48 Alternate Function
<> 161:2cc1468da177 2042 * @{
<> 161:2cc1468da177 2043 *****************************************************************************/
<> 161:2cc1468da177 2044
<> 161:2cc1468da177 2045 #include "efr32mg12p_af_ports.h"
<> 161:2cc1468da177 2046 #include "efr32mg12p_af_pins.h"
<> 161:2cc1468da177 2047
<> 161:2cc1468da177 2048 /** @} End of group EFR32MG12P432F1024GM48_Alternate_Function */
<> 161:2cc1468da177 2049
<> 161:2cc1468da177 2050 /** @} End of group EFR32MG12P432F1024GM48 */
<> 161:2cc1468da177 2051
<> 161:2cc1468da177 2052 /** @} End of group Parts */
<> 161:2cc1468da177 2053
<> 161:2cc1468da177 2054 #ifdef __cplusplus
<> 161:2cc1468da177 2055 }
<> 161:2cc1468da177 2056 #endif
<> 161:2cc1468da177 2057 #endif /* EFR32MG12P432F1024GM48_H */