mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
161:2cc1468da177 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /* @file startup_efr32mg1p.S
<> 161:2cc1468da177 2 * @brief startup file for Silicon Labs EFR32MG1P devices.
<> 161:2cc1468da177 3 * For use with GCC for ARM Embedded Processors
<> 161:2cc1468da177 4 * @version 4.3.0
<> 161:2cc1468da177 5 * Date: 12 June 2014
<> 161:2cc1468da177 6 *
<> 161:2cc1468da177 7 */
<> 161:2cc1468da177 8 /* Copyright (c) 2011 - 2014 ARM LIMITED
<> 161:2cc1468da177 9
<> 161:2cc1468da177 10 All rights reserved.
<> 161:2cc1468da177 11 Redistribution and use in source and binary forms, with or without
<> 161:2cc1468da177 12 modification, are permitted provided that the following conditions are met:
<> 161:2cc1468da177 13 - Redistributions of source code must retain the above copyright
<> 161:2cc1468da177 14 notice, this list of conditions and the following disclaimer.
<> 161:2cc1468da177 15 - Redistributions in binary form must reproduce the above copyright
<> 161:2cc1468da177 16 notice, this list of conditions and the following disclaimer in the
<> 161:2cc1468da177 17 documentation and/or other materials provided with the distribution.
<> 161:2cc1468da177 18 - Neither the name of ARM nor the names of its contributors may be used
<> 161:2cc1468da177 19 to endorse or promote products derived from this software without
<> 161:2cc1468da177 20 specific prior written permission.
<> 161:2cc1468da177 21 *
<> 161:2cc1468da177 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 161:2cc1468da177 25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 161:2cc1468da177 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 161:2cc1468da177 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 161:2cc1468da177 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 161:2cc1468da177 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 161:2cc1468da177 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 161:2cc1468da177 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 161:2cc1468da177 32 POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 33 ---------------------------------------------------------------------------*/
<> 161:2cc1468da177 34
<> 161:2cc1468da177 35 .syntax unified
<> 161:2cc1468da177 36 .arch armv7-m
<> 161:2cc1468da177 37 .section .stack
<> 161:2cc1468da177 38 .align 3
<> 161:2cc1468da177 39 #ifdef __STACK_SIZE
<> 161:2cc1468da177 40 .equ Stack_Size, __STACK_SIZE
<> 161:2cc1468da177 41 #else
<> 161:2cc1468da177 42 .equ Stack_Size, 0x00004000
<> 161:2cc1468da177 43 #endif
<> 161:2cc1468da177 44 .globl __StackTop
<> 161:2cc1468da177 45 .globl __StackLimit
<> 161:2cc1468da177 46 __StackLimit:
<> 161:2cc1468da177 47 .space Stack_Size
<> 161:2cc1468da177 48 .size __StackLimit, . - __StackLimit
<> 161:2cc1468da177 49 __StackTop:
<> 161:2cc1468da177 50 .size __StackTop, . - __StackTop
<> 161:2cc1468da177 51
<> 161:2cc1468da177 52 .section .heap
<> 161:2cc1468da177 53 .align 3
<> 161:2cc1468da177 54 #ifdef __HEAP_SIZE
<> 161:2cc1468da177 55 .equ Heap_Size, __HEAP_SIZE
<> 161:2cc1468da177 56 #else
<> 161:2cc1468da177 57 .equ Heap_Size, 0x00010000
<> 161:2cc1468da177 58 #endif
<> 161:2cc1468da177 59 .globl __HeapBase
<> 161:2cc1468da177 60 .globl __HeapLimit
<> 161:2cc1468da177 61 __HeapBase:
<> 161:2cc1468da177 62 .if Heap_Size
<> 161:2cc1468da177 63 .space Heap_Size
<> 161:2cc1468da177 64 .endif
<> 161:2cc1468da177 65 .size __HeapBase, . - __HeapBase
<> 161:2cc1468da177 66 __HeapLimit:
<> 161:2cc1468da177 67 .size __HeapLimit, . - __HeapLimit
<> 161:2cc1468da177 68
<> 161:2cc1468da177 69 .section .vectors
<> 161:2cc1468da177 70 .align 2
<> 161:2cc1468da177 71 .globl __Vectors
<> 161:2cc1468da177 72 __Vectors:
<> 161:2cc1468da177 73 .long __StackTop /* Top of Stack */
<> 161:2cc1468da177 74 .long Reset_Handler /* Reset Handler */
<> 161:2cc1468da177 75 .long NMI_Handler /* NMI Handler */
<> 161:2cc1468da177 76 .long HardFault_Handler /* Hard Fault Handler */
<> 161:2cc1468da177 77 .long MemManage_Handler /* MPU Fault Handler */
<> 161:2cc1468da177 78 .long BusFault_Handler /* Bus Fault Handler */
<> 161:2cc1468da177 79 .long UsageFault_Handler /* Usage Fault Handler */
<> 161:2cc1468da177 80 .long Default_Handler /* Reserved */
<> 161:2cc1468da177 81 .long Default_Handler /* Reserved */
<> 161:2cc1468da177 82 .long Default_Handler /* Reserved */
<> 161:2cc1468da177 83 .long Default_Handler /* Reserved */
<> 161:2cc1468da177 84 .long SVC_Handler /* SVCall Handler */
<> 161:2cc1468da177 85 .long DebugMon_Handler /* Debug Monitor Handler */
<> 161:2cc1468da177 86 .long Default_Handler /* Reserved */
<> 161:2cc1468da177 87 .long PendSV_Handler /* PendSV Handler */
<> 161:2cc1468da177 88 .long SysTick_Handler /* SysTick Handler */
<> 161:2cc1468da177 89
<> 161:2cc1468da177 90 /* External interrupts */
<> 161:2cc1468da177 91 .long EMU_IRQHandler /* 0 - EMU */
<> 161:2cc1468da177 92 .long FRC_PRI_IRQHandler /* 1 - FRC_PRI */
<> 161:2cc1468da177 93 .long WDOG0_IRQHandler /* 2 - WDOG0 */
<> 161:2cc1468da177 94 .long WDOG1_IRQHandler /* 3 - WDOG1 */
<> 161:2cc1468da177 95 .long FRC_IRQHandler /* 4 - FRC */
<> 161:2cc1468da177 96 .long MODEM_IRQHandler /* 5 - MODEM */
<> 161:2cc1468da177 97 .long RAC_SEQ_IRQHandler /* 6 - RAC_SEQ */
<> 161:2cc1468da177 98 .long RAC_RSM_IRQHandler /* 7 - RAC_RSM */
<> 161:2cc1468da177 99 .long BUFC_IRQHandler /* 8 - BUFC */
<> 161:2cc1468da177 100 .long LDMA_IRQHandler /* 9 - LDMA */
<> 161:2cc1468da177 101 .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */
<> 161:2cc1468da177 102 .long TIMER0_IRQHandler /* 11 - TIMER0 */
<> 161:2cc1468da177 103 .long USART0_RX_IRQHandler /* 12 - USART0_RX */
<> 161:2cc1468da177 104 .long USART0_TX_IRQHandler /* 13 - USART0_TX */
<> 161:2cc1468da177 105 .long ACMP0_IRQHandler /* 14 - ACMP0 */
<> 161:2cc1468da177 106 .long ADC0_IRQHandler /* 15 - ADC0 */
<> 161:2cc1468da177 107 .long IDAC0_IRQHandler /* 16 - IDAC0 */
<> 161:2cc1468da177 108 .long I2C0_IRQHandler /* 17 - I2C0 */
<> 161:2cc1468da177 109 .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */
<> 161:2cc1468da177 110 .long TIMER1_IRQHandler /* 19 - TIMER1 */
<> 161:2cc1468da177 111 .long USART1_RX_IRQHandler /* 20 - USART1_RX */
<> 161:2cc1468da177 112 .long USART1_TX_IRQHandler /* 21 - USART1_TX */
<> 161:2cc1468da177 113 .long LEUART0_IRQHandler /* 22 - LEUART0 */
<> 161:2cc1468da177 114 .long PCNT0_IRQHandler /* 23 - PCNT0 */
<> 161:2cc1468da177 115 .long CMU_IRQHandler /* 24 - CMU */
<> 161:2cc1468da177 116 .long MSC_IRQHandler /* 25 - MSC */
<> 161:2cc1468da177 117 .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */
<> 161:2cc1468da177 118 .long LETIMER0_IRQHandler /* 27 - LETIMER0 */
<> 161:2cc1468da177 119 .long AGC_IRQHandler /* 28 - AGC */
<> 161:2cc1468da177 120 .long PROTIMER_IRQHandler /* 29 - PROTIMER */
<> 161:2cc1468da177 121 .long RTCC_IRQHandler /* 30 - RTCC */
<> 161:2cc1468da177 122 .long SYNTH_IRQHandler /* 31 - SYNTH */
<> 161:2cc1468da177 123 .long CRYOTIMER_IRQHandler /* 32 - CRYOTIMER */
<> 161:2cc1468da177 124 .long RFSENSE_IRQHandler /* 33 - RFSENSE */
<> 161:2cc1468da177 125 .long FPUEH_IRQHandler /* 34 - FPUEH */
<> 161:2cc1468da177 126 .long SMU_IRQHandler /* 35 - SMU */
<> 161:2cc1468da177 127 .long WTIMER0_IRQHandler /* 36 - WTIMER0 */
<> 161:2cc1468da177 128 .long WTIMER1_IRQHandler /* 37 - WTIMER1 */
<> 161:2cc1468da177 129 .long PCNT1_IRQHandler /* 38 - PCNT1 */
<> 161:2cc1468da177 130 .long PCNT2_IRQHandler /* 39 - PCNT2 */
<> 161:2cc1468da177 131 .long USART2_RX_IRQHandler /* 40 - USART2_RX */
<> 161:2cc1468da177 132 .long USART2_TX_IRQHandler /* 41 - USART2_TX */
<> 161:2cc1468da177 133 .long I2C1_IRQHandler /* 42 - I2C1 */
<> 161:2cc1468da177 134 .long USART3_RX_IRQHandler /* 43 - USART3_RX */
<> 161:2cc1468da177 135 .long USART3_TX_IRQHandler /* 44 - USART3_TX */
<> 161:2cc1468da177 136 .long VDAC0_IRQHandler /* 45 - VDAC0 */
<> 161:2cc1468da177 137 .long CSEN_IRQHandler /* 46 - CSEN */
<> 161:2cc1468da177 138 .long LESENSE_IRQHandler /* 47 - LESENSE */
<> 161:2cc1468da177 139 .long CRYPTO1_IRQHandler /* 48 - CRYPTO1 */
<> 161:2cc1468da177 140 .long TRNG0_IRQHandler /* 49 - TRNG0 */
<> 161:2cc1468da177 141 .long Default_Handler /* 50 - Reserved */
<> 161:2cc1468da177 142
<> 161:2cc1468da177 143
<> 161:2cc1468da177 144 .size __Vectors, . - __Vectors
<> 161:2cc1468da177 145
<> 161:2cc1468da177 146 .text
<> 161:2cc1468da177 147 .thumb
<> 161:2cc1468da177 148 .thumb_func
<> 161:2cc1468da177 149 .align 2
<> 161:2cc1468da177 150 .globl Reset_Handler
<> 161:2cc1468da177 151 .type Reset_Handler, %function
<> 161:2cc1468da177 152 Reset_Handler:
<> 161:2cc1468da177 153 #ifndef __NO_SYSTEM_INIT
<> 161:2cc1468da177 154 ldr r0, =SystemInit
<> 161:2cc1468da177 155 blx r0
<> 161:2cc1468da177 156 #endif
<> 161:2cc1468da177 157
<> 161:2cc1468da177 158 /* Firstly it copies data from read only memory to RAM. There are two schemes
<> 161:2cc1468da177 159 * to copy. One can copy more than one sections. Another can only copy
<> 161:2cc1468da177 160 * one section. The former scheme needs more instructions and read-only
<> 161:2cc1468da177 161 * data to implement than the latter.
<> 161:2cc1468da177 162 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
<> 161:2cc1468da177 163
<> 161:2cc1468da177 164 #ifdef __STARTUP_COPY_MULTIPLE
<> 161:2cc1468da177 165 /* Multiple sections scheme.
<> 161:2cc1468da177 166 *
<> 161:2cc1468da177 167 * Between symbol address __copy_table_start__ and __copy_table_end__,
<> 161:2cc1468da177 168 * there are array of triplets, each of which specify:
<> 161:2cc1468da177 169 * offset 0: LMA of start of a section to copy from
<> 161:2cc1468da177 170 * offset 4: VMA of start of a section to copy to
<> 161:2cc1468da177 171 * offset 8: size of the section to copy. Must be multiply of 4
<> 161:2cc1468da177 172 *
<> 161:2cc1468da177 173 * All addresses must be aligned to 4 bytes boundary.
<> 161:2cc1468da177 174 */
<> 161:2cc1468da177 175 ldr r4, =__copy_table_start__
<> 161:2cc1468da177 176 ldr r5, =__copy_table_end__
<> 161:2cc1468da177 177
<> 161:2cc1468da177 178 .L_loop0:
<> 161:2cc1468da177 179 cmp r4, r5
<> 161:2cc1468da177 180 bge .L_loop0_done
<> 161:2cc1468da177 181 ldr r1, [r4]
<> 161:2cc1468da177 182 ldr r2, [r4, #4]
<> 161:2cc1468da177 183 ldr r3, [r4, #8]
<> 161:2cc1468da177 184
<> 161:2cc1468da177 185 .L_loop0_0:
<> 161:2cc1468da177 186 subs r3, #4
<> 161:2cc1468da177 187 ittt ge
<> 161:2cc1468da177 188 ldrge r0, [r1, r3]
<> 161:2cc1468da177 189 strge r0, [r2, r3]
<> 161:2cc1468da177 190 bge .L_loop0_0
<> 161:2cc1468da177 191
<> 161:2cc1468da177 192 adds r4, #12
<> 161:2cc1468da177 193 b .L_loop0
<> 161:2cc1468da177 194
<> 161:2cc1468da177 195 .L_loop0_done:
<> 161:2cc1468da177 196 #else
<> 161:2cc1468da177 197 /* Single section scheme.
<> 161:2cc1468da177 198 *
<> 161:2cc1468da177 199 * The ranges of copy from/to are specified by following symbols
<> 161:2cc1468da177 200 * __etext: LMA of start of the section to copy from. Usually end of text
<> 161:2cc1468da177 201 * __data_start__: VMA of start of the section to copy to
<> 161:2cc1468da177 202 * __data_end__: VMA of end of the section to copy to
<> 161:2cc1468da177 203 *
<> 161:2cc1468da177 204 * All addresses must be aligned to 4 bytes boundary.
<> 161:2cc1468da177 205 */
<> 161:2cc1468da177 206 ldr r1, =__etext
<> 161:2cc1468da177 207 ldr r2, =__data_start__
<> 161:2cc1468da177 208 ldr r3, =__data_end__
<> 161:2cc1468da177 209
<> 161:2cc1468da177 210 .L_loop1:
<> 161:2cc1468da177 211 cmp r2, r3
<> 161:2cc1468da177 212 ittt lt
<> 161:2cc1468da177 213 ldrlt r0, [r1], #4
<> 161:2cc1468da177 214 strlt r0, [r2], #4
<> 161:2cc1468da177 215 blt .L_loop1
<> 161:2cc1468da177 216 #endif /*__STARTUP_COPY_MULTIPLE */
<> 161:2cc1468da177 217
<> 161:2cc1468da177 218 /* This part of work usually is done in C library startup code. Otherwise,
<> 161:2cc1468da177 219 * define this macro to enable it in this startup.
<> 161:2cc1468da177 220 *
<> 161:2cc1468da177 221 * There are two schemes too. One can clear multiple BSS sections. Another
<> 161:2cc1468da177 222 * can only clear one section. The former is more size expensive than the
<> 161:2cc1468da177 223 * latter.
<> 161:2cc1468da177 224 *
<> 161:2cc1468da177 225 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
<> 161:2cc1468da177 226 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
<> 161:2cc1468da177 227 */
<> 161:2cc1468da177 228 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
<> 161:2cc1468da177 229 /* Multiple sections scheme.
<> 161:2cc1468da177 230 *
<> 161:2cc1468da177 231 * Between symbol address __copy_table_start__ and __copy_table_end__,
<> 161:2cc1468da177 232 * there are array of tuples specifying:
<> 161:2cc1468da177 233 * offset 0: Start of a BSS section
<> 161:2cc1468da177 234 * offset 4: Size of this BSS section. Must be multiply of 4
<> 161:2cc1468da177 235 */
<> 161:2cc1468da177 236 ldr r3, =__zero_table_start__
<> 161:2cc1468da177 237 ldr r4, =__zero_table_end__
<> 161:2cc1468da177 238
<> 161:2cc1468da177 239 .L_loop2:
<> 161:2cc1468da177 240 cmp r3, r4
<> 161:2cc1468da177 241 bge .L_loop2_done
<> 161:2cc1468da177 242 ldr r1, [r3]
<> 161:2cc1468da177 243 ldr r2, [r3, #4]
<> 161:2cc1468da177 244 movs r0, 0
<> 161:2cc1468da177 245
<> 161:2cc1468da177 246 .L_loop2_0:
<> 161:2cc1468da177 247 subs r2, #4
<> 161:2cc1468da177 248 itt ge
<> 161:2cc1468da177 249 strge r0, [r1, r2]
<> 161:2cc1468da177 250 bge .L_loop2_0
<> 161:2cc1468da177 251 adds r3, #8
<> 161:2cc1468da177 252 b .L_loop2
<> 161:2cc1468da177 253 .L_loop2_done:
<> 161:2cc1468da177 254 #elif defined (__STARTUP_CLEAR_BSS)
<> 161:2cc1468da177 255 /* Single BSS section scheme.
<> 161:2cc1468da177 256 *
<> 161:2cc1468da177 257 * The BSS section is specified by following symbols
<> 161:2cc1468da177 258 * __bss_start__: start of the BSS section.
<> 161:2cc1468da177 259 * __bss_end__: end of the BSS section.
<> 161:2cc1468da177 260 *
<> 161:2cc1468da177 261 * Both addresses must be aligned to 4 bytes boundary.
<> 161:2cc1468da177 262 */
<> 161:2cc1468da177 263 ldr r1, =__bss_start__
<> 161:2cc1468da177 264 ldr r2, =__bss_end__
<> 161:2cc1468da177 265
<> 161:2cc1468da177 266 movs r0, 0
<> 161:2cc1468da177 267 .L_loop3:
<> 161:2cc1468da177 268 cmp r1, r2
<> 161:2cc1468da177 269 itt lt
<> 161:2cc1468da177 270 strlt r0, [r1], #4
<> 161:2cc1468da177 271 blt .L_loop3
<> 161:2cc1468da177 272 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
<> 161:2cc1468da177 273
<> 161:2cc1468da177 274 #ifndef __START
<> 161:2cc1468da177 275 #define __START _start
<> 161:2cc1468da177 276 #endif
<> 161:2cc1468da177 277 bl __START
<> 161:2cc1468da177 278
<> 161:2cc1468da177 279 .pool
<> 161:2cc1468da177 280 .size Reset_Handler, . - Reset_Handler
<> 161:2cc1468da177 281
<> 161:2cc1468da177 282 .align 1
<> 161:2cc1468da177 283 .thumb_func
<> 161:2cc1468da177 284 .weak Default_Handler
<> 161:2cc1468da177 285 .type Default_Handler, %function
<> 161:2cc1468da177 286 Default_Handler:
<> 161:2cc1468da177 287 b .
<> 161:2cc1468da177 288 .size Default_Handler, . - Default_Handler
<> 161:2cc1468da177 289
<> 161:2cc1468da177 290 /* Macro to define default handlers. Default handler
<> 161:2cc1468da177 291 * will be weak symbol and just dead loops. They can be
<> 161:2cc1468da177 292 * overwritten by other handlers */
<> 161:2cc1468da177 293 .macro def_irq_handler handler_name
<> 161:2cc1468da177 294 .weak \handler_name
<> 161:2cc1468da177 295 .set \handler_name, Default_Handler
<> 161:2cc1468da177 296 .endm
<> 161:2cc1468da177 297
<> 161:2cc1468da177 298 def_irq_handler NMI_Handler
<> 161:2cc1468da177 299 def_irq_handler HardFault_Handler
<> 161:2cc1468da177 300 def_irq_handler MemManage_Handler
<> 161:2cc1468da177 301 def_irq_handler BusFault_Handler
<> 161:2cc1468da177 302 def_irq_handler UsageFault_Handler
<> 161:2cc1468da177 303 def_irq_handler SVC_Handler
<> 161:2cc1468da177 304 def_irq_handler DebugMon_Handler
<> 161:2cc1468da177 305 def_irq_handler PendSV_Handler
<> 161:2cc1468da177 306 def_irq_handler SysTick_Handler
<> 161:2cc1468da177 307
<> 161:2cc1468da177 308
<> 161:2cc1468da177 309 def_irq_handler EMU_IRQHandler
<> 161:2cc1468da177 310 def_irq_handler FRC_PRI_IRQHandler
<> 161:2cc1468da177 311 def_irq_handler WDOG0_IRQHandler
<> 161:2cc1468da177 312 def_irq_handler WDOG1_IRQHandler
<> 161:2cc1468da177 313 def_irq_handler FRC_IRQHandler
<> 161:2cc1468da177 314 def_irq_handler MODEM_IRQHandler
<> 161:2cc1468da177 315 def_irq_handler RAC_SEQ_IRQHandler
<> 161:2cc1468da177 316 def_irq_handler RAC_RSM_IRQHandler
<> 161:2cc1468da177 317 def_irq_handler BUFC_IRQHandler
<> 161:2cc1468da177 318 def_irq_handler LDMA_IRQHandler
<> 161:2cc1468da177 319 def_irq_handler GPIO_EVEN_IRQHandler
<> 161:2cc1468da177 320 def_irq_handler TIMER0_IRQHandler
<> 161:2cc1468da177 321 def_irq_handler USART0_RX_IRQHandler
<> 161:2cc1468da177 322 def_irq_handler USART0_TX_IRQHandler
<> 161:2cc1468da177 323 def_irq_handler ACMP0_IRQHandler
<> 161:2cc1468da177 324 def_irq_handler ADC0_IRQHandler
<> 161:2cc1468da177 325 def_irq_handler IDAC0_IRQHandler
<> 161:2cc1468da177 326 def_irq_handler I2C0_IRQHandler
<> 161:2cc1468da177 327 def_irq_handler GPIO_ODD_IRQHandler
<> 161:2cc1468da177 328 def_irq_handler TIMER1_IRQHandler
<> 161:2cc1468da177 329 def_irq_handler USART1_RX_IRQHandler
<> 161:2cc1468da177 330 def_irq_handler USART1_TX_IRQHandler
<> 161:2cc1468da177 331 def_irq_handler LEUART0_IRQHandler
<> 161:2cc1468da177 332 def_irq_handler PCNT0_IRQHandler
<> 161:2cc1468da177 333 def_irq_handler CMU_IRQHandler
<> 161:2cc1468da177 334 def_irq_handler MSC_IRQHandler
<> 161:2cc1468da177 335 def_irq_handler CRYPTO0_IRQHandler
<> 161:2cc1468da177 336 def_irq_handler LETIMER0_IRQHandler
<> 161:2cc1468da177 337 def_irq_handler AGC_IRQHandler
<> 161:2cc1468da177 338 def_irq_handler PROTIMER_IRQHandler
<> 161:2cc1468da177 339 def_irq_handler RTCC_IRQHandler
<> 161:2cc1468da177 340 def_irq_handler SYNTH_IRQHandler
<> 161:2cc1468da177 341 def_irq_handler CRYOTIMER_IRQHandler
<> 161:2cc1468da177 342 def_irq_handler RFSENSE_IRQHandler
<> 161:2cc1468da177 343 def_irq_handler FPUEH_IRQHandler
<> 161:2cc1468da177 344 def_irq_handler SMU_IRQHandler
<> 161:2cc1468da177 345 def_irq_handler WTIMER0_IRQHandler
<> 161:2cc1468da177 346 def_irq_handler WTIMER1_IRQHandler
<> 161:2cc1468da177 347 def_irq_handler PCNT1_IRQHandler
<> 161:2cc1468da177 348 def_irq_handler PCNT2_IRQHandler
<> 161:2cc1468da177 349 def_irq_handler USART2_RX_IRQHandler
<> 161:2cc1468da177 350 def_irq_handler USART2_TX_IRQHandler
<> 161:2cc1468da177 351 def_irq_handler I2C1_IRQHandler
<> 161:2cc1468da177 352 def_irq_handler USART3_RX_IRQHandler
<> 161:2cc1468da177 353 def_irq_handler USART3_TX_IRQHandler
<> 161:2cc1468da177 354 def_irq_handler VDAC0_IRQHandler
<> 161:2cc1468da177 355 def_irq_handler CSEN_IRQHandler
<> 161:2cc1468da177 356 def_irq_handler LESENSE_IRQHandler
<> 161:2cc1468da177 357 def_irq_handler CRYPTO1_IRQHandler
<> 161:2cc1468da177 358 def_irq_handler TRNG0_IRQHandler
<> 161:2cc1468da177 359
<> 161:2cc1468da177 360 .end