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mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
161:2cc1468da177 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /**************************************************************************//**
<> 153:fa9ff456f731 2 * @file efr32mg1p_emu.h
<> 153:fa9ff456f731 3 * @brief EFR32MG1P_EMU register and bit field definitions
<> 161:2cc1468da177 4 * @version 5.1.2
<> 153:fa9ff456f731 5 ******************************************************************************
<> 153:fa9ff456f731 6 * @section License
<> 161:2cc1468da177 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 153:fa9ff456f731 8 ******************************************************************************
<> 153:fa9ff456f731 9 *
<> 153:fa9ff456f731 10 * Permission is granted to anyone to use this software for any purpose,
<> 153:fa9ff456f731 11 * including commercial applications, and to alter it and redistribute it
<> 153:fa9ff456f731 12 * freely, subject to the following restrictions:
<> 153:fa9ff456f731 13 *
<> 153:fa9ff456f731 14 * 1. The origin of this software must not be misrepresented; you must not
<> 153:fa9ff456f731 15 * claim that you wrote the original software.@n
<> 153:fa9ff456f731 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 153:fa9ff456f731 17 * misrepresented as being the original software.@n
<> 153:fa9ff456f731 18 * 3. This notice may not be removed or altered from any source distribution.
<> 153:fa9ff456f731 19 *
<> 153:fa9ff456f731 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 153:fa9ff456f731 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 153:fa9ff456f731 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 153:fa9ff456f731 23 * kind, including, but not limited to, any implied warranties of
<> 153:fa9ff456f731 24 * merchantability or fitness for any particular purpose or warranties against
<> 153:fa9ff456f731 25 * infringement of any proprietary rights of a third party.
<> 153:fa9ff456f731 26 *
<> 153:fa9ff456f731 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 153:fa9ff456f731 28 * incidental, or special damages, or any other relief, or for any claim by
<> 153:fa9ff456f731 29 * any third party, arising from your use of this Software.
<> 153:fa9ff456f731 30 *
<> 153:fa9ff456f731 31 *****************************************************************************/
<> 153:fa9ff456f731 32 /**************************************************************************//**
<> 153:fa9ff456f731 33 * @addtogroup Parts
<> 153:fa9ff456f731 34 * @{
<> 153:fa9ff456f731 35 ******************************************************************************/
<> 153:fa9ff456f731 36 /**************************************************************************//**
<> 153:fa9ff456f731 37 * @defgroup EFR32MG1P_EMU
<> 153:fa9ff456f731 38 * @{
<> 153:fa9ff456f731 39 * @brief EFR32MG1P_EMU Register Declaration
<> 153:fa9ff456f731 40 *****************************************************************************/
<> 153:fa9ff456f731 41 typedef struct
<> 153:fa9ff456f731 42 {
<> 153:fa9ff456f731 43 __IOM uint32_t CTRL; /**< Control Register */
<> 153:fa9ff456f731 44 __IM uint32_t STATUS; /**< Status Register */
<> 153:fa9ff456f731 45 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 153:fa9ff456f731 46 __IOM uint32_t RAM0CTRL; /**< Memory Control Register */
<> 153:fa9ff456f731 47 __IOM uint32_t CMD; /**< Command Register */
<> 153:fa9ff456f731 48
<> 153:fa9ff456f731 49 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 153:fa9ff456f731 50 __IOM uint32_t EM4CTRL; /**< EM4 Control Register */
<> 153:fa9ff456f731 51 __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */
<> 153:fa9ff456f731 52 __IM uint32_t TEMP; /**< Value of last temperature measurement */
<> 153:fa9ff456f731 53 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 153:fa9ff456f731 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 153:fa9ff456f731 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 153:fa9ff456f731 56 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 153:fa9ff456f731 57 __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
<> 153:fa9ff456f731 58 __IOM uint32_t PWRCFG; /**< Power Configuration Register */
<> 153:fa9ff456f731 59 __IOM uint32_t PWRCTRL; /**< Power Control Register. */
<> 153:fa9ff456f731 60 __IOM uint32_t DCDCCTRL; /**< DCDC Control */
<> 153:fa9ff456f731 61
<> 153:fa9ff456f731 62 uint32_t RESERVED1[2]; /**< Reserved for future use **/
<> 153:fa9ff456f731 63 __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
<> 153:fa9ff456f731 64 __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
<> 153:fa9ff456f731 65 __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
<> 161:2cc1468da177 66 __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */
<> 153:fa9ff456f731 67 __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */
<> 153:fa9ff456f731 68 __IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */
<> 153:fa9ff456f731 69 __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
<> 153:fa9ff456f731 70
<> 161:2cc1468da177 71 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 153:fa9ff456f731 72 __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
<> 153:fa9ff456f731 73 __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
<> 153:fa9ff456f731 74
<> 161:2cc1468da177 75 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 153:fa9ff456f731 76 __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */
<> 153:fa9ff456f731 77
<> 161:2cc1468da177 78 uint32_t RESERVED4[5]; /**< Reserved for future use **/
<> 153:fa9ff456f731 79 __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
<> 153:fa9ff456f731 80 __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
<> 153:fa9ff456f731 81 __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
<> 153:fa9ff456f731 82 __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
<> 161:2cc1468da177 83
<> 161:2cc1468da177 84 uint32_t RESERVED5[49]; /**< Reserved for future use **/
<> 161:2cc1468da177 85 __IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */
<> 161:2cc1468da177 86
<> 161:2cc1468da177 87 uint32_t RESERVED6[10]; /**< Reserved for future use **/
<> 161:2cc1468da177 88 __IOM uint32_t TESTLOCK; /**< Test Lock Register */
<> 161:2cc1468da177 89
<> 161:2cc1468da177 90 uint32_t RESERVED7[2]; /**< Reserved for future use **/
<> 161:2cc1468da177 91 __IOM uint32_t BIASTESTCTRL; /**< Test Control Register for regulator and BIAS */
<> 153:fa9ff456f731 92 } EMU_TypeDef; /** @} */
<> 153:fa9ff456f731 93
<> 153:fa9ff456f731 94 /**************************************************************************//**
<> 153:fa9ff456f731 95 * @defgroup EFR32MG1P_EMU_BitFields
<> 153:fa9ff456f731 96 * @{
<> 153:fa9ff456f731 97 *****************************************************************************/
<> 153:fa9ff456f731 98
<> 153:fa9ff456f731 99 /* Bit fields for EMU CTRL */
<> 153:fa9ff456f731 100 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
<> 153:fa9ff456f731 101 #define _EMU_CTRL_MASK 0x00000002UL /**< Mask for EMU_CTRL */
<> 153:fa9ff456f731 102 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
<> 153:fa9ff456f731 103 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
<> 153:fa9ff456f731 104 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
<> 153:fa9ff456f731 105 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
<> 153:fa9ff456f731 106 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
<> 153:fa9ff456f731 107
<> 153:fa9ff456f731 108 /* Bit fields for EMU STATUS */
<> 153:fa9ff456f731 109 #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
<> 153:fa9ff456f731 110 #define _EMU_STATUS_MASK 0x0010011FUL /**< Mask for EMU_STATUS */
<> 153:fa9ff456f731 111 #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */
<> 153:fa9ff456f731 112 #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
<> 153:fa9ff456f731 113 #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
<> 153:fa9ff456f731 114 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 115 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 116 #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */
<> 153:fa9ff456f731 117 #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
<> 153:fa9ff456f731 118 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
<> 153:fa9ff456f731 119 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 120 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 121 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */
<> 153:fa9ff456f731 122 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
<> 153:fa9ff456f731 123 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
<> 153:fa9ff456f731 124 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 125 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 126 #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */
<> 153:fa9ff456f731 127 #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
<> 153:fa9ff456f731 128 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
<> 153:fa9ff456f731 129 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 130 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 131 #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */
<> 153:fa9ff456f731 132 #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
<> 153:fa9ff456f731 133 #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
<> 153:fa9ff456f731 134 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 135 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 136 #define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */
<> 153:fa9ff456f731 137 #define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */
<> 153:fa9ff456f731 138 #define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */
<> 153:fa9ff456f731 139 #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 140 #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 141 #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */
<> 153:fa9ff456f731 142 #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */
<> 153:fa9ff456f731 143 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */
<> 153:fa9ff456f731 144 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 145 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */
<> 153:fa9ff456f731 146 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */
<> 153:fa9ff456f731 147 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */
<> 153:fa9ff456f731 148 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */
<> 153:fa9ff456f731 149 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */
<> 153:fa9ff456f731 150
<> 153:fa9ff456f731 151 /* Bit fields for EMU LOCK */
<> 153:fa9ff456f731 152 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
<> 153:fa9ff456f731 153 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
<> 153:fa9ff456f731 154 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
<> 153:fa9ff456f731 155 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
<> 153:fa9ff456f731 156 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
<> 153:fa9ff456f731 157 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
<> 153:fa9ff456f731 158 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
<> 153:fa9ff456f731 159 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
<> 153:fa9ff456f731 160 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
<> 153:fa9ff456f731 161 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
<> 153:fa9ff456f731 162 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
<> 153:fa9ff456f731 163 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
<> 153:fa9ff456f731 164 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
<> 153:fa9ff456f731 165 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
<> 153:fa9ff456f731 166
<> 153:fa9ff456f731 167 /* Bit fields for EMU RAM0CTRL */
<> 153:fa9ff456f731 168 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */
<> 153:fa9ff456f731 169 #define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */
<> 153:fa9ff456f731 170 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
<> 153:fa9ff456f731 171 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */
<> 153:fa9ff456f731 172 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */
<> 153:fa9ff456f731 173 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */
<> 153:fa9ff456f731 174 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 175 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 176 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 177 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 178 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
<> 153:fa9ff456f731 179 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */
<> 153:fa9ff456f731 180 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 181 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 182 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 183 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */
<> 153:fa9ff456f731 184
<> 153:fa9ff456f731 185 /* Bit fields for EMU CMD */
<> 153:fa9ff456f731 186 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
<> 153:fa9ff456f731 187 #define _EMU_CMD_MASK 0x00000001UL /**< Mask for EMU_CMD */
<> 153:fa9ff456f731 188 #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */
<> 153:fa9ff456f731 189 #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */
<> 153:fa9ff456f731 190 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */
<> 153:fa9ff456f731 191 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
<> 153:fa9ff456f731 192 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
<> 153:fa9ff456f731 193
<> 153:fa9ff456f731 194 /* Bit fields for EMU EM4CTRL */
<> 153:fa9ff456f731 195 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
<> 153:fa9ff456f731 196 #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */
<> 153:fa9ff456f731 197 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */
<> 153:fa9ff456f731 198 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */
<> 153:fa9ff456f731 199 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */
<> 153:fa9ff456f731 200 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 201 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */
<> 153:fa9ff456f731 202 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */
<> 153:fa9ff456f731 203 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 204 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
<> 153:fa9ff456f731 205 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
<> 153:fa9ff456f731 206 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */
<> 153:fa9ff456f731 207 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
<> 153:fa9ff456f731 208 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
<> 153:fa9ff456f731 209 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 210 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 211 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */
<> 153:fa9ff456f731 212 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
<> 153:fa9ff456f731 213 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
<> 153:fa9ff456f731 214 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 215 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 216 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */
<> 153:fa9ff456f731 217 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
<> 153:fa9ff456f731 218 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
<> 153:fa9ff456f731 219 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 220 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 221 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
<> 153:fa9ff456f731 222 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
<> 153:fa9ff456f731 223 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 224 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
<> 153:fa9ff456f731 225 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
<> 153:fa9ff456f731 226 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
<> 153:fa9ff456f731 227 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 228 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
<> 153:fa9ff456f731 229 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
<> 153:fa9ff456f731 230 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
<> 153:fa9ff456f731 231 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */
<> 153:fa9ff456f731 232 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */
<> 153:fa9ff456f731 233 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 234 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
<> 153:fa9ff456f731 235
<> 153:fa9ff456f731 236 /* Bit fields for EMU TEMPLIMITS */
<> 153:fa9ff456f731 237 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 238 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 239 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
<> 153:fa9ff456f731 240 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */
<> 153:fa9ff456f731 241 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 242 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 243 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */
<> 153:fa9ff456f731 244 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
<> 153:fa9ff456f731 245 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 246 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 247 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */
<> 153:fa9ff456f731 248 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
<> 153:fa9ff456f731 249 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
<> 153:fa9ff456f731 250 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 251 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
<> 153:fa9ff456f731 252
<> 153:fa9ff456f731 253 /* Bit fields for EMU TEMP */
<> 153:fa9ff456f731 254 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
<> 153:fa9ff456f731 255 #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */
<> 153:fa9ff456f731 256 #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */
<> 153:fa9ff456f731 257 #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */
<> 153:fa9ff456f731 258 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
<> 153:fa9ff456f731 259 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
<> 153:fa9ff456f731 260
<> 153:fa9ff456f731 261 /* Bit fields for EMU IF */
<> 153:fa9ff456f731 262 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
<> 153:fa9ff456f731 263 #define _EMU_IF_MASK 0xE11FC0FFUL /**< Mask for EMU_IF */
<> 153:fa9ff456f731 264 #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */
<> 153:fa9ff456f731 265 #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 266 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 267 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 268 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 269 #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */
<> 153:fa9ff456f731 270 #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 271 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 272 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 273 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 274 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */
<> 153:fa9ff456f731 275 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 276 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 277 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 278 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 279 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */
<> 153:fa9ff456f731 280 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 281 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 282 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 283 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 284 #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */
<> 153:fa9ff456f731 285 #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 286 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 287 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 288 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 289 #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */
<> 153:fa9ff456f731 290 #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 291 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 292 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 293 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 294 #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */
<> 153:fa9ff456f731 295 #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 296 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 297 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 298 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 299 #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */
<> 153:fa9ff456f731 300 #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 301 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 302 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 303 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 304 #define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */
<> 153:fa9ff456f731 305 #define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 306 #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 307 #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 308 #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 309 #define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */
<> 153:fa9ff456f731 310 #define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 311 #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 312 #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 313 #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 314 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */
<> 153:fa9ff456f731 315 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 316 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 317 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 318 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 319 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */
<> 153:fa9ff456f731 320 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 321 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 322 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 323 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 324 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */
<> 153:fa9ff456f731 325 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 326 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 327 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 328 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 329 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */
<> 153:fa9ff456f731 330 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 331 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 332 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 333 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 334 #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */
<> 153:fa9ff456f731 335 #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 336 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 337 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 338 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 339 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */
<> 153:fa9ff456f731 340 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 341 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 342 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 343 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 344 #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */
<> 153:fa9ff456f731 345 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
<> 153:fa9ff456f731 346 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
<> 153:fa9ff456f731 347 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 348 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 349 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */
<> 153:fa9ff456f731 350 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
<> 153:fa9ff456f731 351 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
<> 153:fa9ff456f731 352 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 353 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 354 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */
<> 153:fa9ff456f731 355 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
<> 153:fa9ff456f731 356 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
<> 153:fa9ff456f731 357 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 358 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
<> 153:fa9ff456f731 359
<> 153:fa9ff456f731 360 /* Bit fields for EMU IFS */
<> 153:fa9ff456f731 361 #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
<> 161:2cc1468da177 362 #define _EMU_IFS_MASK 0xE11FC0FFUL /**< Mask for EMU_IFS */
<> 153:fa9ff456f731 363 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 364 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 365 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 366 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 367 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 368 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 369 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 370 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 371 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 372 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 373 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 374 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 375 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 376 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 377 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 378 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 379 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 380 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 381 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 382 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 383 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 384 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 385 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 386 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 387 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 388 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 389 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 390 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 391 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 392 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 393 #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */
<> 153:fa9ff456f731 394 #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 395 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 396 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 397 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 398 #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */
<> 153:fa9ff456f731 399 #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 400 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 401 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 402 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 403 #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 404 #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 405 #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 406 #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 407 #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 408 #define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 409 #define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 410 #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 411 #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 412 #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 413 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
<> 153:fa9ff456f731 414 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 415 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 416 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 417 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 418 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
<> 153:fa9ff456f731 419 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 420 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 421 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 422 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 423 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */
<> 153:fa9ff456f731 424 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 425 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 426 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 427 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 428 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */
<> 153:fa9ff456f731 429 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 430 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 431 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 432 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 433 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */
<> 153:fa9ff456f731 434 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 435 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 436 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 437 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 438 #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */
<> 153:fa9ff456f731 439 #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 440 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 441 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 442 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 443 #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */
<> 153:fa9ff456f731 444 #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
<> 153:fa9ff456f731 445 #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
<> 153:fa9ff456f731 446 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 447 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 448 #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */
<> 153:fa9ff456f731 449 #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
<> 153:fa9ff456f731 450 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
<> 153:fa9ff456f731 451 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 452 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 453 #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */
<> 153:fa9ff456f731 454 #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
<> 153:fa9ff456f731 455 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
<> 153:fa9ff456f731 456 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 457 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */
<> 153:fa9ff456f731 458
<> 153:fa9ff456f731 459 /* Bit fields for EMU IFC */
<> 153:fa9ff456f731 460 #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
<> 161:2cc1468da177 461 #define _EMU_IFC_MASK 0xE11FC0FFUL /**< Mask for EMU_IFC */
<> 153:fa9ff456f731 462 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 463 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 464 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 465 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 466 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 467 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 468 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 469 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 470 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 471 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 472 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 473 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 474 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 475 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 476 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 477 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 478 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 479 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 480 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 481 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 482 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 483 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 484 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 485 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 486 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 487 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 488 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 489 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 490 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 491 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 492 #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */
<> 153:fa9ff456f731 493 #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 494 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 495 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 496 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 497 #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */
<> 153:fa9ff456f731 498 #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 499 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 500 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 501 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 502 #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */
<> 153:fa9ff456f731 503 #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 504 #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 505 #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 506 #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 507 #define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */
<> 153:fa9ff456f731 508 #define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 509 #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 510 #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 511 #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 512 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
<> 153:fa9ff456f731 513 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 514 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 515 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 516 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 517 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
<> 153:fa9ff456f731 518 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 519 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 520 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 521 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 522 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */
<> 153:fa9ff456f731 523 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 524 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 525 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 526 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 527 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */
<> 153:fa9ff456f731 528 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 529 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 530 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 531 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 532 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */
<> 153:fa9ff456f731 533 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 534 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 535 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 536 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 537 #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */
<> 153:fa9ff456f731 538 #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 539 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 540 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 541 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 542 #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */
<> 153:fa9ff456f731 543 #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
<> 153:fa9ff456f731 544 #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
<> 153:fa9ff456f731 545 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 546 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 547 #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */
<> 153:fa9ff456f731 548 #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
<> 153:fa9ff456f731 549 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
<> 153:fa9ff456f731 550 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 551 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 552 #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */
<> 153:fa9ff456f731 553 #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
<> 153:fa9ff456f731 554 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
<> 153:fa9ff456f731 555 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 556 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */
<> 153:fa9ff456f731 557
<> 153:fa9ff456f731 558 /* Bit fields for EMU IEN */
<> 153:fa9ff456f731 559 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
<> 161:2cc1468da177 560 #define _EMU_IEN_MASK 0xE11FC0FFUL /**< Mask for EMU_IEN */
<> 153:fa9ff456f731 561 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */
<> 153:fa9ff456f731 562 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 563 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
<> 153:fa9ff456f731 564 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 565 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 566 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */
<> 153:fa9ff456f731 567 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 568 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
<> 153:fa9ff456f731 569 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 570 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 571 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */
<> 153:fa9ff456f731 572 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 573 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
<> 153:fa9ff456f731 574 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 575 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 576 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */
<> 153:fa9ff456f731 577 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 578 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
<> 153:fa9ff456f731 579 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 580 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 581 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */
<> 153:fa9ff456f731 582 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 583 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
<> 153:fa9ff456f731 584 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 585 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 586 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */
<> 153:fa9ff456f731 587 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 588 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
<> 153:fa9ff456f731 589 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 590 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 591 #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */
<> 153:fa9ff456f731 592 #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 593 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
<> 153:fa9ff456f731 594 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 595 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 596 #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */
<> 153:fa9ff456f731 597 #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 598 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
<> 153:fa9ff456f731 599 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 600 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 601 #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */
<> 153:fa9ff456f731 602 #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 603 #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
<> 153:fa9ff456f731 604 #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 605 #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 606 #define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */
<> 153:fa9ff456f731 607 #define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 608 #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
<> 153:fa9ff456f731 609 #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 610 #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 611 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */
<> 153:fa9ff456f731 612 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 613 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 614 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 615 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 616 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */
<> 153:fa9ff456f731 617 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 618 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
<> 153:fa9ff456f731 619 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 620 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 621 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */
<> 153:fa9ff456f731 622 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 623 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
<> 153:fa9ff456f731 624 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 625 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 626 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */
<> 153:fa9ff456f731 627 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 628 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
<> 153:fa9ff456f731 629 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 630 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 631 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */
<> 153:fa9ff456f731 632 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 633 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
<> 153:fa9ff456f731 634 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 635 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 636 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */
<> 153:fa9ff456f731 637 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 638 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
<> 153:fa9ff456f731 639 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 640 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 641 #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */
<> 153:fa9ff456f731 642 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
<> 153:fa9ff456f731 643 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
<> 153:fa9ff456f731 644 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 645 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 646 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */
<> 153:fa9ff456f731 647 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
<> 153:fa9ff456f731 648 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
<> 153:fa9ff456f731 649 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 650 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 651 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */
<> 153:fa9ff456f731 652 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
<> 153:fa9ff456f731 653 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
<> 153:fa9ff456f731 654 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 655 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
<> 153:fa9ff456f731 656
<> 153:fa9ff456f731 657 /* Bit fields for EMU PWRLOCK */
<> 153:fa9ff456f731 658 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */
<> 153:fa9ff456f731 659 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */
<> 153:fa9ff456f731 660 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
<> 153:fa9ff456f731 661 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
<> 153:fa9ff456f731 662 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
<> 153:fa9ff456f731 663 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
<> 153:fa9ff456f731 664 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
<> 153:fa9ff456f731 665 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
<> 153:fa9ff456f731 666 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
<> 153:fa9ff456f731 667 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
<> 153:fa9ff456f731 668 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
<> 153:fa9ff456f731 669 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
<> 153:fa9ff456f731 670 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
<> 153:fa9ff456f731 671 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
<> 153:fa9ff456f731 672
<> 153:fa9ff456f731 673 /* Bit fields for EMU PWRCFG */
<> 153:fa9ff456f731 674 #define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */
<> 153:fa9ff456f731 675 #define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */
<> 153:fa9ff456f731 676 #define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */
<> 153:fa9ff456f731 677 #define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */
<> 153:fa9ff456f731 678 #define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */
<> 153:fa9ff456f731 679 #define _EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL /**< Mode STARTUP for EMU_PWRCFG */
<> 153:fa9ff456f731 680 #define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */
<> 153:fa9ff456f731 681 #define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */
<> 153:fa9ff456f731 682 #define EMU_PWRCFG_PWRCFG_STARTUP (_EMU_PWRCFG_PWRCFG_STARTUP << 0) /**< Shifted mode STARTUP for EMU_PWRCFG */
<> 153:fa9ff456f731 683 #define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */
<> 153:fa9ff456f731 684
<> 153:fa9ff456f731 685 /* Bit fields for EMU PWRCTRL */
<> 153:fa9ff456f731 686 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */
<> 153:fa9ff456f731 687 #define _EMU_PWRCTRL_MASK 0x00000020UL /**< Mask for EMU_PWRCTRL */
<> 153:fa9ff456f731 688 #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */
<> 153:fa9ff456f731 689 #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */
<> 153:fa9ff456f731 690 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */
<> 153:fa9ff456f731 691 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
<> 153:fa9ff456f731 692 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
<> 153:fa9ff456f731 693 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
<> 153:fa9ff456f731 694 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
<> 153:fa9ff456f731 695 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */
<> 153:fa9ff456f731 696 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */
<> 153:fa9ff456f731 697
<> 153:fa9ff456f731 698 /* Bit fields for EMU DCDCCTRL */
<> 153:fa9ff456f731 699 #define _EMU_DCDCCTRL_RESETVALUE 0x00000030UL /**< Default value for EMU_DCDCCTRL */
<> 153:fa9ff456f731 700 #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */
<> 153:fa9ff456f731 701 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */
<> 153:fa9ff456f731 702 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */
<> 153:fa9ff456f731 703 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCTRL */
<> 153:fa9ff456f731 704 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */
<> 153:fa9ff456f731 705 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */
<> 153:fa9ff456f731 706 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */
<> 153:fa9ff456f731 707 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */
<> 153:fa9ff456f731 708 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
<> 153:fa9ff456f731 709 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */
<> 153:fa9ff456f731 710 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
<> 153:fa9ff456f731 711 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
<> 153:fa9ff456f731 712 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */
<> 153:fa9ff456f731 713 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */
<> 153:fa9ff456f731 714 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */
<> 153:fa9ff456f731 715 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */
<> 153:fa9ff456f731 716 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */
<> 153:fa9ff456f731 717 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
<> 153:fa9ff456f731 718 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */
<> 153:fa9ff456f731 719 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */
<> 153:fa9ff456f731 720 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
<> 153:fa9ff456f731 721 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */
<> 153:fa9ff456f731 722 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */
<> 153:fa9ff456f731 723 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */
<> 153:fa9ff456f731 724 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */
<> 153:fa9ff456f731 725 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */
<> 153:fa9ff456f731 726 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
<> 153:fa9ff456f731 727 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */
<> 153:fa9ff456f731 728 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */
<> 153:fa9ff456f731 729 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
<> 153:fa9ff456f731 730 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */
<> 153:fa9ff456f731 731
<> 153:fa9ff456f731 732 /* Bit fields for EMU DCDCMISCCTRL */
<> 153:fa9ff456f731 733 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL /**< Default value for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 734 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL /**< Mask for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 735 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */
<> 153:fa9ff456f731 736 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
<> 153:fa9ff456f731 737 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
<> 153:fa9ff456f731 738 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 739 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 740 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */
<> 153:fa9ff456f731 741 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */
<> 153:fa9ff456f731 742 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 743 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 744 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */
<> 153:fa9ff456f731 745 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */
<> 153:fa9ff456f731 746 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 747 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 748 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */
<> 153:fa9ff456f731 749 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */
<> 153:fa9ff456f731 750 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 751 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 752 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */
<> 153:fa9ff456f731 753 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */
<> 153:fa9ff456f731 754 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 755 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 756 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */
<> 153:fa9ff456f731 757 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */
<> 153:fa9ff456f731 758 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 759 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 760 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28 /**< Shift value for EMU_LPCMPBIAS */
<> 153:fa9ff456f731 761 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIAS */
<> 153:fa9ff456f731 762 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 763 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 764 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 765 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 766 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 767 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 768 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 769 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 770 #define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 771 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
<> 153:fa9ff456f731 772
<> 153:fa9ff456f731 773 /* Bit fields for EMU DCDCZDETCTRL */
<> 153:fa9ff456f731 774 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL /**< Default value for EMU_DCDCZDETCTRL */
<> 153:fa9ff456f731 775 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */
<> 153:fa9ff456f731 776 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */
<> 153:fa9ff456f731 777 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */
<> 153:fa9ff456f731 778 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
<> 153:fa9ff456f731 779 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
<> 153:fa9ff456f731 780 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */
<> 153:fa9ff456f731 781 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */
<> 153:fa9ff456f731 782 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
<> 153:fa9ff456f731 783 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
<> 153:fa9ff456f731 784
<> 153:fa9ff456f731 785 /* Bit fields for EMU DCDCCLIMCTRL */
<> 153:fa9ff456f731 786 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL /**< Default value for EMU_DCDCCLIMCTRL */
<> 153:fa9ff456f731 787 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */
<> 153:fa9ff456f731 788 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */
<> 153:fa9ff456f731 789 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */
<> 153:fa9ff456f731 790 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
<> 153:fa9ff456f731 791 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
<> 153:fa9ff456f731 792 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */
<> 153:fa9ff456f731 793 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */
<> 153:fa9ff456f731 794 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */
<> 153:fa9ff456f731 795 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
<> 153:fa9ff456f731 796 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
<> 153:fa9ff456f731 797
<> 161:2cc1468da177 798 /* Bit fields for EMU DCDCLNCOMPCTRL */
<> 161:2cc1468da177 799 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 800 #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 801 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */
<> 161:2cc1468da177 802 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */
<> 161:2cc1468da177 803 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 804 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 805 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */
<> 161:2cc1468da177 806 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */
<> 161:2cc1468da177 807 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 808 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 809 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */
<> 161:2cc1468da177 810 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */
<> 161:2cc1468da177 811 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 812 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 813 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */
<> 161:2cc1468da177 814 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */
<> 161:2cc1468da177 815 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 816 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 817 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */
<> 161:2cc1468da177 818 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */
<> 161:2cc1468da177 819 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 820 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 821 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */
<> 161:2cc1468da177 822 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */
<> 161:2cc1468da177 823 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 824 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
<> 161:2cc1468da177 825
<> 153:fa9ff456f731 826 /* Bit fields for EMU DCDCLNVCTRL */
<> 153:fa9ff456f731 827 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 828 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 829 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */
<> 153:fa9ff456f731 830 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */
<> 153:fa9ff456f731 831 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */
<> 153:fa9ff456f731 832 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 833 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 834 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 835 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 836 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 837 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 838 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */
<> 153:fa9ff456f731 839 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */
<> 153:fa9ff456f731 840 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 841 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
<> 153:fa9ff456f731 842
<> 153:fa9ff456f731 843 /* Bit fields for EMU DCDCTIMING */
<> 153:fa9ff456f731 844 #define _EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL /**< Default value for EMU_DCDCTIMING */
<> 153:fa9ff456f731 845 #define _EMU_DCDCTIMING_MASK 0x6FF1F8FFUL /**< Mask for EMU_DCDCTIMING */
<> 153:fa9ff456f731 846 #define _EMU_DCDCTIMING_LPINITWAIT_SHIFT 0 /**< Shift value for EMU_LPINITWAIT */
<> 153:fa9ff456f731 847 #define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL /**< Bit mask for EMU_LPINITWAIT */
<> 153:fa9ff456f731 848 #define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 849 #define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 850 #define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN mode precharge enable */
<> 153:fa9ff456f731 851 #define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11 /**< Shift value for EMU_COMPENPRCHGEN */
<> 153:fa9ff456f731 852 #define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL /**< Bit mask for EMU_COMPENPRCHGEN */
<> 153:fa9ff456f731 853 #define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 854 #define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 855 #define _EMU_DCDCTIMING_LNWAIT_SHIFT 12 /**< Shift value for EMU_LNWAIT */
<> 153:fa9ff456f731 856 #define _EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL /**< Bit mask for EMU_LNWAIT */
<> 153:fa9ff456f731 857 #define _EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL /**< Mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 858 #define EMU_DCDCTIMING_LNWAIT_DEFAULT (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 859 #define _EMU_DCDCTIMING_BYPWAIT_SHIFT 20 /**< Shift value for EMU_BYPWAIT */
<> 153:fa9ff456f731 860 #define _EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL /**< Bit mask for EMU_BYPWAIT */
<> 153:fa9ff456f731 861 #define _EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 862 #define EMU_DCDCTIMING_BYPWAIT_DEFAULT (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 863 #define _EMU_DCDCTIMING_DUTYSCALE_SHIFT 29 /**< Shift value for EMU_DUTYSCALE */
<> 153:fa9ff456f731 864 #define _EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL /**< Bit mask for EMU_DUTYSCALE */
<> 153:fa9ff456f731 865 #define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 866 #define EMU_DCDCTIMING_DUTYSCALE_DEFAULT (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
<> 153:fa9ff456f731 867
<> 153:fa9ff456f731 868 /* Bit fields for EMU DCDCLPVCTRL */
<> 153:fa9ff456f731 869 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 870 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 871 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */
<> 153:fa9ff456f731 872 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
<> 153:fa9ff456f731 873 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
<> 153:fa9ff456f731 874 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 875 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 876 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 877 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 878 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 879 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 880 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */
<> 153:fa9ff456f731 881 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */
<> 153:fa9ff456f731 882 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 883 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
<> 153:fa9ff456f731 884
<> 153:fa9ff456f731 885 /* Bit fields for EMU DCDCLPCTRL */
<> 153:fa9ff456f731 886 #define _EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL /**< Default value for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 887 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 888 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSEL */
<> 153:fa9ff456f731 889 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSEL */
<> 153:fa9ff456f731 890 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 891 #define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 892 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */
<> 153:fa9ff456f731 893 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
<> 153:fa9ff456f731 894 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
<> 153:fa9ff456f731 895 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 896 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 897 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */
<> 153:fa9ff456f731 898 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */
<> 153:fa9ff456f731 899 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 900 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
<> 153:fa9ff456f731 901
<> 153:fa9ff456f731 902 /* Bit fields for EMU DCDCLNFREQCTRL */
<> 153:fa9ff456f731 903 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */
<> 153:fa9ff456f731 904 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */
<> 153:fa9ff456f731 905 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */
<> 153:fa9ff456f731 906 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */
<> 153:fa9ff456f731 907 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
<> 153:fa9ff456f731 908 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
<> 153:fa9ff456f731 909 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */
<> 153:fa9ff456f731 910 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */
<> 153:fa9ff456f731 911 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
<> 153:fa9ff456f731 912 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
<> 153:fa9ff456f731 913
<> 153:fa9ff456f731 914 /* Bit fields for EMU DCDCSYNC */
<> 153:fa9ff456f731 915 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
<> 153:fa9ff456f731 916 #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
<> 153:fa9ff456f731 917 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */
<> 153:fa9ff456f731 918 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
<> 153:fa9ff456f731 919 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
<> 153:fa9ff456f731 920 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
<> 153:fa9ff456f731 921 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
<> 153:fa9ff456f731 922
<> 153:fa9ff456f731 923 /* Bit fields for EMU VMONAVDDCTRL */
<> 153:fa9ff456f731 924 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 925 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 926 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */
<> 153:fa9ff456f731 927 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
<> 153:fa9ff456f731 928 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
<> 153:fa9ff456f731 929 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 930 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 931 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
<> 153:fa9ff456f731 932 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
<> 153:fa9ff456f731 933 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
<> 153:fa9ff456f731 934 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 935 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 936 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
<> 153:fa9ff456f731 937 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
<> 153:fa9ff456f731 938 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
<> 153:fa9ff456f731 939 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 940 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 941 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */
<> 153:fa9ff456f731 942 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */
<> 153:fa9ff456f731 943 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 944 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 945 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */
<> 153:fa9ff456f731 946 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */
<> 153:fa9ff456f731 947 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 948 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 949 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */
<> 153:fa9ff456f731 950 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */
<> 153:fa9ff456f731 951 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 952 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 953 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */
<> 153:fa9ff456f731 954 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */
<> 153:fa9ff456f731 955 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 956 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
<> 153:fa9ff456f731 957
<> 153:fa9ff456f731 958 /* Bit fields for EMU VMONALTAVDDCTRL */
<> 153:fa9ff456f731 959 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 960 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 961 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */
<> 153:fa9ff456f731 962 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
<> 153:fa9ff456f731 963 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
<> 153:fa9ff456f731 964 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 965 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 966 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
<> 153:fa9ff456f731 967 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
<> 153:fa9ff456f731 968 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
<> 153:fa9ff456f731 969 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 970 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 971 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
<> 153:fa9ff456f731 972 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
<> 153:fa9ff456f731 973 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
<> 153:fa9ff456f731 974 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 975 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 976 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
<> 153:fa9ff456f731 977 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
<> 153:fa9ff456f731 978 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 979 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 980 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
<> 153:fa9ff456f731 981 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
<> 153:fa9ff456f731 982 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 983 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
<> 153:fa9ff456f731 984
<> 153:fa9ff456f731 985 /* Bit fields for EMU VMONDVDDCTRL */
<> 153:fa9ff456f731 986 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 987 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 988 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */
<> 153:fa9ff456f731 989 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
<> 153:fa9ff456f731 990 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
<> 153:fa9ff456f731 991 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 992 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 993 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
<> 153:fa9ff456f731 994 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
<> 153:fa9ff456f731 995 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
<> 153:fa9ff456f731 996 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 997 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 998 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
<> 153:fa9ff456f731 999 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
<> 153:fa9ff456f731 1000 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
<> 153:fa9ff456f731 1001 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 1002 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 1003 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
<> 153:fa9ff456f731 1004 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
<> 153:fa9ff456f731 1005 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 1006 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 1007 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
<> 153:fa9ff456f731 1008 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
<> 153:fa9ff456f731 1009 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 1010 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
<> 153:fa9ff456f731 1011
<> 153:fa9ff456f731 1012 /* Bit fields for EMU VMONIO0CTRL */
<> 153:fa9ff456f731 1013 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1014 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1015 #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */
<> 153:fa9ff456f731 1016 #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
<> 153:fa9ff456f731 1017 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
<> 153:fa9ff456f731 1018 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1019 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1020 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
<> 153:fa9ff456f731 1021 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
<> 153:fa9ff456f731 1022 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
<> 153:fa9ff456f731 1023 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1024 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1025 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
<> 153:fa9ff456f731 1026 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
<> 153:fa9ff456f731 1027 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
<> 153:fa9ff456f731 1028 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1029 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1030 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */
<> 153:fa9ff456f731 1031 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
<> 153:fa9ff456f731 1032 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
<> 153:fa9ff456f731 1033 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1034 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1035 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
<> 153:fa9ff456f731 1036 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
<> 153:fa9ff456f731 1037 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1038 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1039 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
<> 153:fa9ff456f731 1040 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
<> 153:fa9ff456f731 1041 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1042 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
<> 153:fa9ff456f731 1043
<> 161:2cc1468da177 1044 /* Bit fields for EMU BIASCONF */
<> 161:2cc1468da177 1045 #define _EMU_BIASCONF_RESETVALUE 0x000000F8UL /**< Default value for EMU_BIASCONF */
<> 161:2cc1468da177 1046 #define _EMU_BIASCONF_MASK 0x000000FCUL /**< Mask for EMU_BIASCONF */
<> 161:2cc1468da177 1047 #define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2) /**< NA DUTY in EM01 */
<> 161:2cc1468da177 1048 #define _EMU_BIASCONF_NADUTYEM01_SHIFT 2 /**< Shift value for EMU_NADUTYEM01 */
<> 161:2cc1468da177 1049 #define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL /**< Bit mask for EMU_NADUTYEM01 */
<> 161:2cc1468da177 1050 #define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1051 #define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1052 #define EMU_BIASCONF_LPEM01 (0x1UL << 3) /**< LP in EM01 */
<> 161:2cc1468da177 1053 #define _EMU_BIASCONF_LPEM01_SHIFT 3 /**< Shift value for EMU_LPEM01 */
<> 161:2cc1468da177 1054 #define _EMU_BIASCONF_LPEM01_MASK 0x8UL /**< Bit mask for EMU_LPEM01 */
<> 161:2cc1468da177 1055 #define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1056 #define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1057 #define EMU_BIASCONF_GMCEM23 (0x1UL << 4) /**< GMC in EM234 */
<> 161:2cc1468da177 1058 #define _EMU_BIASCONF_GMCEM23_SHIFT 4 /**< Shift value for EMU_GMCEM23 */
<> 161:2cc1468da177 1059 #define _EMU_BIASCONF_GMCEM23_MASK 0x10UL /**< Bit mask for EMU_GMCEM23 */
<> 161:2cc1468da177 1060 #define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1061 #define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1062 #define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5) /**< UADUTY in EM234 */
<> 161:2cc1468da177 1063 #define _EMU_BIASCONF_UADUTYEM23_SHIFT 5 /**< Shift value for EMU_UADUTYEM23 */
<> 161:2cc1468da177 1064 #define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL /**< Bit mask for EMU_UADUTYEM23 */
<> 161:2cc1468da177 1065 #define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1066 #define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1067 #define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6) /**< NA DUTY in EM234 */
<> 161:2cc1468da177 1068 #define _EMU_BIASCONF_NADUTYEM23_SHIFT 6 /**< Shift value for EMU_NADUTYEM23 */
<> 161:2cc1468da177 1069 #define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL /**< Bit mask for EMU_NADUTYEM23 */
<> 161:2cc1468da177 1070 #define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1071 #define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1072 #define EMU_BIASCONF_LPEM23 (0x1UL << 7) /**< LP in EM234 */
<> 161:2cc1468da177 1073 #define _EMU_BIASCONF_LPEM23_SHIFT 7 /**< Shift value for EMU_LPEM23 */
<> 161:2cc1468da177 1074 #define _EMU_BIASCONF_LPEM23_MASK 0x80UL /**< Bit mask for EMU_LPEM23 */
<> 161:2cc1468da177 1075 #define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1076 #define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_BIASCONF */
<> 161:2cc1468da177 1077
<> 161:2cc1468da177 1078 /* Bit fields for EMU TESTLOCK */
<> 161:2cc1468da177 1079 #define _EMU_TESTLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_TESTLOCK */
<> 161:2cc1468da177 1080 #define _EMU_TESTLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_TESTLOCK */
<> 161:2cc1468da177 1081 #define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
<> 161:2cc1468da177 1082 #define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
<> 161:2cc1468da177 1083 #define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */
<> 161:2cc1468da177 1084 #define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */
<> 161:2cc1468da177 1085 #define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */
<> 161:2cc1468da177 1086 #define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */
<> 161:2cc1468da177 1087 #define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */
<> 161:2cc1468da177 1088 #define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */
<> 161:2cc1468da177 1089 #define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */
<> 161:2cc1468da177 1090 #define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */
<> 161:2cc1468da177 1091 #define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */
<> 161:2cc1468da177 1092 #define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */
<> 161:2cc1468da177 1093
<> 161:2cc1468da177 1094 /* Bit fields for EMU BIASTESTCTRL */
<> 161:2cc1468da177 1095 #define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BIASTESTCTRL */
<> 161:2cc1468da177 1096 #define _EMU_BIASTESTCTRL_MASK 0x00000008UL /**< Mask for EMU_BIASTESTCTRL */
<> 161:2cc1468da177 1097 #define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3) /**< Reset Bias Ripple Counter */
<> 161:2cc1468da177 1098 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3 /**< Shift value for EMU_BIAS_RIP_RESET */
<> 161:2cc1468da177 1099 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL /**< Bit mask for EMU_BIAS_RIP_RESET */
<> 161:2cc1468da177 1100 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */
<> 161:2cc1468da177 1101 #define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */
<> 161:2cc1468da177 1102
<> 153:fa9ff456f731 1103 /** @} End of group EFR32MG1P_EMU */
<> 153:fa9ff456f731 1104 /** @} End of group Parts */
<> 153:fa9ff456f731 1105