mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
161:2cc1468da177 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32pg1b200f256im48.h
<> 150:02e0a0aed4ec 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 150:02e0a0aed4ec 4 * for EFM32PG1B200F256IM48
<> 161:2cc1468da177 5 * @version 5.1.2
<> 150:02e0a0aed4ec 6 ******************************************************************************
<> 150:02e0a0aed4ec 7 * @section License
<> 161:2cc1468da177 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 9 ******************************************************************************
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 12 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 13 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 14 *
<> 150:02e0a0aed4ec 15 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 16 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 18 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 19 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 20 *
<> 150:02e0a0aed4ec 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 24 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 25 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 26 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 27 *
<> 150:02e0a0aed4ec 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 29 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 30 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 *****************************************************************************/
<> 150:02e0a0aed4ec 33
<> 150:02e0a0aed4ec 34 #ifndef EFM32PG1B200F256IM48_H
<> 150:02e0a0aed4ec 35 #define EFM32PG1B200F256IM48_H
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 #ifdef __cplusplus
<> 150:02e0a0aed4ec 38 extern "C" {
<> 150:02e0a0aed4ec 39 #endif
<> 150:02e0a0aed4ec 40
<> 150:02e0a0aed4ec 41 /**************************************************************************//**
<> 150:02e0a0aed4ec 42 * @addtogroup Parts
<> 150:02e0a0aed4ec 43 * @{
<> 150:02e0a0aed4ec 44 *****************************************************************************/
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 /**************************************************************************//**
<> 150:02e0a0aed4ec 47 * @defgroup EFM32PG1B200F256IM48 EFM32PG1B200F256IM48
<> 150:02e0a0aed4ec 48 * @{
<> 150:02e0a0aed4ec 49 *****************************************************************************/
<> 150:02e0a0aed4ec 50
<> 150:02e0a0aed4ec 51 /** Interrupt Number Definition */
<> 150:02e0a0aed4ec 52 typedef enum IRQn
<> 150:02e0a0aed4ec 53 {
<> 150:02e0a0aed4ec 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
<> 150:02e0a0aed4ec 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
<> 150:02e0a0aed4ec 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
<> 150:02e0a0aed4ec 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
<> 150:02e0a0aed4ec 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
<> 150:02e0a0aed4ec 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
<> 150:02e0a0aed4ec 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
<> 150:02e0a0aed4ec 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
<> 150:02e0a0aed4ec 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
<> 150:02e0a0aed4ec 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 /****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
<> 150:02e0a0aed4ec 68 WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
<> 150:02e0a0aed4ec 69 LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
<> 150:02e0a0aed4ec 70 GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
<> 150:02e0a0aed4ec 71 TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
<> 150:02e0a0aed4ec 72 USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
<> 150:02e0a0aed4ec 73 USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
<> 150:02e0a0aed4ec 74 ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
<> 150:02e0a0aed4ec 75 ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
<> 150:02e0a0aed4ec 76 IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
<> 150:02e0a0aed4ec 77 I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
<> 150:02e0a0aed4ec 78 GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
<> 150:02e0a0aed4ec 79 TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
<> 150:02e0a0aed4ec 80 USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
<> 150:02e0a0aed4ec 81 USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
<> 150:02e0a0aed4ec 82 LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
<> 150:02e0a0aed4ec 83 PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
<> 150:02e0a0aed4ec 84 CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
<> 150:02e0a0aed4ec 85 MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
<> 150:02e0a0aed4ec 86 CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
<> 150:02e0a0aed4ec 87 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
<> 150:02e0a0aed4ec 88 RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
<> 150:02e0a0aed4ec 89 CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
<> 150:02e0a0aed4ec 90 FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
<> 150:02e0a0aed4ec 91 } IRQn_Type;
<> 150:02e0a0aed4ec 92
<> 150:02e0a0aed4ec 93 /**************************************************************************//**
<> 150:02e0a0aed4ec 94 * @defgroup EFM32PG1B200F256IM48_Core EFM32PG1B200F256IM48 Core
<> 150:02e0a0aed4ec 95 * @{
<> 150:02e0a0aed4ec 96 * @brief Processor and Core Peripheral Section
<> 150:02e0a0aed4ec 97 *****************************************************************************/
<> 150:02e0a0aed4ec 98 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 150:02e0a0aed4ec 99 #define __FPU_PRESENT 1 /**< Presence of FPU */
<> 150:02e0a0aed4ec 100 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 150:02e0a0aed4ec 101 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 150:02e0a0aed4ec 102 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 150:02e0a0aed4ec 103
<> 150:02e0a0aed4ec 104 /** @} End of group EFM32PG1B200F256IM48_Core */
<> 150:02e0a0aed4ec 105
<> 150:02e0a0aed4ec 106 /**************************************************************************//**
<> 150:02e0a0aed4ec 107 * @defgroup EFM32PG1B200F256IM48_Part EFM32PG1B200F256IM48 Part
<> 150:02e0a0aed4ec 108 * @{
<> 150:02e0a0aed4ec 109 ******************************************************************************/
<> 150:02e0a0aed4ec 110
<> 150:02e0a0aed4ec 111 /** Part family */
<> 161:2cc1468da177 112 #define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */
<> 161:2cc1468da177 113 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 161:2cc1468da177 114 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
<> 161:2cc1468da177 115 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
<> 161:2cc1468da177 116 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
<> 161:2cc1468da177 117 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
<> 161:2cc1468da177 118 #define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
<> 161:2cc1468da177 119 #define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
<> 161:2cc1468da177 120 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
<> 161:2cc1468da177 121 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
<> 161:2cc1468da177 122 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
<> 161:2cc1468da177 123 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
<> 150:02e0a0aed4ec 124
<> 150:02e0a0aed4ec 125 /* If part number is not defined as compiler option, define it */
<> 150:02e0a0aed4ec 126 #if !defined(EFM32PG1B200F256IM48)
<> 150:02e0a0aed4ec 127 #define EFM32PG1B200F256IM48 1 /**< PEARL Gecko Part */
<> 150:02e0a0aed4ec 128 #endif
<> 150:02e0a0aed4ec 129
<> 150:02e0a0aed4ec 130 /** Configure part number */
<> 150:02e0a0aed4ec 131 #define PART_NUMBER "EFM32PG1B200F256IM48" /**< Part Number */
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133 /** Memory Base addresses and limits */
<> 150:02e0a0aed4ec 134 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
<> 150:02e0a0aed4ec 135 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 150:02e0a0aed4ec 136 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
<> 161:2cc1468da177 137 #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
<> 150:02e0a0aed4ec 138 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 150:02e0a0aed4ec 139 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
<> 150:02e0a0aed4ec 140 #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
<> 161:2cc1468da177 141 #define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
<> 150:02e0a0aed4ec 142 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
<> 150:02e0a0aed4ec 143 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
<> 150:02e0a0aed4ec 144 #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
<> 161:2cc1468da177 145 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
<> 150:02e0a0aed4ec 146 #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
<> 150:02e0a0aed4ec 147 #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
<> 150:02e0a0aed4ec 148 #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
<> 161:2cc1468da177 149 #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
<> 150:02e0a0aed4ec 150 #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
<> 150:02e0a0aed4ec 151 #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
<> 150:02e0a0aed4ec 152 #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
<> 161:2cc1468da177 153 #define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
<> 150:02e0a0aed4ec 154 #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
<> 150:02e0a0aed4ec 155 #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
<> 150:02e0a0aed4ec 156 #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
<> 161:2cc1468da177 157 #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
<> 150:02e0a0aed4ec 158 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
<> 150:02e0a0aed4ec 159 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
<> 150:02e0a0aed4ec 160 #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
<> 161:2cc1468da177 161 #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
<> 150:02e0a0aed4ec 162 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 150:02e0a0aed4ec 163 #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
<> 150:02e0a0aed4ec 164 #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
<> 161:2cc1468da177 165 #define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
<> 150:02e0a0aed4ec 166 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 150:02e0a0aed4ec 167 #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
<> 150:02e0a0aed4ec 168 #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
<> 161:2cc1468da177 169 #define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
<> 150:02e0a0aed4ec 170
<> 150:02e0a0aed4ec 171 /** Bit banding area */
<> 150:02e0a0aed4ec 172 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 150:02e0a0aed4ec 173 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 150:02e0a0aed4ec 174
<> 150:02e0a0aed4ec 175 /** Flash and SRAM limits for EFM32PG1B200F256IM48 */
<> 150:02e0a0aed4ec 176 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 150:02e0a0aed4ec 177 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
<> 150:02e0a0aed4ec 178 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
<> 150:02e0a0aed4ec 179 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 150:02e0a0aed4ec 180 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
<> 150:02e0a0aed4ec 181 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
<> 150:02e0a0aed4ec 182 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 150:02e0a0aed4ec 183 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
<> 150:02e0a0aed4ec 184 #define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
<> 150:02e0a0aed4ec 185
<> 150:02e0a0aed4ec 186 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 150:02e0a0aed4ec 187 #define AFCHAN_MAX 72
<> 150:02e0a0aed4ec 188 #define AFCHANLOC_MAX 32
<> 150:02e0a0aed4ec 189 /** Analog AF channels */
<> 150:02e0a0aed4ec 190 #define AFACHAN_MAX 61
<> 150:02e0a0aed4ec 191
<> 150:02e0a0aed4ec 192 /* Part number capabilities */
<> 150:02e0a0aed4ec 193
<> 150:02e0a0aed4ec 194 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 150:02e0a0aed4ec 195 #define TIMER_COUNT 2 /**< 2 TIMERs available */
<> 150:02e0a0aed4ec 196 #define USART_PRESENT /**< USART is available in this part */
<> 150:02e0a0aed4ec 197 #define USART_COUNT 2 /**< 2 USARTs available */
<> 150:02e0a0aed4ec 198 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 150:02e0a0aed4ec 199 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
<> 150:02e0a0aed4ec 200 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 150:02e0a0aed4ec 201 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 150:02e0a0aed4ec 202 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 150:02e0a0aed4ec 203 #define PCNT_COUNT 1 /**< 1 PCNTs available */
<> 150:02e0a0aed4ec 204 #define I2C_PRESENT /**< I2C is available in this part */
<> 150:02e0a0aed4ec 205 #define I2C_COUNT 1 /**< 1 I2Cs available */
<> 150:02e0a0aed4ec 206 #define ADC_PRESENT /**< ADC is available in this part */
<> 150:02e0a0aed4ec 207 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 150:02e0a0aed4ec 208 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 150:02e0a0aed4ec 209 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 150:02e0a0aed4ec 210 #define IDAC_PRESENT /**< IDAC is available in this part */
<> 150:02e0a0aed4ec 211 #define IDAC_COUNT 1 /**< 1 IDACs available */
<> 150:02e0a0aed4ec 212 #define WDOG_PRESENT /**< WDOG is available in this part */
<> 150:02e0a0aed4ec 213 #define WDOG_COUNT 1 /**< 1 WDOGs available */
<> 150:02e0a0aed4ec 214 #define MSC_PRESENT
<> 150:02e0a0aed4ec 215 #define MSC_COUNT 1
<> 150:02e0a0aed4ec 216 #define EMU_PRESENT
<> 150:02e0a0aed4ec 217 #define EMU_COUNT 1
<> 150:02e0a0aed4ec 218 #define RMU_PRESENT
<> 150:02e0a0aed4ec 219 #define RMU_COUNT 1
<> 150:02e0a0aed4ec 220 #define CMU_PRESENT
<> 150:02e0a0aed4ec 221 #define CMU_COUNT 1
<> 150:02e0a0aed4ec 222 #define CRYPTO_PRESENT
<> 150:02e0a0aed4ec 223 #define CRYPTO_COUNT 1
<> 150:02e0a0aed4ec 224 #define GPIO_PRESENT
<> 150:02e0a0aed4ec 225 #define GPIO_COUNT 1
<> 150:02e0a0aed4ec 226 #define PRS_PRESENT
<> 150:02e0a0aed4ec 227 #define PRS_COUNT 1
<> 150:02e0a0aed4ec 228 #define LDMA_PRESENT
<> 150:02e0a0aed4ec 229 #define LDMA_COUNT 1
<> 150:02e0a0aed4ec 230 #define FPUEH_PRESENT
<> 150:02e0a0aed4ec 231 #define FPUEH_COUNT 1
<> 150:02e0a0aed4ec 232 #define GPCRC_PRESENT
<> 150:02e0a0aed4ec 233 #define GPCRC_COUNT 1
<> 150:02e0a0aed4ec 234 #define CRYOTIMER_PRESENT
<> 150:02e0a0aed4ec 235 #define CRYOTIMER_COUNT 1
<> 150:02e0a0aed4ec 236 #define RTCC_PRESENT
<> 150:02e0a0aed4ec 237 #define RTCC_COUNT 1
<> 150:02e0a0aed4ec 238 #define BOOTLOADER_PRESENT
<> 150:02e0a0aed4ec 239 #define BOOTLOADER_COUNT 1
<> 150:02e0a0aed4ec 240
<> 150:02e0a0aed4ec 241 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 150:02e0a0aed4ec 242 #include "system_efm32pg1b.h" /* System Header File */
<> 150:02e0a0aed4ec 243
<> 150:02e0a0aed4ec 244 /** @} End of group EFM32PG1B200F256IM48_Part */
<> 150:02e0a0aed4ec 245
<> 150:02e0a0aed4ec 246 /**************************************************************************//**
<> 150:02e0a0aed4ec 247 * @defgroup EFM32PG1B200F256IM48_Peripheral_TypeDefs EFM32PG1B200F256IM48 Peripheral TypeDefs
<> 150:02e0a0aed4ec 248 * @{
<> 150:02e0a0aed4ec 249 * @brief Device Specific Peripheral Register Structures
<> 150:02e0a0aed4ec 250 *****************************************************************************/
<> 150:02e0a0aed4ec 251
<> 150:02e0a0aed4ec 252 #include "efm32pg1b_msc.h"
<> 150:02e0a0aed4ec 253 #include "efm32pg1b_emu.h"
<> 150:02e0a0aed4ec 254 #include "efm32pg1b_rmu.h"
<> 150:02e0a0aed4ec 255 #include "efm32pg1b_cmu.h"
<> 150:02e0a0aed4ec 256 #include "efm32pg1b_crypto.h"
<> 150:02e0a0aed4ec 257 #include "efm32pg1b_gpio_p.h"
<> 150:02e0a0aed4ec 258 #include "efm32pg1b_gpio.h"
<> 150:02e0a0aed4ec 259 #include "efm32pg1b_prs_ch.h"
<> 150:02e0a0aed4ec 260 #include "efm32pg1b_prs.h"
<> 150:02e0a0aed4ec 261 #include "efm32pg1b_ldma_ch.h"
<> 150:02e0a0aed4ec 262 #include "efm32pg1b_ldma.h"
<> 150:02e0a0aed4ec 263 #include "efm32pg1b_fpueh.h"
<> 150:02e0a0aed4ec 264 #include "efm32pg1b_gpcrc.h"
<> 150:02e0a0aed4ec 265 #include "efm32pg1b_timer_cc.h"
<> 150:02e0a0aed4ec 266 #include "efm32pg1b_timer.h"
<> 150:02e0a0aed4ec 267 #include "efm32pg1b_usart.h"
<> 150:02e0a0aed4ec 268 #include "efm32pg1b_leuart.h"
<> 150:02e0a0aed4ec 269 #include "efm32pg1b_letimer.h"
<> 150:02e0a0aed4ec 270 #include "efm32pg1b_cryotimer.h"
<> 150:02e0a0aed4ec 271 #include "efm32pg1b_pcnt.h"
<> 150:02e0a0aed4ec 272 #include "efm32pg1b_i2c.h"
<> 150:02e0a0aed4ec 273 #include "efm32pg1b_adc.h"
<> 150:02e0a0aed4ec 274 #include "efm32pg1b_acmp.h"
<> 150:02e0a0aed4ec 275 #include "efm32pg1b_idac.h"
<> 150:02e0a0aed4ec 276 #include "efm32pg1b_rtcc_cc.h"
<> 150:02e0a0aed4ec 277 #include "efm32pg1b_rtcc_ret.h"
<> 150:02e0a0aed4ec 278 #include "efm32pg1b_rtcc.h"
<> 150:02e0a0aed4ec 279 #include "efm32pg1b_wdog_pch.h"
<> 150:02e0a0aed4ec 280 #include "efm32pg1b_wdog.h"
<> 150:02e0a0aed4ec 281 #include "efm32pg1b_dma_descriptor.h"
<> 150:02e0a0aed4ec 282 #include "efm32pg1b_devinfo.h"
<> 150:02e0a0aed4ec 283 #include "efm32pg1b_romtable.h"
<> 150:02e0a0aed4ec 284
<> 150:02e0a0aed4ec 285 /** @} End of group EFM32PG1B200F256IM48_Peripheral_TypeDefs */
<> 150:02e0a0aed4ec 286
<> 150:02e0a0aed4ec 287 /**************************************************************************//**
<> 150:02e0a0aed4ec 288 * @defgroup EFM32PG1B200F256IM48_Peripheral_Base EFM32PG1B200F256IM48 Peripheral Memory Map
<> 150:02e0a0aed4ec 289 * @{
<> 150:02e0a0aed4ec 290 *****************************************************************************/
<> 150:02e0a0aed4ec 291
<> 150:02e0a0aed4ec 292 #define MSC_BASE (0x400E0000UL) /**< MSC base address */
<> 150:02e0a0aed4ec 293 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
<> 150:02e0a0aed4ec 294 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
<> 150:02e0a0aed4ec 295 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
<> 150:02e0a0aed4ec 296 #define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
<> 150:02e0a0aed4ec 297 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
<> 150:02e0a0aed4ec 298 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
<> 150:02e0a0aed4ec 299 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
<> 150:02e0a0aed4ec 300 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
<> 150:02e0a0aed4ec 301 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
<> 150:02e0a0aed4ec 302 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
<> 150:02e0a0aed4ec 303 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
<> 150:02e0a0aed4ec 304 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
<> 150:02e0a0aed4ec 305 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
<> 150:02e0a0aed4ec 306 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
<> 150:02e0a0aed4ec 307 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
<> 150:02e0a0aed4ec 308 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
<> 150:02e0a0aed4ec 309 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
<> 150:02e0a0aed4ec 310 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
<> 150:02e0a0aed4ec 311 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 150:02e0a0aed4ec 312 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
<> 150:02e0a0aed4ec 313 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
<> 150:02e0a0aed4ec 314 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
<> 150:02e0a0aed4ec 315 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */
<> 150:02e0a0aed4ec 316 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
<> 150:02e0a0aed4ec 317 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 150:02e0a0aed4ec 318 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 150:02e0a0aed4ec 319 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 150:02e0a0aed4ec 320 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 150:02e0a0aed4ec 321
<> 150:02e0a0aed4ec 322 /** @} End of group EFM32PG1B200F256IM48_Peripheral_Base */
<> 150:02e0a0aed4ec 323
<> 150:02e0a0aed4ec 324 /**************************************************************************//**
<> 150:02e0a0aed4ec 325 * @defgroup EFM32PG1B200F256IM48_Peripheral_Declaration EFM32PG1B200F256IM48 Peripheral Declarations
<> 150:02e0a0aed4ec 326 * @{
<> 150:02e0a0aed4ec 327 *****************************************************************************/
<> 150:02e0a0aed4ec 328
<> 150:02e0a0aed4ec 329 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 150:02e0a0aed4ec 330 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 150:02e0a0aed4ec 331 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 150:02e0a0aed4ec 332 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 150:02e0a0aed4ec 333 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
<> 150:02e0a0aed4ec 334 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 150:02e0a0aed4ec 335 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 150:02e0a0aed4ec 336 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
<> 150:02e0a0aed4ec 337 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
<> 150:02e0a0aed4ec 338 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
<> 150:02e0a0aed4ec 339 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 150:02e0a0aed4ec 340 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 150:02e0a0aed4ec 341 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 150:02e0a0aed4ec 342 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 150:02e0a0aed4ec 343 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 150:02e0a0aed4ec 344 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 150:02e0a0aed4ec 345 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
<> 150:02e0a0aed4ec 346 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 150:02e0a0aed4ec 347 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 150:02e0a0aed4ec 348 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 150:02e0a0aed4ec 349 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 150:02e0a0aed4ec 350 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 150:02e0a0aed4ec 351 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
<> 150:02e0a0aed4ec 352 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
<> 150:02e0a0aed4ec 353 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
<> 150:02e0a0aed4ec 354 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 150:02e0a0aed4ec 355 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 150:02e0a0aed4ec 356
<> 150:02e0a0aed4ec 357 /** @} End of group EFM32PG1B200F256IM48_Peripheral_Declaration */
<> 150:02e0a0aed4ec 358
<> 150:02e0a0aed4ec 359 /**************************************************************************//**
<> 150:02e0a0aed4ec 360 * @defgroup EFM32PG1B200F256IM48_Peripheral_Offsets EFM32PG1B200F256IM48 Peripheral Offsets
<> 150:02e0a0aed4ec 361 * @{
<> 150:02e0a0aed4ec 362 *****************************************************************************/
<> 150:02e0a0aed4ec 363
<> 150:02e0a0aed4ec 364 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
<> 150:02e0a0aed4ec 365 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
<> 150:02e0a0aed4ec 366 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
<> 150:02e0a0aed4ec 367 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
<> 150:02e0a0aed4ec 368 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
<> 150:02e0a0aed4ec 369 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
<> 150:02e0a0aed4ec 370 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
<> 150:02e0a0aed4ec 371 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
<> 150:02e0a0aed4ec 372 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
<> 150:02e0a0aed4ec 373 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
<> 150:02e0a0aed4ec 374
<> 150:02e0a0aed4ec 375 /** @} End of group EFM32PG1B200F256IM48_Peripheral_Offsets */
<> 150:02e0a0aed4ec 376
<> 150:02e0a0aed4ec 377
<> 150:02e0a0aed4ec 378 /**************************************************************************//**
<> 150:02e0a0aed4ec 379 * @defgroup EFM32PG1B200F256IM48_BitFields EFM32PG1B200F256IM48 Bit Fields
<> 150:02e0a0aed4ec 380 * @{
<> 150:02e0a0aed4ec 381 *****************************************************************************/
<> 150:02e0a0aed4ec 382
<> 150:02e0a0aed4ec 383 #include "efm32pg1b_prs_signals.h"
<> 150:02e0a0aed4ec 384 #include "efm32pg1b_dmareq.h"
<> 150:02e0a0aed4ec 385
<> 150:02e0a0aed4ec 386 /**************************************************************************//**
<> 150:02e0a0aed4ec 387 * @defgroup EFM32PG1B200F256IM48_UNLOCK EFM32PG1B200F256IM48 Unlock Codes
<> 150:02e0a0aed4ec 388 * @{
<> 150:02e0a0aed4ec 389 *****************************************************************************/
<> 150:02e0a0aed4ec 390 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 150:02e0a0aed4ec 391 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 150:02e0a0aed4ec 392 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
<> 150:02e0a0aed4ec 393 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 150:02e0a0aed4ec 394 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 150:02e0a0aed4ec 395 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 150:02e0a0aed4ec 396 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
<> 150:02e0a0aed4ec 397
<> 150:02e0a0aed4ec 398 /** @} End of group EFM32PG1B200F256IM48_UNLOCK */
<> 150:02e0a0aed4ec 399
<> 150:02e0a0aed4ec 400 /** @} End of group EFM32PG1B200F256IM48_BitFields */
<> 150:02e0a0aed4ec 401
<> 150:02e0a0aed4ec 402 /**************************************************************************//**
<> 150:02e0a0aed4ec 403 * @defgroup EFM32PG1B200F256IM48_Alternate_Function EFM32PG1B200F256IM48 Alternate Function
<> 150:02e0a0aed4ec 404 * @{
<> 150:02e0a0aed4ec 405 *****************************************************************************/
<> 150:02e0a0aed4ec 406
<> 150:02e0a0aed4ec 407 #include "efm32pg1b_af_ports.h"
<> 150:02e0a0aed4ec 408 #include "efm32pg1b_af_pins.h"
<> 150:02e0a0aed4ec 409
<> 150:02e0a0aed4ec 410 /** @} End of group EFM32PG1B200F256IM48_Alternate_Function */
<> 150:02e0a0aed4ec 411
<> 150:02e0a0aed4ec 412 /**************************************************************************//**
<> 150:02e0a0aed4ec 413 * @brief Set the value of a bit field within a register.
<> 150:02e0a0aed4ec 414 *
<> 150:02e0a0aed4ec 415 * @param REG
<> 150:02e0a0aed4ec 416 * The register to update
<> 150:02e0a0aed4ec 417 * @param MASK
<> 150:02e0a0aed4ec 418 * The mask for the bit field to update
<> 150:02e0a0aed4ec 419 * @param VALUE
<> 150:02e0a0aed4ec 420 * The value to write to the bit field
<> 150:02e0a0aed4ec 421 * @param OFFSET
<> 150:02e0a0aed4ec 422 * The number of bits that the field is offset within the register.
<> 150:02e0a0aed4ec 423 * 0 (zero) means LSB.
<> 150:02e0a0aed4ec 424 *****************************************************************************/
<> 150:02e0a0aed4ec 425 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 150:02e0a0aed4ec 426 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 150:02e0a0aed4ec 427
<> 150:02e0a0aed4ec 428 /** @} End of group EFM32PG1B200F256IM48 */
<> 150:02e0a0aed4ec 429
<> 150:02e0a0aed4ec 430 /** @} End of group Parts */
<> 150:02e0a0aed4ec 431
<> 150:02e0a0aed4ec 432 #ifdef __cplusplus
<> 150:02e0a0aed4ec 433 }
<> 150:02e0a0aed4ec 434 #endif
<> 150:02e0a0aed4ec 435 #endif /* EFM32PG1B200F256IM48_H */