mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/efm32gg11b_uart.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 187:0387e8f68319 1 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 2 * @file efm32gg11b_uart.h
AnnaBridge 187:0387e8f68319 3 * @brief EFM32GG11B_UART register and bit field definitions
AnnaBridge 187:0387e8f68319 4 * @version 5.3.2
AnnaBridge 187:0387e8f68319 5 ******************************************************************************
AnnaBridge 187:0387e8f68319 6 * # License
AnnaBridge 187:0387e8f68319 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 187:0387e8f68319 8 ******************************************************************************
AnnaBridge 187:0387e8f68319 9 *
AnnaBridge 187:0387e8f68319 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 187:0387e8f68319 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 187:0387e8f68319 12 * freely, subject to the following restrictions:
AnnaBridge 187:0387e8f68319 13 *
AnnaBridge 187:0387e8f68319 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 187:0387e8f68319 15 * claim that you wrote the original software.@n
AnnaBridge 187:0387e8f68319 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 187:0387e8f68319 17 * misrepresented as being the original software.@n
AnnaBridge 187:0387e8f68319 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 187:0387e8f68319 19 *
AnnaBridge 187:0387e8f68319 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 187:0387e8f68319 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 187:0387e8f68319 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 187:0387e8f68319 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 187:0387e8f68319 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 187:0387e8f68319 25 * infringement of any proprietary rights of a third party.
AnnaBridge 187:0387e8f68319 26 *
AnnaBridge 187:0387e8f68319 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 187:0387e8f68319 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 187:0387e8f68319 29 * any third party, arising from your use of this Software.
AnnaBridge 187:0387e8f68319 30 *
AnnaBridge 187:0387e8f68319 31 *****************************************************************************/
AnnaBridge 187:0387e8f68319 32
AnnaBridge 187:0387e8f68319 33 #if defined(__ICCARM__)
AnnaBridge 187:0387e8f68319 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 187:0387e8f68319 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 187:0387e8f68319 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 187:0387e8f68319 37 #endif
AnnaBridge 187:0387e8f68319 38
AnnaBridge 187:0387e8f68319 39 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 40 * @addtogroup Parts
AnnaBridge 187:0387e8f68319 41 * @{
AnnaBridge 187:0387e8f68319 42 ******************************************************************************/
AnnaBridge 187:0387e8f68319 43
AnnaBridge 187:0387e8f68319 44 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 45 * @addtogroup EFM32GG11B_UART
AnnaBridge 187:0387e8f68319 46 * @{
AnnaBridge 187:0387e8f68319 47 * @defgroup EFM32GG11B_UART_BitFields UART Bit Fields
AnnaBridge 187:0387e8f68319 48 * @{
AnnaBridge 187:0387e8f68319 49 *****************************************************************************/
AnnaBridge 187:0387e8f68319 50
AnnaBridge 187:0387e8f68319 51 /* Bit fields for UART CTRL */
AnnaBridge 187:0387e8f68319 52 #define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */
AnnaBridge 187:0387e8f68319 53 #define _UART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for UART_CTRL */
AnnaBridge 187:0387e8f68319 54 #define UART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
AnnaBridge 187:0387e8f68319 55 #define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
AnnaBridge 187:0387e8f68319 56 #define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
AnnaBridge 187:0387e8f68319 57 #define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 58 #define UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 59 #define UART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
AnnaBridge 187:0387e8f68319 60 #define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
AnnaBridge 187:0387e8f68319 61 #define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
AnnaBridge 187:0387e8f68319 62 #define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 63 #define UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 64 #define UART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
AnnaBridge 187:0387e8f68319 65 #define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
AnnaBridge 187:0387e8f68319 66 #define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
AnnaBridge 187:0387e8f68319 67 #define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 68 #define UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 69 #define UART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
AnnaBridge 187:0387e8f68319 70 #define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
AnnaBridge 187:0387e8f68319 71 #define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
AnnaBridge 187:0387e8f68319 72 #define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 73 #define UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 74 #define UART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
AnnaBridge 187:0387e8f68319 75 #define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
AnnaBridge 187:0387e8f68319 76 #define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
AnnaBridge 187:0387e8f68319 77 #define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 78 #define UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 79 #define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
AnnaBridge 187:0387e8f68319 80 #define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
AnnaBridge 187:0387e8f68319 81 #define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 82 #define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */
AnnaBridge 187:0387e8f68319 83 #define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */
AnnaBridge 187:0387e8f68319 84 #define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */
AnnaBridge 187:0387e8f68319 85 #define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */
AnnaBridge 187:0387e8f68319 86 #define UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 87 #define UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for UART_CTRL */
AnnaBridge 187:0387e8f68319 88 #define UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for UART_CTRL */
AnnaBridge 187:0387e8f68319 89 #define UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for UART_CTRL */
AnnaBridge 187:0387e8f68319 90 #define UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for UART_CTRL */
AnnaBridge 187:0387e8f68319 91 #define UART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
AnnaBridge 187:0387e8f68319 92 #define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
AnnaBridge 187:0387e8f68319 93 #define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
AnnaBridge 187:0387e8f68319 94 #define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 95 #define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */
AnnaBridge 187:0387e8f68319 96 #define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */
AnnaBridge 187:0387e8f68319 97 #define UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 98 #define UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for UART_CTRL */
AnnaBridge 187:0387e8f68319 99 #define UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */
AnnaBridge 187:0387e8f68319 100 #define UART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
AnnaBridge 187:0387e8f68319 101 #define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
AnnaBridge 187:0387e8f68319 102 #define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
AnnaBridge 187:0387e8f68319 103 #define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 104 #define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */
AnnaBridge 187:0387e8f68319 105 #define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */
AnnaBridge 187:0387e8f68319 106 #define UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 107 #define UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */
AnnaBridge 187:0387e8f68319 108 #define UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */
AnnaBridge 187:0387e8f68319 109 #define UART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
AnnaBridge 187:0387e8f68319 110 #define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
AnnaBridge 187:0387e8f68319 111 #define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
AnnaBridge 187:0387e8f68319 112 #define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 113 #define UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 114 #define UART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
AnnaBridge 187:0387e8f68319 115 #define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
AnnaBridge 187:0387e8f68319 116 #define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
AnnaBridge 187:0387e8f68319 117 #define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 118 #define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */
AnnaBridge 187:0387e8f68319 119 #define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */
AnnaBridge 187:0387e8f68319 120 #define UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 121 #define UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for UART_CTRL */
AnnaBridge 187:0387e8f68319 122 #define UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */
AnnaBridge 187:0387e8f68319 123 #define UART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
AnnaBridge 187:0387e8f68319 124 #define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
AnnaBridge 187:0387e8f68319 125 #define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
AnnaBridge 187:0387e8f68319 126 #define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 127 #define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */
AnnaBridge 187:0387e8f68319 128 #define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */
AnnaBridge 187:0387e8f68319 129 #define UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 130 #define UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for UART_CTRL */
AnnaBridge 187:0387e8f68319 131 #define UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for UART_CTRL */
AnnaBridge 187:0387e8f68319 132 #define UART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
AnnaBridge 187:0387e8f68319 133 #define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
AnnaBridge 187:0387e8f68319 134 #define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
AnnaBridge 187:0387e8f68319 135 #define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 136 #define UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 137 #define UART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
AnnaBridge 187:0387e8f68319 138 #define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
AnnaBridge 187:0387e8f68319 139 #define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
AnnaBridge 187:0387e8f68319 140 #define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 141 #define UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 142 #define UART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
AnnaBridge 187:0387e8f68319 143 #define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
AnnaBridge 187:0387e8f68319 144 #define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
AnnaBridge 187:0387e8f68319 145 #define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 146 #define UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 147 #define UART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
AnnaBridge 187:0387e8f68319 148 #define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
AnnaBridge 187:0387e8f68319 149 #define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
AnnaBridge 187:0387e8f68319 150 #define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 151 #define UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 152 #define UART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
AnnaBridge 187:0387e8f68319 153 #define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
AnnaBridge 187:0387e8f68319 154 #define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
AnnaBridge 187:0387e8f68319 155 #define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 156 #define UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 157 #define UART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
AnnaBridge 187:0387e8f68319 158 #define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
AnnaBridge 187:0387e8f68319 159 #define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
AnnaBridge 187:0387e8f68319 160 #define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 161 #define UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 162 #define UART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
AnnaBridge 187:0387e8f68319 163 #define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
AnnaBridge 187:0387e8f68319 164 #define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
AnnaBridge 187:0387e8f68319 165 #define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 166 #define UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 167 #define UART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
AnnaBridge 187:0387e8f68319 168 #define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
AnnaBridge 187:0387e8f68319 169 #define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
AnnaBridge 187:0387e8f68319 170 #define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 171 #define UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 172 #define UART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
AnnaBridge 187:0387e8f68319 173 #define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
AnnaBridge 187:0387e8f68319 174 #define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
AnnaBridge 187:0387e8f68319 175 #define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 176 #define UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 177 #define UART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
AnnaBridge 187:0387e8f68319 178 #define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
AnnaBridge 187:0387e8f68319 179 #define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
AnnaBridge 187:0387e8f68319 180 #define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 181 #define UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 182 #define UART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
AnnaBridge 187:0387e8f68319 183 #define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
AnnaBridge 187:0387e8f68319 184 #define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
AnnaBridge 187:0387e8f68319 185 #define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 186 #define UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 187 #define UART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
AnnaBridge 187:0387e8f68319 188 #define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
AnnaBridge 187:0387e8f68319 189 #define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
AnnaBridge 187:0387e8f68319 190 #define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 191 #define UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 192 #define UART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
AnnaBridge 187:0387e8f68319 193 #define _UART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
AnnaBridge 187:0387e8f68319 194 #define _UART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
AnnaBridge 187:0387e8f68319 195 #define _UART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 196 #define UART_CTRL_SSSEARLY_DEFAULT (_UART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 197 #define UART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
AnnaBridge 187:0387e8f68319 198 #define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
AnnaBridge 187:0387e8f68319 199 #define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
AnnaBridge 187:0387e8f68319 200 #define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 201 #define UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 202 #define UART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
AnnaBridge 187:0387e8f68319 203 #define _UART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
AnnaBridge 187:0387e8f68319 204 #define _UART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
AnnaBridge 187:0387e8f68319 205 #define _UART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 206 #define UART_CTRL_AUTOTX_DEFAULT (_UART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 207 #define UART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
AnnaBridge 187:0387e8f68319 208 #define _UART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
AnnaBridge 187:0387e8f68319 209 #define _UART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
AnnaBridge 187:0387e8f68319 210 #define _UART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 211 #define UART_CTRL_MVDIS_DEFAULT (_UART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 212 #define UART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
AnnaBridge 187:0387e8f68319 213 #define _UART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
AnnaBridge 187:0387e8f68319 214 #define _UART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
AnnaBridge 187:0387e8f68319 215 #define _UART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 216 #define UART_CTRL_SMSDELAY_DEFAULT (_UART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_CTRL */
AnnaBridge 187:0387e8f68319 217
AnnaBridge 187:0387e8f68319 218 /* Bit fields for UART FRAME */
AnnaBridge 187:0387e8f68319 219 #define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */
AnnaBridge 187:0387e8f68319 220 #define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */
AnnaBridge 187:0387e8f68319 221 #define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
AnnaBridge 187:0387e8f68319 222 #define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
AnnaBridge 187:0387e8f68319 223 #define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */
AnnaBridge 187:0387e8f68319 224 #define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */
AnnaBridge 187:0387e8f68319 225 #define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */
AnnaBridge 187:0387e8f68319 226 #define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 227 #define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */
AnnaBridge 187:0387e8f68319 228 #define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */
AnnaBridge 187:0387e8f68319 229 #define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */
AnnaBridge 187:0387e8f68319 230 #define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 231 #define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 232 #define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */
AnnaBridge 187:0387e8f68319 233 #define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 234 #define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 235 #define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 236 #define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 237 #define UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for UART_FRAME */
AnnaBridge 187:0387e8f68319 238 #define UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for UART_FRAME */
AnnaBridge 187:0387e8f68319 239 #define UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for UART_FRAME */
AnnaBridge 187:0387e8f68319 240 #define UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 241 #define UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_FRAME */
AnnaBridge 187:0387e8f68319 242 #define UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for UART_FRAME */
AnnaBridge 187:0387e8f68319 243 #define UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for UART_FRAME */
AnnaBridge 187:0387e8f68319 244 #define UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 245 #define UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 246 #define UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for UART_FRAME */
AnnaBridge 187:0387e8f68319 247 #define UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 248 #define UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 249 #define UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 250 #define UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 251 #define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
AnnaBridge 187:0387e8f68319 252 #define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
AnnaBridge 187:0387e8f68319 253 #define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */
AnnaBridge 187:0387e8f68319 254 #define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */
AnnaBridge 187:0387e8f68319 255 #define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 256 #define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */
AnnaBridge 187:0387e8f68319 257 #define UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_FRAME */
AnnaBridge 187:0387e8f68319 258 #define UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for UART_FRAME */
AnnaBridge 187:0387e8f68319 259 #define UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for UART_FRAME */
AnnaBridge 187:0387e8f68319 260 #define UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for UART_FRAME */
AnnaBridge 187:0387e8f68319 261 #define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
AnnaBridge 187:0387e8f68319 262 #define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
AnnaBridge 187:0387e8f68319 263 #define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */
AnnaBridge 187:0387e8f68319 264 #define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */
AnnaBridge 187:0387e8f68319 265 #define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */
AnnaBridge 187:0387e8f68319 266 #define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */
AnnaBridge 187:0387e8f68319 267 #define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */
AnnaBridge 187:0387e8f68319 268 #define UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for UART_FRAME */
AnnaBridge 187:0387e8f68319 269 #define UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_FRAME */
AnnaBridge 187:0387e8f68319 270 #define UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for UART_FRAME */
AnnaBridge 187:0387e8f68319 271 #define UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */
AnnaBridge 187:0387e8f68319 272 #define UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for UART_FRAME */
AnnaBridge 187:0387e8f68319 273
AnnaBridge 187:0387e8f68319 274 /* Bit fields for UART TRIGCTRL */
AnnaBridge 187:0387e8f68319 275 #define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 276 #define _UART_TRIGCTRL_MASK 0x001F1FF0UL /**< Mask for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 277 #define UART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
AnnaBridge 187:0387e8f68319 278 #define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
AnnaBridge 187:0387e8f68319 279 #define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
AnnaBridge 187:0387e8f68319 280 #define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 281 #define UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 282 #define UART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
AnnaBridge 187:0387e8f68319 283 #define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
AnnaBridge 187:0387e8f68319 284 #define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
AnnaBridge 187:0387e8f68319 285 #define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 286 #define UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 287 #define UART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
AnnaBridge 187:0387e8f68319 288 #define _UART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
AnnaBridge 187:0387e8f68319 289 #define _UART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
AnnaBridge 187:0387e8f68319 290 #define _UART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 291 #define UART_TRIGCTRL_AUTOTXTEN_DEFAULT (_UART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 292 #define UART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */
AnnaBridge 187:0387e8f68319 293 #define _UART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
AnnaBridge 187:0387e8f68319 294 #define _UART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
AnnaBridge 187:0387e8f68319 295 #define _UART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 296 #define UART_TRIGCTRL_TXARX0EN_DEFAULT (_UART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 297 #define UART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */
AnnaBridge 187:0387e8f68319 298 #define _UART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
AnnaBridge 187:0387e8f68319 299 #define _UART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
AnnaBridge 187:0387e8f68319 300 #define _UART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 301 #define UART_TRIGCTRL_TXARX1EN_DEFAULT (_UART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 302 #define UART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */
AnnaBridge 187:0387e8f68319 303 #define _UART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
AnnaBridge 187:0387e8f68319 304 #define _UART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
AnnaBridge 187:0387e8f68319 305 #define _UART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 306 #define UART_TRIGCTRL_TXARX2EN_DEFAULT (_UART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 307 #define UART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */
AnnaBridge 187:0387e8f68319 308 #define _UART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
AnnaBridge 187:0387e8f68319 309 #define _UART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
AnnaBridge 187:0387e8f68319 310 #define _UART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 311 #define UART_TRIGCTRL_RXATX0EN_DEFAULT (_UART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 312 #define UART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */
AnnaBridge 187:0387e8f68319 313 #define _UART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
AnnaBridge 187:0387e8f68319 314 #define _UART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
AnnaBridge 187:0387e8f68319 315 #define _UART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 316 #define UART_TRIGCTRL_RXATX1EN_DEFAULT (_UART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 317 #define UART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */
AnnaBridge 187:0387e8f68319 318 #define _UART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
AnnaBridge 187:0387e8f68319 319 #define _UART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
AnnaBridge 187:0387e8f68319 320 #define _UART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 321 #define UART_TRIGCTRL_RXATX2EN_DEFAULT (_UART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 322 #define _UART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */
AnnaBridge 187:0387e8f68319 323 #define _UART_TRIGCTRL_TSEL_MASK 0x1F0000UL /**< Bit mask for USART_TSEL */
AnnaBridge 187:0387e8f68319 324 #define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 325 #define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 326 #define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 327 #define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 328 #define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 329 #define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 330 #define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 331 #define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 332 #define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 333 #define _UART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 334 #define _UART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 335 #define _UART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 336 #define _UART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 337 #define _UART_TRIGCTRL_TSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 338 #define _UART_TRIGCTRL_TSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 339 #define _UART_TRIGCTRL_TSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 340 #define _UART_TRIGCTRL_TSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 341 #define _UART_TRIGCTRL_TSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 342 #define _UART_TRIGCTRL_TSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 343 #define _UART_TRIGCTRL_TSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 344 #define _UART_TRIGCTRL_TSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 345 #define _UART_TRIGCTRL_TSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 346 #define _UART_TRIGCTRL_TSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 347 #define _UART_TRIGCTRL_TSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 348 #define _UART_TRIGCTRL_TSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 349 #define UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 350 #define UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 351 #define UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 352 #define UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 353 #define UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 354 #define UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 355 #define UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 356 #define UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 357 #define UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 358 #define UART_TRIGCTRL_TSEL_PRSCH8 (_UART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 359 #define UART_TRIGCTRL_TSEL_PRSCH9 (_UART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 360 #define UART_TRIGCTRL_TSEL_PRSCH10 (_UART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 361 #define UART_TRIGCTRL_TSEL_PRSCH11 (_UART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 362 #define UART_TRIGCTRL_TSEL_PRSCH12 (_UART_TRIGCTRL_TSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 363 #define UART_TRIGCTRL_TSEL_PRSCH13 (_UART_TRIGCTRL_TSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 364 #define UART_TRIGCTRL_TSEL_PRSCH14 (_UART_TRIGCTRL_TSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 365 #define UART_TRIGCTRL_TSEL_PRSCH15 (_UART_TRIGCTRL_TSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 366 #define UART_TRIGCTRL_TSEL_PRSCH16 (_UART_TRIGCTRL_TSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 367 #define UART_TRIGCTRL_TSEL_PRSCH17 (_UART_TRIGCTRL_TSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 368 #define UART_TRIGCTRL_TSEL_PRSCH18 (_UART_TRIGCTRL_TSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 369 #define UART_TRIGCTRL_TSEL_PRSCH19 (_UART_TRIGCTRL_TSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 370 #define UART_TRIGCTRL_TSEL_PRSCH20 (_UART_TRIGCTRL_TSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 371 #define UART_TRIGCTRL_TSEL_PRSCH21 (_UART_TRIGCTRL_TSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 372 #define UART_TRIGCTRL_TSEL_PRSCH22 (_UART_TRIGCTRL_TSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 373 #define UART_TRIGCTRL_TSEL_PRSCH23 (_UART_TRIGCTRL_TSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for UART_TRIGCTRL */
AnnaBridge 187:0387e8f68319 374
AnnaBridge 187:0387e8f68319 375 /* Bit fields for UART CMD */
AnnaBridge 187:0387e8f68319 376 #define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */
AnnaBridge 187:0387e8f68319 377 #define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */
AnnaBridge 187:0387e8f68319 378 #define UART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
AnnaBridge 187:0387e8f68319 379 #define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
AnnaBridge 187:0387e8f68319 380 #define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
AnnaBridge 187:0387e8f68319 381 #define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 382 #define UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 383 #define UART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
AnnaBridge 187:0387e8f68319 384 #define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
AnnaBridge 187:0387e8f68319 385 #define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
AnnaBridge 187:0387e8f68319 386 #define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 387 #define UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 388 #define UART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
AnnaBridge 187:0387e8f68319 389 #define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
AnnaBridge 187:0387e8f68319 390 #define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
AnnaBridge 187:0387e8f68319 391 #define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 392 #define UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 393 #define UART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
AnnaBridge 187:0387e8f68319 394 #define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
AnnaBridge 187:0387e8f68319 395 #define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
AnnaBridge 187:0387e8f68319 396 #define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 397 #define UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 398 #define UART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
AnnaBridge 187:0387e8f68319 399 #define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
AnnaBridge 187:0387e8f68319 400 #define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
AnnaBridge 187:0387e8f68319 401 #define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 402 #define UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 403 #define UART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
AnnaBridge 187:0387e8f68319 404 #define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
AnnaBridge 187:0387e8f68319 405 #define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
AnnaBridge 187:0387e8f68319 406 #define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 407 #define UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 408 #define UART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
AnnaBridge 187:0387e8f68319 409 #define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
AnnaBridge 187:0387e8f68319 410 #define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
AnnaBridge 187:0387e8f68319 411 #define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 412 #define UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 413 #define UART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
AnnaBridge 187:0387e8f68319 414 #define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
AnnaBridge 187:0387e8f68319 415 #define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
AnnaBridge 187:0387e8f68319 416 #define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 417 #define UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 418 #define UART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
AnnaBridge 187:0387e8f68319 419 #define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
AnnaBridge 187:0387e8f68319 420 #define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
AnnaBridge 187:0387e8f68319 421 #define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 422 #define UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 423 #define UART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
AnnaBridge 187:0387e8f68319 424 #define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
AnnaBridge 187:0387e8f68319 425 #define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
AnnaBridge 187:0387e8f68319 426 #define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 427 #define UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 428 #define UART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
AnnaBridge 187:0387e8f68319 429 #define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
AnnaBridge 187:0387e8f68319 430 #define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
AnnaBridge 187:0387e8f68319 431 #define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 432 #define UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 433 #define UART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
AnnaBridge 187:0387e8f68319 434 #define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
AnnaBridge 187:0387e8f68319 435 #define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
AnnaBridge 187:0387e8f68319 436 #define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 437 #define UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CMD */
AnnaBridge 187:0387e8f68319 438
AnnaBridge 187:0387e8f68319 439 /* Bit fields for UART STATUS */
AnnaBridge 187:0387e8f68319 440 #define _UART_STATUS_RESETVALUE 0x00002040UL /**< Default value for UART_STATUS */
AnnaBridge 187:0387e8f68319 441 #define _UART_STATUS_MASK 0x00037FFFUL /**< Mask for UART_STATUS */
AnnaBridge 187:0387e8f68319 442 #define UART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
AnnaBridge 187:0387e8f68319 443 #define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
AnnaBridge 187:0387e8f68319 444 #define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
AnnaBridge 187:0387e8f68319 445 #define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 446 #define UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 447 #define UART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
AnnaBridge 187:0387e8f68319 448 #define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
AnnaBridge 187:0387e8f68319 449 #define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
AnnaBridge 187:0387e8f68319 450 #define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 451 #define UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 452 #define UART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
AnnaBridge 187:0387e8f68319 453 #define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
AnnaBridge 187:0387e8f68319 454 #define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
AnnaBridge 187:0387e8f68319 455 #define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 456 #define UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 457 #define UART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
AnnaBridge 187:0387e8f68319 458 #define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
AnnaBridge 187:0387e8f68319 459 #define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
AnnaBridge 187:0387e8f68319 460 #define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 461 #define UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 462 #define UART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
AnnaBridge 187:0387e8f68319 463 #define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
AnnaBridge 187:0387e8f68319 464 #define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
AnnaBridge 187:0387e8f68319 465 #define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 466 #define UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 467 #define UART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
AnnaBridge 187:0387e8f68319 468 #define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
AnnaBridge 187:0387e8f68319 469 #define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
AnnaBridge 187:0387e8f68319 470 #define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 471 #define UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 472 #define UART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
AnnaBridge 187:0387e8f68319 473 #define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
AnnaBridge 187:0387e8f68319 474 #define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
AnnaBridge 187:0387e8f68319 475 #define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 476 #define UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 477 #define UART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
AnnaBridge 187:0387e8f68319 478 #define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
AnnaBridge 187:0387e8f68319 479 #define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
AnnaBridge 187:0387e8f68319 480 #define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 481 #define UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 482 #define UART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
AnnaBridge 187:0387e8f68319 483 #define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
AnnaBridge 187:0387e8f68319 484 #define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
AnnaBridge 187:0387e8f68319 485 #define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 486 #define UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 487 #define UART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
AnnaBridge 187:0387e8f68319 488 #define _UART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
AnnaBridge 187:0387e8f68319 489 #define _UART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
AnnaBridge 187:0387e8f68319 490 #define _UART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 491 #define UART_STATUS_TXBDRIGHT_DEFAULT (_UART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 492 #define UART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
AnnaBridge 187:0387e8f68319 493 #define _UART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
AnnaBridge 187:0387e8f68319 494 #define _UART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
AnnaBridge 187:0387e8f68319 495 #define _UART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 496 #define UART_STATUS_TXBSRIGHT_DEFAULT (_UART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 497 #define UART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
AnnaBridge 187:0387e8f68319 498 #define _UART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
AnnaBridge 187:0387e8f68319 499 #define _UART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
AnnaBridge 187:0387e8f68319 500 #define _UART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 501 #define UART_STATUS_RXDATAVRIGHT_DEFAULT (_UART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 502 #define UART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
AnnaBridge 187:0387e8f68319 503 #define _UART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
AnnaBridge 187:0387e8f68319 504 #define _UART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
AnnaBridge 187:0387e8f68319 505 #define _UART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 506 #define UART_STATUS_RXFULLRIGHT_DEFAULT (_UART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 507 #define UART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
AnnaBridge 187:0387e8f68319 508 #define _UART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 509 #define _UART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 510 #define _UART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 511 #define UART_STATUS_TXIDLE_DEFAULT (_UART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 512 #define UART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */
AnnaBridge 187:0387e8f68319 513 #define _UART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
AnnaBridge 187:0387e8f68319 514 #define _UART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
AnnaBridge 187:0387e8f68319 515 #define _UART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 516 #define UART_STATUS_TIMERRESTARTED_DEFAULT (_UART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 517 #define _UART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */
AnnaBridge 187:0387e8f68319 518 #define _UART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */
AnnaBridge 187:0387e8f68319 519 #define _UART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 520 #define UART_STATUS_TXBUFCNT_DEFAULT (_UART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_STATUS */
AnnaBridge 187:0387e8f68319 521
AnnaBridge 187:0387e8f68319 522 /* Bit fields for UART CLKDIV */
AnnaBridge 187:0387e8f68319 523 #define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */
AnnaBridge 187:0387e8f68319 524 #define _UART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for UART_CLKDIV */
AnnaBridge 187:0387e8f68319 525 #define _UART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */
AnnaBridge 187:0387e8f68319 526 #define _UART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
AnnaBridge 187:0387e8f68319 527 #define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */
AnnaBridge 187:0387e8f68319 528 #define UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CLKDIV */
AnnaBridge 187:0387e8f68319 529 #define UART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
AnnaBridge 187:0387e8f68319 530 #define _UART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
AnnaBridge 187:0387e8f68319 531 #define _UART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
AnnaBridge 187:0387e8f68319 532 #define _UART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */
AnnaBridge 187:0387e8f68319 533 #define UART_CLKDIV_AUTOBAUDEN_DEFAULT (_UART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_CLKDIV */
AnnaBridge 187:0387e8f68319 534
AnnaBridge 187:0387e8f68319 535 /* Bit fields for UART RXDATAX */
AnnaBridge 187:0387e8f68319 536 #define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 537 #define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 538 #define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
AnnaBridge 187:0387e8f68319 539 #define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
AnnaBridge 187:0387e8f68319 540 #define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 541 #define UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 542 #define UART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
AnnaBridge 187:0387e8f68319 543 #define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
AnnaBridge 187:0387e8f68319 544 #define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
AnnaBridge 187:0387e8f68319 545 #define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 546 #define UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 547 #define UART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
AnnaBridge 187:0387e8f68319 548 #define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
AnnaBridge 187:0387e8f68319 549 #define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
AnnaBridge 187:0387e8f68319 550 #define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 551 #define UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */
AnnaBridge 187:0387e8f68319 552
AnnaBridge 187:0387e8f68319 553 /* Bit fields for UART RXDATA */
AnnaBridge 187:0387e8f68319 554 #define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */
AnnaBridge 187:0387e8f68319 555 #define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */
AnnaBridge 187:0387e8f68319 556 #define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
AnnaBridge 187:0387e8f68319 557 #define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
AnnaBridge 187:0387e8f68319 558 #define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */
AnnaBridge 187:0387e8f68319 559 #define UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATA */
AnnaBridge 187:0387e8f68319 560
AnnaBridge 187:0387e8f68319 561 /* Bit fields for UART RXDOUBLEX */
AnnaBridge 187:0387e8f68319 562 #define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 563 #define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 564 #define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
AnnaBridge 187:0387e8f68319 565 #define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
AnnaBridge 187:0387e8f68319 566 #define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 567 #define UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 568 #define UART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
AnnaBridge 187:0387e8f68319 569 #define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
AnnaBridge 187:0387e8f68319 570 #define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
AnnaBridge 187:0387e8f68319 571 #define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 572 #define UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 573 #define UART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
AnnaBridge 187:0387e8f68319 574 #define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
AnnaBridge 187:0387e8f68319 575 #define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
AnnaBridge 187:0387e8f68319 576 #define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 577 #define UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 578 #define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
AnnaBridge 187:0387e8f68319 579 #define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
AnnaBridge 187:0387e8f68319 580 #define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 581 #define UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 582 #define UART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
AnnaBridge 187:0387e8f68319 583 #define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
AnnaBridge 187:0387e8f68319 584 #define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
AnnaBridge 187:0387e8f68319 585 #define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 586 #define UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 587 #define UART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
AnnaBridge 187:0387e8f68319 588 #define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
AnnaBridge 187:0387e8f68319 589 #define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
AnnaBridge 187:0387e8f68319 590 #define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 591 #define UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
AnnaBridge 187:0387e8f68319 592
AnnaBridge 187:0387e8f68319 593 /* Bit fields for UART RXDOUBLE */
AnnaBridge 187:0387e8f68319 594 #define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */
AnnaBridge 187:0387e8f68319 595 #define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */
AnnaBridge 187:0387e8f68319 596 #define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
AnnaBridge 187:0387e8f68319 597 #define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
AnnaBridge 187:0387e8f68319 598 #define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
AnnaBridge 187:0387e8f68319 599 #define UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
AnnaBridge 187:0387e8f68319 600 #define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
AnnaBridge 187:0387e8f68319 601 #define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
AnnaBridge 187:0387e8f68319 602 #define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
AnnaBridge 187:0387e8f68319 603 #define UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
AnnaBridge 187:0387e8f68319 604
AnnaBridge 187:0387e8f68319 605 /* Bit fields for UART RXDATAXP */
AnnaBridge 187:0387e8f68319 606 #define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 607 #define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 608 #define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
AnnaBridge 187:0387e8f68319 609 #define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
AnnaBridge 187:0387e8f68319 610 #define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 611 #define UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 612 #define UART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
AnnaBridge 187:0387e8f68319 613 #define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
AnnaBridge 187:0387e8f68319 614 #define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
AnnaBridge 187:0387e8f68319 615 #define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 616 #define UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 617 #define UART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
AnnaBridge 187:0387e8f68319 618 #define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
AnnaBridge 187:0387e8f68319 619 #define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
AnnaBridge 187:0387e8f68319 620 #define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 621 #define UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */
AnnaBridge 187:0387e8f68319 622
AnnaBridge 187:0387e8f68319 623 /* Bit fields for UART RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 624 #define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 625 #define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 626 #define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
AnnaBridge 187:0387e8f68319 627 #define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
AnnaBridge 187:0387e8f68319 628 #define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 629 #define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 630 #define UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
AnnaBridge 187:0387e8f68319 631 #define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
AnnaBridge 187:0387e8f68319 632 #define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
AnnaBridge 187:0387e8f68319 633 #define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 634 #define UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 635 #define UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
AnnaBridge 187:0387e8f68319 636 #define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
AnnaBridge 187:0387e8f68319 637 #define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
AnnaBridge 187:0387e8f68319 638 #define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 639 #define UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 640 #define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
AnnaBridge 187:0387e8f68319 641 #define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
AnnaBridge 187:0387e8f68319 642 #define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 643 #define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 644 #define UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
AnnaBridge 187:0387e8f68319 645 #define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
AnnaBridge 187:0387e8f68319 646 #define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
AnnaBridge 187:0387e8f68319 647 #define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 648 #define UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 649 #define UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
AnnaBridge 187:0387e8f68319 650 #define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
AnnaBridge 187:0387e8f68319 651 #define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
AnnaBridge 187:0387e8f68319 652 #define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 653 #define UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
AnnaBridge 187:0387e8f68319 654
AnnaBridge 187:0387e8f68319 655 /* Bit fields for UART TXDATAX */
AnnaBridge 187:0387e8f68319 656 #define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 657 #define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 658 #define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
AnnaBridge 187:0387e8f68319 659 #define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
AnnaBridge 187:0387e8f68319 660 #define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 661 #define UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 662 #define UART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
AnnaBridge 187:0387e8f68319 663 #define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
AnnaBridge 187:0387e8f68319 664 #define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
AnnaBridge 187:0387e8f68319 665 #define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 666 #define UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 667 #define UART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
AnnaBridge 187:0387e8f68319 668 #define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
AnnaBridge 187:0387e8f68319 669 #define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
AnnaBridge 187:0387e8f68319 670 #define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 671 #define UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 672 #define UART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
AnnaBridge 187:0387e8f68319 673 #define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
AnnaBridge 187:0387e8f68319 674 #define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
AnnaBridge 187:0387e8f68319 675 #define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 676 #define UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 677 #define UART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
AnnaBridge 187:0387e8f68319 678 #define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
AnnaBridge 187:0387e8f68319 679 #define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
AnnaBridge 187:0387e8f68319 680 #define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 681 #define UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 682 #define UART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
AnnaBridge 187:0387e8f68319 683 #define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
AnnaBridge 187:0387e8f68319 684 #define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
AnnaBridge 187:0387e8f68319 685 #define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 686 #define UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */
AnnaBridge 187:0387e8f68319 687
AnnaBridge 187:0387e8f68319 688 /* Bit fields for UART TXDATA */
AnnaBridge 187:0387e8f68319 689 #define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */
AnnaBridge 187:0387e8f68319 690 #define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */
AnnaBridge 187:0387e8f68319 691 #define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
AnnaBridge 187:0387e8f68319 692 #define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
AnnaBridge 187:0387e8f68319 693 #define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */
AnnaBridge 187:0387e8f68319 694 #define UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATA */
AnnaBridge 187:0387e8f68319 695
AnnaBridge 187:0387e8f68319 696 /* Bit fields for UART TXDOUBLEX */
AnnaBridge 187:0387e8f68319 697 #define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 698 #define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 699 #define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
AnnaBridge 187:0387e8f68319 700 #define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
AnnaBridge 187:0387e8f68319 701 #define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 702 #define UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 703 #define UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
AnnaBridge 187:0387e8f68319 704 #define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
AnnaBridge 187:0387e8f68319 705 #define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
AnnaBridge 187:0387e8f68319 706 #define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 707 #define UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 708 #define UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
AnnaBridge 187:0387e8f68319 709 #define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
AnnaBridge 187:0387e8f68319 710 #define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
AnnaBridge 187:0387e8f68319 711 #define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 712 #define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 713 #define UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
AnnaBridge 187:0387e8f68319 714 #define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
AnnaBridge 187:0387e8f68319 715 #define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
AnnaBridge 187:0387e8f68319 716 #define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 717 #define UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 718 #define UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
AnnaBridge 187:0387e8f68319 719 #define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
AnnaBridge 187:0387e8f68319 720 #define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
AnnaBridge 187:0387e8f68319 721 #define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 722 #define UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 723 #define UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
AnnaBridge 187:0387e8f68319 724 #define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
AnnaBridge 187:0387e8f68319 725 #define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
AnnaBridge 187:0387e8f68319 726 #define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 727 #define UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 728 #define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
AnnaBridge 187:0387e8f68319 729 #define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
AnnaBridge 187:0387e8f68319 730 #define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 731 #define UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 732 #define UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
AnnaBridge 187:0387e8f68319 733 #define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
AnnaBridge 187:0387e8f68319 734 #define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
AnnaBridge 187:0387e8f68319 735 #define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 736 #define UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 737 #define UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
AnnaBridge 187:0387e8f68319 738 #define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
AnnaBridge 187:0387e8f68319 739 #define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
AnnaBridge 187:0387e8f68319 740 #define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 741 #define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 742 #define UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
AnnaBridge 187:0387e8f68319 743 #define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
AnnaBridge 187:0387e8f68319 744 #define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
AnnaBridge 187:0387e8f68319 745 #define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 746 #define UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 747 #define UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
AnnaBridge 187:0387e8f68319 748 #define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
AnnaBridge 187:0387e8f68319 749 #define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
AnnaBridge 187:0387e8f68319 750 #define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 751 #define UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 752 #define UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
AnnaBridge 187:0387e8f68319 753 #define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
AnnaBridge 187:0387e8f68319 754 #define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
AnnaBridge 187:0387e8f68319 755 #define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 756 #define UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
AnnaBridge 187:0387e8f68319 757
AnnaBridge 187:0387e8f68319 758 /* Bit fields for UART TXDOUBLE */
AnnaBridge 187:0387e8f68319 759 #define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */
AnnaBridge 187:0387e8f68319 760 #define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */
AnnaBridge 187:0387e8f68319 761 #define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
AnnaBridge 187:0387e8f68319 762 #define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
AnnaBridge 187:0387e8f68319 763 #define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
AnnaBridge 187:0387e8f68319 764 #define UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
AnnaBridge 187:0387e8f68319 765 #define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
AnnaBridge 187:0387e8f68319 766 #define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
AnnaBridge 187:0387e8f68319 767 #define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
AnnaBridge 187:0387e8f68319 768 #define UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
AnnaBridge 187:0387e8f68319 769
AnnaBridge 187:0387e8f68319 770 /* Bit fields for UART IF */
AnnaBridge 187:0387e8f68319 771 #define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */
AnnaBridge 187:0387e8f68319 772 #define _UART_IF_MASK 0x0001FFFFUL /**< Mask for UART_IF */
AnnaBridge 187:0387e8f68319 773 #define UART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
AnnaBridge 187:0387e8f68319 774 #define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 187:0387e8f68319 775 #define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 187:0387e8f68319 776 #define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 777 #define UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 778 #define UART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
AnnaBridge 187:0387e8f68319 779 #define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
AnnaBridge 187:0387e8f68319 780 #define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
AnnaBridge 187:0387e8f68319 781 #define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 782 #define UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 783 #define UART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
AnnaBridge 187:0387e8f68319 784 #define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
AnnaBridge 187:0387e8f68319 785 #define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
AnnaBridge 187:0387e8f68319 786 #define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 787 #define UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 788 #define UART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
AnnaBridge 187:0387e8f68319 789 #define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 187:0387e8f68319 790 #define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 187:0387e8f68319 791 #define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 792 #define UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 793 #define UART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 794 #define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 187:0387e8f68319 795 #define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 187:0387e8f68319 796 #define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 797 #define UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 798 #define UART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 799 #define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 187:0387e8f68319 800 #define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 187:0387e8f68319 801 #define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 802 #define UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 803 #define UART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 804 #define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 187:0387e8f68319 805 #define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 187:0387e8f68319 806 #define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 807 #define UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 808 #define UART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 809 #define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 187:0387e8f68319 810 #define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 187:0387e8f68319 811 #define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 812 #define UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 813 #define UART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
AnnaBridge 187:0387e8f68319 814 #define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 187:0387e8f68319 815 #define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 187:0387e8f68319 816 #define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 817 #define UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 818 #define UART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
AnnaBridge 187:0387e8f68319 819 #define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 187:0387e8f68319 820 #define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 187:0387e8f68319 821 #define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 822 #define UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 823 #define UART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
AnnaBridge 187:0387e8f68319 824 #define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 187:0387e8f68319 825 #define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 187:0387e8f68319 826 #define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 827 #define UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 828 #define UART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
AnnaBridge 187:0387e8f68319 829 #define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 187:0387e8f68319 830 #define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 187:0387e8f68319 831 #define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 832 #define UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 833 #define UART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
AnnaBridge 187:0387e8f68319 834 #define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 187:0387e8f68319 835 #define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 187:0387e8f68319 836 #define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 837 #define UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 838 #define UART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
AnnaBridge 187:0387e8f68319 839 #define _UART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 840 #define _UART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 841 #define _UART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 842 #define UART_IF_TXIDLE_DEFAULT (_UART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 843 #define UART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 844 #define _UART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 845 #define _UART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 846 #define _UART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 847 #define UART_IF_TCMP0_DEFAULT (_UART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 848 #define UART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 849 #define _UART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 850 #define _UART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 851 #define _UART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 852 #define UART_IF_TCMP1_DEFAULT (_UART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 853 #define UART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 854 #define _UART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 855 #define _UART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 856 #define _UART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 857 #define UART_IF_TCMP2_DEFAULT (_UART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IF */
AnnaBridge 187:0387e8f68319 858
AnnaBridge 187:0387e8f68319 859 /* Bit fields for UART IFS */
AnnaBridge 187:0387e8f68319 860 #define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */
AnnaBridge 187:0387e8f68319 861 #define _UART_IFS_MASK 0x0001FFF9UL /**< Mask for UART_IFS */
AnnaBridge 187:0387e8f68319 862 #define UART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
AnnaBridge 187:0387e8f68319 863 #define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 187:0387e8f68319 864 #define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 187:0387e8f68319 865 #define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 866 #define UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 867 #define UART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */
AnnaBridge 187:0387e8f68319 868 #define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 187:0387e8f68319 869 #define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 187:0387e8f68319 870 #define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 871 #define UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 872 #define UART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */
AnnaBridge 187:0387e8f68319 873 #define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 187:0387e8f68319 874 #define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 187:0387e8f68319 875 #define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 876 #define UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 877 #define UART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */
AnnaBridge 187:0387e8f68319 878 #define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 187:0387e8f68319 879 #define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 187:0387e8f68319 880 #define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 881 #define UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 882 #define UART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */
AnnaBridge 187:0387e8f68319 883 #define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 187:0387e8f68319 884 #define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 187:0387e8f68319 885 #define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 886 #define UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 887 #define UART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */
AnnaBridge 187:0387e8f68319 888 #define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 187:0387e8f68319 889 #define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 187:0387e8f68319 890 #define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 891 #define UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 892 #define UART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */
AnnaBridge 187:0387e8f68319 893 #define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 187:0387e8f68319 894 #define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 187:0387e8f68319 895 #define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 896 #define UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 897 #define UART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */
AnnaBridge 187:0387e8f68319 898 #define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 187:0387e8f68319 899 #define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 187:0387e8f68319 900 #define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 901 #define UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 902 #define UART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */
AnnaBridge 187:0387e8f68319 903 #define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 187:0387e8f68319 904 #define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 187:0387e8f68319 905 #define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 906 #define UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 907 #define UART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */
AnnaBridge 187:0387e8f68319 908 #define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 187:0387e8f68319 909 #define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 187:0387e8f68319 910 #define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 911 #define UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 912 #define UART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */
AnnaBridge 187:0387e8f68319 913 #define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 187:0387e8f68319 914 #define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 187:0387e8f68319 915 #define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 916 #define UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 917 #define UART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */
AnnaBridge 187:0387e8f68319 918 #define _UART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 919 #define _UART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 920 #define _UART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 921 #define UART_IFS_TXIDLE_DEFAULT (_UART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 922 #define UART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 923 #define _UART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 924 #define _UART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 925 #define _UART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 926 #define UART_IFS_TCMP0_DEFAULT (_UART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 927 #define UART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 928 #define _UART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 929 #define _UART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 930 #define _UART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 931 #define UART_IFS_TCMP1_DEFAULT (_UART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 932 #define UART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 933 #define _UART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 934 #define _UART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 935 #define _UART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 936 #define UART_IFS_TCMP2_DEFAULT (_UART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IFS */
AnnaBridge 187:0387e8f68319 937
AnnaBridge 187:0387e8f68319 938 /* Bit fields for UART IFC */
AnnaBridge 187:0387e8f68319 939 #define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */
AnnaBridge 187:0387e8f68319 940 #define _UART_IFC_MASK 0x0001FFF9UL /**< Mask for UART_IFC */
AnnaBridge 187:0387e8f68319 941 #define UART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
AnnaBridge 187:0387e8f68319 942 #define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 187:0387e8f68319 943 #define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 187:0387e8f68319 944 #define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 945 #define UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 946 #define UART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */
AnnaBridge 187:0387e8f68319 947 #define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 187:0387e8f68319 948 #define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 187:0387e8f68319 949 #define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 950 #define UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 951 #define UART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */
AnnaBridge 187:0387e8f68319 952 #define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 187:0387e8f68319 953 #define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 187:0387e8f68319 954 #define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 955 #define UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 956 #define UART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */
AnnaBridge 187:0387e8f68319 957 #define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 187:0387e8f68319 958 #define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 187:0387e8f68319 959 #define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 960 #define UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 961 #define UART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */
AnnaBridge 187:0387e8f68319 962 #define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 187:0387e8f68319 963 #define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 187:0387e8f68319 964 #define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 965 #define UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 966 #define UART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */
AnnaBridge 187:0387e8f68319 967 #define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 187:0387e8f68319 968 #define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 187:0387e8f68319 969 #define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 970 #define UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 971 #define UART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */
AnnaBridge 187:0387e8f68319 972 #define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 187:0387e8f68319 973 #define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 187:0387e8f68319 974 #define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 975 #define UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 976 #define UART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */
AnnaBridge 187:0387e8f68319 977 #define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 187:0387e8f68319 978 #define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 187:0387e8f68319 979 #define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 980 #define UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 981 #define UART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */
AnnaBridge 187:0387e8f68319 982 #define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 187:0387e8f68319 983 #define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 187:0387e8f68319 984 #define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 985 #define UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 986 #define UART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */
AnnaBridge 187:0387e8f68319 987 #define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 187:0387e8f68319 988 #define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 187:0387e8f68319 989 #define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 990 #define UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 991 #define UART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */
AnnaBridge 187:0387e8f68319 992 #define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 187:0387e8f68319 993 #define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 187:0387e8f68319 994 #define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 995 #define UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 996 #define UART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */
AnnaBridge 187:0387e8f68319 997 #define _UART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 998 #define _UART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 999 #define _UART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1000 #define UART_IFC_TXIDLE_DEFAULT (_UART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1001 #define UART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1002 #define _UART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 1003 #define _UART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 1004 #define _UART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1005 #define UART_IFC_TCMP0_DEFAULT (_UART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1006 #define UART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1007 #define _UART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 1008 #define _UART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 1009 #define _UART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1010 #define UART_IFC_TCMP1_DEFAULT (_UART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1011 #define UART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1012 #define _UART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 1013 #define _UART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 1014 #define _UART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1015 #define UART_IFC_TCMP2_DEFAULT (_UART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IFC */
AnnaBridge 187:0387e8f68319 1016
AnnaBridge 187:0387e8f68319 1017 /* Bit fields for UART IEN */
AnnaBridge 187:0387e8f68319 1018 #define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */
AnnaBridge 187:0387e8f68319 1019 #define _UART_IEN_MASK 0x0001FFFFUL /**< Mask for UART_IEN */
AnnaBridge 187:0387e8f68319 1020 #define UART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
AnnaBridge 187:0387e8f68319 1021 #define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 187:0387e8f68319 1022 #define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 187:0387e8f68319 1023 #define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1024 #define UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1025 #define UART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
AnnaBridge 187:0387e8f68319 1026 #define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
AnnaBridge 187:0387e8f68319 1027 #define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
AnnaBridge 187:0387e8f68319 1028 #define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1029 #define UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1030 #define UART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
AnnaBridge 187:0387e8f68319 1031 #define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
AnnaBridge 187:0387e8f68319 1032 #define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
AnnaBridge 187:0387e8f68319 1033 #define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1034 #define UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1035 #define UART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */
AnnaBridge 187:0387e8f68319 1036 #define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 187:0387e8f68319 1037 #define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 187:0387e8f68319 1038 #define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1039 #define UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1040 #define UART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1041 #define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 187:0387e8f68319 1042 #define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 187:0387e8f68319 1043 #define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1044 #define UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1045 #define UART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1046 #define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 187:0387e8f68319 1047 #define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 187:0387e8f68319 1048 #define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1049 #define UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1050 #define UART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1051 #define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 187:0387e8f68319 1052 #define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 187:0387e8f68319 1053 #define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1054 #define UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1055 #define UART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1056 #define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 187:0387e8f68319 1057 #define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 187:0387e8f68319 1058 #define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1059 #define UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1060 #define UART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */
AnnaBridge 187:0387e8f68319 1061 #define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 187:0387e8f68319 1062 #define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 187:0387e8f68319 1063 #define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1064 #define UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1065 #define UART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */
AnnaBridge 187:0387e8f68319 1066 #define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 187:0387e8f68319 1067 #define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 187:0387e8f68319 1068 #define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1069 #define UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1070 #define UART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1071 #define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 187:0387e8f68319 1072 #define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 187:0387e8f68319 1073 #define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1074 #define UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1075 #define UART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */
AnnaBridge 187:0387e8f68319 1076 #define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 187:0387e8f68319 1077 #define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 187:0387e8f68319 1078 #define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1079 #define UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1080 #define UART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1081 #define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 187:0387e8f68319 1082 #define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 187:0387e8f68319 1083 #define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1084 #define UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1085 #define UART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */
AnnaBridge 187:0387e8f68319 1086 #define _UART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 1087 #define _UART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
AnnaBridge 187:0387e8f68319 1088 #define _UART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1089 #define UART_IEN_TXIDLE_DEFAULT (_UART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1090 #define UART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1091 #define _UART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 1092 #define _UART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
AnnaBridge 187:0387e8f68319 1093 #define _UART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1094 #define UART_IEN_TCMP0_DEFAULT (_UART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1095 #define UART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1096 #define _UART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 1097 #define _UART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
AnnaBridge 187:0387e8f68319 1098 #define _UART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1099 #define UART_IEN_TCMP1_DEFAULT (_UART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1100 #define UART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1101 #define _UART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 1102 #define _UART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
AnnaBridge 187:0387e8f68319 1103 #define _UART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1104 #define UART_IEN_TCMP2_DEFAULT (_UART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IEN */
AnnaBridge 187:0387e8f68319 1105
AnnaBridge 187:0387e8f68319 1106 /* Bit fields for UART IRCTRL */
AnnaBridge 187:0387e8f68319 1107 #define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1108 #define _UART_IRCTRL_MASK 0x00001F8FUL /**< Mask for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1109 #define UART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
AnnaBridge 187:0387e8f68319 1110 #define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
AnnaBridge 187:0387e8f68319 1111 #define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
AnnaBridge 187:0387e8f68319 1112 #define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1113 #define UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1114 #define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
AnnaBridge 187:0387e8f68319 1115 #define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
AnnaBridge 187:0387e8f68319 1116 #define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1117 #define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1118 #define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1119 #define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1120 #define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1121 #define UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1122 #define UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1123 #define UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1124 #define UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1125 #define UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1126 #define UART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
AnnaBridge 187:0387e8f68319 1127 #define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
AnnaBridge 187:0387e8f68319 1128 #define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
AnnaBridge 187:0387e8f68319 1129 #define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1130 #define UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1131 #define UART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
AnnaBridge 187:0387e8f68319 1132 #define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
AnnaBridge 187:0387e8f68319 1133 #define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
AnnaBridge 187:0387e8f68319 1134 #define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1135 #define UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1136 #define _UART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */
AnnaBridge 187:0387e8f68319 1137 #define _UART_IRCTRL_IRPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_IRPRSSEL */
AnnaBridge 187:0387e8f68319 1138 #define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1139 #define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1140 #define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1141 #define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1142 #define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1143 #define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1144 #define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1145 #define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1146 #define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1147 #define _UART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1148 #define _UART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1149 #define _UART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1150 #define _UART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1151 #define _UART_IRCTRL_IRPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1152 #define _UART_IRCTRL_IRPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1153 #define _UART_IRCTRL_IRPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1154 #define _UART_IRCTRL_IRPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1155 #define _UART_IRCTRL_IRPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1156 #define _UART_IRCTRL_IRPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1157 #define _UART_IRCTRL_IRPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1158 #define _UART_IRCTRL_IRPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1159 #define _UART_IRCTRL_IRPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1160 #define _UART_IRCTRL_IRPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1161 #define _UART_IRCTRL_IRPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1162 #define _UART_IRCTRL_IRPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1163 #define UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1164 #define UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1165 #define UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1166 #define UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1167 #define UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1168 #define UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1169 #define UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1170 #define UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1171 #define UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1172 #define UART_IRCTRL_IRPRSSEL_PRSCH8 (_UART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1173 #define UART_IRCTRL_IRPRSSEL_PRSCH9 (_UART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1174 #define UART_IRCTRL_IRPRSSEL_PRSCH10 (_UART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1175 #define UART_IRCTRL_IRPRSSEL_PRSCH11 (_UART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1176 #define UART_IRCTRL_IRPRSSEL_PRSCH12 (_UART_IRCTRL_IRPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1177 #define UART_IRCTRL_IRPRSSEL_PRSCH13 (_UART_IRCTRL_IRPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1178 #define UART_IRCTRL_IRPRSSEL_PRSCH14 (_UART_IRCTRL_IRPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1179 #define UART_IRCTRL_IRPRSSEL_PRSCH15 (_UART_IRCTRL_IRPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1180 #define UART_IRCTRL_IRPRSSEL_PRSCH16 (_UART_IRCTRL_IRPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1181 #define UART_IRCTRL_IRPRSSEL_PRSCH17 (_UART_IRCTRL_IRPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1182 #define UART_IRCTRL_IRPRSSEL_PRSCH18 (_UART_IRCTRL_IRPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1183 #define UART_IRCTRL_IRPRSSEL_PRSCH19 (_UART_IRCTRL_IRPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1184 #define UART_IRCTRL_IRPRSSEL_PRSCH20 (_UART_IRCTRL_IRPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1185 #define UART_IRCTRL_IRPRSSEL_PRSCH21 (_UART_IRCTRL_IRPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1186 #define UART_IRCTRL_IRPRSSEL_PRSCH22 (_UART_IRCTRL_IRPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1187 #define UART_IRCTRL_IRPRSSEL_PRSCH23 (_UART_IRCTRL_IRPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for UART_IRCTRL */
AnnaBridge 187:0387e8f68319 1188
AnnaBridge 187:0387e8f68319 1189 /* Bit fields for UART INPUT */
AnnaBridge 187:0387e8f68319 1190 #define _UART_INPUT_RESETVALUE 0x00000000UL /**< Default value for UART_INPUT */
AnnaBridge 187:0387e8f68319 1191 #define _UART_INPUT_MASK 0x00009F9FUL /**< Mask for UART_INPUT */
AnnaBridge 187:0387e8f68319 1192 #define _UART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
AnnaBridge 187:0387e8f68319 1193 #define _UART_INPUT_RXPRSSEL_MASK 0x1FUL /**< Bit mask for USART_RXPRSSEL */
AnnaBridge 187:0387e8f68319 1194 #define _UART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1195 #define _UART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1196 #define _UART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1197 #define _UART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1198 #define _UART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1199 #define _UART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1200 #define _UART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1201 #define _UART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1202 #define _UART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1203 #define _UART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1204 #define _UART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1205 #define _UART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1206 #define _UART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1207 #define _UART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1208 #define _UART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1209 #define _UART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1210 #define _UART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1211 #define _UART_INPUT_RXPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1212 #define _UART_INPUT_RXPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1213 #define _UART_INPUT_RXPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1214 #define _UART_INPUT_RXPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1215 #define _UART_INPUT_RXPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1216 #define _UART_INPUT_RXPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1217 #define _UART_INPUT_RXPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1218 #define _UART_INPUT_RXPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1219 #define UART_INPUT_RXPRSSEL_DEFAULT (_UART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1220 #define UART_INPUT_RXPRSSEL_PRSCH0 (_UART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1221 #define UART_INPUT_RXPRSSEL_PRSCH1 (_UART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1222 #define UART_INPUT_RXPRSSEL_PRSCH2 (_UART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1223 #define UART_INPUT_RXPRSSEL_PRSCH3 (_UART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1224 #define UART_INPUT_RXPRSSEL_PRSCH4 (_UART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1225 #define UART_INPUT_RXPRSSEL_PRSCH5 (_UART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1226 #define UART_INPUT_RXPRSSEL_PRSCH6 (_UART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1227 #define UART_INPUT_RXPRSSEL_PRSCH7 (_UART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1228 #define UART_INPUT_RXPRSSEL_PRSCH8 (_UART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1229 #define UART_INPUT_RXPRSSEL_PRSCH9 (_UART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1230 #define UART_INPUT_RXPRSSEL_PRSCH10 (_UART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1231 #define UART_INPUT_RXPRSSEL_PRSCH11 (_UART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1232 #define UART_INPUT_RXPRSSEL_PRSCH12 (_UART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1233 #define UART_INPUT_RXPRSSEL_PRSCH13 (_UART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1234 #define UART_INPUT_RXPRSSEL_PRSCH14 (_UART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1235 #define UART_INPUT_RXPRSSEL_PRSCH15 (_UART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1236 #define UART_INPUT_RXPRSSEL_PRSCH16 (_UART_INPUT_RXPRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1237 #define UART_INPUT_RXPRSSEL_PRSCH17 (_UART_INPUT_RXPRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1238 #define UART_INPUT_RXPRSSEL_PRSCH18 (_UART_INPUT_RXPRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1239 #define UART_INPUT_RXPRSSEL_PRSCH19 (_UART_INPUT_RXPRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1240 #define UART_INPUT_RXPRSSEL_PRSCH20 (_UART_INPUT_RXPRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1241 #define UART_INPUT_RXPRSSEL_PRSCH21 (_UART_INPUT_RXPRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1242 #define UART_INPUT_RXPRSSEL_PRSCH22 (_UART_INPUT_RXPRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1243 #define UART_INPUT_RXPRSSEL_PRSCH23 (_UART_INPUT_RXPRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1244 #define UART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */
AnnaBridge 187:0387e8f68319 1245 #define _UART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */
AnnaBridge 187:0387e8f68319 1246 #define _UART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */
AnnaBridge 187:0387e8f68319 1247 #define _UART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1248 #define UART_INPUT_RXPRS_DEFAULT (_UART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1249 #define _UART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */
AnnaBridge 187:0387e8f68319 1250 #define _UART_INPUT_CLKPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_CLKPRSSEL */
AnnaBridge 187:0387e8f68319 1251 #define _UART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1252 #define _UART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1253 #define _UART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1254 #define _UART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1255 #define _UART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1256 #define _UART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1257 #define _UART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1258 #define _UART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1259 #define _UART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1260 #define _UART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1261 #define _UART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1262 #define _UART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1263 #define _UART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1264 #define _UART_INPUT_CLKPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1265 #define _UART_INPUT_CLKPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1266 #define _UART_INPUT_CLKPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1267 #define _UART_INPUT_CLKPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1268 #define _UART_INPUT_CLKPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1269 #define _UART_INPUT_CLKPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1270 #define _UART_INPUT_CLKPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1271 #define _UART_INPUT_CLKPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1272 #define _UART_INPUT_CLKPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1273 #define _UART_INPUT_CLKPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1274 #define _UART_INPUT_CLKPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1275 #define _UART_INPUT_CLKPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1276 #define UART_INPUT_CLKPRSSEL_DEFAULT (_UART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1277 #define UART_INPUT_CLKPRSSEL_PRSCH0 (_UART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1278 #define UART_INPUT_CLKPRSSEL_PRSCH1 (_UART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1279 #define UART_INPUT_CLKPRSSEL_PRSCH2 (_UART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1280 #define UART_INPUT_CLKPRSSEL_PRSCH3 (_UART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1281 #define UART_INPUT_CLKPRSSEL_PRSCH4 (_UART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1282 #define UART_INPUT_CLKPRSSEL_PRSCH5 (_UART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1283 #define UART_INPUT_CLKPRSSEL_PRSCH6 (_UART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1284 #define UART_INPUT_CLKPRSSEL_PRSCH7 (_UART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1285 #define UART_INPUT_CLKPRSSEL_PRSCH8 (_UART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1286 #define UART_INPUT_CLKPRSSEL_PRSCH9 (_UART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1287 #define UART_INPUT_CLKPRSSEL_PRSCH10 (_UART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1288 #define UART_INPUT_CLKPRSSEL_PRSCH11 (_UART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1289 #define UART_INPUT_CLKPRSSEL_PRSCH12 (_UART_INPUT_CLKPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1290 #define UART_INPUT_CLKPRSSEL_PRSCH13 (_UART_INPUT_CLKPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1291 #define UART_INPUT_CLKPRSSEL_PRSCH14 (_UART_INPUT_CLKPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1292 #define UART_INPUT_CLKPRSSEL_PRSCH15 (_UART_INPUT_CLKPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1293 #define UART_INPUT_CLKPRSSEL_PRSCH16 (_UART_INPUT_CLKPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1294 #define UART_INPUT_CLKPRSSEL_PRSCH17 (_UART_INPUT_CLKPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1295 #define UART_INPUT_CLKPRSSEL_PRSCH18 (_UART_INPUT_CLKPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1296 #define UART_INPUT_CLKPRSSEL_PRSCH19 (_UART_INPUT_CLKPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1297 #define UART_INPUT_CLKPRSSEL_PRSCH20 (_UART_INPUT_CLKPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1298 #define UART_INPUT_CLKPRSSEL_PRSCH21 (_UART_INPUT_CLKPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1299 #define UART_INPUT_CLKPRSSEL_PRSCH22 (_UART_INPUT_CLKPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1300 #define UART_INPUT_CLKPRSSEL_PRSCH23 (_UART_INPUT_CLKPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for UART_INPUT */
AnnaBridge 187:0387e8f68319 1301 #define UART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */
AnnaBridge 187:0387e8f68319 1302 #define _UART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */
AnnaBridge 187:0387e8f68319 1303 #define _UART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */
AnnaBridge 187:0387e8f68319 1304 #define _UART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1305 #define UART_INPUT_CLKPRS_DEFAULT (_UART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_INPUT */
AnnaBridge 187:0387e8f68319 1306
AnnaBridge 187:0387e8f68319 1307 /* Bit fields for UART I2SCTRL */
AnnaBridge 187:0387e8f68319 1308 #define _UART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1309 #define _UART_I2SCTRL_MASK 0x0000071FUL /**< Mask for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1310 #define UART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
AnnaBridge 187:0387e8f68319 1311 #define _UART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
AnnaBridge 187:0387e8f68319 1312 #define _UART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
AnnaBridge 187:0387e8f68319 1313 #define _UART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1314 #define UART_I2SCTRL_EN_DEFAULT (_UART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1315 #define UART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
AnnaBridge 187:0387e8f68319 1316 #define _UART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
AnnaBridge 187:0387e8f68319 1317 #define _UART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
AnnaBridge 187:0387e8f68319 1318 #define _UART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1319 #define UART_I2SCTRL_MONO_DEFAULT (_UART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1320 #define UART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
AnnaBridge 187:0387e8f68319 1321 #define _UART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
AnnaBridge 187:0387e8f68319 1322 #define _UART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
AnnaBridge 187:0387e8f68319 1323 #define _UART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1324 #define _UART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1325 #define _UART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1326 #define UART_I2SCTRL_JUSTIFY_DEFAULT (_UART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1327 #define UART_I2SCTRL_JUSTIFY_LEFT (_UART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1328 #define UART_I2SCTRL_JUSTIFY_RIGHT (_UART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1329 #define UART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
AnnaBridge 187:0387e8f68319 1330 #define _UART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
AnnaBridge 187:0387e8f68319 1331 #define _UART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
AnnaBridge 187:0387e8f68319 1332 #define _UART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1333 #define UART_I2SCTRL_DMASPLIT_DEFAULT (_UART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1334 #define UART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
AnnaBridge 187:0387e8f68319 1335 #define _UART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
AnnaBridge 187:0387e8f68319 1336 #define _UART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
AnnaBridge 187:0387e8f68319 1337 #define _UART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1338 #define UART_I2SCTRL_DELAY_DEFAULT (_UART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1339 #define _UART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
AnnaBridge 187:0387e8f68319 1340 #define _UART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
AnnaBridge 187:0387e8f68319 1341 #define _UART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1342 #define _UART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1343 #define _UART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1344 #define _UART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1345 #define _UART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1346 #define _UART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1347 #define _UART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1348 #define _UART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1349 #define _UART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1350 #define UART_I2SCTRL_FORMAT_DEFAULT (_UART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1351 #define UART_I2SCTRL_FORMAT_W32D32 (_UART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1352 #define UART_I2SCTRL_FORMAT_W32D24M (_UART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1353 #define UART_I2SCTRL_FORMAT_W32D24 (_UART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1354 #define UART_I2SCTRL_FORMAT_W32D16 (_UART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1355 #define UART_I2SCTRL_FORMAT_W32D8 (_UART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1356 #define UART_I2SCTRL_FORMAT_W16D16 (_UART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1357 #define UART_I2SCTRL_FORMAT_W16D8 (_UART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1358 #define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */
AnnaBridge 187:0387e8f68319 1359
AnnaBridge 187:0387e8f68319 1360 /* Bit fields for UART TIMING */
AnnaBridge 187:0387e8f68319 1361 #define _UART_TIMING_RESETVALUE 0x00000000UL /**< Default value for UART_TIMING */
AnnaBridge 187:0387e8f68319 1362 #define _UART_TIMING_MASK 0x77770000UL /**< Mask for UART_TIMING */
AnnaBridge 187:0387e8f68319 1363 #define _UART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */
AnnaBridge 187:0387e8f68319 1364 #define _UART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */
AnnaBridge 187:0387e8f68319 1365 #define _UART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1366 #define _UART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1367 #define _UART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1368 #define _UART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1369 #define _UART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1370 #define _UART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1371 #define _UART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1372 #define _UART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1373 #define _UART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1374 #define UART_TIMING_TXDELAY_DEFAULT (_UART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1375 #define UART_TIMING_TXDELAY_DISABLE (_UART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1376 #define UART_TIMING_TXDELAY_ONE (_UART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1377 #define UART_TIMING_TXDELAY_TWO (_UART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1378 #define UART_TIMING_TXDELAY_THREE (_UART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1379 #define UART_TIMING_TXDELAY_SEVEN (_UART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1380 #define UART_TIMING_TXDELAY_TCMP0 (_UART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1381 #define UART_TIMING_TXDELAY_TCMP1 (_UART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1382 #define UART_TIMING_TXDELAY_TCMP2 (_UART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1383 #define _UART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */
AnnaBridge 187:0387e8f68319 1384 #define _UART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */
AnnaBridge 187:0387e8f68319 1385 #define _UART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1386 #define _UART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1387 #define _UART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1388 #define _UART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1389 #define _UART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1390 #define _UART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1391 #define _UART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1392 #define _UART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1393 #define _UART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1394 #define UART_TIMING_CSSETUP_DEFAULT (_UART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1395 #define UART_TIMING_CSSETUP_ZERO (_UART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1396 #define UART_TIMING_CSSETUP_ONE (_UART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1397 #define UART_TIMING_CSSETUP_TWO (_UART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1398 #define UART_TIMING_CSSETUP_THREE (_UART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1399 #define UART_TIMING_CSSETUP_SEVEN (_UART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1400 #define UART_TIMING_CSSETUP_TCMP0 (_UART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1401 #define UART_TIMING_CSSETUP_TCMP1 (_UART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1402 #define UART_TIMING_CSSETUP_TCMP2 (_UART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1403 #define _UART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */
AnnaBridge 187:0387e8f68319 1404 #define _UART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */
AnnaBridge 187:0387e8f68319 1405 #define _UART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1406 #define _UART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1407 #define _UART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1408 #define _UART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1409 #define _UART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1410 #define _UART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1411 #define _UART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1412 #define _UART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1413 #define _UART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1414 #define UART_TIMING_ICS_DEFAULT (_UART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1415 #define UART_TIMING_ICS_ZERO (_UART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1416 #define UART_TIMING_ICS_ONE (_UART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1417 #define UART_TIMING_ICS_TWO (_UART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1418 #define UART_TIMING_ICS_THREE (_UART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1419 #define UART_TIMING_ICS_SEVEN (_UART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1420 #define UART_TIMING_ICS_TCMP0 (_UART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1421 #define UART_TIMING_ICS_TCMP1 (_UART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1422 #define UART_TIMING_ICS_TCMP2 (_UART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1423 #define _UART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */
AnnaBridge 187:0387e8f68319 1424 #define _UART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */
AnnaBridge 187:0387e8f68319 1425 #define _UART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1426 #define _UART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1427 #define _UART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1428 #define _UART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1429 #define _UART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1430 #define _UART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1431 #define _UART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1432 #define _UART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1433 #define _UART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1434 #define UART_TIMING_CSHOLD_DEFAULT (_UART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TIMING */
AnnaBridge 187:0387e8f68319 1435 #define UART_TIMING_CSHOLD_ZERO (_UART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1436 #define UART_TIMING_CSHOLD_ONE (_UART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1437 #define UART_TIMING_CSHOLD_TWO (_UART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for UART_TIMING */
AnnaBridge 187:0387e8f68319 1438 #define UART_TIMING_CSHOLD_THREE (_UART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for UART_TIMING */
AnnaBridge 187:0387e8f68319 1439 #define UART_TIMING_CSHOLD_SEVEN (_UART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for UART_TIMING */
AnnaBridge 187:0387e8f68319 1440 #define UART_TIMING_CSHOLD_TCMP0 (_UART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1441 #define UART_TIMING_CSHOLD_TCMP1 (_UART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1442 #define UART_TIMING_CSHOLD_TCMP2 (_UART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for UART_TIMING */
AnnaBridge 187:0387e8f68319 1443
AnnaBridge 187:0387e8f68319 1444 /* Bit fields for UART CTRLX */
AnnaBridge 187:0387e8f68319 1445 #define _UART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1446 #define _UART_CTRLX_MASK 0x0000000FUL /**< Mask for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1447 #define UART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */
AnnaBridge 187:0387e8f68319 1448 #define _UART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
AnnaBridge 187:0387e8f68319 1449 #define _UART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
AnnaBridge 187:0387e8f68319 1450 #define _UART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1451 #define UART_CTRLX_DBGHALT_DEFAULT (_UART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1452 #define UART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */
AnnaBridge 187:0387e8f68319 1453 #define _UART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */
AnnaBridge 187:0387e8f68319 1454 #define _UART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
AnnaBridge 187:0387e8f68319 1455 #define _UART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1456 #define UART_CTRLX_CTSINV_DEFAULT (_UART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1457 #define UART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */
AnnaBridge 187:0387e8f68319 1458 #define _UART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
AnnaBridge 187:0387e8f68319 1459 #define _UART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
AnnaBridge 187:0387e8f68319 1460 #define _UART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1461 #define UART_CTRLX_CTSEN_DEFAULT (_UART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1462 #define UART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */
AnnaBridge 187:0387e8f68319 1463 #define _UART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */
AnnaBridge 187:0387e8f68319 1464 #define _UART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */
AnnaBridge 187:0387e8f68319 1465 #define _UART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1466 #define UART_CTRLX_RTSINV_DEFAULT (_UART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRLX */
AnnaBridge 187:0387e8f68319 1467
AnnaBridge 187:0387e8f68319 1468 /* Bit fields for UART TIMECMP0 */
AnnaBridge 187:0387e8f68319 1469 #define _UART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1470 #define _UART_TIMECMP0_MASK 0x017700FFUL /**< Mask for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1471 #define _UART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
AnnaBridge 187:0387e8f68319 1472 #define _UART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
AnnaBridge 187:0387e8f68319 1473 #define _UART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1474 #define UART_TIMECMP0_TCMPVAL_DEFAULT (_UART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1475 #define _UART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
AnnaBridge 187:0387e8f68319 1476 #define _UART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
AnnaBridge 187:0387e8f68319 1477 #define _UART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1478 #define _UART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1479 #define _UART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1480 #define _UART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1481 #define _UART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1482 #define _UART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1483 #define UART_TIMECMP0_TSTART_DEFAULT (_UART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1484 #define UART_TIMECMP0_TSTART_DISABLE (_UART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1485 #define UART_TIMECMP0_TSTART_TXEOF (_UART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1486 #define UART_TIMECMP0_TSTART_TXC (_UART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1487 #define UART_TIMECMP0_TSTART_RXACT (_UART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1488 #define UART_TIMECMP0_TSTART_RXEOF (_UART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1489 #define _UART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
AnnaBridge 187:0387e8f68319 1490 #define _UART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
AnnaBridge 187:0387e8f68319 1491 #define _UART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1492 #define _UART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1493 #define _UART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1494 #define _UART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1495 #define _UART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1496 #define UART_TIMECMP0_TSTOP_DEFAULT (_UART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1497 #define UART_TIMECMP0_TSTOP_TCMP0 (_UART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1498 #define UART_TIMECMP0_TSTOP_TXST (_UART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1499 #define UART_TIMECMP0_TSTOP_RXACT (_UART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1500 #define UART_TIMECMP0_TSTOP_RXACTN (_UART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1501 #define UART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */
AnnaBridge 187:0387e8f68319 1502 #define _UART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
AnnaBridge 187:0387e8f68319 1503 #define _UART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
AnnaBridge 187:0387e8f68319 1504 #define _UART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1505 #define UART_TIMECMP0_RESTARTEN_DEFAULT (_UART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP0 */
AnnaBridge 187:0387e8f68319 1506
AnnaBridge 187:0387e8f68319 1507 /* Bit fields for UART TIMECMP1 */
AnnaBridge 187:0387e8f68319 1508 #define _UART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1509 #define _UART_TIMECMP1_MASK 0x017700FFUL /**< Mask for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1510 #define _UART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
AnnaBridge 187:0387e8f68319 1511 #define _UART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
AnnaBridge 187:0387e8f68319 1512 #define _UART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1513 #define UART_TIMECMP1_TCMPVAL_DEFAULT (_UART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1514 #define _UART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
AnnaBridge 187:0387e8f68319 1515 #define _UART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
AnnaBridge 187:0387e8f68319 1516 #define _UART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1517 #define _UART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1518 #define _UART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1519 #define _UART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1520 #define _UART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1521 #define _UART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1522 #define UART_TIMECMP1_TSTART_DEFAULT (_UART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1523 #define UART_TIMECMP1_TSTART_DISABLE (_UART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1524 #define UART_TIMECMP1_TSTART_TXEOF (_UART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1525 #define UART_TIMECMP1_TSTART_TXC (_UART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1526 #define UART_TIMECMP1_TSTART_RXACT (_UART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1527 #define UART_TIMECMP1_TSTART_RXEOF (_UART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1528 #define _UART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
AnnaBridge 187:0387e8f68319 1529 #define _UART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
AnnaBridge 187:0387e8f68319 1530 #define _UART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1531 #define _UART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1532 #define _UART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1533 #define _UART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1534 #define _UART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1535 #define UART_TIMECMP1_TSTOP_DEFAULT (_UART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1536 #define UART_TIMECMP1_TSTOP_TCMP1 (_UART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1537 #define UART_TIMECMP1_TSTOP_TXST (_UART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1538 #define UART_TIMECMP1_TSTOP_RXACT (_UART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1539 #define UART_TIMECMP1_TSTOP_RXACTN (_UART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1540 #define UART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */
AnnaBridge 187:0387e8f68319 1541 #define _UART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
AnnaBridge 187:0387e8f68319 1542 #define _UART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
AnnaBridge 187:0387e8f68319 1543 #define _UART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1544 #define UART_TIMECMP1_RESTARTEN_DEFAULT (_UART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP1 */
AnnaBridge 187:0387e8f68319 1545
AnnaBridge 187:0387e8f68319 1546 /* Bit fields for UART TIMECMP2 */
AnnaBridge 187:0387e8f68319 1547 #define _UART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1548 #define _UART_TIMECMP2_MASK 0x017700FFUL /**< Mask for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1549 #define _UART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
AnnaBridge 187:0387e8f68319 1550 #define _UART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
AnnaBridge 187:0387e8f68319 1551 #define _UART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1552 #define UART_TIMECMP2_TCMPVAL_DEFAULT (_UART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1553 #define _UART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
AnnaBridge 187:0387e8f68319 1554 #define _UART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
AnnaBridge 187:0387e8f68319 1555 #define _UART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1556 #define _UART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1557 #define _UART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1558 #define _UART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1559 #define _UART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1560 #define _UART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1561 #define UART_TIMECMP2_TSTART_DEFAULT (_UART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1562 #define UART_TIMECMP2_TSTART_DISABLE (_UART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1563 #define UART_TIMECMP2_TSTART_TXEOF (_UART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1564 #define UART_TIMECMP2_TSTART_TXC (_UART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1565 #define UART_TIMECMP2_TSTART_RXACT (_UART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1566 #define UART_TIMECMP2_TSTART_RXEOF (_UART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1567 #define _UART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
AnnaBridge 187:0387e8f68319 1568 #define _UART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
AnnaBridge 187:0387e8f68319 1569 #define _UART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1570 #define _UART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1571 #define _UART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1572 #define _UART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1573 #define _UART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1574 #define UART_TIMECMP2_TSTOP_DEFAULT (_UART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1575 #define UART_TIMECMP2_TSTOP_TCMP2 (_UART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1576 #define UART_TIMECMP2_TSTOP_TXST (_UART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1577 #define UART_TIMECMP2_TSTOP_RXACT (_UART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1578 #define UART_TIMECMP2_TSTOP_RXACTN (_UART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1579 #define UART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */
AnnaBridge 187:0387e8f68319 1580 #define _UART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
AnnaBridge 187:0387e8f68319 1581 #define _UART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
AnnaBridge 187:0387e8f68319 1582 #define _UART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1583 #define UART_TIMECMP2_RESTARTEN_DEFAULT (_UART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP2 */
AnnaBridge 187:0387e8f68319 1584
AnnaBridge 187:0387e8f68319 1585 /* Bit fields for UART ROUTEPEN */
AnnaBridge 187:0387e8f68319 1586 #define _UART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1587 #define _UART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1588 #define UART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
AnnaBridge 187:0387e8f68319 1589 #define _UART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
AnnaBridge 187:0387e8f68319 1590 #define _UART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
AnnaBridge 187:0387e8f68319 1591 #define _UART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1592 #define UART_ROUTEPEN_RXPEN_DEFAULT (_UART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1593 #define UART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
AnnaBridge 187:0387e8f68319 1594 #define _UART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
AnnaBridge 187:0387e8f68319 1595 #define _UART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
AnnaBridge 187:0387e8f68319 1596 #define _UART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1597 #define UART_ROUTEPEN_TXPEN_DEFAULT (_UART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1598 #define UART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */
AnnaBridge 187:0387e8f68319 1599 #define _UART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
AnnaBridge 187:0387e8f68319 1600 #define _UART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
AnnaBridge 187:0387e8f68319 1601 #define _UART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1602 #define UART_ROUTEPEN_CSPEN_DEFAULT (_UART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1603 #define UART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
AnnaBridge 187:0387e8f68319 1604 #define _UART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
AnnaBridge 187:0387e8f68319 1605 #define _UART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
AnnaBridge 187:0387e8f68319 1606 #define _UART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1607 #define UART_ROUTEPEN_CLKPEN_DEFAULT (_UART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1608 #define UART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */
AnnaBridge 187:0387e8f68319 1609 #define _UART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */
AnnaBridge 187:0387e8f68319 1610 #define _UART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */
AnnaBridge 187:0387e8f68319 1611 #define _UART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1612 #define UART_ROUTEPEN_CTSPEN_DEFAULT (_UART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1613 #define UART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */
AnnaBridge 187:0387e8f68319 1614 #define _UART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */
AnnaBridge 187:0387e8f68319 1615 #define _UART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */
AnnaBridge 187:0387e8f68319 1616 #define _UART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1617 #define UART_ROUTEPEN_RTSPEN_DEFAULT (_UART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1618
AnnaBridge 187:0387e8f68319 1619 /* Bit fields for UART ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1620 #define _UART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1621 #define _UART_ROUTELOC0_MASK 0x07070707UL /**< Mask for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1622 #define _UART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */
AnnaBridge 187:0387e8f68319 1623 #define _UART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for USART_RXLOC */
AnnaBridge 187:0387e8f68319 1624 #define _UART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1625 #define _UART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1626 #define _UART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1627 #define _UART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1628 #define _UART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1629 #define _UART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1630 #define _UART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1631 #define _UART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1632 #define UART_ROUTELOC0_RXLOC_LOC0 (_UART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1633 #define UART_ROUTELOC0_RXLOC_DEFAULT (_UART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1634 #define UART_ROUTELOC0_RXLOC_LOC1 (_UART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1635 #define UART_ROUTELOC0_RXLOC_LOC2 (_UART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1636 #define UART_ROUTELOC0_RXLOC_LOC3 (_UART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1637 #define UART_ROUTELOC0_RXLOC_LOC4 (_UART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1638 #define UART_ROUTELOC0_RXLOC_LOC5 (_UART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1639 #define UART_ROUTELOC0_RXLOC_LOC6 (_UART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1640 #define _UART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */
AnnaBridge 187:0387e8f68319 1641 #define _UART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for USART_TXLOC */
AnnaBridge 187:0387e8f68319 1642 #define _UART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1643 #define _UART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1644 #define _UART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1645 #define _UART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1646 #define _UART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1647 #define _UART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1648 #define _UART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1649 #define _UART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1650 #define UART_ROUTELOC0_TXLOC_LOC0 (_UART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1651 #define UART_ROUTELOC0_TXLOC_DEFAULT (_UART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1652 #define UART_ROUTELOC0_TXLOC_LOC1 (_UART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1653 #define UART_ROUTELOC0_TXLOC_LOC2 (_UART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1654 #define UART_ROUTELOC0_TXLOC_LOC3 (_UART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1655 #define UART_ROUTELOC0_TXLOC_LOC4 (_UART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1656 #define UART_ROUTELOC0_TXLOC_LOC5 (_UART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1657 #define UART_ROUTELOC0_TXLOC_LOC6 (_UART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1658 #define _UART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */
AnnaBridge 187:0387e8f68319 1659 #define _UART_ROUTELOC0_CSLOC_MASK 0x70000UL /**< Bit mask for USART_CSLOC */
AnnaBridge 187:0387e8f68319 1660 #define _UART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1661 #define _UART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1662 #define _UART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1663 #define _UART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1664 #define _UART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1665 #define _UART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1666 #define _UART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1667 #define _UART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1668 #define UART_ROUTELOC0_CSLOC_LOC0 (_UART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1669 #define UART_ROUTELOC0_CSLOC_DEFAULT (_UART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1670 #define UART_ROUTELOC0_CSLOC_LOC1 (_UART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1671 #define UART_ROUTELOC0_CSLOC_LOC2 (_UART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1672 #define UART_ROUTELOC0_CSLOC_LOC3 (_UART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1673 #define UART_ROUTELOC0_CSLOC_LOC4 (_UART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1674 #define UART_ROUTELOC0_CSLOC_LOC5 (_UART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1675 #define UART_ROUTELOC0_CSLOC_LOC6 (_UART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1676 #define _UART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */
AnnaBridge 187:0387e8f68319 1677 #define _UART_ROUTELOC0_CLKLOC_MASK 0x7000000UL /**< Bit mask for USART_CLKLOC */
AnnaBridge 187:0387e8f68319 1678 #define _UART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1679 #define _UART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1680 #define _UART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1681 #define _UART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1682 #define _UART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1683 #define _UART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1684 #define _UART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1685 #define _UART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1686 #define UART_ROUTELOC0_CLKLOC_LOC0 (_UART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1687 #define UART_ROUTELOC0_CLKLOC_DEFAULT (_UART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1688 #define UART_ROUTELOC0_CLKLOC_LOC1 (_UART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1689 #define UART_ROUTELOC0_CLKLOC_LOC2 (_UART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1690 #define UART_ROUTELOC0_CLKLOC_LOC3 (_UART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1691 #define UART_ROUTELOC0_CLKLOC_LOC4 (_UART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1692 #define UART_ROUTELOC0_CLKLOC_LOC5 (_UART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1693 #define UART_ROUTELOC0_CLKLOC_LOC6 (_UART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for UART_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1694
AnnaBridge 187:0387e8f68319 1695 /* Bit fields for UART ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1696 #define _UART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1697 #define _UART_ROUTELOC1_MASK 0x00000707UL /**< Mask for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1698 #define _UART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */
AnnaBridge 187:0387e8f68319 1699 #define _UART_ROUTELOC1_CTSLOC_MASK 0x7UL /**< Bit mask for USART_CTSLOC */
AnnaBridge 187:0387e8f68319 1700 #define _UART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1701 #define _UART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1702 #define _UART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1703 #define _UART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1704 #define _UART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1705 #define _UART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1706 #define _UART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1707 #define _UART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1708 #define UART_ROUTELOC1_CTSLOC_LOC0 (_UART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1709 #define UART_ROUTELOC1_CTSLOC_DEFAULT (_UART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1710 #define UART_ROUTELOC1_CTSLOC_LOC1 (_UART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1711 #define UART_ROUTELOC1_CTSLOC_LOC2 (_UART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1712 #define UART_ROUTELOC1_CTSLOC_LOC3 (_UART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1713 #define UART_ROUTELOC1_CTSLOC_LOC4 (_UART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1714 #define UART_ROUTELOC1_CTSLOC_LOC5 (_UART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1715 #define UART_ROUTELOC1_CTSLOC_LOC6 (_UART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1716 #define _UART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */
AnnaBridge 187:0387e8f68319 1717 #define _UART_ROUTELOC1_RTSLOC_MASK 0x700UL /**< Bit mask for USART_RTSLOC */
AnnaBridge 187:0387e8f68319 1718 #define _UART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1719 #define _UART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1720 #define _UART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1721 #define _UART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1722 #define _UART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1723 #define _UART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1724 #define _UART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1725 #define _UART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1726 #define UART_ROUTELOC1_RTSLOC_LOC0 (_UART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1727 #define UART_ROUTELOC1_RTSLOC_DEFAULT (_UART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1728 #define UART_ROUTELOC1_RTSLOC_LOC1 (_UART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1729 #define UART_ROUTELOC1_RTSLOC_LOC2 (_UART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1730 #define UART_ROUTELOC1_RTSLOC_LOC3 (_UART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1731 #define UART_ROUTELOC1_RTSLOC_LOC4 (_UART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1732 #define UART_ROUTELOC1_RTSLOC_LOC5 (_UART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1733 #define UART_ROUTELOC1_RTSLOC_LOC6 (_UART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for UART_ROUTELOC1 */
AnnaBridge 187:0387e8f68319 1734
AnnaBridge 187:0387e8f68319 1735 /** @} */
AnnaBridge 187:0387e8f68319 1736 /** @} End of group EFM32GG11B_UART */
AnnaBridge 187:0387e8f68319 1737 /** @} End of group Parts */