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mbed library sources. Supersedes mbed-src.
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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/efm32gg11b_prs.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 187:0387e8f68319
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 187:0387e8f68319 | 1 | /**************************************************************************//** |
| AnnaBridge | 187:0387e8f68319 | 2 | * @file efm32gg11b_prs.h |
| AnnaBridge | 187:0387e8f68319 | 3 | * @brief EFM32GG11B_PRS register and bit field definitions |
| AnnaBridge | 187:0387e8f68319 | 4 | * @version 5.3.2 |
| AnnaBridge | 187:0387e8f68319 | 5 | ****************************************************************************** |
| AnnaBridge | 187:0387e8f68319 | 6 | * # License |
| AnnaBridge | 187:0387e8f68319 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 187:0387e8f68319 | 8 | ****************************************************************************** |
| AnnaBridge | 187:0387e8f68319 | 9 | * |
| AnnaBridge | 187:0387e8f68319 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 187:0387e8f68319 | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 187:0387e8f68319 | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 187:0387e8f68319 | 13 | * |
| AnnaBridge | 187:0387e8f68319 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 187:0387e8f68319 | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 187:0387e8f68319 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 187:0387e8f68319 | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 187:0387e8f68319 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 187:0387e8f68319 | 19 | * |
| AnnaBridge | 187:0387e8f68319 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 187:0387e8f68319 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 187:0387e8f68319 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 187:0387e8f68319 | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 187:0387e8f68319 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 187:0387e8f68319 | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 187:0387e8f68319 | 26 | * |
| AnnaBridge | 187:0387e8f68319 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 187:0387e8f68319 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 187:0387e8f68319 | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 187:0387e8f68319 | 30 | * |
| AnnaBridge | 187:0387e8f68319 | 31 | *****************************************************************************/ |
| AnnaBridge | 187:0387e8f68319 | 32 | |
| AnnaBridge | 187:0387e8f68319 | 33 | #if defined(__ICCARM__) |
| AnnaBridge | 187:0387e8f68319 | 34 | #pragma system_include /* Treat file as system include file. */ |
| AnnaBridge | 187:0387e8f68319 | 35 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| AnnaBridge | 187:0387e8f68319 | 36 | #pragma clang system_header /* Treat file as system include file. */ |
| AnnaBridge | 187:0387e8f68319 | 37 | #endif |
| AnnaBridge | 187:0387e8f68319 | 38 | |
| AnnaBridge | 187:0387e8f68319 | 39 | /**************************************************************************//** |
| AnnaBridge | 187:0387e8f68319 | 40 | * @addtogroup Parts |
| AnnaBridge | 187:0387e8f68319 | 41 | * @{ |
| AnnaBridge | 187:0387e8f68319 | 42 | ******************************************************************************/ |
| AnnaBridge | 187:0387e8f68319 | 43 | /**************************************************************************//** |
| AnnaBridge | 187:0387e8f68319 | 44 | * @defgroup EFM32GG11B_PRS PRS |
| AnnaBridge | 187:0387e8f68319 | 45 | * @{ |
| AnnaBridge | 187:0387e8f68319 | 46 | * @brief EFM32GG11B_PRS Register Declaration |
| AnnaBridge | 187:0387e8f68319 | 47 | *****************************************************************************/ |
| AnnaBridge | 187:0387e8f68319 | 48 | /** PRS Register Declaration */ |
| AnnaBridge | 187:0387e8f68319 | 49 | typedef struct { |
| AnnaBridge | 187:0387e8f68319 | 50 | __IOM uint32_t SWPULSE; /**< Software Pulse Register */ |
| AnnaBridge | 187:0387e8f68319 | 51 | __IOM uint32_t SWLEVEL; /**< Software Level Register */ |
| AnnaBridge | 187:0387e8f68319 | 52 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
| AnnaBridge | 187:0387e8f68319 | 53 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| AnnaBridge | 187:0387e8f68319 | 54 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
| AnnaBridge | 187:0387e8f68319 | 55 | __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ |
| AnnaBridge | 187:0387e8f68319 | 56 | __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ |
| AnnaBridge | 187:0387e8f68319 | 57 | __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ |
| AnnaBridge | 187:0387e8f68319 | 58 | __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ |
| AnnaBridge | 187:0387e8f68319 | 59 | __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ |
| AnnaBridge | 187:0387e8f68319 | 60 | uint32_t RESERVED1[2]; /**< Reserved for future use **/ |
| AnnaBridge | 187:0387e8f68319 | 61 | __IOM uint32_t CTRL; /**< Control Register */ |
| AnnaBridge | 187:0387e8f68319 | 62 | __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ |
| AnnaBridge | 187:0387e8f68319 | 63 | __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ |
| AnnaBridge | 187:0387e8f68319 | 64 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| AnnaBridge | 187:0387e8f68319 | 65 | __IM uint32_t PEEK; /**< PRS Channel Values */ |
| AnnaBridge | 187:0387e8f68319 | 66 | |
| AnnaBridge | 187:0387e8f68319 | 67 | uint32_t RESERVED3[3]; /**< Reserved registers */ |
| AnnaBridge | 187:0387e8f68319 | 68 | PRS_CH_TypeDef CH[24]; /**< Channel registers */ |
| AnnaBridge | 187:0387e8f68319 | 69 | } PRS_TypeDef; /** @} */ |
| AnnaBridge | 187:0387e8f68319 | 70 | |
| AnnaBridge | 187:0387e8f68319 | 71 | /**************************************************************************//** |
| AnnaBridge | 187:0387e8f68319 | 72 | * @addtogroup EFM32GG11B_PRS |
| AnnaBridge | 187:0387e8f68319 | 73 | * @{ |
| AnnaBridge | 187:0387e8f68319 | 74 | * @defgroup EFM32GG11B_PRS_BitFields PRS Bit Fields |
| AnnaBridge | 187:0387e8f68319 | 75 | * @{ |
| AnnaBridge | 187:0387e8f68319 | 76 | *****************************************************************************/ |
| AnnaBridge | 187:0387e8f68319 | 77 | |
| AnnaBridge | 187:0387e8f68319 | 78 | /* Bit fields for PRS SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 79 | #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 80 | #define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 81 | #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 82 | #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 83 | #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 84 | #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 85 | #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 86 | #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 87 | #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 88 | #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 89 | #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 90 | #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 91 | #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 92 | #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 93 | #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 94 | #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 95 | #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 96 | #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 97 | #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 98 | #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 99 | #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 100 | #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 101 | #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 102 | #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 103 | #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 104 | #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 105 | #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 106 | #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 107 | #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 108 | #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 109 | #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 110 | #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 111 | #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 112 | #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 113 | #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 114 | #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 115 | #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 116 | #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 117 | #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 118 | #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 119 | #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 120 | #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 121 | #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 122 | #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 123 | #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 124 | #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 125 | #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 126 | #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 127 | #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 128 | #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 129 | #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 130 | #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 131 | #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 132 | #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 133 | #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 134 | #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 135 | #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 136 | #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 137 | #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 138 | #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 139 | #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 140 | #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 141 | #define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 142 | #define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 143 | #define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 144 | #define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 145 | #define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 146 | #define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 147 | #define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 148 | #define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 149 | #define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 150 | #define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 151 | #define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 152 | #define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 153 | #define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 154 | #define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 155 | #define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 156 | #define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 157 | #define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 158 | #define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 159 | #define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 160 | #define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 161 | #define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 162 | #define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 163 | #define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 164 | #define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 165 | #define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 166 | #define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 167 | #define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 168 | #define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 169 | #define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 170 | #define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 171 | #define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 172 | #define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 173 | #define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 174 | #define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 175 | #define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 176 | #define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 177 | #define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 178 | #define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 179 | #define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 180 | #define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 181 | #define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 182 | #define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 183 | #define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 184 | #define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 185 | #define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 186 | #define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 187 | #define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 188 | #define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 189 | #define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 190 | #define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 191 | #define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 192 | #define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 193 | #define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 194 | #define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 195 | #define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 196 | #define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ |
| AnnaBridge | 187:0387e8f68319 | 197 | #define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 198 | #define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ |
| AnnaBridge | 187:0387e8f68319 | 199 | #define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 200 | #define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| AnnaBridge | 187:0387e8f68319 | 201 | |
| AnnaBridge | 187:0387e8f68319 | 202 | /* Bit fields for PRS SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 203 | #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 204 | #define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 205 | #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 206 | #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 207 | #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 208 | #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 209 | #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 210 | #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 211 | #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 212 | #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 213 | #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 214 | #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 215 | #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 216 | #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 217 | #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 218 | #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 219 | #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 220 | #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 221 | #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 222 | #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 223 | #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 224 | #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 225 | #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 226 | #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 227 | #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 228 | #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 229 | #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 230 | #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 231 | #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 232 | #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 233 | #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 234 | #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 235 | #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 236 | #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 237 | #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 238 | #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 239 | #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 240 | #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 241 | #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 242 | #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 243 | #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 244 | #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 245 | #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 246 | #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 247 | #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 248 | #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 249 | #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 250 | #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 251 | #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 252 | #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 253 | #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 254 | #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 255 | #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 256 | #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 257 | #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 258 | #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 259 | #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 260 | #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 261 | #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 262 | #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 263 | #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 264 | #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 265 | #define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 266 | #define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 267 | #define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 268 | #define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 269 | #define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 270 | #define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 271 | #define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 272 | #define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 273 | #define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 274 | #define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 275 | #define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 276 | #define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 277 | #define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 278 | #define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 279 | #define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 280 | #define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 281 | #define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 282 | #define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 283 | #define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 284 | #define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 285 | #define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 286 | #define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 287 | #define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 288 | #define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 289 | #define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 290 | #define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 291 | #define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 292 | #define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 293 | #define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 294 | #define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 295 | #define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 296 | #define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 297 | #define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 298 | #define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 299 | #define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 300 | #define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 301 | #define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 302 | #define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 303 | #define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 304 | #define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 305 | #define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 306 | #define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 307 | #define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 308 | #define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 309 | #define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 310 | #define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 311 | #define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 312 | #define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 313 | #define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 314 | #define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 315 | #define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 316 | #define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 317 | #define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 318 | #define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 319 | #define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 320 | #define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ |
| AnnaBridge | 187:0387e8f68319 | 321 | #define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 322 | #define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 323 | #define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 324 | #define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| AnnaBridge | 187:0387e8f68319 | 325 | |
| AnnaBridge | 187:0387e8f68319 | 326 | /* Bit fields for PRS ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 327 | #define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 328 | #define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 329 | #define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 330 | #define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ |
| AnnaBridge | 187:0387e8f68319 | 331 | #define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ |
| AnnaBridge | 187:0387e8f68319 | 332 | #define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 333 | #define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 334 | #define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 335 | #define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ |
| AnnaBridge | 187:0387e8f68319 | 336 | #define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ |
| AnnaBridge | 187:0387e8f68319 | 337 | #define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 338 | #define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 339 | #define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 340 | #define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ |
| AnnaBridge | 187:0387e8f68319 | 341 | #define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ |
| AnnaBridge | 187:0387e8f68319 | 342 | #define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 343 | #define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 344 | #define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 345 | #define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ |
| AnnaBridge | 187:0387e8f68319 | 346 | #define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ |
| AnnaBridge | 187:0387e8f68319 | 347 | #define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 348 | #define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 349 | #define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 350 | #define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ |
| AnnaBridge | 187:0387e8f68319 | 351 | #define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ |
| AnnaBridge | 187:0387e8f68319 | 352 | #define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 353 | #define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 354 | #define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 355 | #define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ |
| AnnaBridge | 187:0387e8f68319 | 356 | #define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ |
| AnnaBridge | 187:0387e8f68319 | 357 | #define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 358 | #define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 359 | #define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 360 | #define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ |
| AnnaBridge | 187:0387e8f68319 | 361 | #define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ |
| AnnaBridge | 187:0387e8f68319 | 362 | #define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 363 | #define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 364 | #define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 365 | #define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ |
| AnnaBridge | 187:0387e8f68319 | 366 | #define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ |
| AnnaBridge | 187:0387e8f68319 | 367 | #define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 368 | #define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 369 | #define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 370 | #define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ |
| AnnaBridge | 187:0387e8f68319 | 371 | #define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ |
| AnnaBridge | 187:0387e8f68319 | 372 | #define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 373 | #define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 374 | #define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 375 | #define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ |
| AnnaBridge | 187:0387e8f68319 | 376 | #define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ |
| AnnaBridge | 187:0387e8f68319 | 377 | #define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 378 | #define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 379 | #define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 380 | #define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ |
| AnnaBridge | 187:0387e8f68319 | 381 | #define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ |
| AnnaBridge | 187:0387e8f68319 | 382 | #define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 383 | #define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 384 | #define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 385 | #define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ |
| AnnaBridge | 187:0387e8f68319 | 386 | #define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ |
| AnnaBridge | 187:0387e8f68319 | 387 | #define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 388 | #define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 389 | #define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 390 | #define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ |
| AnnaBridge | 187:0387e8f68319 | 391 | #define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ |
| AnnaBridge | 187:0387e8f68319 | 392 | #define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 393 | #define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 394 | #define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 395 | #define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ |
| AnnaBridge | 187:0387e8f68319 | 396 | #define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ |
| AnnaBridge | 187:0387e8f68319 | 397 | #define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 398 | #define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 399 | #define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 400 | #define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ |
| AnnaBridge | 187:0387e8f68319 | 401 | #define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ |
| AnnaBridge | 187:0387e8f68319 | 402 | #define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 403 | #define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 404 | #define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 405 | #define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ |
| AnnaBridge | 187:0387e8f68319 | 406 | #define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ |
| AnnaBridge | 187:0387e8f68319 | 407 | #define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 408 | #define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 409 | #define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 410 | #define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ |
| AnnaBridge | 187:0387e8f68319 | 411 | #define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ |
| AnnaBridge | 187:0387e8f68319 | 412 | #define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 413 | #define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 414 | #define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 415 | #define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ |
| AnnaBridge | 187:0387e8f68319 | 416 | #define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ |
| AnnaBridge | 187:0387e8f68319 | 417 | #define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 418 | #define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 419 | #define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 420 | #define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ |
| AnnaBridge | 187:0387e8f68319 | 421 | #define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ |
| AnnaBridge | 187:0387e8f68319 | 422 | #define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 423 | #define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 424 | #define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 425 | #define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ |
| AnnaBridge | 187:0387e8f68319 | 426 | #define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ |
| AnnaBridge | 187:0387e8f68319 | 427 | #define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 428 | #define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 429 | #define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 430 | #define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ |
| AnnaBridge | 187:0387e8f68319 | 431 | #define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ |
| AnnaBridge | 187:0387e8f68319 | 432 | #define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 433 | #define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 434 | #define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 435 | #define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ |
| AnnaBridge | 187:0387e8f68319 | 436 | #define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ |
| AnnaBridge | 187:0387e8f68319 | 437 | #define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 438 | #define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 439 | #define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 440 | #define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ |
| AnnaBridge | 187:0387e8f68319 | 441 | #define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ |
| AnnaBridge | 187:0387e8f68319 | 442 | #define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 443 | #define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 444 | #define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ |
| AnnaBridge | 187:0387e8f68319 | 445 | #define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ |
| AnnaBridge | 187:0387e8f68319 | 446 | #define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ |
| AnnaBridge | 187:0387e8f68319 | 447 | #define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 448 | #define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
| AnnaBridge | 187:0387e8f68319 | 449 | |
| AnnaBridge | 187:0387e8f68319 | 450 | /* Bit fields for PRS ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 451 | #define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 452 | #define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 453 | #define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ |
| AnnaBridge | 187:0387e8f68319 | 454 | #define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ |
| AnnaBridge | 187:0387e8f68319 | 455 | #define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 456 | #define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 457 | #define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 458 | #define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 459 | #define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 460 | #define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 461 | #define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 462 | #define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 463 | #define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 464 | #define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 465 | #define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ |
| AnnaBridge | 187:0387e8f68319 | 466 | #define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ |
| AnnaBridge | 187:0387e8f68319 | 467 | #define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 468 | #define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 469 | #define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 470 | #define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 471 | #define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 472 | #define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 473 | #define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 474 | #define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 475 | #define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 476 | #define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 477 | #define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ |
| AnnaBridge | 187:0387e8f68319 | 478 | #define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ |
| AnnaBridge | 187:0387e8f68319 | 479 | #define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 480 | #define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 481 | #define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 482 | #define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 483 | #define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 484 | #define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 485 | #define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 486 | #define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 487 | #define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 488 | #define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 489 | #define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ |
| AnnaBridge | 187:0387e8f68319 | 490 | #define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ |
| AnnaBridge | 187:0387e8f68319 | 491 | #define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 492 | #define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 493 | #define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 494 | #define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 495 | #define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 496 | #define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 497 | #define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 498 | #define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 499 | #define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 500 | #define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
| AnnaBridge | 187:0387e8f68319 | 501 | |
| AnnaBridge | 187:0387e8f68319 | 502 | /* Bit fields for PRS ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 503 | #define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 504 | #define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 505 | #define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ |
| AnnaBridge | 187:0387e8f68319 | 506 | #define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ |
| AnnaBridge | 187:0387e8f68319 | 507 | #define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 508 | #define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 509 | #define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 510 | #define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 511 | #define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 512 | #define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 513 | #define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 514 | #define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 515 | #define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ |
| AnnaBridge | 187:0387e8f68319 | 516 | #define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ |
| AnnaBridge | 187:0387e8f68319 | 517 | #define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 518 | #define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 519 | #define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 520 | #define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 521 | #define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 522 | #define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 523 | #define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 524 | #define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 525 | #define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ |
| AnnaBridge | 187:0387e8f68319 | 526 | #define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ |
| AnnaBridge | 187:0387e8f68319 | 527 | #define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 528 | #define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 529 | #define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 530 | #define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 531 | #define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 532 | #define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 533 | #define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 534 | #define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 535 | #define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ |
| AnnaBridge | 187:0387e8f68319 | 536 | #define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ |
| AnnaBridge | 187:0387e8f68319 | 537 | #define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 538 | #define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 539 | #define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 540 | #define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 541 | #define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 542 | #define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 543 | #define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 544 | #define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
| AnnaBridge | 187:0387e8f68319 | 545 | |
| AnnaBridge | 187:0387e8f68319 | 546 | /* Bit fields for PRS ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 547 | #define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 548 | #define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 549 | #define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ |
| AnnaBridge | 187:0387e8f68319 | 550 | #define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ |
| AnnaBridge | 187:0387e8f68319 | 551 | #define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 552 | #define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 553 | #define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 554 | #define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 555 | #define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 556 | #define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 557 | #define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 558 | #define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 559 | #define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ |
| AnnaBridge | 187:0387e8f68319 | 560 | #define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ |
| AnnaBridge | 187:0387e8f68319 | 561 | #define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 562 | #define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 563 | #define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 564 | #define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 565 | #define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 566 | #define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 567 | #define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 568 | #define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 569 | #define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ |
| AnnaBridge | 187:0387e8f68319 | 570 | #define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ |
| AnnaBridge | 187:0387e8f68319 | 571 | #define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 572 | #define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 573 | #define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 574 | #define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 575 | #define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 576 | #define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 577 | #define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 578 | #define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 579 | #define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ |
| AnnaBridge | 187:0387e8f68319 | 580 | #define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ |
| AnnaBridge | 187:0387e8f68319 | 581 | #define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 582 | #define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 583 | #define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 584 | #define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 585 | #define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 586 | #define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 587 | #define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 588 | #define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
| AnnaBridge | 187:0387e8f68319 | 589 | |
| AnnaBridge | 187:0387e8f68319 | 590 | /* Bit fields for PRS ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 591 | #define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 592 | #define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 593 | #define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ |
| AnnaBridge | 187:0387e8f68319 | 594 | #define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ |
| AnnaBridge | 187:0387e8f68319 | 595 | #define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 596 | #define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 597 | #define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 598 | #define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 599 | #define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 600 | #define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 601 | #define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 602 | #define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 603 | #define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ |
| AnnaBridge | 187:0387e8f68319 | 604 | #define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ |
| AnnaBridge | 187:0387e8f68319 | 605 | #define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 606 | #define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 607 | #define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 608 | #define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 609 | #define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 610 | #define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 611 | #define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 612 | #define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 613 | #define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ |
| AnnaBridge | 187:0387e8f68319 | 614 | #define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ |
| AnnaBridge | 187:0387e8f68319 | 615 | #define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 616 | #define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 617 | #define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 618 | #define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 619 | #define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 620 | #define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 621 | #define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 622 | #define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 623 | #define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ |
| AnnaBridge | 187:0387e8f68319 | 624 | #define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ |
| AnnaBridge | 187:0387e8f68319 | 625 | #define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 626 | #define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 627 | #define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 628 | #define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 629 | #define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 630 | #define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 631 | #define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 632 | #define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
| AnnaBridge | 187:0387e8f68319 | 633 | |
| AnnaBridge | 187:0387e8f68319 | 634 | /* Bit fields for PRS ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 635 | #define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 636 | #define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 637 | #define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ |
| AnnaBridge | 187:0387e8f68319 | 638 | #define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ |
| AnnaBridge | 187:0387e8f68319 | 639 | #define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 640 | #define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 641 | #define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 642 | #define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 643 | #define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 644 | #define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 645 | #define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 646 | #define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 647 | #define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ |
| AnnaBridge | 187:0387e8f68319 | 648 | #define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ |
| AnnaBridge | 187:0387e8f68319 | 649 | #define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 650 | #define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 651 | #define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 652 | #define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 653 | #define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 654 | #define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 655 | #define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 656 | #define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 657 | #define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ |
| AnnaBridge | 187:0387e8f68319 | 658 | #define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ |
| AnnaBridge | 187:0387e8f68319 | 659 | #define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 660 | #define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 661 | #define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 662 | #define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 663 | #define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 664 | #define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 665 | #define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 666 | #define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 667 | #define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ |
| AnnaBridge | 187:0387e8f68319 | 668 | #define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ |
| AnnaBridge | 187:0387e8f68319 | 669 | #define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 670 | #define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 671 | #define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 672 | #define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 673 | #define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 674 | #define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 675 | #define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 676 | #define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
| AnnaBridge | 187:0387e8f68319 | 677 | |
| AnnaBridge | 187:0387e8f68319 | 678 | /* Bit fields for PRS ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 679 | #define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 680 | #define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 681 | #define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ |
| AnnaBridge | 187:0387e8f68319 | 682 | #define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ |
| AnnaBridge | 187:0387e8f68319 | 683 | #define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 684 | #define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 685 | #define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 686 | #define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 687 | #define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 688 | #define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 689 | #define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 690 | #define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 691 | #define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ |
| AnnaBridge | 187:0387e8f68319 | 692 | #define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ |
| AnnaBridge | 187:0387e8f68319 | 693 | #define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 694 | #define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 695 | #define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 696 | #define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 697 | #define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 698 | #define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 699 | #define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 700 | #define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 701 | #define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ |
| AnnaBridge | 187:0387e8f68319 | 702 | #define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ |
| AnnaBridge | 187:0387e8f68319 | 703 | #define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 704 | #define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 705 | #define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 706 | #define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 707 | #define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 708 | #define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 709 | #define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 710 | #define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 711 | #define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ |
| AnnaBridge | 187:0387e8f68319 | 712 | #define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ |
| AnnaBridge | 187:0387e8f68319 | 713 | #define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 714 | #define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 715 | #define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 716 | #define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 717 | #define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 718 | #define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 719 | #define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 720 | #define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
| AnnaBridge | 187:0387e8f68319 | 721 | |
| AnnaBridge | 187:0387e8f68319 | 722 | /* Bit fields for PRS CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 723 | #define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 724 | #define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 725 | #define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ |
| AnnaBridge | 187:0387e8f68319 | 726 | #define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ |
| AnnaBridge | 187:0387e8f68319 | 727 | #define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ |
| AnnaBridge | 187:0387e8f68319 | 728 | #define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 729 | #define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 730 | #define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ |
| AnnaBridge | 187:0387e8f68319 | 731 | #define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ |
| AnnaBridge | 187:0387e8f68319 | 732 | #define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 733 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 734 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 735 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 736 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 737 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 738 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 739 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 740 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 741 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 742 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 743 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 744 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 745 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 746 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 747 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 748 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 749 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 750 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 751 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 752 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 753 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 754 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 755 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 756 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 757 | #define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 758 | #define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 759 | #define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 760 | #define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 761 | #define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 762 | #define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 763 | #define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 764 | #define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 765 | #define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 766 | #define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 767 | #define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 768 | #define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 769 | #define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 770 | #define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 771 | #define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 772 | #define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 773 | #define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 774 | #define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 775 | #define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 776 | #define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 777 | #define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 778 | #define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 779 | #define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 780 | #define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 781 | #define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 782 | |
| AnnaBridge | 187:0387e8f68319 | 783 | /* Bit fields for PRS DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 784 | #define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 785 | #define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 786 | #define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ |
| AnnaBridge | 187:0387e8f68319 | 787 | #define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ |
| AnnaBridge | 187:0387e8f68319 | 788 | #define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 789 | #define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 790 | #define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 791 | #define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 792 | #define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 793 | #define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 794 | #define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 795 | #define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 796 | #define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 797 | #define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 798 | #define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 799 | #define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 800 | #define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 801 | #define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 802 | #define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 803 | #define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 804 | #define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 805 | #define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 806 | #define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 807 | #define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 808 | #define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 809 | #define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 810 | #define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 811 | #define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 812 | #define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 813 | #define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 814 | #define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 815 | #define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 816 | #define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 817 | #define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 818 | #define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 819 | #define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 820 | #define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 821 | #define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 822 | #define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 823 | #define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 824 | #define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 825 | #define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 826 | #define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 827 | #define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 828 | #define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 829 | #define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 830 | #define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 831 | #define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 832 | #define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 833 | #define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 834 | #define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 835 | #define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 836 | #define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 837 | #define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ |
| AnnaBridge | 187:0387e8f68319 | 838 | |
| AnnaBridge | 187:0387e8f68319 | 839 | /* Bit fields for PRS DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 840 | #define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 841 | #define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 842 | #define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ |
| AnnaBridge | 187:0387e8f68319 | 843 | #define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ |
| AnnaBridge | 187:0387e8f68319 | 844 | #define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 845 | #define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 846 | #define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 847 | #define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 848 | #define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 849 | #define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 850 | #define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 851 | #define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 852 | #define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 853 | #define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 854 | #define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 855 | #define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 856 | #define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 857 | #define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 858 | #define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 859 | #define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 860 | #define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 861 | #define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 862 | #define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 863 | #define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 864 | #define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 865 | #define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 866 | #define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 867 | #define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 868 | #define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 869 | #define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 870 | #define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 871 | #define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 872 | #define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 873 | #define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 874 | #define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 875 | #define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 876 | #define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 877 | #define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 878 | #define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 879 | #define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 880 | #define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 881 | #define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 882 | #define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 883 | #define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 884 | #define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 885 | #define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 886 | #define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 887 | #define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 888 | #define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 889 | #define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 890 | #define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 891 | #define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 892 | #define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 893 | #define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ |
| AnnaBridge | 187:0387e8f68319 | 894 | |
| AnnaBridge | 187:0387e8f68319 | 895 | /* Bit fields for PRS PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 896 | #define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 897 | #define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 898 | #define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 899 | #define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ |
| AnnaBridge | 187:0387e8f68319 | 900 | #define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ |
| AnnaBridge | 187:0387e8f68319 | 901 | #define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 902 | #define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 903 | #define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 904 | #define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ |
| AnnaBridge | 187:0387e8f68319 | 905 | #define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ |
| AnnaBridge | 187:0387e8f68319 | 906 | #define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 907 | #define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 908 | #define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 909 | #define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ |
| AnnaBridge | 187:0387e8f68319 | 910 | #define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ |
| AnnaBridge | 187:0387e8f68319 | 911 | #define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 912 | #define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 913 | #define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 914 | #define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ |
| AnnaBridge | 187:0387e8f68319 | 915 | #define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ |
| AnnaBridge | 187:0387e8f68319 | 916 | #define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 917 | #define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 918 | #define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 919 | #define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ |
| AnnaBridge | 187:0387e8f68319 | 920 | #define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ |
| AnnaBridge | 187:0387e8f68319 | 921 | #define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 922 | #define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 923 | #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 924 | #define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ |
| AnnaBridge | 187:0387e8f68319 | 925 | #define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ |
| AnnaBridge | 187:0387e8f68319 | 926 | #define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 927 | #define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 928 | #define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 929 | #define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ |
| AnnaBridge | 187:0387e8f68319 | 930 | #define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ |
| AnnaBridge | 187:0387e8f68319 | 931 | #define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 932 | #define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 933 | #define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 934 | #define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ |
| AnnaBridge | 187:0387e8f68319 | 935 | #define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ |
| AnnaBridge | 187:0387e8f68319 | 936 | #define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 937 | #define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 938 | #define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 939 | #define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ |
| AnnaBridge | 187:0387e8f68319 | 940 | #define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ |
| AnnaBridge | 187:0387e8f68319 | 941 | #define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 942 | #define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 943 | #define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 944 | #define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ |
| AnnaBridge | 187:0387e8f68319 | 945 | #define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ |
| AnnaBridge | 187:0387e8f68319 | 946 | #define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 947 | #define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 948 | #define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 949 | #define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ |
| AnnaBridge | 187:0387e8f68319 | 950 | #define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ |
| AnnaBridge | 187:0387e8f68319 | 951 | #define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 952 | #define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 953 | #define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 954 | #define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ |
| AnnaBridge | 187:0387e8f68319 | 955 | #define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ |
| AnnaBridge | 187:0387e8f68319 | 956 | #define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 957 | #define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 958 | #define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 959 | #define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ |
| AnnaBridge | 187:0387e8f68319 | 960 | #define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ |
| AnnaBridge | 187:0387e8f68319 | 961 | #define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 962 | #define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 963 | #define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 964 | #define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ |
| AnnaBridge | 187:0387e8f68319 | 965 | #define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ |
| AnnaBridge | 187:0387e8f68319 | 966 | #define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 967 | #define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 968 | #define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 969 | #define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ |
| AnnaBridge | 187:0387e8f68319 | 970 | #define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ |
| AnnaBridge | 187:0387e8f68319 | 971 | #define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 972 | #define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 973 | #define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 974 | #define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ |
| AnnaBridge | 187:0387e8f68319 | 975 | #define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ |
| AnnaBridge | 187:0387e8f68319 | 976 | #define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 977 | #define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 978 | #define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 979 | #define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ |
| AnnaBridge | 187:0387e8f68319 | 980 | #define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ |
| AnnaBridge | 187:0387e8f68319 | 981 | #define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 982 | #define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 983 | #define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 984 | #define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ |
| AnnaBridge | 187:0387e8f68319 | 985 | #define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ |
| AnnaBridge | 187:0387e8f68319 | 986 | #define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 987 | #define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 988 | #define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 989 | #define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ |
| AnnaBridge | 187:0387e8f68319 | 990 | #define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ |
| AnnaBridge | 187:0387e8f68319 | 991 | #define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 992 | #define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 993 | #define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 994 | #define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ |
| AnnaBridge | 187:0387e8f68319 | 995 | #define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ |
| AnnaBridge | 187:0387e8f68319 | 996 | #define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 997 | #define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 998 | #define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 999 | #define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1000 | #define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1001 | #define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1002 | #define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1003 | #define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 1004 | #define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1005 | #define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1006 | #define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1007 | #define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1008 | #define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 1009 | #define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1010 | #define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1011 | #define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1012 | #define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1013 | #define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ |
| AnnaBridge | 187:0387e8f68319 | 1014 | #define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1015 | #define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ |
| AnnaBridge | 187:0387e8f68319 | 1016 | #define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1017 | #define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ |
| AnnaBridge | 187:0387e8f68319 | 1018 | |
| AnnaBridge | 187:0387e8f68319 | 1019 | /* Bit fields for PRS CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1020 | #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1021 | #define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1022 | #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ |
| AnnaBridge | 187:0387e8f68319 | 1023 | #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ |
| AnnaBridge | 187:0387e8f68319 | 1024 | #define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1025 | #define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1026 | #define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1027 | #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1028 | #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1029 | #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1030 | #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1031 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1032 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1033 | #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1034 | #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1035 | #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1036 | #define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1037 | #define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1038 | #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1039 | #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1040 | #define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1041 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1042 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1043 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1044 | #define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1045 | #define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1046 | #define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1047 | #define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1048 | #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1049 | #define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1050 | #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1051 | #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1052 | #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1053 | #define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1054 | #define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1055 | #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1056 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1057 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1058 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1059 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1060 | #define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1061 | #define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1062 | #define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1063 | #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1064 | #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1065 | #define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1066 | #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1067 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1068 | #define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1069 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1070 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1071 | #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1072 | #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1073 | #define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1074 | #define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1075 | #define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1076 | #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1077 | #define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1078 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1079 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1080 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1081 | #define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1082 | #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1083 | #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1084 | #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1085 | #define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1086 | #define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1087 | #define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1088 | #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1089 | #define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1090 | #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1091 | #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1092 | #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1093 | #define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1094 | #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1095 | #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1096 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1097 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1098 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1099 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1100 | #define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1101 | #define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1102 | #define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1103 | #define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1104 | #define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1105 | #define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1106 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1107 | #define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1108 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1109 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1110 | #define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1111 | #define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1112 | #define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1113 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1114 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1115 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1116 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1117 | #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1118 | #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1119 | #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1120 | #define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1121 | #define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1122 | #define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1123 | #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1124 | #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1125 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1126 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1127 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1128 | #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1129 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1130 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1131 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1132 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1133 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1134 | #define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1135 | #define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1136 | #define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1137 | #define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1138 | #define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1139 | #define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1140 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1141 | #define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1142 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1143 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1144 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1145 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1146 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1147 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1148 | #define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1149 | #define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1150 | #define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1151 | #define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1152 | #define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1153 | #define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1154 | #define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1155 | #define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1156 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1157 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1158 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1159 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1160 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1161 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1162 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1163 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1164 | #define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1165 | #define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1166 | #define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1167 | #define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1168 | #define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1169 | #define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1170 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1171 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1172 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1173 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1174 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1175 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1176 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1177 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1178 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1179 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1180 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1181 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1182 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1183 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1184 | #define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1185 | #define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1186 | #define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1187 | #define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1188 | #define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1189 | #define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1190 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1191 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1192 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1193 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1194 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1195 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1196 | #define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1197 | #define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1198 | #define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1199 | #define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1200 | #define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1201 | #define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1202 | #define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1203 | #define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1204 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1205 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1206 | #define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1207 | #define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1208 | #define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1209 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1210 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1211 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1212 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1213 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1214 | #define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1215 | #define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1216 | #define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1217 | #define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1218 | #define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1219 | #define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1220 | #define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1221 | #define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1222 | #define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1223 | #define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1224 | #define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1225 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1226 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1227 | #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1228 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1229 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1230 | #define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1231 | #define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1232 | #define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1233 | #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1234 | #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1235 | #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1236 | #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1237 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1238 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1239 | #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1240 | #define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1241 | #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1242 | #define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1243 | #define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1244 | #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1245 | #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1246 | #define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1247 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1248 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1249 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1250 | #define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1251 | #define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1252 | #define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1253 | #define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1254 | #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1255 | #define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1256 | #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1257 | #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1258 | #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1259 | #define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1260 | #define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1261 | #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1262 | #define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1263 | #define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1264 | #define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1265 | #define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1266 | #define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1267 | #define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1268 | #define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1269 | #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1270 | #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1271 | #define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1272 | #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1273 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1274 | #define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1275 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1276 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1277 | #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1278 | #define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1279 | #define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1280 | #define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1281 | #define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1282 | #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1283 | #define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1284 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1285 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1286 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1287 | #define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1288 | #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1289 | #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1290 | #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1291 | #define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1292 | #define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1293 | #define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1294 | #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1295 | #define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1296 | #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1297 | #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1298 | #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1299 | #define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1300 | #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1301 | #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1302 | #define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1303 | #define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1304 | #define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1305 | #define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1306 | #define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1307 | #define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1308 | #define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1309 | #define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1310 | #define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1311 | #define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1312 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1313 | #define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1314 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1315 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1316 | #define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1317 | #define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1318 | #define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1319 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1320 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1321 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1322 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1323 | #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1324 | #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1325 | #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1326 | #define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1327 | #define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1328 | #define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1329 | #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1330 | #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1331 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1332 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1333 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1334 | #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1335 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1336 | #define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1337 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1338 | #define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1339 | #define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1340 | #define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1341 | #define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1342 | #define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1343 | #define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1344 | #define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1345 | #define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1346 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1347 | #define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1348 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1349 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1350 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1351 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1352 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1353 | #define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1354 | #define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1355 | #define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1356 | #define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1357 | #define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1358 | #define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1359 | #define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1360 | #define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1361 | #define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1362 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1363 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1364 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1365 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1366 | #define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1367 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1368 | #define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1369 | #define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1370 | #define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1371 | #define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1372 | #define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1373 | #define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1374 | #define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1375 | #define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1376 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1377 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1378 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1379 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1380 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1381 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1382 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1383 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1384 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1385 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1386 | #define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1387 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1388 | #define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1389 | #define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1390 | #define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1391 | #define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1392 | #define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1393 | #define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1394 | #define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1395 | #define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1396 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1397 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1398 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1399 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1400 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1401 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1402 | #define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1403 | #define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1404 | #define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1405 | #define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1406 | #define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1407 | #define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1408 | #define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1409 | #define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1410 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1411 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1412 | #define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1413 | #define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1414 | #define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1415 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1416 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1417 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1418 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1419 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1420 | #define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1421 | #define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1422 | #define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1423 | #define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1424 | #define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1425 | #define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1426 | #define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1427 | #define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1428 | #define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1429 | #define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1430 | #define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1431 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1432 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1433 | #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1434 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1435 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1436 | #define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ |
| AnnaBridge | 187:0387e8f68319 | 1437 | #define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ |
| AnnaBridge | 187:0387e8f68319 | 1438 | #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1439 | #define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1440 | #define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1441 | #define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1442 | #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1443 | #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1444 | #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1445 | #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1446 | #define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1447 | #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1448 | #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1449 | #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1450 | #define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1451 | #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1452 | #define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1453 | #define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1454 | #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1455 | #define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1456 | #define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1457 | #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1458 | #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1459 | #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1460 | #define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1461 | #define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1462 | #define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1463 | #define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1464 | #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1465 | #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1466 | #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1467 | #define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1468 | #define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1469 | #define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1470 | #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1471 | #define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1472 | #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1473 | #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1474 | #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1475 | #define _PRS_CH_CTRL_SOURCESEL_USB 0x00000040UL /**< Mode USB for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1476 | #define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1477 | #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1478 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1479 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1480 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1481 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1482 | #define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1483 | #define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1484 | #define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1485 | #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1486 | #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1487 | #define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1488 | #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1489 | #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1490 | #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1491 | #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1492 | #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1493 | #define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1494 | #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1495 | #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1496 | #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1497 | #define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1498 | #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1499 | #define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1500 | #define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1501 | #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1502 | #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1503 | #define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1504 | #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1505 | #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1506 | #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1507 | #define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1508 | #define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1509 | #define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1510 | #define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1511 | #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1512 | #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1513 | #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1514 | #define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1515 | #define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1516 | #define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1517 | #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1518 | #define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1519 | #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1520 | #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1521 | #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1522 | #define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 8) /**< Shifted mode USB for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1523 | #define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1524 | #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1525 | #define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1526 | #define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1527 | #define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1528 | #define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1529 | #define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1530 | #define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1531 | #define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1532 | #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ |
| AnnaBridge | 187:0387e8f68319 | 1533 | #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ |
| AnnaBridge | 187:0387e8f68319 | 1534 | #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1535 | #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1536 | #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1537 | #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1538 | #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1539 | #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1540 | #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1541 | #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1542 | #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1543 | #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1544 | #define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ |
| AnnaBridge | 187:0387e8f68319 | 1545 | #define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ |
| AnnaBridge | 187:0387e8f68319 | 1546 | #define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ |
| AnnaBridge | 187:0387e8f68319 | 1547 | #define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1548 | #define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1549 | #define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ |
| AnnaBridge | 187:0387e8f68319 | 1550 | #define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ |
| AnnaBridge | 187:0387e8f68319 | 1551 | #define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ |
| AnnaBridge | 187:0387e8f68319 | 1552 | #define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1553 | #define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1554 | #define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ |
| AnnaBridge | 187:0387e8f68319 | 1555 | #define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ |
| AnnaBridge | 187:0387e8f68319 | 1556 | #define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ |
| AnnaBridge | 187:0387e8f68319 | 1557 | #define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1558 | #define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1559 | #define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ |
| AnnaBridge | 187:0387e8f68319 | 1560 | #define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ |
| AnnaBridge | 187:0387e8f68319 | 1561 | #define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ |
| AnnaBridge | 187:0387e8f68319 | 1562 | #define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1563 | #define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1564 | #define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */ |
| AnnaBridge | 187:0387e8f68319 | 1565 | #define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ |
| AnnaBridge | 187:0387e8f68319 | 1566 | #define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ |
| AnnaBridge | 187:0387e8f68319 | 1567 | #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1568 | #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| AnnaBridge | 187:0387e8f68319 | 1569 | |
| AnnaBridge | 187:0387e8f68319 | 1570 | /** @} */ |
| AnnaBridge | 187:0387e8f68319 | 1571 | /** @} End of group EFM32GG11B_PRS */ |
| AnnaBridge | 187:0387e8f68319 | 1572 | /** @} End of group Parts */ |
