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mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/efm32gg11b_can.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 187:0387e8f68319 1 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 2 * @file efm32gg11b_can.h
AnnaBridge 187:0387e8f68319 3 * @brief EFM32GG11B_CAN register and bit field definitions
AnnaBridge 187:0387e8f68319 4 * @version 5.3.2
AnnaBridge 187:0387e8f68319 5 ******************************************************************************
AnnaBridge 187:0387e8f68319 6 * # License
AnnaBridge 187:0387e8f68319 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 187:0387e8f68319 8 ******************************************************************************
AnnaBridge 187:0387e8f68319 9 *
AnnaBridge 187:0387e8f68319 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 187:0387e8f68319 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 187:0387e8f68319 12 * freely, subject to the following restrictions:
AnnaBridge 187:0387e8f68319 13 *
AnnaBridge 187:0387e8f68319 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 187:0387e8f68319 15 * claim that you wrote the original software.@n
AnnaBridge 187:0387e8f68319 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 187:0387e8f68319 17 * misrepresented as being the original software.@n
AnnaBridge 187:0387e8f68319 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 187:0387e8f68319 19 *
AnnaBridge 187:0387e8f68319 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 187:0387e8f68319 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 187:0387e8f68319 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 187:0387e8f68319 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 187:0387e8f68319 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 187:0387e8f68319 25 * infringement of any proprietary rights of a third party.
AnnaBridge 187:0387e8f68319 26 *
AnnaBridge 187:0387e8f68319 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 187:0387e8f68319 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 187:0387e8f68319 29 * any third party, arising from your use of this Software.
AnnaBridge 187:0387e8f68319 30 *
AnnaBridge 187:0387e8f68319 31 *****************************************************************************/
AnnaBridge 187:0387e8f68319 32
AnnaBridge 187:0387e8f68319 33 #if defined(__ICCARM__)
AnnaBridge 187:0387e8f68319 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 187:0387e8f68319 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 187:0387e8f68319 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 187:0387e8f68319 37 #endif
AnnaBridge 187:0387e8f68319 38
AnnaBridge 187:0387e8f68319 39 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 40 * @addtogroup Parts
AnnaBridge 187:0387e8f68319 41 * @{
AnnaBridge 187:0387e8f68319 42 ******************************************************************************/
AnnaBridge 187:0387e8f68319 43 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 44 * @defgroup EFM32GG11B_CAN CAN
AnnaBridge 187:0387e8f68319 45 * @{
AnnaBridge 187:0387e8f68319 46 * @brief EFM32GG11B_CAN Register Declaration
AnnaBridge 187:0387e8f68319 47 *****************************************************************************/
AnnaBridge 187:0387e8f68319 48 /** CAN Register Declaration */
AnnaBridge 187:0387e8f68319 49 typedef struct {
AnnaBridge 187:0387e8f68319 50 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 187:0387e8f68319 51 __IOM uint32_t STATUS; /**< Status Register */
AnnaBridge 187:0387e8f68319 52 __IM uint32_t ERRCNT; /**< Error Count Register */
AnnaBridge 187:0387e8f68319 53 __IOM uint32_t BITTIMING; /**< Bit Timing Register */
AnnaBridge 187:0387e8f68319 54 __IM uint32_t INTID; /**< Interrupt Identification Register */
AnnaBridge 187:0387e8f68319 55 __IOM uint32_t TEST; /**< Test Register */
AnnaBridge 187:0387e8f68319 56 __IOM uint32_t BRPE; /**< BRP Extension Register */
AnnaBridge 187:0387e8f68319 57 __IM uint32_t TRANSREQ; /**< Transmission Request Register */
AnnaBridge 187:0387e8f68319 58 __IM uint32_t MESSAGEDATA; /**< New Data Register */
AnnaBridge 187:0387e8f68319 59
AnnaBridge 187:0387e8f68319 60 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 187:0387e8f68319 61 __IM uint32_t MESSAGESTATE; /**< Message Valid Register */
AnnaBridge 187:0387e8f68319 62 __IOM uint32_t CONFIG; /**< Configuration Register */
AnnaBridge 187:0387e8f68319 63 __IM uint32_t IF0IF; /**< Message Object Interrupt Flag Register */
AnnaBridge 187:0387e8f68319 64 __IOM uint32_t IF0IFS; /**< Message Object Interrupt Flag Set Register */
AnnaBridge 187:0387e8f68319 65 __IOM uint32_t IF0IFC; /**< Message Object Interrupt Flag Clear Register */
AnnaBridge 187:0387e8f68319 66 __IOM uint32_t IF0IEN; /**< Message Object Interrupt Enable Register */
AnnaBridge 187:0387e8f68319 67 __IM uint32_t IF1IF; /**< Status Interrupt Flag Register */
AnnaBridge 187:0387e8f68319 68 __IOM uint32_t IF1IFS; /**< Message Object Interrupt Flag Set Register */
AnnaBridge 187:0387e8f68319 69 __IOM uint32_t IF1IFC; /**< Message Object Interrupt Flag Clear Register */
AnnaBridge 187:0387e8f68319 70 __IOM uint32_t IF1IEN; /**< Status Interrupt Enable Register */
AnnaBridge 187:0387e8f68319 71 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 187:0387e8f68319 72
AnnaBridge 187:0387e8f68319 73 uint32_t RESERVED1[3]; /**< Reserved registers */
AnnaBridge 187:0387e8f68319 74 CAN_MIR_TypeDef MIR[2]; /**< Interface Registers */
AnnaBridge 187:0387e8f68319 75 } CAN_TypeDef; /** @} */
AnnaBridge 187:0387e8f68319 76
AnnaBridge 187:0387e8f68319 77 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 78 * @addtogroup EFM32GG11B_CAN
AnnaBridge 187:0387e8f68319 79 * @{
AnnaBridge 187:0387e8f68319 80 * @defgroup EFM32GG11B_CAN_BitFields CAN Bit Fields
AnnaBridge 187:0387e8f68319 81 * @{
AnnaBridge 187:0387e8f68319 82 *****************************************************************************/
AnnaBridge 187:0387e8f68319 83
AnnaBridge 187:0387e8f68319 84 /* Bit fields for CAN CTRL */
AnnaBridge 187:0387e8f68319 85 #define _CAN_CTRL_RESETVALUE 0x00000001UL /**< Default value for CAN_CTRL */
AnnaBridge 187:0387e8f68319 86 #define _CAN_CTRL_MASK 0x000000EFUL /**< Mask for CAN_CTRL */
AnnaBridge 187:0387e8f68319 87 #define CAN_CTRL_INIT (0x1UL << 0) /**< Initialize */
AnnaBridge 187:0387e8f68319 88 #define _CAN_CTRL_INIT_SHIFT 0 /**< Shift value for CAN_INIT */
AnnaBridge 187:0387e8f68319 89 #define _CAN_CTRL_INIT_MASK 0x1UL /**< Bit mask for CAN_INIT */
AnnaBridge 187:0387e8f68319 90 #define _CAN_CTRL_INIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 91 #define CAN_CTRL_INIT_DEFAULT (_CAN_CTRL_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 92 #define CAN_CTRL_IE (0x1UL << 1) /**< Module Interrupt Enable */
AnnaBridge 187:0387e8f68319 93 #define _CAN_CTRL_IE_SHIFT 1 /**< Shift value for CAN_IE */
AnnaBridge 187:0387e8f68319 94 #define _CAN_CTRL_IE_MASK 0x2UL /**< Bit mask for CAN_IE */
AnnaBridge 187:0387e8f68319 95 #define _CAN_CTRL_IE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 96 #define CAN_CTRL_IE_DEFAULT (_CAN_CTRL_IE_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 97 #define CAN_CTRL_SIE (0x1UL << 2) /**< Status Change Interrupt Enable */
AnnaBridge 187:0387e8f68319 98 #define _CAN_CTRL_SIE_SHIFT 2 /**< Shift value for CAN_SIE */
AnnaBridge 187:0387e8f68319 99 #define _CAN_CTRL_SIE_MASK 0x4UL /**< Bit mask for CAN_SIE */
AnnaBridge 187:0387e8f68319 100 #define _CAN_CTRL_SIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 101 #define CAN_CTRL_SIE_DEFAULT (_CAN_CTRL_SIE_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 102 #define CAN_CTRL_EIE (0x1UL << 3) /**< Error Interrupt Enable */
AnnaBridge 187:0387e8f68319 103 #define _CAN_CTRL_EIE_SHIFT 3 /**< Shift value for CAN_EIE */
AnnaBridge 187:0387e8f68319 104 #define _CAN_CTRL_EIE_MASK 0x8UL /**< Bit mask for CAN_EIE */
AnnaBridge 187:0387e8f68319 105 #define _CAN_CTRL_EIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 106 #define CAN_CTRL_EIE_DEFAULT (_CAN_CTRL_EIE_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 107 #define CAN_CTRL_DAR (0x1UL << 5) /**< Disable Automatic Retransmission */
AnnaBridge 187:0387e8f68319 108 #define _CAN_CTRL_DAR_SHIFT 5 /**< Shift value for CAN_DAR */
AnnaBridge 187:0387e8f68319 109 #define _CAN_CTRL_DAR_MASK 0x20UL /**< Bit mask for CAN_DAR */
AnnaBridge 187:0387e8f68319 110 #define _CAN_CTRL_DAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 111 #define CAN_CTRL_DAR_DEFAULT (_CAN_CTRL_DAR_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 112 #define CAN_CTRL_CCE (0x1UL << 6) /**< Configuration Change Enable */
AnnaBridge 187:0387e8f68319 113 #define _CAN_CTRL_CCE_SHIFT 6 /**< Shift value for CAN_CCE */
AnnaBridge 187:0387e8f68319 114 #define _CAN_CTRL_CCE_MASK 0x40UL /**< Bit mask for CAN_CCE */
AnnaBridge 187:0387e8f68319 115 #define _CAN_CTRL_CCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 116 #define CAN_CTRL_CCE_DEFAULT (_CAN_CTRL_CCE_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 117 #define CAN_CTRL_TEST (0x1UL << 7) /**< Test Mode Enable Write access to the Test Register is enabled by setting bit test in the CAN Control Register */
AnnaBridge 187:0387e8f68319 118 #define _CAN_CTRL_TEST_SHIFT 7 /**< Shift value for CAN_TEST */
AnnaBridge 187:0387e8f68319 119 #define _CAN_CTRL_TEST_MASK 0x80UL /**< Bit mask for CAN_TEST */
AnnaBridge 187:0387e8f68319 120 #define _CAN_CTRL_TEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 121 #define CAN_CTRL_TEST_DEFAULT (_CAN_CTRL_TEST_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_CTRL */
AnnaBridge 187:0387e8f68319 122
AnnaBridge 187:0387e8f68319 123 /* Bit fields for CAN STATUS */
AnnaBridge 187:0387e8f68319 124 #define _CAN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CAN_STATUS */
AnnaBridge 187:0387e8f68319 125 #define _CAN_STATUS_MASK 0x000000FFUL /**< Mask for CAN_STATUS */
AnnaBridge 187:0387e8f68319 126 #define _CAN_STATUS_LEC_SHIFT 0 /**< Shift value for CAN_LEC */
AnnaBridge 187:0387e8f68319 127 #define _CAN_STATUS_LEC_MASK 0x7UL /**< Bit mask for CAN_LEC */
AnnaBridge 187:0387e8f68319 128 #define _CAN_STATUS_LEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 129 #define _CAN_STATUS_LEC_NONE 0x00000000UL /**< Mode NONE for CAN_STATUS */
AnnaBridge 187:0387e8f68319 130 #define _CAN_STATUS_LEC_STUFF 0x00000001UL /**< Mode STUFF for CAN_STATUS */
AnnaBridge 187:0387e8f68319 131 #define _CAN_STATUS_LEC_FORM 0x00000002UL /**< Mode FORM for CAN_STATUS */
AnnaBridge 187:0387e8f68319 132 #define _CAN_STATUS_LEC_ACK 0x00000003UL /**< Mode ACK for CAN_STATUS */
AnnaBridge 187:0387e8f68319 133 #define _CAN_STATUS_LEC_BIT1 0x00000004UL /**< Mode BIT1 for CAN_STATUS */
AnnaBridge 187:0387e8f68319 134 #define _CAN_STATUS_LEC_BIT0 0x00000005UL /**< Mode BIT0 for CAN_STATUS */
AnnaBridge 187:0387e8f68319 135 #define _CAN_STATUS_LEC_CRC 0x00000006UL /**< Mode CRC for CAN_STATUS */
AnnaBridge 187:0387e8f68319 136 #define _CAN_STATUS_LEC_UNUSED 0x00000007UL /**< Mode UNUSED for CAN_STATUS */
AnnaBridge 187:0387e8f68319 137 #define CAN_STATUS_LEC_DEFAULT (_CAN_STATUS_LEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 138 #define CAN_STATUS_LEC_NONE (_CAN_STATUS_LEC_NONE << 0) /**< Shifted mode NONE for CAN_STATUS */
AnnaBridge 187:0387e8f68319 139 #define CAN_STATUS_LEC_STUFF (_CAN_STATUS_LEC_STUFF << 0) /**< Shifted mode STUFF for CAN_STATUS */
AnnaBridge 187:0387e8f68319 140 #define CAN_STATUS_LEC_FORM (_CAN_STATUS_LEC_FORM << 0) /**< Shifted mode FORM for CAN_STATUS */
AnnaBridge 187:0387e8f68319 141 #define CAN_STATUS_LEC_ACK (_CAN_STATUS_LEC_ACK << 0) /**< Shifted mode ACK for CAN_STATUS */
AnnaBridge 187:0387e8f68319 142 #define CAN_STATUS_LEC_BIT1 (_CAN_STATUS_LEC_BIT1 << 0) /**< Shifted mode BIT1 for CAN_STATUS */
AnnaBridge 187:0387e8f68319 143 #define CAN_STATUS_LEC_BIT0 (_CAN_STATUS_LEC_BIT0 << 0) /**< Shifted mode BIT0 for CAN_STATUS */
AnnaBridge 187:0387e8f68319 144 #define CAN_STATUS_LEC_CRC (_CAN_STATUS_LEC_CRC << 0) /**< Shifted mode CRC for CAN_STATUS */
AnnaBridge 187:0387e8f68319 145 #define CAN_STATUS_LEC_UNUSED (_CAN_STATUS_LEC_UNUSED << 0) /**< Shifted mode UNUSED for CAN_STATUS */
AnnaBridge 187:0387e8f68319 146 #define CAN_STATUS_TXOK (0x1UL << 3) /**< Transmitted a message successfully */
AnnaBridge 187:0387e8f68319 147 #define _CAN_STATUS_TXOK_SHIFT 3 /**< Shift value for CAN_TXOK */
AnnaBridge 187:0387e8f68319 148 #define _CAN_STATUS_TXOK_MASK 0x8UL /**< Bit mask for CAN_TXOK */
AnnaBridge 187:0387e8f68319 149 #define _CAN_STATUS_TXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 150 #define CAN_STATUS_TXOK_DEFAULT (_CAN_STATUS_TXOK_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 151 #define CAN_STATUS_RXOK (0x1UL << 4) /**< Received a Message Successfully */
AnnaBridge 187:0387e8f68319 152 #define _CAN_STATUS_RXOK_SHIFT 4 /**< Shift value for CAN_RXOK */
AnnaBridge 187:0387e8f68319 153 #define _CAN_STATUS_RXOK_MASK 0x10UL /**< Bit mask for CAN_RXOK */
AnnaBridge 187:0387e8f68319 154 #define _CAN_STATUS_RXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 155 #define CAN_STATUS_RXOK_DEFAULT (_CAN_STATUS_RXOK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 156 #define CAN_STATUS_EPASS (0x1UL << 5) /**< Error Passive */
AnnaBridge 187:0387e8f68319 157 #define _CAN_STATUS_EPASS_SHIFT 5 /**< Shift value for CAN_EPASS */
AnnaBridge 187:0387e8f68319 158 #define _CAN_STATUS_EPASS_MASK 0x20UL /**< Bit mask for CAN_EPASS */
AnnaBridge 187:0387e8f68319 159 #define _CAN_STATUS_EPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 160 #define CAN_STATUS_EPASS_DEFAULT (_CAN_STATUS_EPASS_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 161 #define CAN_STATUS_EWARN (0x1UL << 6) /**< Warning Status */
AnnaBridge 187:0387e8f68319 162 #define _CAN_STATUS_EWARN_SHIFT 6 /**< Shift value for CAN_EWARN */
AnnaBridge 187:0387e8f68319 163 #define _CAN_STATUS_EWARN_MASK 0x40UL /**< Bit mask for CAN_EWARN */
AnnaBridge 187:0387e8f68319 164 #define _CAN_STATUS_EWARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 165 #define CAN_STATUS_EWARN_DEFAULT (_CAN_STATUS_EWARN_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 166 #define CAN_STATUS_BOFF (0x1UL << 7) /**< Bus Off Status */
AnnaBridge 187:0387e8f68319 167 #define _CAN_STATUS_BOFF_SHIFT 7 /**< Shift value for CAN_BOFF */
AnnaBridge 187:0387e8f68319 168 #define _CAN_STATUS_BOFF_MASK 0x80UL /**< Bit mask for CAN_BOFF */
AnnaBridge 187:0387e8f68319 169 #define _CAN_STATUS_BOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 170 #define CAN_STATUS_BOFF_DEFAULT (_CAN_STATUS_BOFF_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_STATUS */
AnnaBridge 187:0387e8f68319 171
AnnaBridge 187:0387e8f68319 172 /* Bit fields for CAN ERRCNT */
AnnaBridge 187:0387e8f68319 173 #define _CAN_ERRCNT_RESETVALUE 0x00000000UL /**< Default value for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 174 #define _CAN_ERRCNT_MASK 0x0000FFFFUL /**< Mask for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 175 #define _CAN_ERRCNT_TEC_SHIFT 0 /**< Shift value for CAN_TEC */
AnnaBridge 187:0387e8f68319 176 #define _CAN_ERRCNT_TEC_MASK 0xFFUL /**< Bit mask for CAN_TEC */
AnnaBridge 187:0387e8f68319 177 #define _CAN_ERRCNT_TEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 178 #define CAN_ERRCNT_TEC_DEFAULT (_CAN_ERRCNT_TEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 179 #define _CAN_ERRCNT_REC_SHIFT 8 /**< Shift value for CAN_REC */
AnnaBridge 187:0387e8f68319 180 #define _CAN_ERRCNT_REC_MASK 0x7F00UL /**< Bit mask for CAN_REC */
AnnaBridge 187:0387e8f68319 181 #define _CAN_ERRCNT_REC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 182 #define CAN_ERRCNT_REC_DEFAULT (_CAN_ERRCNT_REC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 183 #define CAN_ERRCNT_RECERRP (0x1UL << 15) /**< Receive Error Passive */
AnnaBridge 187:0387e8f68319 184 #define _CAN_ERRCNT_RECERRP_SHIFT 15 /**< Shift value for CAN_RECERRP */
AnnaBridge 187:0387e8f68319 185 #define _CAN_ERRCNT_RECERRP_MASK 0x8000UL /**< Bit mask for CAN_RECERRP */
AnnaBridge 187:0387e8f68319 186 #define _CAN_ERRCNT_RECERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 187 #define _CAN_ERRCNT_RECERRP_FALSE 0x00000000UL /**< Mode FALSE for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 188 #define _CAN_ERRCNT_RECERRP_TRUE 0x00000001UL /**< Mode TRUE for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 189 #define CAN_ERRCNT_RECERRP_DEFAULT (_CAN_ERRCNT_RECERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 190 #define CAN_ERRCNT_RECERRP_FALSE (_CAN_ERRCNT_RECERRP_FALSE << 15) /**< Shifted mode FALSE for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 191 #define CAN_ERRCNT_RECERRP_TRUE (_CAN_ERRCNT_RECERRP_TRUE << 15) /**< Shifted mode TRUE for CAN_ERRCNT */
AnnaBridge 187:0387e8f68319 192
AnnaBridge 187:0387e8f68319 193 /* Bit fields for CAN BITTIMING */
AnnaBridge 187:0387e8f68319 194 #define _CAN_BITTIMING_RESETVALUE 0x00002301UL /**< Default value for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 195 #define _CAN_BITTIMING_MASK 0x00007FFFUL /**< Mask for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 196 #define _CAN_BITTIMING_BRP_SHIFT 0 /**< Shift value for CAN_BRP */
AnnaBridge 187:0387e8f68319 197 #define _CAN_BITTIMING_BRP_MASK 0x3FUL /**< Bit mask for CAN_BRP */
AnnaBridge 187:0387e8f68319 198 #define _CAN_BITTIMING_BRP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 199 #define CAN_BITTIMING_BRP_DEFAULT (_CAN_BITTIMING_BRP_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 200 #define _CAN_BITTIMING_SJW_SHIFT 6 /**< Shift value for CAN_SJW */
AnnaBridge 187:0387e8f68319 201 #define _CAN_BITTIMING_SJW_MASK 0xC0UL /**< Bit mask for CAN_SJW */
AnnaBridge 187:0387e8f68319 202 #define _CAN_BITTIMING_SJW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 203 #define CAN_BITTIMING_SJW_DEFAULT (_CAN_BITTIMING_SJW_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 204 #define _CAN_BITTIMING_TSEG1_SHIFT 8 /**< Shift value for CAN_TSEG1 */
AnnaBridge 187:0387e8f68319 205 #define _CAN_BITTIMING_TSEG1_MASK 0xF00UL /**< Bit mask for CAN_TSEG1 */
AnnaBridge 187:0387e8f68319 206 #define _CAN_BITTIMING_TSEG1_DEFAULT 0x00000003UL /**< Mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 207 #define CAN_BITTIMING_TSEG1_DEFAULT (_CAN_BITTIMING_TSEG1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 208 #define _CAN_BITTIMING_TSEG2_SHIFT 12 /**< Shift value for CAN_TSEG2 */
AnnaBridge 187:0387e8f68319 209 #define _CAN_BITTIMING_TSEG2_MASK 0x7000UL /**< Bit mask for CAN_TSEG2 */
AnnaBridge 187:0387e8f68319 210 #define _CAN_BITTIMING_TSEG2_DEFAULT 0x00000002UL /**< Mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 211 #define CAN_BITTIMING_TSEG2_DEFAULT (_CAN_BITTIMING_TSEG2_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_BITTIMING */
AnnaBridge 187:0387e8f68319 212
AnnaBridge 187:0387e8f68319 213 /* Bit fields for CAN INTID */
AnnaBridge 187:0387e8f68319 214 #define _CAN_INTID_RESETVALUE 0x00000000UL /**< Default value for CAN_INTID */
AnnaBridge 187:0387e8f68319 215 #define _CAN_INTID_MASK 0x0000803FUL /**< Mask for CAN_INTID */
AnnaBridge 187:0387e8f68319 216 #define _CAN_INTID_INTID_SHIFT 0 /**< Shift value for CAN_INTID */
AnnaBridge 187:0387e8f68319 217 #define _CAN_INTID_INTID_MASK 0x3FUL /**< Bit mask for CAN_INTID */
AnnaBridge 187:0387e8f68319 218 #define _CAN_INTID_INTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */
AnnaBridge 187:0387e8f68319 219 #define CAN_INTID_INTID_DEFAULT (_CAN_INTID_INTID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_INTID */
AnnaBridge 187:0387e8f68319 220 #define CAN_INTID_INTSTAT (0x1UL << 15) /**< Status Interupt */
AnnaBridge 187:0387e8f68319 221 #define _CAN_INTID_INTSTAT_SHIFT 15 /**< Shift value for CAN_INTSTAT */
AnnaBridge 187:0387e8f68319 222 #define _CAN_INTID_INTSTAT_MASK 0x8000UL /**< Bit mask for CAN_INTSTAT */
AnnaBridge 187:0387e8f68319 223 #define _CAN_INTID_INTSTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */
AnnaBridge 187:0387e8f68319 224 #define _CAN_INTID_INTSTAT_FALSE 0x00000000UL /**< Mode FALSE for CAN_INTID */
AnnaBridge 187:0387e8f68319 225 #define _CAN_INTID_INTSTAT_TRUE 0x00000001UL /**< Mode TRUE for CAN_INTID */
AnnaBridge 187:0387e8f68319 226 #define CAN_INTID_INTSTAT_DEFAULT (_CAN_INTID_INTSTAT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_INTID */
AnnaBridge 187:0387e8f68319 227 #define CAN_INTID_INTSTAT_FALSE (_CAN_INTID_INTSTAT_FALSE << 15) /**< Shifted mode FALSE for CAN_INTID */
AnnaBridge 187:0387e8f68319 228 #define CAN_INTID_INTSTAT_TRUE (_CAN_INTID_INTSTAT_TRUE << 15) /**< Shifted mode TRUE for CAN_INTID */
AnnaBridge 187:0387e8f68319 229
AnnaBridge 187:0387e8f68319 230 /* Bit fields for CAN TEST */
AnnaBridge 187:0387e8f68319 231 #define _CAN_TEST_RESETVALUE 0x00000000UL /**< Default value for CAN_TEST */
AnnaBridge 187:0387e8f68319 232 #define _CAN_TEST_MASK 0x000000FCUL /**< Mask for CAN_TEST */
AnnaBridge 187:0387e8f68319 233 #define CAN_TEST_BASIC (0x1UL << 2) /**< Basic Mode */
AnnaBridge 187:0387e8f68319 234 #define _CAN_TEST_BASIC_SHIFT 2 /**< Shift value for CAN_BASIC */
AnnaBridge 187:0387e8f68319 235 #define _CAN_TEST_BASIC_MASK 0x4UL /**< Bit mask for CAN_BASIC */
AnnaBridge 187:0387e8f68319 236 #define _CAN_TEST_BASIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 237 #define CAN_TEST_BASIC_DEFAULT (_CAN_TEST_BASIC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 238 #define CAN_TEST_SILENT (0x1UL << 3) /**< Silent Mode */
AnnaBridge 187:0387e8f68319 239 #define _CAN_TEST_SILENT_SHIFT 3 /**< Shift value for CAN_SILENT */
AnnaBridge 187:0387e8f68319 240 #define _CAN_TEST_SILENT_MASK 0x8UL /**< Bit mask for CAN_SILENT */
AnnaBridge 187:0387e8f68319 241 #define _CAN_TEST_SILENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 242 #define CAN_TEST_SILENT_DEFAULT (_CAN_TEST_SILENT_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 243 #define CAN_TEST_LBACK (0x1UL << 4) /**< Loopback Mode */
AnnaBridge 187:0387e8f68319 244 #define _CAN_TEST_LBACK_SHIFT 4 /**< Shift value for CAN_LBACK */
AnnaBridge 187:0387e8f68319 245 #define _CAN_TEST_LBACK_MASK 0x10UL /**< Bit mask for CAN_LBACK */
AnnaBridge 187:0387e8f68319 246 #define _CAN_TEST_LBACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 247 #define CAN_TEST_LBACK_DEFAULT (_CAN_TEST_LBACK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 248 #define _CAN_TEST_TX_SHIFT 5 /**< Shift value for CAN_TX */
AnnaBridge 187:0387e8f68319 249 #define _CAN_TEST_TX_MASK 0x60UL /**< Bit mask for CAN_TX */
AnnaBridge 187:0387e8f68319 250 #define _CAN_TEST_TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 251 #define _CAN_TEST_TX_CORE 0x00000000UL /**< Mode CORE for CAN_TEST */
AnnaBridge 187:0387e8f68319 252 #define _CAN_TEST_TX_SAMPT 0x00000001UL /**< Mode SAMPT for CAN_TEST */
AnnaBridge 187:0387e8f68319 253 #define _CAN_TEST_TX_LOW 0x00000002UL /**< Mode LOW for CAN_TEST */
AnnaBridge 187:0387e8f68319 254 #define _CAN_TEST_TX_HIGH 0x00000003UL /**< Mode HIGH for CAN_TEST */
AnnaBridge 187:0387e8f68319 255 #define CAN_TEST_TX_DEFAULT (_CAN_TEST_TX_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 256 #define CAN_TEST_TX_CORE (_CAN_TEST_TX_CORE << 5) /**< Shifted mode CORE for CAN_TEST */
AnnaBridge 187:0387e8f68319 257 #define CAN_TEST_TX_SAMPT (_CAN_TEST_TX_SAMPT << 5) /**< Shifted mode SAMPT for CAN_TEST */
AnnaBridge 187:0387e8f68319 258 #define CAN_TEST_TX_LOW (_CAN_TEST_TX_LOW << 5) /**< Shifted mode LOW for CAN_TEST */
AnnaBridge 187:0387e8f68319 259 #define CAN_TEST_TX_HIGH (_CAN_TEST_TX_HIGH << 5) /**< Shifted mode HIGH for CAN_TEST */
AnnaBridge 187:0387e8f68319 260 #define CAN_TEST_RX (0x1UL << 7) /**< Monitors the actual value of CAN_RX pin */
AnnaBridge 187:0387e8f68319 261 #define _CAN_TEST_RX_SHIFT 7 /**< Shift value for CAN_RX */
AnnaBridge 187:0387e8f68319 262 #define _CAN_TEST_RX_MASK 0x80UL /**< Bit mask for CAN_RX */
AnnaBridge 187:0387e8f68319 263 #define _CAN_TEST_RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 264 #define _CAN_TEST_RX_LOW 0x00000000UL /**< Mode LOW for CAN_TEST */
AnnaBridge 187:0387e8f68319 265 #define _CAN_TEST_RX_HIGH 0x00000001UL /**< Mode HIGH for CAN_TEST */
AnnaBridge 187:0387e8f68319 266 #define CAN_TEST_RX_DEFAULT (_CAN_TEST_RX_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_TEST */
AnnaBridge 187:0387e8f68319 267 #define CAN_TEST_RX_LOW (_CAN_TEST_RX_LOW << 7) /**< Shifted mode LOW for CAN_TEST */
AnnaBridge 187:0387e8f68319 268 #define CAN_TEST_RX_HIGH (_CAN_TEST_RX_HIGH << 7) /**< Shifted mode HIGH for CAN_TEST */
AnnaBridge 187:0387e8f68319 269
AnnaBridge 187:0387e8f68319 270 /* Bit fields for CAN BRPE */
AnnaBridge 187:0387e8f68319 271 #define _CAN_BRPE_RESETVALUE 0x00000000UL /**< Default value for CAN_BRPE */
AnnaBridge 187:0387e8f68319 272 #define _CAN_BRPE_MASK 0x0000000FUL /**< Mask for CAN_BRPE */
AnnaBridge 187:0387e8f68319 273 #define _CAN_BRPE_BRPE_SHIFT 0 /**< Shift value for CAN_BRPE */
AnnaBridge 187:0387e8f68319 274 #define _CAN_BRPE_BRPE_MASK 0xFUL /**< Bit mask for CAN_BRPE */
AnnaBridge 187:0387e8f68319 275 #define _CAN_BRPE_BRPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BRPE */
AnnaBridge 187:0387e8f68319 276 #define CAN_BRPE_BRPE_DEFAULT (_CAN_BRPE_BRPE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BRPE */
AnnaBridge 187:0387e8f68319 277
AnnaBridge 187:0387e8f68319 278 /* Bit fields for CAN TRANSREQ */
AnnaBridge 187:0387e8f68319 279 #define _CAN_TRANSREQ_RESETVALUE 0x00000000UL /**< Default value for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 280 #define _CAN_TRANSREQ_MASK 0xFFFFFFFFUL /**< Mask for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 281 #define _CAN_TRANSREQ_TXRQSTOUT_SHIFT 0 /**< Shift value for CAN_TXRQSTOUT */
AnnaBridge 187:0387e8f68319 282 #define _CAN_TRANSREQ_TXRQSTOUT_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_TXRQSTOUT */
AnnaBridge 187:0387e8f68319 283 #define _CAN_TRANSREQ_TXRQSTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 284 #define _CAN_TRANSREQ_TXRQSTOUT_FALSE 0x00000000UL /**< Mode FALSE for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 285 #define _CAN_TRANSREQ_TXRQSTOUT_TRUE 0x00000001UL /**< Mode TRUE for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 286 #define CAN_TRANSREQ_TXRQSTOUT_DEFAULT (_CAN_TRANSREQ_TXRQSTOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 287 #define CAN_TRANSREQ_TXRQSTOUT_FALSE (_CAN_TRANSREQ_TXRQSTOUT_FALSE << 0) /**< Shifted mode FALSE for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 288 #define CAN_TRANSREQ_TXRQSTOUT_TRUE (_CAN_TRANSREQ_TXRQSTOUT_TRUE << 0) /**< Shifted mode TRUE for CAN_TRANSREQ */
AnnaBridge 187:0387e8f68319 289
AnnaBridge 187:0387e8f68319 290 /* Bit fields for CAN MESSAGEDATA */
AnnaBridge 187:0387e8f68319 291 #define _CAN_MESSAGEDATA_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGEDATA */
AnnaBridge 187:0387e8f68319 292 #define _CAN_MESSAGEDATA_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGEDATA */
AnnaBridge 187:0387e8f68319 293 #define _CAN_MESSAGEDATA_VALID_SHIFT 0 /**< Shift value for CAN_VALID */
AnnaBridge 187:0387e8f68319 294 #define _CAN_MESSAGEDATA_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */
AnnaBridge 187:0387e8f68319 295 #define _CAN_MESSAGEDATA_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGEDATA */
AnnaBridge 187:0387e8f68319 296 #define CAN_MESSAGEDATA_VALID_DEFAULT (_CAN_MESSAGEDATA_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGEDATA */
AnnaBridge 187:0387e8f68319 297
AnnaBridge 187:0387e8f68319 298 /* Bit fields for CAN MESSAGESTATE */
AnnaBridge 187:0387e8f68319 299 #define _CAN_MESSAGESTATE_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGESTATE */
AnnaBridge 187:0387e8f68319 300 #define _CAN_MESSAGESTATE_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGESTATE */
AnnaBridge 187:0387e8f68319 301 #define _CAN_MESSAGESTATE_VALID_SHIFT 0 /**< Shift value for CAN_VALID */
AnnaBridge 187:0387e8f68319 302 #define _CAN_MESSAGESTATE_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */
AnnaBridge 187:0387e8f68319 303 #define _CAN_MESSAGESTATE_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGESTATE */
AnnaBridge 187:0387e8f68319 304 #define CAN_MESSAGESTATE_VALID_DEFAULT (_CAN_MESSAGESTATE_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGESTATE */
AnnaBridge 187:0387e8f68319 305
AnnaBridge 187:0387e8f68319 306 /* Bit fields for CAN CONFIG */
AnnaBridge 187:0387e8f68319 307 #define _CAN_CONFIG_RESETVALUE 0x00000000UL /**< Default value for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 308 #define _CAN_CONFIG_MASK 0x00008000UL /**< Mask for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 309 #define CAN_CONFIG_DBGHALT (0x1UL << 15) /**< Debug Halt */
AnnaBridge 187:0387e8f68319 310 #define _CAN_CONFIG_DBGHALT_SHIFT 15 /**< Shift value for CAN_DBGHALT */
AnnaBridge 187:0387e8f68319 311 #define _CAN_CONFIG_DBGHALT_MASK 0x8000UL /**< Bit mask for CAN_DBGHALT */
AnnaBridge 187:0387e8f68319 312 #define _CAN_CONFIG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 313 #define _CAN_CONFIG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 314 #define _CAN_CONFIG_DBGHALT_STALL 0x00000001UL /**< Mode STALL for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 315 #define CAN_CONFIG_DBGHALT_DEFAULT (_CAN_CONFIG_DBGHALT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 316 #define CAN_CONFIG_DBGHALT_NORMAL (_CAN_CONFIG_DBGHALT_NORMAL << 15) /**< Shifted mode NORMAL for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 317 #define CAN_CONFIG_DBGHALT_STALL (_CAN_CONFIG_DBGHALT_STALL << 15) /**< Shifted mode STALL for CAN_CONFIG */
AnnaBridge 187:0387e8f68319 318
AnnaBridge 187:0387e8f68319 319 /* Bit fields for CAN IF0IF */
AnnaBridge 187:0387e8f68319 320 #define _CAN_IF0IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IF */
AnnaBridge 187:0387e8f68319 321 #define _CAN_IF0IF_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IF */
AnnaBridge 187:0387e8f68319 322 #define _CAN_IF0IF_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 323 #define _CAN_IF0IF_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 324 #define _CAN_IF0IF_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IF */
AnnaBridge 187:0387e8f68319 325 #define CAN_IF0IF_MESSAGE_DEFAULT (_CAN_IF0IF_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IF */
AnnaBridge 187:0387e8f68319 326
AnnaBridge 187:0387e8f68319 327 /* Bit fields for CAN IF0IFS */
AnnaBridge 187:0387e8f68319 328 #define _CAN_IF0IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFS */
AnnaBridge 187:0387e8f68319 329 #define _CAN_IF0IFS_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFS */
AnnaBridge 187:0387e8f68319 330 #define _CAN_IF0IFS_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 331 #define _CAN_IF0IFS_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 332 #define _CAN_IF0IFS_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFS */
AnnaBridge 187:0387e8f68319 333 #define CAN_IF0IFS_MESSAGE_DEFAULT (_CAN_IF0IFS_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFS */
AnnaBridge 187:0387e8f68319 334
AnnaBridge 187:0387e8f68319 335 /* Bit fields for CAN IF0IFC */
AnnaBridge 187:0387e8f68319 336 #define _CAN_IF0IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFC */
AnnaBridge 187:0387e8f68319 337 #define _CAN_IF0IFC_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFC */
AnnaBridge 187:0387e8f68319 338 #define _CAN_IF0IFC_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 339 #define _CAN_IF0IFC_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 340 #define _CAN_IF0IFC_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFC */
AnnaBridge 187:0387e8f68319 341 #define CAN_IF0IFC_MESSAGE_DEFAULT (_CAN_IF0IFC_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFC */
AnnaBridge 187:0387e8f68319 342
AnnaBridge 187:0387e8f68319 343 /* Bit fields for CAN IF0IEN */
AnnaBridge 187:0387e8f68319 344 #define _CAN_IF0IEN_RESETVALUE 0xFFFFFFFFUL /**< Default value for CAN_IF0IEN */
AnnaBridge 187:0387e8f68319 345 #define _CAN_IF0IEN_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IEN */
AnnaBridge 187:0387e8f68319 346 #define _CAN_IF0IEN_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 347 #define _CAN_IF0IEN_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
AnnaBridge 187:0387e8f68319 348 #define _CAN_IF0IEN_MESSAGE_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for CAN_IF0IEN */
AnnaBridge 187:0387e8f68319 349 #define CAN_IF0IEN_MESSAGE_DEFAULT (_CAN_IF0IEN_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IEN */
AnnaBridge 187:0387e8f68319 350
AnnaBridge 187:0387e8f68319 351 /* Bit fields for CAN IF1IF */
AnnaBridge 187:0387e8f68319 352 #define _CAN_IF1IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IF */
AnnaBridge 187:0387e8f68319 353 #define _CAN_IF1IF_MASK 0x00000001UL /**< Mask for CAN_IF1IF */
AnnaBridge 187:0387e8f68319 354 #define CAN_IF1IF_STATUS (0x1UL << 0) /**< Status Interrupt Flag */
AnnaBridge 187:0387e8f68319 355 #define _CAN_IF1IF_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
AnnaBridge 187:0387e8f68319 356 #define _CAN_IF1IF_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
AnnaBridge 187:0387e8f68319 357 #define _CAN_IF1IF_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IF */
AnnaBridge 187:0387e8f68319 358 #define CAN_IF1IF_STATUS_DEFAULT (_CAN_IF1IF_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IF */
AnnaBridge 187:0387e8f68319 359
AnnaBridge 187:0387e8f68319 360 /* Bit fields for CAN IF1IFS */
AnnaBridge 187:0387e8f68319 361 #define _CAN_IF1IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFS */
AnnaBridge 187:0387e8f68319 362 #define _CAN_IF1IFS_MASK 0x00000001UL /**< Mask for CAN_IF1IFS */
AnnaBridge 187:0387e8f68319 363 #define CAN_IF1IFS_STATUS (0x1UL << 0) /**< Set STATUS Interrupt Flag */
AnnaBridge 187:0387e8f68319 364 #define _CAN_IF1IFS_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
AnnaBridge 187:0387e8f68319 365 #define _CAN_IF1IFS_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
AnnaBridge 187:0387e8f68319 366 #define _CAN_IF1IFS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFS */
AnnaBridge 187:0387e8f68319 367 #define CAN_IF1IFS_STATUS_DEFAULT (_CAN_IF1IFS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFS */
AnnaBridge 187:0387e8f68319 368
AnnaBridge 187:0387e8f68319 369 /* Bit fields for CAN IF1IFC */
AnnaBridge 187:0387e8f68319 370 #define _CAN_IF1IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFC */
AnnaBridge 187:0387e8f68319 371 #define _CAN_IF1IFC_MASK 0x00000001UL /**< Mask for CAN_IF1IFC */
AnnaBridge 187:0387e8f68319 372 #define CAN_IF1IFC_STATUS (0x1UL << 0) /**< Clear STATUS Interrupt Flag */
AnnaBridge 187:0387e8f68319 373 #define _CAN_IF1IFC_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
AnnaBridge 187:0387e8f68319 374 #define _CAN_IF1IFC_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
AnnaBridge 187:0387e8f68319 375 #define _CAN_IF1IFC_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFC */
AnnaBridge 187:0387e8f68319 376 #define CAN_IF1IFC_STATUS_DEFAULT (_CAN_IF1IFC_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFC */
AnnaBridge 187:0387e8f68319 377
AnnaBridge 187:0387e8f68319 378 /* Bit fields for CAN IF1IEN */
AnnaBridge 187:0387e8f68319 379 #define _CAN_IF1IEN_RESETVALUE 0x00000001UL /**< Default value for CAN_IF1IEN */
AnnaBridge 187:0387e8f68319 380 #define _CAN_IF1IEN_MASK 0x00000001UL /**< Mask for CAN_IF1IEN */
AnnaBridge 187:0387e8f68319 381 #define CAN_IF1IEN_STATUS (0x1UL << 0) /**< STATUS Interrupt Enable */
AnnaBridge 187:0387e8f68319 382 #define _CAN_IF1IEN_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
AnnaBridge 187:0387e8f68319 383 #define _CAN_IF1IEN_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
AnnaBridge 187:0387e8f68319 384 #define _CAN_IF1IEN_STATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_IF1IEN */
AnnaBridge 187:0387e8f68319 385 #define CAN_IF1IEN_STATUS_DEFAULT (_CAN_IF1IEN_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IEN */
AnnaBridge 187:0387e8f68319 386
AnnaBridge 187:0387e8f68319 387 /* Bit fields for CAN ROUTE */
AnnaBridge 187:0387e8f68319 388 #define _CAN_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 389 #define _CAN_ROUTE_MASK 0x0000071DUL /**< Mask for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 390 #define CAN_ROUTE_TXPEN (0x1UL << 0) /**< TX Pin Enable */
AnnaBridge 187:0387e8f68319 391 #define _CAN_ROUTE_TXPEN_SHIFT 0 /**< Shift value for CAN_TXPEN */
AnnaBridge 187:0387e8f68319 392 #define _CAN_ROUTE_TXPEN_MASK 0x1UL /**< Bit mask for CAN_TXPEN */
AnnaBridge 187:0387e8f68319 393 #define _CAN_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 394 #define CAN_ROUTE_TXPEN_DEFAULT (_CAN_ROUTE_TXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 395 #define _CAN_ROUTE_RXLOC_SHIFT 2 /**< Shift value for CAN_RXLOC */
AnnaBridge 187:0387e8f68319 396 #define _CAN_ROUTE_RXLOC_MASK 0x1CUL /**< Bit mask for CAN_RXLOC */
AnnaBridge 187:0387e8f68319 397 #define _CAN_ROUTE_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 398 #define _CAN_ROUTE_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 399 #define _CAN_ROUTE_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 400 #define _CAN_ROUTE_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 401 #define _CAN_ROUTE_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 402 #define _CAN_ROUTE_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 403 #define _CAN_ROUTE_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 404 #define _CAN_ROUTE_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 405 #define _CAN_ROUTE_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 406 #define CAN_ROUTE_RXLOC_LOC0 (_CAN_ROUTE_RXLOC_LOC0 << 2) /**< Shifted mode LOC0 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 407 #define CAN_ROUTE_RXLOC_DEFAULT (_CAN_ROUTE_RXLOC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 408 #define CAN_ROUTE_RXLOC_LOC1 (_CAN_ROUTE_RXLOC_LOC1 << 2) /**< Shifted mode LOC1 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 409 #define CAN_ROUTE_RXLOC_LOC2 (_CAN_ROUTE_RXLOC_LOC2 << 2) /**< Shifted mode LOC2 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 410 #define CAN_ROUTE_RXLOC_LOC3 (_CAN_ROUTE_RXLOC_LOC3 << 2) /**< Shifted mode LOC3 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 411 #define CAN_ROUTE_RXLOC_LOC4 (_CAN_ROUTE_RXLOC_LOC4 << 2) /**< Shifted mode LOC4 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 412 #define CAN_ROUTE_RXLOC_LOC5 (_CAN_ROUTE_RXLOC_LOC5 << 2) /**< Shifted mode LOC5 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 413 #define CAN_ROUTE_RXLOC_LOC6 (_CAN_ROUTE_RXLOC_LOC6 << 2) /**< Shifted mode LOC6 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 414 #define CAN_ROUTE_RXLOC_LOC7 (_CAN_ROUTE_RXLOC_LOC7 << 2) /**< Shifted mode LOC7 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 415 #define _CAN_ROUTE_TXLOC_SHIFT 8 /**< Shift value for CAN_TXLOC */
AnnaBridge 187:0387e8f68319 416 #define _CAN_ROUTE_TXLOC_MASK 0x700UL /**< Bit mask for CAN_TXLOC */
AnnaBridge 187:0387e8f68319 417 #define _CAN_ROUTE_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 418 #define _CAN_ROUTE_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 419 #define _CAN_ROUTE_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 420 #define _CAN_ROUTE_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 421 #define _CAN_ROUTE_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 422 #define _CAN_ROUTE_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 423 #define _CAN_ROUTE_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 424 #define _CAN_ROUTE_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 425 #define _CAN_ROUTE_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 426 #define CAN_ROUTE_TXLOC_LOC0 (_CAN_ROUTE_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 427 #define CAN_ROUTE_TXLOC_DEFAULT (_CAN_ROUTE_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 428 #define CAN_ROUTE_TXLOC_LOC1 (_CAN_ROUTE_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 429 #define CAN_ROUTE_TXLOC_LOC2 (_CAN_ROUTE_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 430 #define CAN_ROUTE_TXLOC_LOC3 (_CAN_ROUTE_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 431 #define CAN_ROUTE_TXLOC_LOC4 (_CAN_ROUTE_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 432 #define CAN_ROUTE_TXLOC_LOC5 (_CAN_ROUTE_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 433 #define CAN_ROUTE_TXLOC_LOC6 (_CAN_ROUTE_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 434 #define CAN_ROUTE_TXLOC_LOC7 (_CAN_ROUTE_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for CAN_ROUTE */
AnnaBridge 187:0387e8f68319 435
AnnaBridge 187:0387e8f68319 436 /* Bit fields for CAN MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 437 #define _CAN_MIR_CMDMASK_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 438 #define _CAN_MIR_CMDMASK_MASK 0x000000FFUL /**< Mask for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 439 #define CAN_MIR_CMDMASK_DATAB (0x1UL << 0) /**< CC Channel Mode */
AnnaBridge 187:0387e8f68319 440 #define _CAN_MIR_CMDMASK_DATAB_SHIFT 0 /**< Shift value for CAN_DATAB */
AnnaBridge 187:0387e8f68319 441 #define _CAN_MIR_CMDMASK_DATAB_MASK 0x1UL /**< Bit mask for CAN_DATAB */
AnnaBridge 187:0387e8f68319 442 #define _CAN_MIR_CMDMASK_DATAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 443 #define CAN_MIR_CMDMASK_DATAB_DEFAULT (_CAN_MIR_CMDMASK_DATAB_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 444 #define CAN_MIR_CMDMASK_DATAA (0x1UL << 1) /**< Access Data Bytes 0-3 */
AnnaBridge 187:0387e8f68319 445 #define _CAN_MIR_CMDMASK_DATAA_SHIFT 1 /**< Shift value for CAN_DATAA */
AnnaBridge 187:0387e8f68319 446 #define _CAN_MIR_CMDMASK_DATAA_MASK 0x2UL /**< Bit mask for CAN_DATAA */
AnnaBridge 187:0387e8f68319 447 #define _CAN_MIR_CMDMASK_DATAA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 448 #define CAN_MIR_CMDMASK_DATAA_DEFAULT (_CAN_MIR_CMDMASK_DATAA_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 449 #define CAN_MIR_CMDMASK_TXRQSTNEWDAT (0x1UL << 2) /**< Transmission Request Bit/ New Data Bit */
AnnaBridge 187:0387e8f68319 450 #define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_SHIFT 2 /**< Shift value for CAN_TXRQSTNEWDAT */
AnnaBridge 187:0387e8f68319 451 #define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_MASK 0x4UL /**< Bit mask for CAN_TXRQSTNEWDAT */
AnnaBridge 187:0387e8f68319 452 #define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 453 #define CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT (_CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 454 #define CAN_MIR_CMDMASK_CLRINTPND (0x1UL << 3) /**< Clear Interrupt Pending Bit */
AnnaBridge 187:0387e8f68319 455 #define _CAN_MIR_CMDMASK_CLRINTPND_SHIFT 3 /**< Shift value for CAN_CLRINTPND */
AnnaBridge 187:0387e8f68319 456 #define _CAN_MIR_CMDMASK_CLRINTPND_MASK 0x8UL /**< Bit mask for CAN_CLRINTPND */
AnnaBridge 187:0387e8f68319 457 #define _CAN_MIR_CMDMASK_CLRINTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 458 #define CAN_MIR_CMDMASK_CLRINTPND_DEFAULT (_CAN_MIR_CMDMASK_CLRINTPND_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 459 #define CAN_MIR_CMDMASK_CONTROL (0x1UL << 4) /**< Access Control Bits */
AnnaBridge 187:0387e8f68319 460 #define _CAN_MIR_CMDMASK_CONTROL_SHIFT 4 /**< Shift value for CAN_CONTROL */
AnnaBridge 187:0387e8f68319 461 #define _CAN_MIR_CMDMASK_CONTROL_MASK 0x10UL /**< Bit mask for CAN_CONTROL */
AnnaBridge 187:0387e8f68319 462 #define _CAN_MIR_CMDMASK_CONTROL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 463 #define CAN_MIR_CMDMASK_CONTROL_DEFAULT (_CAN_MIR_CMDMASK_CONTROL_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 464 #define CAN_MIR_CMDMASK_ARBACC (0x1UL << 5) /**< Access Arbitration bits */
AnnaBridge 187:0387e8f68319 465 #define _CAN_MIR_CMDMASK_ARBACC_SHIFT 5 /**< Shift value for CAN_ARBACC */
AnnaBridge 187:0387e8f68319 466 #define _CAN_MIR_CMDMASK_ARBACC_MASK 0x20UL /**< Bit mask for CAN_ARBACC */
AnnaBridge 187:0387e8f68319 467 #define _CAN_MIR_CMDMASK_ARBACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 468 #define CAN_MIR_CMDMASK_ARBACC_DEFAULT (_CAN_MIR_CMDMASK_ARBACC_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 469 #define CAN_MIR_CMDMASK_MASKACC (0x1UL << 6) /**< Access Mask bits */
AnnaBridge 187:0387e8f68319 470 #define _CAN_MIR_CMDMASK_MASKACC_SHIFT 6 /**< Shift value for CAN_MASKACC */
AnnaBridge 187:0387e8f68319 471 #define _CAN_MIR_CMDMASK_MASKACC_MASK 0x40UL /**< Bit mask for CAN_MASKACC */
AnnaBridge 187:0387e8f68319 472 #define _CAN_MIR_CMDMASK_MASKACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 473 #define CAN_MIR_CMDMASK_MASKACC_DEFAULT (_CAN_MIR_CMDMASK_MASKACC_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 474 #define CAN_MIR_CMDMASK_WRRD (0x1UL << 7) /**< Write/Read RAM */
AnnaBridge 187:0387e8f68319 475 #define _CAN_MIR_CMDMASK_WRRD_SHIFT 7 /**< Shift value for CAN_WRRD */
AnnaBridge 187:0387e8f68319 476 #define _CAN_MIR_CMDMASK_WRRD_MASK 0x80UL /**< Bit mask for CAN_WRRD */
AnnaBridge 187:0387e8f68319 477 #define _CAN_MIR_CMDMASK_WRRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 478 #define _CAN_MIR_CMDMASK_WRRD_READ 0x00000000UL /**< Mode READ for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 479 #define _CAN_MIR_CMDMASK_WRRD_WRITE 0x00000001UL /**< Mode WRITE for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 480 #define CAN_MIR_CMDMASK_WRRD_DEFAULT (_CAN_MIR_CMDMASK_WRRD_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 481 #define CAN_MIR_CMDMASK_WRRD_READ (_CAN_MIR_CMDMASK_WRRD_READ << 7) /**< Shifted mode READ for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 482 #define CAN_MIR_CMDMASK_WRRD_WRITE (_CAN_MIR_CMDMASK_WRRD_WRITE << 7) /**< Shifted mode WRITE for CAN_MIR_CMDMASK */
AnnaBridge 187:0387e8f68319 483
AnnaBridge 187:0387e8f68319 484 /* Bit fields for CAN MIR_MASK */
AnnaBridge 187:0387e8f68319 485 #define _CAN_MIR_MASK_RESETVALUE 0xDFFFFFFFUL /**< Default value for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 486 #define _CAN_MIR_MASK_MASK 0xDFFFFFFFUL /**< Mask for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 487 #define _CAN_MIR_MASK_MASK_SHIFT 0 /**< Shift value for CAN_MASK */
AnnaBridge 187:0387e8f68319 488 #define _CAN_MIR_MASK_MASK_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_MASK */
AnnaBridge 187:0387e8f68319 489 #define _CAN_MIR_MASK_MASK_DEFAULT 0x1FFFFFFFUL /**< Mode DEFAULT for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 490 #define CAN_MIR_MASK_MASK_DEFAULT (_CAN_MIR_MASK_MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 491 #define CAN_MIR_MASK_MDIR (0x1UL << 30) /**< Mask Message Direction */
AnnaBridge 187:0387e8f68319 492 #define _CAN_MIR_MASK_MDIR_SHIFT 30 /**< Shift value for CAN_MDIR */
AnnaBridge 187:0387e8f68319 493 #define _CAN_MIR_MASK_MDIR_MASK 0x40000000UL /**< Bit mask for CAN_MDIR */
AnnaBridge 187:0387e8f68319 494 #define _CAN_MIR_MASK_MDIR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 495 #define CAN_MIR_MASK_MDIR_DEFAULT (_CAN_MIR_MASK_MDIR_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 496 #define CAN_MIR_MASK_MXTD (0x1UL << 31) /**< Mask Extended Identifier */
AnnaBridge 187:0387e8f68319 497 #define _CAN_MIR_MASK_MXTD_SHIFT 31 /**< Shift value for CAN_MXTD */
AnnaBridge 187:0387e8f68319 498 #define _CAN_MIR_MASK_MXTD_MASK 0x80000000UL /**< Bit mask for CAN_MXTD */
AnnaBridge 187:0387e8f68319 499 #define _CAN_MIR_MASK_MXTD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 500 #define CAN_MIR_MASK_MXTD_DEFAULT (_CAN_MIR_MASK_MXTD_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
AnnaBridge 187:0387e8f68319 501
AnnaBridge 187:0387e8f68319 502 /* Bit fields for CAN MIR_ARB */
AnnaBridge 187:0387e8f68319 503 #define _CAN_MIR_ARB_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 504 #define _CAN_MIR_ARB_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 505 #define _CAN_MIR_ARB_ID_SHIFT 0 /**< Shift value for CAN_ID */
AnnaBridge 187:0387e8f68319 506 #define _CAN_MIR_ARB_ID_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_ID */
AnnaBridge 187:0387e8f68319 507 #define _CAN_MIR_ARB_ID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 508 #define CAN_MIR_ARB_ID_DEFAULT (_CAN_MIR_ARB_ID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 509 #define CAN_MIR_ARB_DIR (0x1UL << 29) /**< Message Direction */
AnnaBridge 187:0387e8f68319 510 #define _CAN_MIR_ARB_DIR_SHIFT 29 /**< Shift value for CAN_DIR */
AnnaBridge 187:0387e8f68319 511 #define _CAN_MIR_ARB_DIR_MASK 0x20000000UL /**< Bit mask for CAN_DIR */
AnnaBridge 187:0387e8f68319 512 #define _CAN_MIR_ARB_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 513 #define _CAN_MIR_ARB_DIR_RX 0x00000000UL /**< Mode RX for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 514 #define _CAN_MIR_ARB_DIR_TX 0x00000001UL /**< Mode TX for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 515 #define CAN_MIR_ARB_DIR_DEFAULT (_CAN_MIR_ARB_DIR_DEFAULT << 29) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 516 #define CAN_MIR_ARB_DIR_RX (_CAN_MIR_ARB_DIR_RX << 29) /**< Shifted mode RX for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 517 #define CAN_MIR_ARB_DIR_TX (_CAN_MIR_ARB_DIR_TX << 29) /**< Shifted mode TX for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 518 #define CAN_MIR_ARB_XTD (0x1UL << 30) /**< Extended Identifier */
AnnaBridge 187:0387e8f68319 519 #define _CAN_MIR_ARB_XTD_SHIFT 30 /**< Shift value for CAN_XTD */
AnnaBridge 187:0387e8f68319 520 #define _CAN_MIR_ARB_XTD_MASK 0x40000000UL /**< Bit mask for CAN_XTD */
AnnaBridge 187:0387e8f68319 521 #define _CAN_MIR_ARB_XTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 522 #define _CAN_MIR_ARB_XTD_STD 0x00000000UL /**< Mode STD for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 523 #define _CAN_MIR_ARB_XTD_EXT 0x00000001UL /**< Mode EXT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 524 #define CAN_MIR_ARB_XTD_DEFAULT (_CAN_MIR_ARB_XTD_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 525 #define CAN_MIR_ARB_XTD_STD (_CAN_MIR_ARB_XTD_STD << 30) /**< Shifted mode STD for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 526 #define CAN_MIR_ARB_XTD_EXT (_CAN_MIR_ARB_XTD_EXT << 30) /**< Shifted mode EXT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 527 #define CAN_MIR_ARB_MSGVAL (0x1UL << 31) /**< Message Valid */
AnnaBridge 187:0387e8f68319 528 #define _CAN_MIR_ARB_MSGVAL_SHIFT 31 /**< Shift value for CAN_MSGVAL */
AnnaBridge 187:0387e8f68319 529 #define _CAN_MIR_ARB_MSGVAL_MASK 0x80000000UL /**< Bit mask for CAN_MSGVAL */
AnnaBridge 187:0387e8f68319 530 #define _CAN_MIR_ARB_MSGVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 531 #define CAN_MIR_ARB_MSGVAL_DEFAULT (_CAN_MIR_ARB_MSGVAL_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
AnnaBridge 187:0387e8f68319 532
AnnaBridge 187:0387e8f68319 533 /* Bit fields for CAN MIR_CTRL */
AnnaBridge 187:0387e8f68319 534 #define _CAN_MIR_CTRL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 535 #define _CAN_MIR_CTRL_MASK 0x0000FF8FUL /**< Mask for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 536 #define _CAN_MIR_CTRL_DLC_SHIFT 0 /**< Shift value for CAN_DLC */
AnnaBridge 187:0387e8f68319 537 #define _CAN_MIR_CTRL_DLC_MASK 0xFUL /**< Bit mask for CAN_DLC */
AnnaBridge 187:0387e8f68319 538 #define _CAN_MIR_CTRL_DLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 539 #define CAN_MIR_CTRL_DLC_DEFAULT (_CAN_MIR_CTRL_DLC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 540 #define CAN_MIR_CTRL_EOB (0x1UL << 7) /**< End of Buffer */
AnnaBridge 187:0387e8f68319 541 #define _CAN_MIR_CTRL_EOB_SHIFT 7 /**< Shift value for CAN_EOB */
AnnaBridge 187:0387e8f68319 542 #define _CAN_MIR_CTRL_EOB_MASK 0x80UL /**< Bit mask for CAN_EOB */
AnnaBridge 187:0387e8f68319 543 #define _CAN_MIR_CTRL_EOB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 544 #define CAN_MIR_CTRL_EOB_DEFAULT (_CAN_MIR_CTRL_EOB_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 545 #define CAN_MIR_CTRL_TXRQST (0x1UL << 8) /**< Transmit Request */
AnnaBridge 187:0387e8f68319 546 #define _CAN_MIR_CTRL_TXRQST_SHIFT 8 /**< Shift value for CAN_TXRQST */
AnnaBridge 187:0387e8f68319 547 #define _CAN_MIR_CTRL_TXRQST_MASK 0x100UL /**< Bit mask for CAN_TXRQST */
AnnaBridge 187:0387e8f68319 548 #define _CAN_MIR_CTRL_TXRQST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 549 #define CAN_MIR_CTRL_TXRQST_DEFAULT (_CAN_MIR_CTRL_TXRQST_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 550 #define CAN_MIR_CTRL_RMTEN (0x1UL << 9) /**< Remote Enable */
AnnaBridge 187:0387e8f68319 551 #define _CAN_MIR_CTRL_RMTEN_SHIFT 9 /**< Shift value for CAN_RMTEN */
AnnaBridge 187:0387e8f68319 552 #define _CAN_MIR_CTRL_RMTEN_MASK 0x200UL /**< Bit mask for CAN_RMTEN */
AnnaBridge 187:0387e8f68319 553 #define _CAN_MIR_CTRL_RMTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 554 #define CAN_MIR_CTRL_RMTEN_DEFAULT (_CAN_MIR_CTRL_RMTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 555 #define CAN_MIR_CTRL_RXIE (0x1UL << 10) /**< Receive Interrupt Enable */
AnnaBridge 187:0387e8f68319 556 #define _CAN_MIR_CTRL_RXIE_SHIFT 10 /**< Shift value for CAN_RXIE */
AnnaBridge 187:0387e8f68319 557 #define _CAN_MIR_CTRL_RXIE_MASK 0x400UL /**< Bit mask for CAN_RXIE */
AnnaBridge 187:0387e8f68319 558 #define _CAN_MIR_CTRL_RXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 559 #define CAN_MIR_CTRL_RXIE_DEFAULT (_CAN_MIR_CTRL_RXIE_DEFAULT << 10) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 560 #define CAN_MIR_CTRL_TXIE (0x1UL << 11) /**< Transmit Interrupt Enable */
AnnaBridge 187:0387e8f68319 561 #define _CAN_MIR_CTRL_TXIE_SHIFT 11 /**< Shift value for CAN_TXIE */
AnnaBridge 187:0387e8f68319 562 #define _CAN_MIR_CTRL_TXIE_MASK 0x800UL /**< Bit mask for CAN_TXIE */
AnnaBridge 187:0387e8f68319 563 #define _CAN_MIR_CTRL_TXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 564 #define CAN_MIR_CTRL_TXIE_DEFAULT (_CAN_MIR_CTRL_TXIE_DEFAULT << 11) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 565 #define CAN_MIR_CTRL_UMASK (0x1UL << 12) /**< Use Acceptance Mask */
AnnaBridge 187:0387e8f68319 566 #define _CAN_MIR_CTRL_UMASK_SHIFT 12 /**< Shift value for CAN_UMASK */
AnnaBridge 187:0387e8f68319 567 #define _CAN_MIR_CTRL_UMASK_MASK 0x1000UL /**< Bit mask for CAN_UMASK */
AnnaBridge 187:0387e8f68319 568 #define _CAN_MIR_CTRL_UMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 569 #define CAN_MIR_CTRL_UMASK_DEFAULT (_CAN_MIR_CTRL_UMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 570 #define CAN_MIR_CTRL_INTPND (0x1UL << 13) /**< Interrupt Pending */
AnnaBridge 187:0387e8f68319 571 #define _CAN_MIR_CTRL_INTPND_SHIFT 13 /**< Shift value for CAN_INTPND */
AnnaBridge 187:0387e8f68319 572 #define _CAN_MIR_CTRL_INTPND_MASK 0x2000UL /**< Bit mask for CAN_INTPND */
AnnaBridge 187:0387e8f68319 573 #define _CAN_MIR_CTRL_INTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 574 #define CAN_MIR_CTRL_INTPND_DEFAULT (_CAN_MIR_CTRL_INTPND_DEFAULT << 13) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 575 #define CAN_MIR_CTRL_MESSAGEOF (0x1UL << 14) /**< Message Lost (only valid for Message Objects with direction = receive) */
AnnaBridge 187:0387e8f68319 576 #define _CAN_MIR_CTRL_MESSAGEOF_SHIFT 14 /**< Shift value for CAN_MESSAGEOF */
AnnaBridge 187:0387e8f68319 577 #define _CAN_MIR_CTRL_MESSAGEOF_MASK 0x4000UL /**< Bit mask for CAN_MESSAGEOF */
AnnaBridge 187:0387e8f68319 578 #define _CAN_MIR_CTRL_MESSAGEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 579 #define CAN_MIR_CTRL_MESSAGEOF_DEFAULT (_CAN_MIR_CTRL_MESSAGEOF_DEFAULT << 14) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 580 #define CAN_MIR_CTRL_DATAVALID (0x1UL << 15) /**< New Data */
AnnaBridge 187:0387e8f68319 581 #define _CAN_MIR_CTRL_DATAVALID_SHIFT 15 /**< Shift value for CAN_DATAVALID */
AnnaBridge 187:0387e8f68319 582 #define _CAN_MIR_CTRL_DATAVALID_MASK 0x8000UL /**< Bit mask for CAN_DATAVALID */
AnnaBridge 187:0387e8f68319 583 #define _CAN_MIR_CTRL_DATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 584 #define CAN_MIR_CTRL_DATAVALID_DEFAULT (_CAN_MIR_CTRL_DATAVALID_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
AnnaBridge 187:0387e8f68319 585
AnnaBridge 187:0387e8f68319 586 /* Bit fields for CAN MIR_DATAL */
AnnaBridge 187:0387e8f68319 587 #define _CAN_MIR_DATAL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 588 #define _CAN_MIR_DATAL_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 589 #define _CAN_MIR_DATAL_DATA0_SHIFT 0 /**< Shift value for CAN_DATA0 */
AnnaBridge 187:0387e8f68319 590 #define _CAN_MIR_DATAL_DATA0_MASK 0xFFUL /**< Bit mask for CAN_DATA0 */
AnnaBridge 187:0387e8f68319 591 #define _CAN_MIR_DATAL_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 592 #define CAN_MIR_DATAL_DATA0_DEFAULT (_CAN_MIR_DATAL_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 593 #define _CAN_MIR_DATAL_DATA1_SHIFT 8 /**< Shift value for CAN_DATA1 */
AnnaBridge 187:0387e8f68319 594 #define _CAN_MIR_DATAL_DATA1_MASK 0xFF00UL /**< Bit mask for CAN_DATA1 */
AnnaBridge 187:0387e8f68319 595 #define _CAN_MIR_DATAL_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 596 #define CAN_MIR_DATAL_DATA1_DEFAULT (_CAN_MIR_DATAL_DATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 597 #define _CAN_MIR_DATAL_DATA2_SHIFT 16 /**< Shift value for CAN_DATA2 */
AnnaBridge 187:0387e8f68319 598 #define _CAN_MIR_DATAL_DATA2_MASK 0xFF0000UL /**< Bit mask for CAN_DATA2 */
AnnaBridge 187:0387e8f68319 599 #define _CAN_MIR_DATAL_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 600 #define CAN_MIR_DATAL_DATA2_DEFAULT (_CAN_MIR_DATAL_DATA2_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 601 #define _CAN_MIR_DATAL_DATA3_SHIFT 24 /**< Shift value for CAN_DATA3 */
AnnaBridge 187:0387e8f68319 602 #define _CAN_MIR_DATAL_DATA3_MASK 0xFF000000UL /**< Bit mask for CAN_DATA3 */
AnnaBridge 187:0387e8f68319 603 #define _CAN_MIR_DATAL_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 604 #define CAN_MIR_DATAL_DATA3_DEFAULT (_CAN_MIR_DATAL_DATA3_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
AnnaBridge 187:0387e8f68319 605
AnnaBridge 187:0387e8f68319 606 /* Bit fields for CAN MIR_DATAH */
AnnaBridge 187:0387e8f68319 607 #define _CAN_MIR_DATAH_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 608 #define _CAN_MIR_DATAH_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 609 #define _CAN_MIR_DATAH_DATA4_SHIFT 0 /**< Shift value for CAN_DATA4 */
AnnaBridge 187:0387e8f68319 610 #define _CAN_MIR_DATAH_DATA4_MASK 0xFFUL /**< Bit mask for CAN_DATA4 */
AnnaBridge 187:0387e8f68319 611 #define _CAN_MIR_DATAH_DATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 612 #define CAN_MIR_DATAH_DATA4_DEFAULT (_CAN_MIR_DATAH_DATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 613 #define _CAN_MIR_DATAH_DATA5_SHIFT 8 /**< Shift value for CAN_DATA5 */
AnnaBridge 187:0387e8f68319 614 #define _CAN_MIR_DATAH_DATA5_MASK 0xFF00UL /**< Bit mask for CAN_DATA5 */
AnnaBridge 187:0387e8f68319 615 #define _CAN_MIR_DATAH_DATA5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 616 #define CAN_MIR_DATAH_DATA5_DEFAULT (_CAN_MIR_DATAH_DATA5_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 617 #define _CAN_MIR_DATAH_DATA6_SHIFT 16 /**< Shift value for CAN_DATA6 */
AnnaBridge 187:0387e8f68319 618 #define _CAN_MIR_DATAH_DATA6_MASK 0xFF0000UL /**< Bit mask for CAN_DATA6 */
AnnaBridge 187:0387e8f68319 619 #define _CAN_MIR_DATAH_DATA6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 620 #define CAN_MIR_DATAH_DATA6_DEFAULT (_CAN_MIR_DATAH_DATA6_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 621 #define _CAN_MIR_DATAH_DATA7_SHIFT 24 /**< Shift value for CAN_DATA7 */
AnnaBridge 187:0387e8f68319 622 #define _CAN_MIR_DATAH_DATA7_MASK 0xFF000000UL /**< Bit mask for CAN_DATA7 */
AnnaBridge 187:0387e8f68319 623 #define _CAN_MIR_DATAH_DATA7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 624 #define CAN_MIR_DATAH_DATA7_DEFAULT (_CAN_MIR_DATAH_DATA7_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
AnnaBridge 187:0387e8f68319 625
AnnaBridge 187:0387e8f68319 626 /* Bit fields for CAN MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 627 #define _CAN_MIR_CMDREQ_RESETVALUE 0x00000001UL /**< Default value for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 628 #define _CAN_MIR_CMDREQ_MASK 0x0000803FUL /**< Mask for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 629 #define _CAN_MIR_CMDREQ_MSGNUM_SHIFT 0 /**< Shift value for CAN_MSGNUM */
AnnaBridge 187:0387e8f68319 630 #define _CAN_MIR_CMDREQ_MSGNUM_MASK 0x3FUL /**< Bit mask for CAN_MSGNUM */
AnnaBridge 187:0387e8f68319 631 #define _CAN_MIR_CMDREQ_MSGNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 632 #define CAN_MIR_CMDREQ_MSGNUM_DEFAULT (_CAN_MIR_CMDREQ_MSGNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 633 #define CAN_MIR_CMDREQ_BUSY (0x1UL << 15) /**< Busy Flag */
AnnaBridge 187:0387e8f68319 634 #define _CAN_MIR_CMDREQ_BUSY_SHIFT 15 /**< Shift value for CAN_BUSY */
AnnaBridge 187:0387e8f68319 635 #define _CAN_MIR_CMDREQ_BUSY_MASK 0x8000UL /**< Bit mask for CAN_BUSY */
AnnaBridge 187:0387e8f68319 636 #define _CAN_MIR_CMDREQ_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 637 #define _CAN_MIR_CMDREQ_BUSY_FALSE 0x00000000UL /**< Mode FALSE for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 638 #define _CAN_MIR_CMDREQ_BUSY_TRUE 0x00000001UL /**< Mode TRUE for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 639 #define CAN_MIR_CMDREQ_BUSY_DEFAULT (_CAN_MIR_CMDREQ_BUSY_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 640 #define CAN_MIR_CMDREQ_BUSY_FALSE (_CAN_MIR_CMDREQ_BUSY_FALSE << 15) /**< Shifted mode FALSE for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 641 #define CAN_MIR_CMDREQ_BUSY_TRUE (_CAN_MIR_CMDREQ_BUSY_TRUE << 15) /**< Shifted mode TRUE for CAN_MIR_CMDREQ */
AnnaBridge 187:0387e8f68319 642
AnnaBridge 187:0387e8f68319 643 /** @} */
AnnaBridge 187:0387e8f68319 644 /** @} End of group EFM32GG11B_CAN */
AnnaBridge 187:0387e8f68319 645 /** @} End of group Parts */