mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/efm32gg11b820f2048iq100.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 187:0387e8f68319 1 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 2 * @file efm32gg11b820f2048iq100.h
AnnaBridge 187:0387e8f68319 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
AnnaBridge 187:0387e8f68319 4 * for EFM32GG11B820F2048IQ100
AnnaBridge 187:0387e8f68319 5 * @version 5.3.2
AnnaBridge 187:0387e8f68319 6 ******************************************************************************
AnnaBridge 187:0387e8f68319 7 * # License
AnnaBridge 187:0387e8f68319 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 187:0387e8f68319 9 ******************************************************************************
AnnaBridge 187:0387e8f68319 10 *
AnnaBridge 187:0387e8f68319 11 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 187:0387e8f68319 12 * including commercial applications, and to alter it and redistribute it
AnnaBridge 187:0387e8f68319 13 * freely, subject to the following restrictions:
AnnaBridge 187:0387e8f68319 14 *
AnnaBridge 187:0387e8f68319 15 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 187:0387e8f68319 16 * claim that you wrote the original software.@n
AnnaBridge 187:0387e8f68319 17 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 187:0387e8f68319 18 * misrepresented as being the original software.@n
AnnaBridge 187:0387e8f68319 19 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 187:0387e8f68319 20 *
AnnaBridge 187:0387e8f68319 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 187:0387e8f68319 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 187:0387e8f68319 23 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 187:0387e8f68319 24 * kind, including, but not limited to, any implied warranties of
AnnaBridge 187:0387e8f68319 25 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 187:0387e8f68319 26 * infringement of any proprietary rights of a third party.
AnnaBridge 187:0387e8f68319 27 *
AnnaBridge 187:0387e8f68319 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 187:0387e8f68319 29 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 187:0387e8f68319 30 * any third party, arising from your use of this Software.
AnnaBridge 187:0387e8f68319 31 *
AnnaBridge 187:0387e8f68319 32 *****************************************************************************/
AnnaBridge 187:0387e8f68319 33
AnnaBridge 187:0387e8f68319 34 #if defined(__ICCARM__)
AnnaBridge 187:0387e8f68319 35 #pragma system_include /* Treat file as system include file. */
AnnaBridge 187:0387e8f68319 36 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 187:0387e8f68319 37 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 187:0387e8f68319 38 #endif
AnnaBridge 187:0387e8f68319 39
AnnaBridge 187:0387e8f68319 40 #ifndef EFM32GG11B820F2048IQ100_H
AnnaBridge 187:0387e8f68319 41 #define EFM32GG11B820F2048IQ100_H
AnnaBridge 187:0387e8f68319 42
AnnaBridge 187:0387e8f68319 43 #ifdef __cplusplus
AnnaBridge 187:0387e8f68319 44 extern "C" {
AnnaBridge 187:0387e8f68319 45 #endif
AnnaBridge 187:0387e8f68319 46
AnnaBridge 187:0387e8f68319 47 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 48 * @addtogroup Parts
AnnaBridge 187:0387e8f68319 49 * @{
AnnaBridge 187:0387e8f68319 50 *****************************************************************************/
AnnaBridge 187:0387e8f68319 51
AnnaBridge 187:0387e8f68319 52 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 53 * @defgroup EFM32GG11B820F2048IQ100 EFM32GG11B820F2048IQ100
AnnaBridge 187:0387e8f68319 54 * @{
AnnaBridge 187:0387e8f68319 55 *****************************************************************************/
AnnaBridge 187:0387e8f68319 56
AnnaBridge 187:0387e8f68319 57 /** Interrupt Number Definition */
AnnaBridge 187:0387e8f68319 58 typedef enum IRQn{
AnnaBridge 187:0387e8f68319 59 /****** Cortex-M4 Processor Exceptions Numbers *******************************************/
AnnaBridge 187:0387e8f68319 60 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 187:0387e8f68319 61 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
AnnaBridge 187:0387e8f68319 62 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 187:0387e8f68319 63 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 187:0387e8f68319 64 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 187:0387e8f68319 65 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 187:0387e8f68319 66 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 187:0387e8f68319 67 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 187:0387e8f68319 68 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 187:0387e8f68319 69
AnnaBridge 187:0387e8f68319 70 /****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/
AnnaBridge 187:0387e8f68319 71
AnnaBridge 187:0387e8f68319 72 EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
AnnaBridge 187:0387e8f68319 73 WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */
AnnaBridge 187:0387e8f68319 74 LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */
AnnaBridge 187:0387e8f68319 75 GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */
AnnaBridge 187:0387e8f68319 76 SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */
AnnaBridge 187:0387e8f68319 77 TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */
AnnaBridge 187:0387e8f68319 78 USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */
AnnaBridge 187:0387e8f68319 79 USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */
AnnaBridge 187:0387e8f68319 80 ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */
AnnaBridge 187:0387e8f68319 81 ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */
AnnaBridge 187:0387e8f68319 82 IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */
AnnaBridge 187:0387e8f68319 83 I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */
AnnaBridge 187:0387e8f68319 84 I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */
AnnaBridge 187:0387e8f68319 85 GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */
AnnaBridge 187:0387e8f68319 86 TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */
AnnaBridge 187:0387e8f68319 87 TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */
AnnaBridge 187:0387e8f68319 88 TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */
AnnaBridge 187:0387e8f68319 89 USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */
AnnaBridge 187:0387e8f68319 90 USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */
AnnaBridge 187:0387e8f68319 91 USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */
AnnaBridge 187:0387e8f68319 92 USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */
AnnaBridge 187:0387e8f68319 93 UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */
AnnaBridge 187:0387e8f68319 94 UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */
AnnaBridge 187:0387e8f68319 95 UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */
AnnaBridge 187:0387e8f68319 96 UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */
AnnaBridge 187:0387e8f68319 97 LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */
AnnaBridge 187:0387e8f68319 98 LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */
AnnaBridge 187:0387e8f68319 99 LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */
AnnaBridge 187:0387e8f68319 100 PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */
AnnaBridge 187:0387e8f68319 101 PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */
AnnaBridge 187:0387e8f68319 102 PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */
AnnaBridge 187:0387e8f68319 103 RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */
AnnaBridge 187:0387e8f68319 104 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
AnnaBridge 187:0387e8f68319 105 MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */
AnnaBridge 187:0387e8f68319 106 CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */
AnnaBridge 187:0387e8f68319 107 CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */
AnnaBridge 187:0387e8f68319 108 FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */
AnnaBridge 187:0387e8f68319 109 USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */
AnnaBridge 187:0387e8f68319 110 USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */
AnnaBridge 187:0387e8f68319 111 USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */
AnnaBridge 187:0387e8f68319 112 USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */
AnnaBridge 187:0387e8f68319 113 WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */
AnnaBridge 187:0387e8f68319 114 WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */
AnnaBridge 187:0387e8f68319 115 WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */
AnnaBridge 187:0387e8f68319 116 WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */
AnnaBridge 187:0387e8f68319 117 I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */
AnnaBridge 187:0387e8f68319 118 VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */
AnnaBridge 187:0387e8f68319 119 TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */
AnnaBridge 187:0387e8f68319 120 TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */
AnnaBridge 187:0387e8f68319 121 TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */
AnnaBridge 187:0387e8f68319 122 USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */
AnnaBridge 187:0387e8f68319 123 USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */
AnnaBridge 187:0387e8f68319 124 CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */
AnnaBridge 187:0387e8f68319 125 LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */
AnnaBridge 187:0387e8f68319 126 EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */
AnnaBridge 187:0387e8f68319 127 ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */
AnnaBridge 187:0387e8f68319 128 ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */
AnnaBridge 187:0387e8f68319 129 LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */
AnnaBridge 187:0387e8f68319 130 SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */
AnnaBridge 187:0387e8f68319 131 ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */
AnnaBridge 187:0387e8f68319 132 CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */
AnnaBridge 187:0387e8f68319 133 CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */
AnnaBridge 187:0387e8f68319 134 USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */
AnnaBridge 187:0387e8f68319 135 RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */
AnnaBridge 187:0387e8f68319 136 WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */
AnnaBridge 187:0387e8f68319 137 LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */
AnnaBridge 187:0387e8f68319 138 TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */
AnnaBridge 187:0387e8f68319 139 QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */
AnnaBridge 187:0387e8f68319 140 } IRQn_Type;
AnnaBridge 187:0387e8f68319 141
AnnaBridge 187:0387e8f68319 142 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 143 * @defgroup EFM32GG11B820F2048IQ100_Core Core
AnnaBridge 187:0387e8f68319 144 * @{
AnnaBridge 187:0387e8f68319 145 * @brief Processor and Core Peripheral Section
AnnaBridge 187:0387e8f68319 146 *****************************************************************************/
AnnaBridge 187:0387e8f68319 147 #define __MPU_PRESENT 1 /**< Presence of MPU */
AnnaBridge 187:0387e8f68319 148 #define __FPU_PRESENT 1 /**< Presence of FPU */
AnnaBridge 187:0387e8f68319 149 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
AnnaBridge 187:0387e8f68319 150 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
AnnaBridge 187:0387e8f68319 151 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
AnnaBridge 187:0387e8f68319 152
AnnaBridge 187:0387e8f68319 153 /** @} End of group EFM32GG11B820F2048IQ100_Core */
AnnaBridge 187:0387e8f68319 154
AnnaBridge 187:0387e8f68319 155 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 156 * @defgroup EFM32GG11B820F2048IQ100_Part Part
AnnaBridge 187:0387e8f68319 157 * @{
AnnaBridge 187:0387e8f68319 158 ******************************************************************************/
AnnaBridge 187:0387e8f68319 159
AnnaBridge 187:0387e8f68319 160 /** Part family */
AnnaBridge 187:0387e8f68319 161
AnnaBridge 187:0387e8f68319 162 #define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */
AnnaBridge 187:0387e8f68319 163 #define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */
AnnaBridge 187:0387e8f68319 164 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
AnnaBridge 187:0387e8f68319 165 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
AnnaBridge 187:0387e8f68319 166 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
AnnaBridge 187:0387e8f68319 167 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
AnnaBridge 187:0387e8f68319 168 #define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */
AnnaBridge 187:0387e8f68319 169 #define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */
AnnaBridge 187:0387e8f68319 170 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
AnnaBridge 187:0387e8f68319 171 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
AnnaBridge 187:0387e8f68319 172 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
AnnaBridge 187:0387e8f68319 173 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
AnnaBridge 187:0387e8f68319 174
AnnaBridge 187:0387e8f68319 175 /* If part number is not defined as compiler option, define it */
AnnaBridge 187:0387e8f68319 176 #if !defined(EFM32GG11B820F2048IQ100)
AnnaBridge 187:0387e8f68319 177 #define EFM32GG11B820F2048IQ100 1 /**< GIANT Gecko Part */
AnnaBridge 187:0387e8f68319 178 #endif
AnnaBridge 187:0387e8f68319 179
AnnaBridge 187:0387e8f68319 180 /** Configure part number */
AnnaBridge 187:0387e8f68319 181 #define PART_NUMBER "EFM32GG11B820F2048IQ100" /**< Part Number */
AnnaBridge 187:0387e8f68319 182
AnnaBridge 187:0387e8f68319 183 /** Memory Base addresses and limits */
AnnaBridge 187:0387e8f68319 184 #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
AnnaBridge 187:0387e8f68319 185 #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
AnnaBridge 187:0387e8f68319 186 #define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
AnnaBridge 187:0387e8f68319 187 #define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
AnnaBridge 187:0387e8f68319 188 #define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
AnnaBridge 187:0387e8f68319 189 #define RAM2_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM2 available address space */
AnnaBridge 187:0387e8f68319 190 #define RAM2_MEM_END ((uint32_t) 0x2007FFFFUL) /**< RAM2 end address */
AnnaBridge 187:0387e8f68319 191 #define RAM2_MEM_BITS ((uint32_t) 0x00000012UL) /**< RAM2 used bits */
AnnaBridge 187:0387e8f68319 192 #define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
AnnaBridge 187:0387e8f68319 193 #define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
AnnaBridge 187:0387e8f68319 194 #define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
AnnaBridge 187:0387e8f68319 195 #define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
AnnaBridge 187:0387e8f68319 196 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
AnnaBridge 187:0387e8f68319 197 #define PER_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER available address space */
AnnaBridge 187:0387e8f68319 198 #define PER_MEM_END ((uint32_t) 0x4004FFFFUL) /**< PER end address */
AnnaBridge 187:0387e8f68319 199 #define PER_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER used bits */
AnnaBridge 187:0387e8f68319 200 #define SDIO_MEM_BASE ((uint32_t) 0x400F1000UL) /**< SDIO base address */
AnnaBridge 187:0387e8f68319 201 #define SDIO_MEM_SIZE ((uint32_t) 0x1000UL) /**< SDIO available address space */
AnnaBridge 187:0387e8f68319 202 #define SDIO_MEM_END ((uint32_t) 0x400F1FFFUL) /**< SDIO end address */
AnnaBridge 187:0387e8f68319 203 #define SDIO_MEM_BITS ((uint32_t) 0x0000000CUL) /**< SDIO used bits */
AnnaBridge 187:0387e8f68319 204 #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
AnnaBridge 187:0387e8f68319 205 #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
AnnaBridge 187:0387e8f68319 206 #define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
AnnaBridge 187:0387e8f68319 207 #define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
AnnaBridge 187:0387e8f68319 208 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
AnnaBridge 187:0387e8f68319 209 #define FLASH_MEM_SIZE ((uint32_t) 0x4000000UL) /**< FLASH available address space */
AnnaBridge 187:0387e8f68319 210 #define FLASH_MEM_END ((uint32_t) 0x03FFFFFFUL) /**< FLASH end address */
AnnaBridge 187:0387e8f68319 211 #define FLASH_MEM_BITS ((uint32_t) 0x0000001AUL) /**< FLASH used bits */
AnnaBridge 187:0387e8f68319 212 #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
AnnaBridge 187:0387e8f68319 213 #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
AnnaBridge 187:0387e8f68319 214 #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
AnnaBridge 187:0387e8f68319 215 #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
AnnaBridge 187:0387e8f68319 216 #define QSPI0_MEM_BASE ((uint32_t) 0xC0000000UL) /**< QSPI0 base address */
AnnaBridge 187:0387e8f68319 217 #define QSPI0_MEM_SIZE ((uint32_t) 0x10000000UL) /**< QSPI0 available address space */
AnnaBridge 187:0387e8f68319 218 #define QSPI0_MEM_END ((uint32_t) 0xCFFFFFFFUL) /**< QSPI0 end address */
AnnaBridge 187:0387e8f68319 219 #define QSPI0_MEM_BITS ((uint32_t) 0x0000001CUL) /**< QSPI0 used bits */
AnnaBridge 187:0387e8f68319 220 #define PER1_BITCLR_MEM_BASE ((uint32_t) 0x44050000UL) /**< PER1_BITCLR base address */
AnnaBridge 187:0387e8f68319 221 #define PER1_BITCLR_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1_BITCLR available address space */
AnnaBridge 187:0387e8f68319 222 #define PER1_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER1_BITCLR end address */
AnnaBridge 187:0387e8f68319 223 #define PER1_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1_BITCLR used bits */
AnnaBridge 187:0387e8f68319 224 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
AnnaBridge 187:0387e8f68319 225 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER_BITCLR available address space */
AnnaBridge 187:0387e8f68319 226 #define PER_BITCLR_MEM_END ((uint32_t) 0x4404FFFFUL) /**< PER_BITCLR end address */
AnnaBridge 187:0387e8f68319 227 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER_BITCLR used bits */
AnnaBridge 187:0387e8f68319 228 #define PER1_BITSET_MEM_BASE ((uint32_t) 0x46050000UL) /**< PER1_BITSET base address */
AnnaBridge 187:0387e8f68319 229 #define PER1_BITSET_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1_BITSET available address space */
AnnaBridge 187:0387e8f68319 230 #define PER1_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER1_BITSET end address */
AnnaBridge 187:0387e8f68319 231 #define PER1_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1_BITSET used bits */
AnnaBridge 187:0387e8f68319 232 #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
AnnaBridge 187:0387e8f68319 233 #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
AnnaBridge 187:0387e8f68319 234 #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
AnnaBridge 187:0387e8f68319 235 #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
AnnaBridge 187:0387e8f68319 236 #define USB_MEM_BASE ((uint32_t) 0x40100000UL) /**< USB base address */
AnnaBridge 187:0387e8f68319 237 #define USB_MEM_SIZE ((uint32_t) 0x40000UL) /**< USB available address space */
AnnaBridge 187:0387e8f68319 238 #define USB_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USB end address */
AnnaBridge 187:0387e8f68319 239 #define USB_MEM_BITS ((uint32_t) 0x00000012UL) /**< USB used bits */
AnnaBridge 187:0387e8f68319 240 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
AnnaBridge 187:0387e8f68319 241 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
AnnaBridge 187:0387e8f68319 242 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
AnnaBridge 187:0387e8f68319 243 #define EBI_CODE_MEM_BITS ((uint32_t) 0x0000001CUL) /**< EBI_CODE used bits */
AnnaBridge 187:0387e8f68319 244 #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
AnnaBridge 187:0387e8f68319 245 #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
AnnaBridge 187:0387e8f68319 246 #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
AnnaBridge 187:0387e8f68319 247 #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
AnnaBridge 187:0387e8f68319 248 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
AnnaBridge 187:0387e8f68319 249 #define PER_BITSET_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER_BITSET available address space */
AnnaBridge 187:0387e8f68319 250 #define PER_BITSET_MEM_END ((uint32_t) 0x4604FFFFUL) /**< PER_BITSET end address */
AnnaBridge 187:0387e8f68319 251 #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER_BITSET used bits */
AnnaBridge 187:0387e8f68319 252 #define PER1_MEM_BASE ((uint32_t) 0x40050000UL) /**< PER1 base address */
AnnaBridge 187:0387e8f68319 253 #define PER1_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1 available address space */
AnnaBridge 187:0387e8f68319 254 #define PER1_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER1 end address */
AnnaBridge 187:0387e8f68319 255 #define PER1_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1 used bits */
AnnaBridge 187:0387e8f68319 256 #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
AnnaBridge 187:0387e8f68319 257 #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM2_CODE available address space */
AnnaBridge 187:0387e8f68319 258 #define RAM2_CODE_MEM_END ((uint32_t) 0x1007FFFFUL) /**< RAM2_CODE end address */
AnnaBridge 187:0387e8f68319 259 #define RAM2_CODE_MEM_BITS ((uint32_t) 0x00000012UL) /**< RAM2_CODE used bits */
AnnaBridge 187:0387e8f68319 260 #define QSPI0_CODE_MEM_BASE ((uint32_t) 0x04000000UL) /**< QSPI0_CODE base address */
AnnaBridge 187:0387e8f68319 261 #define QSPI0_CODE_MEM_SIZE ((uint32_t) 0x8000000UL) /**< QSPI0_CODE available address space */
AnnaBridge 187:0387e8f68319 262 #define QSPI0_CODE_MEM_END ((uint32_t) 0x0BFFFFFFUL) /**< QSPI0_CODE end address */
AnnaBridge 187:0387e8f68319 263 #define QSPI0_CODE_MEM_BITS ((uint32_t) 0x0000001BUL) /**< QSPI0_CODE used bits */
AnnaBridge 187:0387e8f68319 264 #define FLASH_INFO_MEM_BASE ((uint32_t) 0x0F000000UL) /**< FLASH_INFO base address */
AnnaBridge 187:0387e8f68319 265 #define FLASH_INFO_MEM_SIZE ((uint32_t) 0x1000000UL) /**< FLASH_INFO available address space */
AnnaBridge 187:0387e8f68319 266 #define FLASH_INFO_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH_INFO end address */
AnnaBridge 187:0387e8f68319 267 #define FLASH_INFO_MEM_BITS ((uint32_t) 0x00000018UL) /**< FLASH_INFO used bits */
AnnaBridge 187:0387e8f68319 268 #define RAM0_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM0 base address */
AnnaBridge 187:0387e8f68319 269 #define RAM0_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0 available address space */
AnnaBridge 187:0387e8f68319 270 #define RAM0_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM0 end address */
AnnaBridge 187:0387e8f68319 271 #define RAM0_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0 used bits */
AnnaBridge 187:0387e8f68319 272 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
AnnaBridge 187:0387e8f68319 273 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
AnnaBridge 187:0387e8f68319 274 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
AnnaBridge 187:0387e8f68319 275 #define EBI_MEM_BITS ((uint32_t) 0x0000001EUL) /**< EBI used bits */
AnnaBridge 187:0387e8f68319 276
AnnaBridge 187:0387e8f68319 277 /** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */
AnnaBridge 187:0387e8f68319 278 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
AnnaBridge 187:0387e8f68319 279 #define RAM_MEM_SIZE ((uint32_t) 0x80000UL) /**< RAM available address space */
AnnaBridge 187:0387e8f68319 280 #define RAM_MEM_END ((uint32_t) 0x2007FFFFUL) /**< RAM end address */
AnnaBridge 187:0387e8f68319 281 #define RAM_MEM_BITS ((uint32_t) 0x00000013UL) /**< RAM used bits */
AnnaBridge 187:0387e8f68319 282
AnnaBridge 187:0387e8f68319 283 /** Bit banding area */
AnnaBridge 187:0387e8f68319 284 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
AnnaBridge 187:0387e8f68319 285 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
AnnaBridge 187:0387e8f68319 286
AnnaBridge 187:0387e8f68319 287 /** Flash and SRAM limits for EFM32GG11B820F2048IQ100 */
AnnaBridge 187:0387e8f68319 288 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
AnnaBridge 187:0387e8f68319 289 #define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */
AnnaBridge 187:0387e8f68319 290 #define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */
AnnaBridge 187:0387e8f68319 291 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
AnnaBridge 187:0387e8f68319 292 #define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */
AnnaBridge 187:0387e8f68319 293 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
AnnaBridge 187:0387e8f68319 294 #define PRS_CHAN_COUNT 24 /**< Number of PRS channels */
AnnaBridge 187:0387e8f68319 295 #define DMA_CHAN_COUNT 24 /**< Number of DMA channels */
AnnaBridge 187:0387e8f68319 296 #define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */
AnnaBridge 187:0387e8f68319 297
AnnaBridge 187:0387e8f68319 298 /** AF channels connect the different on-chip peripherals with the af-mux */
AnnaBridge 187:0387e8f68319 299 #define AFCHAN_MAX 355
AnnaBridge 187:0387e8f68319 300 /** AF channel maximum location number */
AnnaBridge 187:0387e8f68319 301 #define AFCHANLOC_MAX 8
AnnaBridge 187:0387e8f68319 302 /** Analog AF channels */
AnnaBridge 187:0387e8f68319 303 #define AFACHAN_MAX 184
AnnaBridge 187:0387e8f68319 304
AnnaBridge 187:0387e8f68319 305 /* Part number capabilities */
AnnaBridge 187:0387e8f68319 306
AnnaBridge 187:0387e8f68319 307 #define CRYPTO_PRESENT /**< CRYPTO is available in this part */
AnnaBridge 187:0387e8f68319 308 #define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */
AnnaBridge 187:0387e8f68319 309 #define CAN_PRESENT /**< CAN is available in this part */
AnnaBridge 187:0387e8f68319 310 #define CAN_COUNT 2 /**< 2 CANs available */
AnnaBridge 187:0387e8f68319 311 #define TIMER_PRESENT /**< TIMER is available in this part */
AnnaBridge 187:0387e8f68319 312 #define TIMER_COUNT 7 /**< 7 TIMERs available */
AnnaBridge 187:0387e8f68319 313 #define WTIMER_PRESENT /**< WTIMER is available in this part */
AnnaBridge 187:0387e8f68319 314 #define WTIMER_COUNT 4 /**< 4 WTIMERs available */
AnnaBridge 187:0387e8f68319 315 #define USART_PRESENT /**< USART is available in this part */
AnnaBridge 187:0387e8f68319 316 #define USART_COUNT 6 /**< 6 USARTs available */
AnnaBridge 187:0387e8f68319 317 #define UART_PRESENT /**< UART is available in this part */
AnnaBridge 187:0387e8f68319 318 #define UART_COUNT 2 /**< 2 UARTs available */
AnnaBridge 187:0387e8f68319 319 #define QSPI_PRESENT /**< QSPI is available in this part */
AnnaBridge 187:0387e8f68319 320 #define QSPI_COUNT 1 /**< 1 QSPIs available */
AnnaBridge 187:0387e8f68319 321 #define LEUART_PRESENT /**< LEUART is available in this part */
AnnaBridge 187:0387e8f68319 322 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
AnnaBridge 187:0387e8f68319 323 #define LETIMER_PRESENT /**< LETIMER is available in this part */
AnnaBridge 187:0387e8f68319 324 #define LETIMER_COUNT 2 /**< 2 LETIMERs available */
AnnaBridge 187:0387e8f68319 325 #define PCNT_PRESENT /**< PCNT is available in this part */
AnnaBridge 187:0387e8f68319 326 #define PCNT_COUNT 3 /**< 3 PCNTs available */
AnnaBridge 187:0387e8f68319 327 #define I2C_PRESENT /**< I2C is available in this part */
AnnaBridge 187:0387e8f68319 328 #define I2C_COUNT 3 /**< 3 I2Cs available */
AnnaBridge 187:0387e8f68319 329 #define ADC_PRESENT /**< ADC is available in this part */
AnnaBridge 187:0387e8f68319 330 #define ADC_COUNT 2 /**< 2 ADCs available */
AnnaBridge 187:0387e8f68319 331 #define ACMP_PRESENT /**< ACMP is available in this part */
AnnaBridge 187:0387e8f68319 332 #define ACMP_COUNT 4 /**< 4 ACMPs available */
AnnaBridge 187:0387e8f68319 333 #define VDAC_PRESENT /**< VDAC is available in this part */
AnnaBridge 187:0387e8f68319 334 #define VDAC_COUNT 1 /**< 1 VDACs available */
AnnaBridge 187:0387e8f68319 335 #define IDAC_PRESENT /**< IDAC is available in this part */
AnnaBridge 187:0387e8f68319 336 #define IDAC_COUNT 1 /**< 1 IDACs available */
AnnaBridge 187:0387e8f68319 337 #define WDOG_PRESENT /**< WDOG is available in this part */
AnnaBridge 187:0387e8f68319 338 #define WDOG_COUNT 2 /**< 2 WDOGs available */
AnnaBridge 187:0387e8f68319 339 #define TRNG_PRESENT /**< TRNG is available in this part */
AnnaBridge 187:0387e8f68319 340 #define TRNG_COUNT 1 /**< 1 TRNGs available */
AnnaBridge 187:0387e8f68319 341 #define MSC_PRESENT /**< MSC is available in this part */
AnnaBridge 187:0387e8f68319 342 #define MSC_COUNT 1 /**< 1 MSC available */
AnnaBridge 187:0387e8f68319 343 #define EMU_PRESENT /**< EMU is available in this part */
AnnaBridge 187:0387e8f68319 344 #define EMU_COUNT 1 /**< 1 EMU available */
AnnaBridge 187:0387e8f68319 345 #define RMU_PRESENT /**< RMU is available in this part */
AnnaBridge 187:0387e8f68319 346 #define RMU_COUNT 1 /**< 1 RMU available */
AnnaBridge 187:0387e8f68319 347 #define CMU_PRESENT /**< CMU is available in this part */
AnnaBridge 187:0387e8f68319 348 #define CMU_COUNT 1 /**< 1 CMU available */
AnnaBridge 187:0387e8f68319 349 #define LESENSE_PRESENT /**< LESENSE is available in this part */
AnnaBridge 187:0387e8f68319 350 #define LESENSE_COUNT 1 /**< 1 LESENSE available */
AnnaBridge 187:0387e8f68319 351 #define EBI_PRESENT /**< EBI is available in this part */
AnnaBridge 187:0387e8f68319 352 #define EBI_COUNT 1 /**< 1 EBI available */
AnnaBridge 187:0387e8f68319 353 #define ETH_PRESENT /**< ETH is available in this part */
AnnaBridge 187:0387e8f68319 354 #define ETH_COUNT 1 /**< 1 ETH available */
AnnaBridge 187:0387e8f68319 355 #define SDIO_PRESENT /**< SDIO is available in this part */
AnnaBridge 187:0387e8f68319 356 #define SDIO_COUNT 1 /**< 1 SDIO available */
AnnaBridge 187:0387e8f68319 357 #define GPIO_PRESENT /**< GPIO is available in this part */
AnnaBridge 187:0387e8f68319 358 #define GPIO_COUNT 1 /**< 1 GPIO available */
AnnaBridge 187:0387e8f68319 359 #define PRS_PRESENT /**< PRS is available in this part */
AnnaBridge 187:0387e8f68319 360 #define PRS_COUNT 1 /**< 1 PRS available */
AnnaBridge 187:0387e8f68319 361 #define LDMA_PRESENT /**< LDMA is available in this part */
AnnaBridge 187:0387e8f68319 362 #define LDMA_COUNT 1 /**< 1 LDMA available */
AnnaBridge 187:0387e8f68319 363 #define FPUEH_PRESENT /**< FPUEH is available in this part */
AnnaBridge 187:0387e8f68319 364 #define FPUEH_COUNT 1 /**< 1 FPUEH available */
AnnaBridge 187:0387e8f68319 365 #define GPCRC_PRESENT /**< GPCRC is available in this part */
AnnaBridge 187:0387e8f68319 366 #define GPCRC_COUNT 1 /**< 1 GPCRC available */
AnnaBridge 187:0387e8f68319 367 #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
AnnaBridge 187:0387e8f68319 368 #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
AnnaBridge 187:0387e8f68319 369 #define USB_PRESENT /**< USB is available in this part */
AnnaBridge 187:0387e8f68319 370 #define USB_COUNT 1 /**< 1 USB available */
AnnaBridge 187:0387e8f68319 371 #define CSEN_PRESENT /**< CSEN is available in this part */
AnnaBridge 187:0387e8f68319 372 #define CSEN_COUNT 1 /**< 1 CSEN available */
AnnaBridge 187:0387e8f68319 373 #define LCD_PRESENT /**< LCD is available in this part */
AnnaBridge 187:0387e8f68319 374 #define LCD_COUNT 1 /**< 1 LCD available */
AnnaBridge 187:0387e8f68319 375 #define RTC_PRESENT /**< RTC is available in this part */
AnnaBridge 187:0387e8f68319 376 #define RTC_COUNT 1 /**< 1 RTC available */
AnnaBridge 187:0387e8f68319 377 #define RTCC_PRESENT /**< RTCC is available in this part */
AnnaBridge 187:0387e8f68319 378 #define RTCC_COUNT 1 /**< 1 RTCC available */
AnnaBridge 187:0387e8f68319 379 #define ETM_PRESENT /**< ETM is available in this part */
AnnaBridge 187:0387e8f68319 380 #define ETM_COUNT 1 /**< 1 ETM available */
AnnaBridge 187:0387e8f68319 381 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
AnnaBridge 187:0387e8f68319 382 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
AnnaBridge 187:0387e8f68319 383 #define SMU_PRESENT /**< SMU is available in this part */
AnnaBridge 187:0387e8f68319 384 #define SMU_COUNT 1 /**< 1 SMU available */
AnnaBridge 187:0387e8f68319 385
AnnaBridge 187:0387e8f68319 386 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 187:0387e8f68319 387 #include "system_efm32gg11b.h" /* System Header File */
AnnaBridge 187:0387e8f68319 388
AnnaBridge 187:0387e8f68319 389 /** @} End of group EFM32GG11B820F2048IQ100_Part */
AnnaBridge 187:0387e8f68319 390
AnnaBridge 187:0387e8f68319 391 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 392 * @defgroup EFM32GG11B820F2048IQ100_Peripheral_TypeDefs Peripheral TypeDefs
AnnaBridge 187:0387e8f68319 393 * @{
AnnaBridge 187:0387e8f68319 394 * @brief Device Specific Peripheral Register Structures
AnnaBridge 187:0387e8f68319 395 *****************************************************************************/
AnnaBridge 187:0387e8f68319 396
AnnaBridge 187:0387e8f68319 397 #include "efm32gg11b_msc.h"
AnnaBridge 187:0387e8f68319 398 #include "efm32gg11b_emu.h"
AnnaBridge 187:0387e8f68319 399 #include "efm32gg11b_rmu.h"
AnnaBridge 187:0387e8f68319 400 #include "efm32gg11b_cmu.h"
AnnaBridge 187:0387e8f68319 401 #include "efm32gg11b_crypto.h"
AnnaBridge 187:0387e8f68319 402 #include "efm32gg11b_lesense_st.h"
AnnaBridge 187:0387e8f68319 403 #include "efm32gg11b_lesense_buf.h"
AnnaBridge 187:0387e8f68319 404 #include "efm32gg11b_lesense_ch.h"
AnnaBridge 187:0387e8f68319 405 #include "efm32gg11b_lesense.h"
AnnaBridge 187:0387e8f68319 406 #include "efm32gg11b_ebi.h"
AnnaBridge 187:0387e8f68319 407 #include "efm32gg11b_eth.h"
AnnaBridge 187:0387e8f68319 408 #include "efm32gg11b_sdio.h"
AnnaBridge 187:0387e8f68319 409 #include "efm32gg11b_gpio_p.h"
AnnaBridge 187:0387e8f68319 410 #include "efm32gg11b_gpio.h"
AnnaBridge 187:0387e8f68319 411 #include "efm32gg11b_prs_ch.h"
AnnaBridge 187:0387e8f68319 412 #include "efm32gg11b_prs.h"
AnnaBridge 187:0387e8f68319 413 #include "efm32gg11b_ldma_ch.h"
AnnaBridge 187:0387e8f68319 414 #include "efm32gg11b_ldma.h"
AnnaBridge 187:0387e8f68319 415 #include "efm32gg11b_fpueh.h"
AnnaBridge 187:0387e8f68319 416 #include "efm32gg11b_gpcrc.h"
AnnaBridge 187:0387e8f68319 417 #include "efm32gg11b_can_mir.h"
AnnaBridge 187:0387e8f68319 418 #include "efm32gg11b_can.h"
AnnaBridge 187:0387e8f68319 419 #include "efm32gg11b_timer_cc.h"
AnnaBridge 187:0387e8f68319 420 #include "efm32gg11b_timer.h"
AnnaBridge 187:0387e8f68319 421 #include "efm32gg11b_usart.h"
AnnaBridge 187:0387e8f68319 422 #include "efm32gg11b_qspi.h"
AnnaBridge 187:0387e8f68319 423 #include "efm32gg11b_leuart.h"
AnnaBridge 187:0387e8f68319 424 #include "efm32gg11b_letimer.h"
AnnaBridge 187:0387e8f68319 425 #include "efm32gg11b_cryotimer.h"
AnnaBridge 187:0387e8f68319 426 #include "efm32gg11b_pcnt.h"
AnnaBridge 187:0387e8f68319 427 #include "efm32gg11b_i2c.h"
AnnaBridge 187:0387e8f68319 428 #include "efm32gg11b_adc.h"
AnnaBridge 187:0387e8f68319 429 #include "efm32gg11b_acmp.h"
AnnaBridge 187:0387e8f68319 430 #include "efm32gg11b_vdac_opa.h"
AnnaBridge 187:0387e8f68319 431 #include "efm32gg11b_vdac.h"
AnnaBridge 187:0387e8f68319 432 #include "efm32gg11b_usb_hc.h"
AnnaBridge 187:0387e8f68319 433 #include "efm32gg11b_usb_diep.h"
AnnaBridge 187:0387e8f68319 434 #include "efm32gg11b_usb_doep.h"
AnnaBridge 187:0387e8f68319 435 #include "efm32gg11b_usb.h"
AnnaBridge 187:0387e8f68319 436 #include "efm32gg11b_idac.h"
AnnaBridge 187:0387e8f68319 437 #include "efm32gg11b_csen.h"
AnnaBridge 187:0387e8f68319 438 #include "efm32gg11b_lcd.h"
AnnaBridge 187:0387e8f68319 439 #include "efm32gg11b_rtc_comp.h"
AnnaBridge 187:0387e8f68319 440 #include "efm32gg11b_rtc.h"
AnnaBridge 187:0387e8f68319 441 #include "efm32gg11b_rtcc_cc.h"
AnnaBridge 187:0387e8f68319 442 #include "efm32gg11b_rtcc_ret.h"
AnnaBridge 187:0387e8f68319 443 #include "efm32gg11b_rtcc.h"
AnnaBridge 187:0387e8f68319 444 #include "efm32gg11b_wdog_pch.h"
AnnaBridge 187:0387e8f68319 445 #include "efm32gg11b_wdog.h"
AnnaBridge 187:0387e8f68319 446 #include "efm32gg11b_etm.h"
AnnaBridge 187:0387e8f68319 447 #include "efm32gg11b_smu.h"
AnnaBridge 187:0387e8f68319 448 #include "efm32gg11b_trng.h"
AnnaBridge 187:0387e8f68319 449 #include "efm32gg11b_dma_descriptor.h"
AnnaBridge 187:0387e8f68319 450 #include "efm32gg11b_perpriv_register.h"
AnnaBridge 187:0387e8f68319 451 #include "efm32gg11b_devinfo.h"
AnnaBridge 187:0387e8f68319 452 #include "efm32gg11b_romtable.h"
AnnaBridge 187:0387e8f68319 453
AnnaBridge 187:0387e8f68319 454 /** @} End of group EFM32GG11B820F2048IQ100_Peripheral_TypeDefs */
AnnaBridge 187:0387e8f68319 455
AnnaBridge 187:0387e8f68319 456 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 457 * @defgroup EFM32GG11B820F2048IQ100_Peripheral_Base Peripheral Memory Map
AnnaBridge 187:0387e8f68319 458 * @{
AnnaBridge 187:0387e8f68319 459 *****************************************************************************/
AnnaBridge 187:0387e8f68319 460
AnnaBridge 187:0387e8f68319 461 #define MSC_BASE (0x40000000UL) /**< MSC base address */
AnnaBridge 187:0387e8f68319 462 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
AnnaBridge 187:0387e8f68319 463 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
AnnaBridge 187:0387e8f68319 464 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
AnnaBridge 187:0387e8f68319 465 #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */
AnnaBridge 187:0387e8f68319 466 #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
AnnaBridge 187:0387e8f68319 467 #define EBI_BASE (0x4000B000UL) /**< EBI base address */
AnnaBridge 187:0387e8f68319 468 #define ETH_BASE (0x40024000UL) /**< ETH base address */
AnnaBridge 187:0387e8f68319 469 #define SDIO_BASE (0x400F1000UL) /**< SDIO base address */
AnnaBridge 187:0387e8f68319 470 #define GPIO_BASE (0x40088000UL) /**< GPIO base address */
AnnaBridge 187:0387e8f68319 471 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
AnnaBridge 187:0387e8f68319 472 #define LDMA_BASE (0x40002000UL) /**< LDMA base address */
AnnaBridge 187:0387e8f68319 473 #define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */
AnnaBridge 187:0387e8f68319 474 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
AnnaBridge 187:0387e8f68319 475 #define CAN0_BASE (0x40004000UL) /**< CAN0 base address */
AnnaBridge 187:0387e8f68319 476 #define CAN1_BASE (0x40004400UL) /**< CAN1 base address */
AnnaBridge 187:0387e8f68319 477 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
AnnaBridge 187:0387e8f68319 478 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
AnnaBridge 187:0387e8f68319 479 #define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */
AnnaBridge 187:0387e8f68319 480 #define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */
AnnaBridge 187:0387e8f68319 481 #define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */
AnnaBridge 187:0387e8f68319 482 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */
AnnaBridge 187:0387e8f68319 483 #define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */
AnnaBridge 187:0387e8f68319 484 #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
AnnaBridge 187:0387e8f68319 485 #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
AnnaBridge 187:0387e8f68319 486 #define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */
AnnaBridge 187:0387e8f68319 487 #define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */
AnnaBridge 187:0387e8f68319 488 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
AnnaBridge 187:0387e8f68319 489 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
AnnaBridge 187:0387e8f68319 490 #define USART2_BASE (0x40010800UL) /**< USART2 base address */
AnnaBridge 187:0387e8f68319 491 #define USART3_BASE (0x40010C00UL) /**< USART3 base address */
AnnaBridge 187:0387e8f68319 492 #define USART4_BASE (0x40011000UL) /**< USART4 base address */
AnnaBridge 187:0387e8f68319 493 #define USART5_BASE (0x40011400UL) /**< USART5 base address */
AnnaBridge 187:0387e8f68319 494 #define UART0_BASE (0x40014000UL) /**< UART0 base address */
AnnaBridge 187:0387e8f68319 495 #define UART1_BASE (0x40014400UL) /**< UART1 base address */
AnnaBridge 187:0387e8f68319 496 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */
AnnaBridge 187:0387e8f68319 497 #define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */
AnnaBridge 187:0387e8f68319 498 #define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */
AnnaBridge 187:0387e8f68319 499 #define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */
AnnaBridge 187:0387e8f68319 500 #define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */
AnnaBridge 187:0387e8f68319 501 #define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */
AnnaBridge 187:0387e8f68319 502 #define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */
AnnaBridge 187:0387e8f68319 503 #define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */
AnnaBridge 187:0387e8f68319 504 #define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */
AnnaBridge 187:0387e8f68319 505 #define I2C0_BASE (0x40089000UL) /**< I2C0 base address */
AnnaBridge 187:0387e8f68319 506 #define I2C1_BASE (0x40089400UL) /**< I2C1 base address */
AnnaBridge 187:0387e8f68319 507 #define I2C2_BASE (0x40089800UL) /**< I2C2 base address */
AnnaBridge 187:0387e8f68319 508 #define ADC0_BASE (0x40082000UL) /**< ADC0 base address */
AnnaBridge 187:0387e8f68319 509 #define ADC1_BASE (0x40082400UL) /**< ADC1 base address */
AnnaBridge 187:0387e8f68319 510 #define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */
AnnaBridge 187:0387e8f68319 511 #define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */
AnnaBridge 187:0387e8f68319 512 #define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */
AnnaBridge 187:0387e8f68319 513 #define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */
AnnaBridge 187:0387e8f68319 514 #define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */
AnnaBridge 187:0387e8f68319 515 #define USB_BASE (0x40022000UL) /**< USB base address */
AnnaBridge 187:0387e8f68319 516 #define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */
AnnaBridge 187:0387e8f68319 517 #define CSEN_BASE (0x4008E000UL) /**< CSEN base address */
AnnaBridge 187:0387e8f68319 518 #define LCD_BASE (0x40054000UL) /**< LCD base address */
AnnaBridge 187:0387e8f68319 519 #define RTC_BASE (0x40060000UL) /**< RTC base address */
AnnaBridge 187:0387e8f68319 520 #define RTCC_BASE (0x40062000UL) /**< RTCC base address */
AnnaBridge 187:0387e8f68319 521 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
AnnaBridge 187:0387e8f68319 522 #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
AnnaBridge 187:0387e8f68319 523 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
AnnaBridge 187:0387e8f68319 524 #define SMU_BASE (0x40020000UL) /**< SMU base address */
AnnaBridge 187:0387e8f68319 525 #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
AnnaBridge 187:0387e8f68319 526 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
AnnaBridge 187:0387e8f68319 527 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
AnnaBridge 187:0387e8f68319 528 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
AnnaBridge 187:0387e8f68319 529 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
AnnaBridge 187:0387e8f68319 530
AnnaBridge 187:0387e8f68319 531 /** @} End of group EFM32GG11B820F2048IQ100_Peripheral_Base */
AnnaBridge 187:0387e8f68319 532
AnnaBridge 187:0387e8f68319 533 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 534 * @defgroup EFM32GG11B820F2048IQ100_Peripheral_Declaration Peripheral Declarations
AnnaBridge 187:0387e8f68319 535 * @{
AnnaBridge 187:0387e8f68319 536 *****************************************************************************/
AnnaBridge 187:0387e8f68319 537
AnnaBridge 187:0387e8f68319 538 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
AnnaBridge 187:0387e8f68319 539 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
AnnaBridge 187:0387e8f68319 540 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
AnnaBridge 187:0387e8f68319 541 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
AnnaBridge 187:0387e8f68319 542 #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */
AnnaBridge 187:0387e8f68319 543 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
AnnaBridge 187:0387e8f68319 544 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
AnnaBridge 187:0387e8f68319 545 #define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */
AnnaBridge 187:0387e8f68319 546 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */
AnnaBridge 187:0387e8f68319 547 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
AnnaBridge 187:0387e8f68319 548 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
AnnaBridge 187:0387e8f68319 549 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
AnnaBridge 187:0387e8f68319 550 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
AnnaBridge 187:0387e8f68319 551 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
AnnaBridge 187:0387e8f68319 552 #define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */
AnnaBridge 187:0387e8f68319 553 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */
AnnaBridge 187:0387e8f68319 554 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
AnnaBridge 187:0387e8f68319 555 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
AnnaBridge 187:0387e8f68319 556 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
AnnaBridge 187:0387e8f68319 557 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
AnnaBridge 187:0387e8f68319 558 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */
AnnaBridge 187:0387e8f68319 559 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
AnnaBridge 187:0387e8f68319 560 #define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */
AnnaBridge 187:0387e8f68319 561 #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
AnnaBridge 187:0387e8f68319 562 #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
AnnaBridge 187:0387e8f68319 563 #define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */
AnnaBridge 187:0387e8f68319 564 #define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */
AnnaBridge 187:0387e8f68319 565 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
AnnaBridge 187:0387e8f68319 566 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
AnnaBridge 187:0387e8f68319 567 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
AnnaBridge 187:0387e8f68319 568 #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
AnnaBridge 187:0387e8f68319 569 #define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */
AnnaBridge 187:0387e8f68319 570 #define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */
AnnaBridge 187:0387e8f68319 571 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
AnnaBridge 187:0387e8f68319 572 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
AnnaBridge 187:0387e8f68319 573 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
AnnaBridge 187:0387e8f68319 574 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
AnnaBridge 187:0387e8f68319 575 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
AnnaBridge 187:0387e8f68319 576 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
AnnaBridge 187:0387e8f68319 577 #define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */
AnnaBridge 187:0387e8f68319 578 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
AnnaBridge 187:0387e8f68319 579 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
AnnaBridge 187:0387e8f68319 580 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
AnnaBridge 187:0387e8f68319 581 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
AnnaBridge 187:0387e8f68319 582 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
AnnaBridge 187:0387e8f68319 583 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
AnnaBridge 187:0387e8f68319 584 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */
AnnaBridge 187:0387e8f68319 585 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
AnnaBridge 187:0387e8f68319 586 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */
AnnaBridge 187:0387e8f68319 587 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
AnnaBridge 187:0387e8f68319 588 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
AnnaBridge 187:0387e8f68319 589 #define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */
AnnaBridge 187:0387e8f68319 590 #define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */
AnnaBridge 187:0387e8f68319 591 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
AnnaBridge 187:0387e8f68319 592 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
AnnaBridge 187:0387e8f68319 593 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
AnnaBridge 187:0387e8f68319 594 #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
AnnaBridge 187:0387e8f68319 595 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
AnnaBridge 187:0387e8f68319 596 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
AnnaBridge 187:0387e8f68319 597 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
AnnaBridge 187:0387e8f68319 598 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
AnnaBridge 187:0387e8f68319 599 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
AnnaBridge 187:0387e8f68319 600 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
AnnaBridge 187:0387e8f68319 601 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
AnnaBridge 187:0387e8f68319 602 #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
AnnaBridge 187:0387e8f68319 603 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
AnnaBridge 187:0387e8f68319 604 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
AnnaBridge 187:0387e8f68319 605
AnnaBridge 187:0387e8f68319 606 /** @} End of group EFM32GG11B820F2048IQ100_Peripheral_Declaration */
AnnaBridge 187:0387e8f68319 607
AnnaBridge 187:0387e8f68319 608 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 609 * @defgroup EFM32GG11B820F2048IQ100_Peripheral_Offsets Peripheral Offsets
AnnaBridge 187:0387e8f68319 610 * @{
AnnaBridge 187:0387e8f68319 611 *****************************************************************************/
AnnaBridge 187:0387e8f68319 612
AnnaBridge 187:0387e8f68319 613 #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
AnnaBridge 187:0387e8f68319 614 #define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */
AnnaBridge 187:0387e8f68319 615 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
AnnaBridge 187:0387e8f68319 616 #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */
AnnaBridge 187:0387e8f68319 617 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
AnnaBridge 187:0387e8f68319 618 #define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */
AnnaBridge 187:0387e8f68319 619 #define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */
AnnaBridge 187:0387e8f68319 620 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
AnnaBridge 187:0387e8f68319 621 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
AnnaBridge 187:0387e8f68319 622 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
AnnaBridge 187:0387e8f68319 623 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
AnnaBridge 187:0387e8f68319 624 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
AnnaBridge 187:0387e8f68319 625 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
AnnaBridge 187:0387e8f68319 626 #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
AnnaBridge 187:0387e8f68319 627 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
AnnaBridge 187:0387e8f68319 628 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
AnnaBridge 187:0387e8f68319 629 #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
AnnaBridge 187:0387e8f68319 630
AnnaBridge 187:0387e8f68319 631 /** @} End of group EFM32GG11B820F2048IQ100_Peripheral_Offsets */
AnnaBridge 187:0387e8f68319 632
AnnaBridge 187:0387e8f68319 633 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 634 * @defgroup EFM32GG11B820F2048IQ100_BitFields Bit Fields
AnnaBridge 187:0387e8f68319 635 * @{
AnnaBridge 187:0387e8f68319 636 *****************************************************************************/
AnnaBridge 187:0387e8f68319 637
AnnaBridge 187:0387e8f68319 638 #include "efm32gg11b_prs_signals.h"
AnnaBridge 187:0387e8f68319 639 #include "efm32gg11b_dmareq.h"
AnnaBridge 187:0387e8f68319 640
AnnaBridge 187:0387e8f68319 641 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 642 * @addtogroup EFM32GG11B820F2048IQ100_WTIMER
AnnaBridge 187:0387e8f68319 643 * @{
AnnaBridge 187:0387e8f68319 644 * @defgroup EFM32GG11B820F2048IQ100_WTIMER_BitFields WTIMER Bit Fields
AnnaBridge 187:0387e8f68319 645 * @{
AnnaBridge 187:0387e8f68319 646 *****************************************************************************/
AnnaBridge 187:0387e8f68319 647
AnnaBridge 187:0387e8f68319 648 /* Bit fields for WTIMER CTRL */
AnnaBridge 187:0387e8f68319 649 #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 650 #define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 651 #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
AnnaBridge 187:0387e8f68319 652 #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
AnnaBridge 187:0387e8f68319 653 #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 654 #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 655 #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 656 #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 657 #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 658 #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 659 #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 660 #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 661 #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 662 #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 663 #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
AnnaBridge 187:0387e8f68319 664 #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
AnnaBridge 187:0387e8f68319 665 #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
AnnaBridge 187:0387e8f68319 666 #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 667 #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 668 #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
AnnaBridge 187:0387e8f68319 669 #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
AnnaBridge 187:0387e8f68319 670 #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
AnnaBridge 187:0387e8f68319 671 #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 672 #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 673 #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
AnnaBridge 187:0387e8f68319 674 #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
AnnaBridge 187:0387e8f68319 675 #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
AnnaBridge 187:0387e8f68319 676 #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 677 #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 678 #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 679 #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 680 #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 681 #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 682 #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
AnnaBridge 187:0387e8f68319 683 #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
AnnaBridge 187:0387e8f68319 684 #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
AnnaBridge 187:0387e8f68319 685 #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 686 #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 687 #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
AnnaBridge 187:0387e8f68319 688 #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
AnnaBridge 187:0387e8f68319 689 #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
AnnaBridge 187:0387e8f68319 690 #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 691 #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 692 #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
AnnaBridge 187:0387e8f68319 693 #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
AnnaBridge 187:0387e8f68319 694 #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 695 #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 696 #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 697 #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 698 #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 699 #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 700 #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 701 #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 702 #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 703 #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 704 #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
AnnaBridge 187:0387e8f68319 705 #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
AnnaBridge 187:0387e8f68319 706 #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 707 #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 708 #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 709 #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 710 #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 711 #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 712 #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 713 #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 714 #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 715 #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 716 #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
AnnaBridge 187:0387e8f68319 717 #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
AnnaBridge 187:0387e8f68319 718 #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
AnnaBridge 187:0387e8f68319 719 #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 720 #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 721 #define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer from Start/Stop/Reload other Synchronized Timers */
AnnaBridge 187:0387e8f68319 722 #define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
AnnaBridge 187:0387e8f68319 723 #define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
AnnaBridge 187:0387e8f68319 724 #define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 725 #define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 726 #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
AnnaBridge 187:0387e8f68319 727 #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
AnnaBridge 187:0387e8f68319 728 #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 729 #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 730 #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 731 #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 732 #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 733 #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 734 #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 735 #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 736 #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
AnnaBridge 187:0387e8f68319 737 #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
AnnaBridge 187:0387e8f68319 738 #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 739 #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 740 #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 741 #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 742 #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 743 #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 744 #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 745 #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 746 #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 747 #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 748 #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 749 #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 750 #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 751 #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 752 #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 753 #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 754 #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 755 #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 756 #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 757 #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 758 #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 759 #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 760 #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 761 #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 762 #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
AnnaBridge 187:0387e8f68319 763 #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
AnnaBridge 187:0387e8f68319 764 #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
AnnaBridge 187:0387e8f68319 765 #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 766 #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 767 #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
AnnaBridge 187:0387e8f68319 768 #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
AnnaBridge 187:0387e8f68319 769 #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
AnnaBridge 187:0387e8f68319 770 #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 771 #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 187:0387e8f68319 772
AnnaBridge 187:0387e8f68319 773 /* Bit fields for WTIMER CMD */
AnnaBridge 187:0387e8f68319 774 #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */
AnnaBridge 187:0387e8f68319 775 #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */
AnnaBridge 187:0387e8f68319 776 #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */
AnnaBridge 187:0387e8f68319 777 #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
AnnaBridge 187:0387e8f68319 778 #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
AnnaBridge 187:0387e8f68319 779 #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
AnnaBridge 187:0387e8f68319 780 #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */
AnnaBridge 187:0387e8f68319 781 #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
AnnaBridge 187:0387e8f68319 782 #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
AnnaBridge 187:0387e8f68319 783 #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
AnnaBridge 187:0387e8f68319 784 #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
AnnaBridge 187:0387e8f68319 785 #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */
AnnaBridge 187:0387e8f68319 786
AnnaBridge 187:0387e8f68319 787 /* Bit fields for WTIMER STATUS */
AnnaBridge 187:0387e8f68319 788 #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 789 #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 790 #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
AnnaBridge 187:0387e8f68319 791 #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
AnnaBridge 187:0387e8f68319 792 #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
AnnaBridge 187:0387e8f68319 793 #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 794 #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 795 #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
AnnaBridge 187:0387e8f68319 796 #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
AnnaBridge 187:0387e8f68319 797 #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
AnnaBridge 187:0387e8f68319 798 #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 799 #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 800 #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 801 #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 802 #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 803 #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 804 #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
AnnaBridge 187:0387e8f68319 805 #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
AnnaBridge 187:0387e8f68319 806 #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
AnnaBridge 187:0387e8f68319 807 #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 808 #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 809 #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
AnnaBridge 187:0387e8f68319 810 #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
AnnaBridge 187:0387e8f68319 811 #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
AnnaBridge 187:0387e8f68319 812 #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 813 #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 814 #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
AnnaBridge 187:0387e8f68319 815 #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
AnnaBridge 187:0387e8f68319 816 #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
AnnaBridge 187:0387e8f68319 817 #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 818 #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 819 #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
AnnaBridge 187:0387e8f68319 820 #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
AnnaBridge 187:0387e8f68319 821 #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
AnnaBridge 187:0387e8f68319 822 #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 823 #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 824 #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
AnnaBridge 187:0387e8f68319 825 #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
AnnaBridge 187:0387e8f68319 826 #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
AnnaBridge 187:0387e8f68319 827 #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 828 #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 829 #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
AnnaBridge 187:0387e8f68319 830 #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
AnnaBridge 187:0387e8f68319 831 #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
AnnaBridge 187:0387e8f68319 832 #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 833 #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 834 #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
AnnaBridge 187:0387e8f68319 835 #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
AnnaBridge 187:0387e8f68319 836 #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
AnnaBridge 187:0387e8f68319 837 #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 838 #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 839 #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
AnnaBridge 187:0387e8f68319 840 #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
AnnaBridge 187:0387e8f68319 841 #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
AnnaBridge 187:0387e8f68319 842 #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 843 #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 844 #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
AnnaBridge 187:0387e8f68319 845 #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
AnnaBridge 187:0387e8f68319 846 #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
AnnaBridge 187:0387e8f68319 847 #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 848 #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 849 #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
AnnaBridge 187:0387e8f68319 850 #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
AnnaBridge 187:0387e8f68319 851 #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
AnnaBridge 187:0387e8f68319 852 #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 853 #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 854 #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 855 #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 856 #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 857 #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 858 #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
AnnaBridge 187:0387e8f68319 859 #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
AnnaBridge 187:0387e8f68319 860 #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
AnnaBridge 187:0387e8f68319 861 #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 862 #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 863 #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 864 #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 865 #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 866 #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 867 #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
AnnaBridge 187:0387e8f68319 868 #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
AnnaBridge 187:0387e8f68319 869 #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
AnnaBridge 187:0387e8f68319 870 #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 871 #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 872 #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 873 #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 874 #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 875 #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 876 #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
AnnaBridge 187:0387e8f68319 877 #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
AnnaBridge 187:0387e8f68319 878 #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
AnnaBridge 187:0387e8f68319 879 #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 880 #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 881 #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 882 #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 883 #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 884 #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 187:0387e8f68319 885
AnnaBridge 187:0387e8f68319 886 /* Bit fields for WTIMER IF */
AnnaBridge 187:0387e8f68319 887 #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */
AnnaBridge 187:0387e8f68319 888 #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */
AnnaBridge 187:0387e8f68319 889 #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 890 #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 187:0387e8f68319 891 #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 187:0387e8f68319 892 #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 893 #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 894 #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 895 #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 187:0387e8f68319 896 #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 187:0387e8f68319 897 #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 898 #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 899 #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
AnnaBridge 187:0387e8f68319 900 #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 901 #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 902 #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 903 #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 904 #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 905 #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 906 #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 907 #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 908 #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 909 #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 910 #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 911 #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 912 #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 913 #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 914 #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 915 #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 916 #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 917 #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 918 #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 919 #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
AnnaBridge 187:0387e8f68319 920 #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 921 #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 922 #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 923 #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 924 #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 925 #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 926 #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 927 #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 928 #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 929 #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 930 #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 931 #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 932 #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 933 #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 934 #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 935 #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 936 #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 937 #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 938 #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 939 #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 187:0387e8f68319 940 #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 941 #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 942 #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 943 #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 187:0387e8f68319 944
AnnaBridge 187:0387e8f68319 945 /* Bit fields for WTIMER IFS */
AnnaBridge 187:0387e8f68319 946 #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 947 #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 948 #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
AnnaBridge 187:0387e8f68319 949 #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 187:0387e8f68319 950 #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 187:0387e8f68319 951 #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 952 #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 953 #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
AnnaBridge 187:0387e8f68319 954 #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 187:0387e8f68319 955 #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 187:0387e8f68319 956 #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 957 #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 958 #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
AnnaBridge 187:0387e8f68319 959 #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 960 #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 961 #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 962 #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 963 #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 964 #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 965 #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 966 #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 967 #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 968 #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 969 #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 970 #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 971 #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 972 #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 973 #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 974 #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 975 #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 976 #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 977 #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 978 #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
AnnaBridge 187:0387e8f68319 979 #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 980 #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 981 #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 982 #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 983 #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 984 #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 985 #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 986 #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 987 #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 988 #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 989 #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 990 #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 991 #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 992 #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 993 #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 994 #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 995 #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 996 #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 997 #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 998 #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
AnnaBridge 187:0387e8f68319 999 #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 1000 #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 1001 #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 1002 #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 187:0387e8f68319 1003
AnnaBridge 187:0387e8f68319 1004 /* Bit fields for WTIMER IFC */
AnnaBridge 187:0387e8f68319 1005 #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1006 #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1007 #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
AnnaBridge 187:0387e8f68319 1008 #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 187:0387e8f68319 1009 #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 187:0387e8f68319 1010 #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1011 #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1012 #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
AnnaBridge 187:0387e8f68319 1013 #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 187:0387e8f68319 1014 #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 187:0387e8f68319 1015 #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1016 #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1017 #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
AnnaBridge 187:0387e8f68319 1018 #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 1019 #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 1020 #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1021 #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1022 #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1023 #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 1024 #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 1025 #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1026 #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1027 #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1028 #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 1029 #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 1030 #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1031 #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1032 #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1033 #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 1034 #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 1035 #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1036 #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1037 #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1038 #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 1039 #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 1040 #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1041 #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1042 #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1043 #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 1044 #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 1045 #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1046 #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1047 #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1048 #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 1049 #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 1050 #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1051 #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1052 #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1053 #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 1054 #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 1055 #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1056 #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1057 #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
AnnaBridge 187:0387e8f68319 1058 #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 1059 #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 1060 #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1061 #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 187:0387e8f68319 1062
AnnaBridge 187:0387e8f68319 1063 /* Bit fields for WTIMER IEN */
AnnaBridge 187:0387e8f68319 1064 #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1065 #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1066 #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1067 #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 187:0387e8f68319 1068 #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 187:0387e8f68319 1069 #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1070 #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1071 #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
AnnaBridge 187:0387e8f68319 1072 #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 187:0387e8f68319 1073 #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 187:0387e8f68319 1074 #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1075 #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1076 #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
AnnaBridge 187:0387e8f68319 1077 #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 1078 #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 187:0387e8f68319 1079 #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1080 #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1081 #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1082 #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 1083 #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 187:0387e8f68319 1084 #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1085 #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1086 #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1087 #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 1088 #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 187:0387e8f68319 1089 #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1090 #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1091 #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1092 #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 1093 #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 187:0387e8f68319 1094 #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1095 #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1096 #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1097 #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 1098 #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 187:0387e8f68319 1099 #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1100 #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1101 #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1102 #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 1103 #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 187:0387e8f68319 1104 #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1105 #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1106 #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1107 #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 1108 #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 187:0387e8f68319 1109 #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1110 #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1111 #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1112 #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 1113 #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 187:0387e8f68319 1114 #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1115 #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1116 #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
AnnaBridge 187:0387e8f68319 1117 #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 1118 #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 187:0387e8f68319 1119 #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1120 #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 187:0387e8f68319 1121
AnnaBridge 187:0387e8f68319 1122 /* Bit fields for WTIMER TOP */
AnnaBridge 187:0387e8f68319 1123 #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */
AnnaBridge 187:0387e8f68319 1124 #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */
AnnaBridge 187:0387e8f68319 1125 #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
AnnaBridge 187:0387e8f68319 1126 #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */
AnnaBridge 187:0387e8f68319 1127 #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */
AnnaBridge 187:0387e8f68319 1128 #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */
AnnaBridge 187:0387e8f68319 1129
AnnaBridge 187:0387e8f68319 1130 /* Bit fields for WTIMER TOPB */
AnnaBridge 187:0387e8f68319 1131 #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */
AnnaBridge 187:0387e8f68319 1132 #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */
AnnaBridge 187:0387e8f68319 1133 #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
AnnaBridge 187:0387e8f68319 1134 #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */
AnnaBridge 187:0387e8f68319 1135 #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */
AnnaBridge 187:0387e8f68319 1136 #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */
AnnaBridge 187:0387e8f68319 1137
AnnaBridge 187:0387e8f68319 1138 /* Bit fields for WTIMER CNT */
AnnaBridge 187:0387e8f68319 1139 #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */
AnnaBridge 187:0387e8f68319 1140 #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */
AnnaBridge 187:0387e8f68319 1141 #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
AnnaBridge 187:0387e8f68319 1142 #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */
AnnaBridge 187:0387e8f68319 1143 #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */
AnnaBridge 187:0387e8f68319 1144 #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */
AnnaBridge 187:0387e8f68319 1145
AnnaBridge 187:0387e8f68319 1146 /* Bit fields for WTIMER LOCK */
AnnaBridge 187:0387e8f68319 1147 #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1148 #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1149 #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
AnnaBridge 187:0387e8f68319 1150 #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
AnnaBridge 187:0387e8f68319 1151 #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1152 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1153 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1154 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1155 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1156 #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1157 #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1158 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1159 #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1160 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
AnnaBridge 187:0387e8f68319 1161
AnnaBridge 187:0387e8f68319 1162 /* Bit fields for WTIMER ROUTEPEN */
AnnaBridge 187:0387e8f68319 1163 #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1164 #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1165 #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
AnnaBridge 187:0387e8f68319 1166 #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
AnnaBridge 187:0387e8f68319 1167 #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
AnnaBridge 187:0387e8f68319 1168 #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1169 #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1170 #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
AnnaBridge 187:0387e8f68319 1171 #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
AnnaBridge 187:0387e8f68319 1172 #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
AnnaBridge 187:0387e8f68319 1173 #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1174 #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1175 #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
AnnaBridge 187:0387e8f68319 1176 #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
AnnaBridge 187:0387e8f68319 1177 #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
AnnaBridge 187:0387e8f68319 1178 #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1179 #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1180 #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
AnnaBridge 187:0387e8f68319 1181 #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
AnnaBridge 187:0387e8f68319 1182 #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
AnnaBridge 187:0387e8f68319 1183 #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1184 #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1185 #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
AnnaBridge 187:0387e8f68319 1186 #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
AnnaBridge 187:0387e8f68319 1187 #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
AnnaBridge 187:0387e8f68319 1188 #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1189 #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1190 #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
AnnaBridge 187:0387e8f68319 1191 #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
AnnaBridge 187:0387e8f68319 1192 #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
AnnaBridge 187:0387e8f68319 1193 #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1194 #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1195 #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
AnnaBridge 187:0387e8f68319 1196 #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
AnnaBridge 187:0387e8f68319 1197 #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
AnnaBridge 187:0387e8f68319 1198 #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1199 #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 187:0387e8f68319 1200
AnnaBridge 187:0387e8f68319 1201 /* Bit fields for WTIMER ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1202 #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1203 #define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1204 #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
AnnaBridge 187:0387e8f68319 1205 #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */
AnnaBridge 187:0387e8f68319 1206 #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1207 #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1208 #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1209 #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1210 #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1211 #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1212 #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1213 #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1214 #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1215 #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1216 #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1217 #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1218 #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1219 #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1220 #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1221 #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1222 #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1223 #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1224 #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
AnnaBridge 187:0387e8f68319 1225 #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */
AnnaBridge 187:0387e8f68319 1226 #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1227 #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1228 #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1229 #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1230 #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1231 #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1232 #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1233 #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1234 #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1235 #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1236 #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1237 #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1238 #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1239 #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1240 #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1241 #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1242 #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1243 #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1244 #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
AnnaBridge 187:0387e8f68319 1245 #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */
AnnaBridge 187:0387e8f68319 1246 #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1247 #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1248 #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1249 #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1250 #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1251 #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1252 #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1253 #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1254 #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1255 #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1256 #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1257 #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1258 #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1259 #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1260 #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1261 #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1262 #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1263 #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1264 #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
AnnaBridge 187:0387e8f68319 1265 #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */
AnnaBridge 187:0387e8f68319 1266 #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1267 #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1268 #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1269 #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1270 #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1271 #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1272 #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1273 #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1274 #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1275 #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1276 #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1277 #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1278 #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1279 #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1280 #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1281 #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1282 #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1283 #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 187:0387e8f68319 1284
AnnaBridge 187:0387e8f68319 1285 /* Bit fields for WTIMER ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1286 #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1287 #define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1288 #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
AnnaBridge 187:0387e8f68319 1289 #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */
AnnaBridge 187:0387e8f68319 1290 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1291 #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1292 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1293 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1294 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1295 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1296 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1297 #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1298 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1299 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1300 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1301 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1302 #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
AnnaBridge 187:0387e8f68319 1303 #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */
AnnaBridge 187:0387e8f68319 1304 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1305 #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1306 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1307 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1308 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1309 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1310 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1311 #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1312 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1313 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1314 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1315 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1316 #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
AnnaBridge 187:0387e8f68319 1317 #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */
AnnaBridge 187:0387e8f68319 1318 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1319 #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1320 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1321 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1322 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1323 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1324 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1325 #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1326 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1327 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1328 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1329 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 187:0387e8f68319 1330
AnnaBridge 187:0387e8f68319 1331 /* Bit fields for WTIMER CC_CTRL */
AnnaBridge 187:0387e8f68319 1332 #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1333 #define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1334 #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
AnnaBridge 187:0387e8f68319 1335 #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
AnnaBridge 187:0387e8f68319 1336 #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1337 #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1338 #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1339 #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1340 #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1341 #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1342 #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1343 #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1344 #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1345 #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1346 #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
AnnaBridge 187:0387e8f68319 1347 #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
AnnaBridge 187:0387e8f68319 1348 #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
AnnaBridge 187:0387e8f68319 1349 #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1350 #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1351 #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
AnnaBridge 187:0387e8f68319 1352 #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
AnnaBridge 187:0387e8f68319 1353 #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
AnnaBridge 187:0387e8f68319 1354 #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1355 #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1356 #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
AnnaBridge 187:0387e8f68319 1357 #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
AnnaBridge 187:0387e8f68319 1358 #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1359 #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1360 #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1361 #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1362 #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1363 #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1364 #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1365 #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1366 #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1367 #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1368 #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
AnnaBridge 187:0387e8f68319 1369 #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
AnnaBridge 187:0387e8f68319 1370 #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1371 #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1372 #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1373 #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1374 #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1375 #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1376 #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1377 #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1378 #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1379 #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1380 #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
AnnaBridge 187:0387e8f68319 1381 #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
AnnaBridge 187:0387e8f68319 1382 #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1383 #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1384 #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1385 #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1386 #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1387 #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1388 #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1389 #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1390 #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1391 #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1392 #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
AnnaBridge 187:0387e8f68319 1393 #define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */
AnnaBridge 187:0387e8f68319 1394 #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1395 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1396 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1397 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1398 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1399 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1400 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1401 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1402 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1403 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1404 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1405 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1406 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1407 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1408 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1409 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1410 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1411 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1412 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1413 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1414 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1415 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1416 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1417 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1418 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1419 #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1420 #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1421 #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1422 #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1423 #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1424 #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1425 #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1426 #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1427 #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1428 #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1429 #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1430 #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1431 #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1432 #define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1433 #define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1434 #define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1435 #define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1436 #define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1437 #define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1438 #define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1439 #define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1440 #define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1441 #define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1442 #define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1443 #define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1444 #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
AnnaBridge 187:0387e8f68319 1445 #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
AnnaBridge 187:0387e8f68319 1446 #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1447 #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1448 #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1449 #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1450 #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1451 #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1452 #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1453 #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1454 #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1455 #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1456 #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
AnnaBridge 187:0387e8f68319 1457 #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
AnnaBridge 187:0387e8f68319 1458 #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1459 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1460 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1461 #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1462 #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1463 #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1464 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1465 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1466 #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1467 #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1468 #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
AnnaBridge 187:0387e8f68319 1469 #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
AnnaBridge 187:0387e8f68319 1470 #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
AnnaBridge 187:0387e8f68319 1471 #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1472 #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1473 #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1474 #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1475 #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1476 #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1477 #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
AnnaBridge 187:0387e8f68319 1478 #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
AnnaBridge 187:0387e8f68319 1479 #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
AnnaBridge 187:0387e8f68319 1480 #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1481 #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1482 #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1483 #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1484 #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1485 #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1486 #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
AnnaBridge 187:0387e8f68319 1487 #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
AnnaBridge 187:0387e8f68319 1488 #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
AnnaBridge 187:0387e8f68319 1489 #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1490 #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1491 #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1492 #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1493 #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1494 #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */
AnnaBridge 187:0387e8f68319 1495
AnnaBridge 187:0387e8f68319 1496 /* Bit fields for WTIMER CC_CCV */
AnnaBridge 187:0387e8f68319 1497 #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */
AnnaBridge 187:0387e8f68319 1498 #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */
AnnaBridge 187:0387e8f68319 1499 #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
AnnaBridge 187:0387e8f68319 1500 #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */
AnnaBridge 187:0387e8f68319 1501 #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */
AnnaBridge 187:0387e8f68319 1502 #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */
AnnaBridge 187:0387e8f68319 1503
AnnaBridge 187:0387e8f68319 1504 /* Bit fields for WTIMER CC_CCVP */
AnnaBridge 187:0387e8f68319 1505 #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */
AnnaBridge 187:0387e8f68319 1506 #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */
AnnaBridge 187:0387e8f68319 1507 #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
AnnaBridge 187:0387e8f68319 1508 #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */
AnnaBridge 187:0387e8f68319 1509 #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */
AnnaBridge 187:0387e8f68319 1510 #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */
AnnaBridge 187:0387e8f68319 1511
AnnaBridge 187:0387e8f68319 1512 /* Bit fields for WTIMER CC_CCVB */
AnnaBridge 187:0387e8f68319 1513 #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */
AnnaBridge 187:0387e8f68319 1514 #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */
AnnaBridge 187:0387e8f68319 1515 #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
AnnaBridge 187:0387e8f68319 1516 #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */
AnnaBridge 187:0387e8f68319 1517 #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */
AnnaBridge 187:0387e8f68319 1518 #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */
AnnaBridge 187:0387e8f68319 1519
AnnaBridge 187:0387e8f68319 1520 /* Bit fields for WTIMER DTCTRL */
AnnaBridge 187:0387e8f68319 1521 #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1522 #define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1523 #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
AnnaBridge 187:0387e8f68319 1524 #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
AnnaBridge 187:0387e8f68319 1525 #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
AnnaBridge 187:0387e8f68319 1526 #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1527 #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1528 #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
AnnaBridge 187:0387e8f68319 1529 #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
AnnaBridge 187:0387e8f68319 1530 #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
AnnaBridge 187:0387e8f68319 1531 #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1532 #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1533 #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1534 #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1535 #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1536 #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1537 #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
AnnaBridge 187:0387e8f68319 1538 #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
AnnaBridge 187:0387e8f68319 1539 #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
AnnaBridge 187:0387e8f68319 1540 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1541 #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1542 #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
AnnaBridge 187:0387e8f68319 1543 #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
AnnaBridge 187:0387e8f68319 1544 #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
AnnaBridge 187:0387e8f68319 1545 #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1546 #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1547 #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
AnnaBridge 187:0387e8f68319 1548 #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */
AnnaBridge 187:0387e8f68319 1549 #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1550 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1551 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1552 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1553 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1554 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1555 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1556 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1557 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1558 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1559 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1560 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1561 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1562 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1563 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1564 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1565 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1566 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1567 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1568 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1569 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1570 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1571 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1572 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1573 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1574 #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1575 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1576 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1577 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1578 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1579 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1580 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1581 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1582 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1583 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1584 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1585 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1586 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1587 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1588 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1589 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1590 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1591 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1592 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1593 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1594 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1595 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1596 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1597 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1598 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1599 #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
AnnaBridge 187:0387e8f68319 1600 #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
AnnaBridge 187:0387e8f68319 1601 #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
AnnaBridge 187:0387e8f68319 1602 #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1603 #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1604 #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
AnnaBridge 187:0387e8f68319 1605 #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
AnnaBridge 187:0387e8f68319 1606 #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
AnnaBridge 187:0387e8f68319 1607 #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1608 #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1609 #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
AnnaBridge 187:0387e8f68319 1610 #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
AnnaBridge 187:0387e8f68319 1611 #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
AnnaBridge 187:0387e8f68319 1612 #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1613 #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 187:0387e8f68319 1614
AnnaBridge 187:0387e8f68319 1615 /* Bit fields for WTIMER DTTIME */
AnnaBridge 187:0387e8f68319 1616 #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1617 #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1618 #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
AnnaBridge 187:0387e8f68319 1619 #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
AnnaBridge 187:0387e8f68319 1620 #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1621 #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1622 #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1623 #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1624 #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1625 #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1626 #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1627 #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1628 #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1629 #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1630 #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1631 #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1632 #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1633 #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1634 #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1635 #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1636 #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1637 #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1638 #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1639 #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1640 #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1641 #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1642 #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1643 #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1644 #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
AnnaBridge 187:0387e8f68319 1645 #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
AnnaBridge 187:0387e8f68319 1646 #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1647 #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1648 #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
AnnaBridge 187:0387e8f68319 1649 #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
AnnaBridge 187:0387e8f68319 1650 #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1651 #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 187:0387e8f68319 1652
AnnaBridge 187:0387e8f68319 1653 /* Bit fields for WTIMER DTFC */
AnnaBridge 187:0387e8f68319 1654 #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1655 #define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1656 #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
AnnaBridge 187:0387e8f68319 1657 #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */
AnnaBridge 187:0387e8f68319 1658 #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1659 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1660 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1661 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1662 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1663 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1664 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1665 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1666 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1667 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1668 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1669 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1670 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1671 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1672 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1673 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1674 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1675 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1676 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1677 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1678 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1679 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1680 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1681 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1682 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1683 #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1684 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1685 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1686 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1687 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1688 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1689 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1690 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1691 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1692 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1693 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1694 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1695 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1696 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1697 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1698 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1699 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1700 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1701 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1702 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1703 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1704 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1705 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1706 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1707 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1708 #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
AnnaBridge 187:0387e8f68319 1709 #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */
AnnaBridge 187:0387e8f68319 1710 #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1711 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1712 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1713 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1714 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1715 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1716 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1717 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1718 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1719 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1720 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1721 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1722 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1723 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1724 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1725 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1726 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1727 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1728 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1729 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1730 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1731 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1732 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1733 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1734 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1735 #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1736 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1737 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1738 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1739 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1740 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1741 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1742 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1743 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1744 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1745 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1746 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1747 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1748 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1749 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1750 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1751 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1752 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1753 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1754 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1755 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1756 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1757 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1758 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1759 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1760 #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
AnnaBridge 187:0387e8f68319 1761 #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
AnnaBridge 187:0387e8f68319 1762 #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1763 #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1764 #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1765 #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1766 #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1767 #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1768 #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1769 #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1770 #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1771 #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1772 #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
AnnaBridge 187:0387e8f68319 1773 #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
AnnaBridge 187:0387e8f68319 1774 #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
AnnaBridge 187:0387e8f68319 1775 #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1776 #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1777 #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
AnnaBridge 187:0387e8f68319 1778 #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
AnnaBridge 187:0387e8f68319 1779 #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
AnnaBridge 187:0387e8f68319 1780 #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1781 #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1782 #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
AnnaBridge 187:0387e8f68319 1783 #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
AnnaBridge 187:0387e8f68319 1784 #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
AnnaBridge 187:0387e8f68319 1785 #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1786 #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1787 #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
AnnaBridge 187:0387e8f68319 1788 #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
AnnaBridge 187:0387e8f68319 1789 #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
AnnaBridge 187:0387e8f68319 1790 #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1791 #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 187:0387e8f68319 1792
AnnaBridge 187:0387e8f68319 1793 /* Bit fields for WTIMER DTOGEN */
AnnaBridge 187:0387e8f68319 1794 #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1795 #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1796 #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
AnnaBridge 187:0387e8f68319 1797 #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
AnnaBridge 187:0387e8f68319 1798 #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
AnnaBridge 187:0387e8f68319 1799 #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1800 #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1801 #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
AnnaBridge 187:0387e8f68319 1802 #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
AnnaBridge 187:0387e8f68319 1803 #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
AnnaBridge 187:0387e8f68319 1804 #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1805 #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1806 #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
AnnaBridge 187:0387e8f68319 1807 #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
AnnaBridge 187:0387e8f68319 1808 #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
AnnaBridge 187:0387e8f68319 1809 #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1810 #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1811 #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
AnnaBridge 187:0387e8f68319 1812 #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
AnnaBridge 187:0387e8f68319 1813 #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
AnnaBridge 187:0387e8f68319 1814 #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1815 #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1816 #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
AnnaBridge 187:0387e8f68319 1817 #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
AnnaBridge 187:0387e8f68319 1818 #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
AnnaBridge 187:0387e8f68319 1819 #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1820 #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1821 #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
AnnaBridge 187:0387e8f68319 1822 #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
AnnaBridge 187:0387e8f68319 1823 #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
AnnaBridge 187:0387e8f68319 1824 #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1825 #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 187:0387e8f68319 1826
AnnaBridge 187:0387e8f68319 1827 /* Bit fields for WTIMER DTFAULT */
AnnaBridge 187:0387e8f68319 1828 #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1829 #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1830 #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
AnnaBridge 187:0387e8f68319 1831 #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
AnnaBridge 187:0387e8f68319 1832 #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
AnnaBridge 187:0387e8f68319 1833 #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1834 #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1835 #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
AnnaBridge 187:0387e8f68319 1836 #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
AnnaBridge 187:0387e8f68319 1837 #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
AnnaBridge 187:0387e8f68319 1838 #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1839 #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1840 #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
AnnaBridge 187:0387e8f68319 1841 #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
AnnaBridge 187:0387e8f68319 1842 #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
AnnaBridge 187:0387e8f68319 1843 #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1844 #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1845 #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
AnnaBridge 187:0387e8f68319 1846 #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
AnnaBridge 187:0387e8f68319 1847 #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
AnnaBridge 187:0387e8f68319 1848 #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1849 #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 187:0387e8f68319 1850
AnnaBridge 187:0387e8f68319 1851 /* Bit fields for WTIMER DTFAULTC */
AnnaBridge 187:0387e8f68319 1852 #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1853 #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1854 #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
AnnaBridge 187:0387e8f68319 1855 #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
AnnaBridge 187:0387e8f68319 1856 #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
AnnaBridge 187:0387e8f68319 1857 #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1858 #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1859 #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
AnnaBridge 187:0387e8f68319 1860 #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
AnnaBridge 187:0387e8f68319 1861 #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
AnnaBridge 187:0387e8f68319 1862 #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1863 #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1864 #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
AnnaBridge 187:0387e8f68319 1865 #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
AnnaBridge 187:0387e8f68319 1866 #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
AnnaBridge 187:0387e8f68319 1867 #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1868 #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1869 #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
AnnaBridge 187:0387e8f68319 1870 #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
AnnaBridge 187:0387e8f68319 1871 #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
AnnaBridge 187:0387e8f68319 1872 #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1873 #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 187:0387e8f68319 1874
AnnaBridge 187:0387e8f68319 1875 /* Bit fields for WTIMER DTLOCK */
AnnaBridge 187:0387e8f68319 1876 #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1877 #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1878 #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
AnnaBridge 187:0387e8f68319 1879 #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
AnnaBridge 187:0387e8f68319 1880 #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1881 #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1882 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1883 #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1884 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1885 #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1886 #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1887 #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1888 #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1889 #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
AnnaBridge 187:0387e8f68319 1890
AnnaBridge 187:0387e8f68319 1891 /** @} */
AnnaBridge 187:0387e8f68319 1892 /** @} End of group EFM32GG11B820F2048IQ100_WTIMER */
AnnaBridge 187:0387e8f68319 1893
AnnaBridge 187:0387e8f68319 1894 #include "efm32gg11b_uart.h"
AnnaBridge 187:0387e8f68319 1895
AnnaBridge 187:0387e8f68319 1896 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 1897 * @defgroup EFM32GG11B820F2048IQ100_UNLOCK Unlock Codes
AnnaBridge 187:0387e8f68319 1898 * @{
AnnaBridge 187:0387e8f68319 1899 *****************************************************************************/
AnnaBridge 187:0387e8f68319 1900 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
AnnaBridge 187:0387e8f68319 1901 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
AnnaBridge 187:0387e8f68319 1902 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
AnnaBridge 187:0387e8f68319 1903 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
AnnaBridge 187:0387e8f68319 1904 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
AnnaBridge 187:0387e8f68319 1905 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
AnnaBridge 187:0387e8f68319 1906 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
AnnaBridge 187:0387e8f68319 1907
AnnaBridge 187:0387e8f68319 1908 /** @} End of group EFM32GG11B820F2048IQ100_UNLOCK */
AnnaBridge 187:0387e8f68319 1909
AnnaBridge 187:0387e8f68319 1910 /** @} End of group EFM32GG11B820F2048IQ100_BitFields */
AnnaBridge 187:0387e8f68319 1911
AnnaBridge 187:0387e8f68319 1912 #include "efm32gg11b_af_ports.h"
AnnaBridge 187:0387e8f68319 1913 #include "efm32gg11b_af_pins.h"
AnnaBridge 187:0387e8f68319 1914
AnnaBridge 187:0387e8f68319 1915 /** @} End of group EFM32GG11B820F2048IQ100 */
AnnaBridge 187:0387e8f68319 1916
AnnaBridge 187:0387e8f68319 1917 /** @} End of group Parts */
AnnaBridge 187:0387e8f68319 1918
AnnaBridge 187:0387e8f68319 1919 #ifdef __cplusplus
AnnaBridge 187:0387e8f68319 1920 }
AnnaBridge 187:0387e8f68319 1921 #endif
AnnaBridge 187:0387e8f68319 1922 #endif /* EFM32GG11B820F2048IQ100_H */