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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
181:57724642e740 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_exti.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of EXTI LL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 167:e84263d55307 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32L4xx_LL_EXTI_H
<> 144:ef7eb2e8f9f7 38 #define __STM32L4xx_LL_EXTI_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32l4xx.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #if defined (EXTI)
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup EXTI_LL EXTI
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private Macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 62 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @}
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 #endif /*USE_FULL_LL_DRIVER*/
<> 144:ef7eb2e8f9f7 69 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 70 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 71 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
<> 144:ef7eb2e8f9f7 72 * @{
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 typedef struct
<> 144:ef7eb2e8f9f7 75 {
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 78 This parameter can be any combination of @ref EXTI_LL_EC_LINE */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 81 This parameter can be any combination of @ref EXTI_LL_EC_LINE */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
<> 144:ef7eb2e8f9f7 84 This parameter can be set either to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
<> 144:ef7eb2e8f9f7 87 This parameter can be a value of @ref EXTI_LL_EC_MODE. */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
<> 144:ef7eb2e8f9f7 91 } LL_EXTI_InitTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @}
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 #endif /*USE_FULL_LL_DRIVER*/
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
<> 144:ef7eb2e8f9f7 100 * @{
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @defgroup EXTI_LL_EC_LINE LINE
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 #define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
<> 144:ef7eb2e8f9f7 107 #define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
<> 144:ef7eb2e8f9f7 108 #define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
<> 144:ef7eb2e8f9f7 109 #define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
<> 144:ef7eb2e8f9f7 110 #define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
<> 144:ef7eb2e8f9f7 111 #define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
<> 144:ef7eb2e8f9f7 112 #define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
<> 144:ef7eb2e8f9f7 113 #define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
<> 144:ef7eb2e8f9f7 114 #define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
<> 144:ef7eb2e8f9f7 115 #define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
<> 144:ef7eb2e8f9f7 116 #define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
<> 144:ef7eb2e8f9f7 117 #define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
<> 144:ef7eb2e8f9f7 118 #define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
<> 144:ef7eb2e8f9f7 119 #define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
<> 144:ef7eb2e8f9f7 120 #define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
<> 144:ef7eb2e8f9f7 121 #define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
<> 144:ef7eb2e8f9f7 122 #if defined(EXTI_IMR1_IM16)
<> 144:ef7eb2e8f9f7 123 #define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
<> 144:ef7eb2e8f9f7 124 #endif
<> 144:ef7eb2e8f9f7 125 #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
AnnaBridge 167:e84263d55307 126 #if defined(EXTI_IMR1_IM18)
<> 144:ef7eb2e8f9f7 127 #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
AnnaBridge 167:e84263d55307 128 #endif
<> 144:ef7eb2e8f9f7 129 #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
<> 144:ef7eb2e8f9f7 130 #if defined(EXTI_IMR1_IM20)
<> 144:ef7eb2e8f9f7 131 #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
<> 144:ef7eb2e8f9f7 132 #endif
<> 144:ef7eb2e8f9f7 133 #if defined(EXTI_IMR1_IM21)
<> 144:ef7eb2e8f9f7 134 #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
<> 144:ef7eb2e8f9f7 135 #endif
<> 144:ef7eb2e8f9f7 136 #if defined(EXTI_IMR1_IM22)
<> 144:ef7eb2e8f9f7 137 #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
<> 144:ef7eb2e8f9f7 138 #endif
<> 144:ef7eb2e8f9f7 139 #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
<> 144:ef7eb2e8f9f7 140 #if defined(EXTI_IMR1_IM24)
<> 144:ef7eb2e8f9f7 141 #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
<> 144:ef7eb2e8f9f7 142 #endif
<> 144:ef7eb2e8f9f7 143 #if defined(EXTI_IMR1_IM25)
<> 144:ef7eb2e8f9f7 144 #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146 #if defined(EXTI_IMR1_IM26)
<> 144:ef7eb2e8f9f7 147 #define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */
<> 144:ef7eb2e8f9f7 148 #endif
<> 144:ef7eb2e8f9f7 149 #if defined(EXTI_IMR1_IM27)
<> 144:ef7eb2e8f9f7 150 #define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */
<> 144:ef7eb2e8f9f7 151 #endif
<> 144:ef7eb2e8f9f7 152 #if defined(EXTI_IMR1_IM28)
<> 144:ef7eb2e8f9f7 153 #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
<> 144:ef7eb2e8f9f7 154 #endif
<> 144:ef7eb2e8f9f7 155 #if defined(EXTI_IMR1_IM29)
<> 144:ef7eb2e8f9f7 156 #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
<> 144:ef7eb2e8f9f7 157 #endif
<> 144:ef7eb2e8f9f7 158 #if defined(EXTI_IMR1_IM30)
<> 144:ef7eb2e8f9f7 159 #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
<> 144:ef7eb2e8f9f7 160 #endif
<> 144:ef7eb2e8f9f7 161 #if defined(EXTI_IMR1_IM31)
<> 144:ef7eb2e8f9f7 162 #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
<> 144:ef7eb2e8f9f7 163 #endif
<> 144:ef7eb2e8f9f7 164 #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
AnnaBridge 167:e84263d55307 167 #if defined(EXTI_IMR2_IM33)
<> 144:ef7eb2e8f9f7 168 #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
AnnaBridge 167:e84263d55307 169 #endif
AnnaBridge 167:e84263d55307 170 #if defined(EXTI_IMR2_IM34)
<> 144:ef7eb2e8f9f7 171 #define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
AnnaBridge 167:e84263d55307 172 #endif
AnnaBridge 167:e84263d55307 173 #if defined(EXTI_IMR2_IM35)
<> 144:ef7eb2e8f9f7 174 #define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
AnnaBridge 167:e84263d55307 175 #endif
AnnaBridge 167:e84263d55307 176 #if defined(EXTI_IMR2_IM36)
<> 144:ef7eb2e8f9f7 177 #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
AnnaBridge 167:e84263d55307 178 #endif
AnnaBridge 167:e84263d55307 179 #if defined(EXTI_IMR2_IM37)
<> 144:ef7eb2e8f9f7 180 #define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
AnnaBridge 167:e84263d55307 181 #endif
AnnaBridge 167:e84263d55307 182 #if defined(EXTI_IMR2_IM38)
<> 144:ef7eb2e8f9f7 183 #define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
AnnaBridge 167:e84263d55307 184 #endif
AnnaBridge 167:e84263d55307 185 #if defined(EXTI_IMR2_IM39)
<> 144:ef7eb2e8f9f7 186 #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
AnnaBridge 167:e84263d55307 187 #endif
AnnaBridge 181:57724642e740 188 #if defined(EXTI_IMR2_IM40)
AnnaBridge 181:57724642e740 189 #define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
AnnaBridge 181:57724642e740 190 #endif
<> 144:ef7eb2e8f9f7 191 #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/
<> 144:ef7eb2e8f9f7 192
AnnaBridge 167:e84263d55307 193
AnnaBridge 167:e84263d55307 194 #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 167:e84263d55307 197 #define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
<> 144:ef7eb2e8f9f7 198 #endif /*USE_FULL_LL_DRIVER*/
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @}
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup EXTI_LL_EC_MODE Mode
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 #define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
<> 144:ef7eb2e8f9f7 209 #define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
<> 144:ef7eb2e8f9f7 210 #define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @}
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
<> 144:ef7eb2e8f9f7 216 * @{
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 #define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
<> 144:ef7eb2e8f9f7 219 #define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
<> 144:ef7eb2e8f9f7 220 #define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
<> 144:ef7eb2e8f9f7 221 #define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #endif /*USE_FULL_LL_DRIVER*/
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @}
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 236 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
<> 144:ef7eb2e8f9f7 237 * @{
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief Write a value in EXTI register
<> 144:ef7eb2e8f9f7 246 * @param __REG__ Register to be written
<> 144:ef7eb2e8f9f7 247 * @param __VALUE__ Value to be written in the register
<> 144:ef7eb2e8f9f7 248 * @retval None
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @brief Read a value in EXTI register
<> 144:ef7eb2e8f9f7 254 * @param __REG__ Register to be read
<> 144:ef7eb2e8f9f7 255 * @retval Register value
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @}
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 270 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 279 * @note The reset value for the direct or internal lines (see RM)
<> 144:ef7eb2e8f9f7 280 * is set to 1 in order to enable the interrupt by default.
<> 144:ef7eb2e8f9f7 281 * Bits are set automatically at Power on.
<> 144:ef7eb2e8f9f7 282 * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
<> 144:ef7eb2e8f9f7 283 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 284 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 285 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 286 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 287 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 288 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 289 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 290 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 291 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 292 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 293 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 294 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 295 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 296 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 297 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 298 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 299 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 300 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 301 * @arg @ref LL_EXTI_LINE_17
<> 144:ef7eb2e8f9f7 302 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 303 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 304 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 305 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 306 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 307 * @arg @ref LL_EXTI_LINE_23
<> 144:ef7eb2e8f9f7 308 * @arg @ref LL_EXTI_LINE_24
<> 144:ef7eb2e8f9f7 309 * @arg @ref LL_EXTI_LINE_25
<> 144:ef7eb2e8f9f7 310 * @arg @ref LL_EXTI_LINE_26
<> 144:ef7eb2e8f9f7 311 * @arg @ref LL_EXTI_LINE_27
<> 144:ef7eb2e8f9f7 312 * @arg @ref LL_EXTI_LINE_28
<> 144:ef7eb2e8f9f7 313 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 314 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 315 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 316 * @arg @ref LL_EXTI_LINE_ALL_0_31
<> 144:ef7eb2e8f9f7 317 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 318 * @retval None
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 SET_BIT(EXTI->IMR1, ExtiLine);
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 326 * @note The reset value for the direct lines (lines from 32 to 34, line
<> 144:ef7eb2e8f9f7 327 * 39) is set to 1 in order to enable the interrupt by default.
<> 144:ef7eb2e8f9f7 328 * Bits are set automatically at Power on.
<> 144:ef7eb2e8f9f7 329 * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
<> 144:ef7eb2e8f9f7 330 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 331 * @arg @ref LL_EXTI_LINE_32
<> 144:ef7eb2e8f9f7 332 * @arg @ref LL_EXTI_LINE_33
AnnaBridge 181:57724642e740 333 * @arg @ref LL_EXTI_LINE_34(*)
<> 144:ef7eb2e8f9f7 334 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 335 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 336 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 337 * @arg @ref LL_EXTI_LINE_38
AnnaBridge 181:57724642e740 338 * @arg @ref LL_EXTI_LINE_39(*)
AnnaBridge 181:57724642e740 339 * @arg @ref LL_EXTI_LINE_40(*)
<> 144:ef7eb2e8f9f7 340 * @arg @ref LL_EXTI_LINE_ALL_32_63
AnnaBridge 181:57724642e740 341 * @note (*): Available in some devices
<> 144:ef7eb2e8f9f7 342 * @retval None
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 SET_BIT(EXTI->IMR2, ExtiLine);
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 351 * @note The reset value for the direct or internal lines (see RM)
<> 144:ef7eb2e8f9f7 352 * is set to 1 in order to enable the interrupt by default.
<> 144:ef7eb2e8f9f7 353 * Bits are set automatically at Power on.
<> 144:ef7eb2e8f9f7 354 * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
<> 144:ef7eb2e8f9f7 355 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 356 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 357 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 358 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 359 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 360 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 361 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 362 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 363 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 364 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 365 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 366 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 367 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 368 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 369 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 370 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 371 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 372 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 373 * @arg @ref LL_EXTI_LINE_17
<> 144:ef7eb2e8f9f7 374 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 375 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 376 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 377 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 378 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 379 * @arg @ref LL_EXTI_LINE_23
<> 144:ef7eb2e8f9f7 380 * @arg @ref LL_EXTI_LINE_24
<> 144:ef7eb2e8f9f7 381 * @arg @ref LL_EXTI_LINE_25
<> 144:ef7eb2e8f9f7 382 * @arg @ref LL_EXTI_LINE_26
<> 144:ef7eb2e8f9f7 383 * @arg @ref LL_EXTI_LINE_27
<> 144:ef7eb2e8f9f7 384 * @arg @ref LL_EXTI_LINE_28
<> 144:ef7eb2e8f9f7 385 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 386 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 387 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 388 * @arg @ref LL_EXTI_LINE_ALL_0_31
<> 144:ef7eb2e8f9f7 389 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 390 * @retval None
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 CLEAR_BIT(EXTI->IMR1, ExtiLine);
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /**
<> 144:ef7eb2e8f9f7 398 * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 399 * @note The reset value for the direct lines (lines from 32 to 34, line
<> 144:ef7eb2e8f9f7 400 * 39) is set to 1 in order to enable the interrupt by default.
<> 144:ef7eb2e8f9f7 401 * Bits are set automatically at Power on.
<> 144:ef7eb2e8f9f7 402 * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
<> 144:ef7eb2e8f9f7 403 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 404 * @arg @ref LL_EXTI_LINE_32
<> 144:ef7eb2e8f9f7 405 * @arg @ref LL_EXTI_LINE_33
AnnaBridge 181:57724642e740 406 * @arg @ref LL_EXTI_LINE_34(*)
<> 144:ef7eb2e8f9f7 407 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 408 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 409 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 410 * @arg @ref LL_EXTI_LINE_38
AnnaBridge 181:57724642e740 411 * @arg @ref LL_EXTI_LINE_39(*)
AnnaBridge 181:57724642e740 412 * @arg @ref LL_EXTI_LINE_40(*)
<> 144:ef7eb2e8f9f7 413 * @arg @ref LL_EXTI_LINE_ALL_32_63
AnnaBridge 181:57724642e740 414 * @note (*): Available in some devices
<> 144:ef7eb2e8f9f7 415 * @retval None
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 CLEAR_BIT(EXTI->IMR2, ExtiLine);
<> 144:ef7eb2e8f9f7 420 }
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 424 * @note The reset value for the direct or internal lines (see RM)
<> 144:ef7eb2e8f9f7 425 * is set to 1 in order to enable the interrupt by default.
<> 144:ef7eb2e8f9f7 426 * Bits are set automatically at Power on.
<> 144:ef7eb2e8f9f7 427 * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
<> 144:ef7eb2e8f9f7 428 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 429 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 430 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 431 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 432 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 433 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 434 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 435 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 436 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 437 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 438 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 439 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 440 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 441 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 442 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 443 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 444 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 445 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 446 * @arg @ref LL_EXTI_LINE_17
<> 144:ef7eb2e8f9f7 447 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 448 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 449 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 450 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 451 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 452 * @arg @ref LL_EXTI_LINE_23
<> 144:ef7eb2e8f9f7 453 * @arg @ref LL_EXTI_LINE_24
<> 144:ef7eb2e8f9f7 454 * @arg @ref LL_EXTI_LINE_25
<> 144:ef7eb2e8f9f7 455 * @arg @ref LL_EXTI_LINE_26
<> 144:ef7eb2e8f9f7 456 * @arg @ref LL_EXTI_LINE_27
<> 144:ef7eb2e8f9f7 457 * @arg @ref LL_EXTI_LINE_28
<> 144:ef7eb2e8f9f7 458 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 459 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 460 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 461 * @arg @ref LL_EXTI_LINE_ALL_0_31
<> 144:ef7eb2e8f9f7 462 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 463 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 return (READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 472 * @note The reset value for the direct lines (lines from 32 to 34, line
<> 144:ef7eb2e8f9f7 473 * 39) is set to 1 in order to enable the interrupt by default.
<> 144:ef7eb2e8f9f7 474 * Bits are set automatically at Power on.
<> 144:ef7eb2e8f9f7 475 * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
<> 144:ef7eb2e8f9f7 476 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 477 * @arg @ref LL_EXTI_LINE_32
<> 144:ef7eb2e8f9f7 478 * @arg @ref LL_EXTI_LINE_33
AnnaBridge 181:57724642e740 479 * @arg @ref LL_EXTI_LINE_34(*)
<> 144:ef7eb2e8f9f7 480 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 481 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 482 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 483 * @arg @ref LL_EXTI_LINE_38
AnnaBridge 181:57724642e740 484 * @arg @ref LL_EXTI_LINE_39(*)
AnnaBridge 181:57724642e740 485 * @arg @ref LL_EXTI_LINE_40(*)
<> 144:ef7eb2e8f9f7 486 * @arg @ref LL_EXTI_LINE_ALL_32_63
AnnaBridge 181:57724642e740 487 * @note (*): Available in some devices
<> 144:ef7eb2e8f9f7 488 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @}
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
<> 144:ef7eb2e8f9f7 500 * @{
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief Enable ExtiLine Event request for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 505 * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
<> 144:ef7eb2e8f9f7 506 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 507 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 508 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 509 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 510 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 511 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 512 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 513 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 514 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 515 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 516 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 517 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 518 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 519 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 520 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 521 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 522 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 523 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 524 * @arg @ref LL_EXTI_LINE_17
<> 144:ef7eb2e8f9f7 525 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 526 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 527 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 528 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 529 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 530 * @arg @ref LL_EXTI_LINE_23
<> 144:ef7eb2e8f9f7 531 * @arg @ref LL_EXTI_LINE_24
<> 144:ef7eb2e8f9f7 532 * @arg @ref LL_EXTI_LINE_25
<> 144:ef7eb2e8f9f7 533 * @arg @ref LL_EXTI_LINE_26
<> 144:ef7eb2e8f9f7 534 * @arg @ref LL_EXTI_LINE_27
<> 144:ef7eb2e8f9f7 535 * @arg @ref LL_EXTI_LINE_28
<> 144:ef7eb2e8f9f7 536 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 537 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 538 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 539 * @arg @ref LL_EXTI_LINE_ALL_0_31
<> 144:ef7eb2e8f9f7 540 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 541 * @retval None
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 SET_BIT(EXTI->EMR1, ExtiLine);
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /**
<> 144:ef7eb2e8f9f7 550 * @brief Enable ExtiLine Event request for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 551 * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
<> 144:ef7eb2e8f9f7 552 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 553 * @arg @ref LL_EXTI_LINE_32
<> 144:ef7eb2e8f9f7 554 * @arg @ref LL_EXTI_LINE_33
AnnaBridge 181:57724642e740 555 * @arg @ref LL_EXTI_LINE_34(*)
<> 144:ef7eb2e8f9f7 556 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 557 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 558 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 559 * @arg @ref LL_EXTI_LINE_38
AnnaBridge 181:57724642e740 560 * @arg @ref LL_EXTI_LINE_39(*)
AnnaBridge 181:57724642e740 561 * @arg @ref LL_EXTI_LINE_40(*)
<> 144:ef7eb2e8f9f7 562 * @arg @ref LL_EXTI_LINE_ALL_32_63
AnnaBridge 181:57724642e740 563 * @note (*): Available in some devices
<> 144:ef7eb2e8f9f7 564 * @retval None
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 SET_BIT(EXTI->EMR2, ExtiLine);
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @brief Disable ExtiLine Event request for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 573 * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
<> 144:ef7eb2e8f9f7 574 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 575 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 576 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 577 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 578 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 579 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 580 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 581 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 582 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 583 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 584 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 585 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 586 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 587 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 588 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 589 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 590 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 591 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 592 * @arg @ref LL_EXTI_LINE_17
<> 144:ef7eb2e8f9f7 593 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 594 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 595 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 596 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 597 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 598 * @arg @ref LL_EXTI_LINE_23
<> 144:ef7eb2e8f9f7 599 * @arg @ref LL_EXTI_LINE_24
<> 144:ef7eb2e8f9f7 600 * @arg @ref LL_EXTI_LINE_25
<> 144:ef7eb2e8f9f7 601 * @arg @ref LL_EXTI_LINE_26
<> 144:ef7eb2e8f9f7 602 * @arg @ref LL_EXTI_LINE_27
<> 144:ef7eb2e8f9f7 603 * @arg @ref LL_EXTI_LINE_28
<> 144:ef7eb2e8f9f7 604 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 605 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 606 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 607 * @arg @ref LL_EXTI_LINE_ALL_0_31
<> 144:ef7eb2e8f9f7 608 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 609 * @retval None
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 CLEAR_BIT(EXTI->EMR1, ExtiLine);
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @brief Disable ExtiLine Event request for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 618 * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
<> 144:ef7eb2e8f9f7 619 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 620 * @arg @ref LL_EXTI_LINE_32
<> 144:ef7eb2e8f9f7 621 * @arg @ref LL_EXTI_LINE_33
AnnaBridge 181:57724642e740 622 * @arg @ref LL_EXTI_LINE_34(*)
<> 144:ef7eb2e8f9f7 623 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 624 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 625 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 626 * @arg @ref LL_EXTI_LINE_38
AnnaBridge 181:57724642e740 627 * @arg @ref LL_EXTI_LINE_39(*)
AnnaBridge 181:57724642e740 628 * @arg @ref LL_EXTI_LINE_40(*)
<> 144:ef7eb2e8f9f7 629 * @arg @ref LL_EXTI_LINE_ALL_32_63
AnnaBridge 181:57724642e740 630 * @note (*): Available in some devices
<> 144:ef7eb2e8f9f7 631 * @retval None
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 CLEAR_BIT(EXTI->EMR2, ExtiLine);
<> 144:ef7eb2e8f9f7 636 }
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 640 * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
<> 144:ef7eb2e8f9f7 641 * @param ExtiLine This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 642 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 643 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 644 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 645 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 646 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 647 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 648 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 649 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 650 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 651 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 652 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 653 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 654 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 655 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 656 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 657 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 658 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 659 * @arg @ref LL_EXTI_LINE_17
<> 144:ef7eb2e8f9f7 660 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 661 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 662 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 663 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 664 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 665 * @arg @ref LL_EXTI_LINE_23
<> 144:ef7eb2e8f9f7 666 * @arg @ref LL_EXTI_LINE_24
<> 144:ef7eb2e8f9f7 667 * @arg @ref LL_EXTI_LINE_25
<> 144:ef7eb2e8f9f7 668 * @arg @ref LL_EXTI_LINE_26
<> 144:ef7eb2e8f9f7 669 * @arg @ref LL_EXTI_LINE_27
<> 144:ef7eb2e8f9f7 670 * @arg @ref LL_EXTI_LINE_28
<> 144:ef7eb2e8f9f7 671 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 672 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 673 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 674 * @arg @ref LL_EXTI_LINE_ALL_0_31
<> 144:ef7eb2e8f9f7 675 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 676 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 return (READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /**
<> 144:ef7eb2e8f9f7 685 * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 686 * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
<> 144:ef7eb2e8f9f7 687 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 688 * @arg @ref LL_EXTI_LINE_32
<> 144:ef7eb2e8f9f7 689 * @arg @ref LL_EXTI_LINE_33
AnnaBridge 181:57724642e740 690 * @arg @ref LL_EXTI_LINE_34(*)
<> 144:ef7eb2e8f9f7 691 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 692 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 693 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 694 * @arg @ref LL_EXTI_LINE_38
AnnaBridge 181:57724642e740 695 * @arg @ref LL_EXTI_LINE_39(*)
AnnaBridge 181:57724642e740 696 * @arg @ref LL_EXTI_LINE_40(*)
<> 144:ef7eb2e8f9f7 697 * @arg @ref LL_EXTI_LINE_ALL_32_63
AnnaBridge 181:57724642e740 698 * @note (*): Available in some devices
<> 144:ef7eb2e8f9f7 699 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @}
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
<> 144:ef7eb2e8f9f7 711 * @{
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /**
<> 144:ef7eb2e8f9f7 715 * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 716 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 717 * generated on these lines. If a rising edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 718 * line occurs during a write operation in the EXTI_RTSR register, the
<> 144:ef7eb2e8f9f7 719 * pending bit is not set.
<> 144:ef7eb2e8f9f7 720 * Rising and falling edge triggers can be set for
<> 144:ef7eb2e8f9f7 721 * the same interrupt line. In this case, both generate a trigger
<> 144:ef7eb2e8f9f7 722 * condition.
<> 144:ef7eb2e8f9f7 723 * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
<> 144:ef7eb2e8f9f7 724 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 725 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 726 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 727 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 728 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 729 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 730 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 731 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 732 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 733 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 734 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 735 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 736 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 737 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 738 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 739 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 740 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 741 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 742 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 743 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 744 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 745 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 746 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 747 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 748 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 749 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 750 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 751 * @retval None
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 754 {
<> 144:ef7eb2e8f9f7 755 SET_BIT(EXTI->RTSR1, ExtiLine);
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /**
<> 144:ef7eb2e8f9f7 760 * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 761 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 762 * generated on these lines. If a rising edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 763 * line occurs during a write operation in the EXTI_RTSR register, the
<> 144:ef7eb2e8f9f7 764 * pending bit is not set.Rising and falling edge triggers can be set for
<> 144:ef7eb2e8f9f7 765 * the same interrupt line. In this case, both generate a trigger
<> 144:ef7eb2e8f9f7 766 * condition.
<> 144:ef7eb2e8f9f7 767 * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
<> 144:ef7eb2e8f9f7 768 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 769 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 770 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 771 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 772 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 773 * @retval None
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 SET_BIT(EXTI->RTSR2, ExtiLine);
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /**
<> 144:ef7eb2e8f9f7 781 * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 782 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 783 * generated on these lines. If a rising edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 784 * line occurs during a write operation in the EXTI_RTSR register, the
<> 144:ef7eb2e8f9f7 785 * pending bit is not set.
<> 144:ef7eb2e8f9f7 786 * Rising and falling edge triggers can be set for
<> 144:ef7eb2e8f9f7 787 * the same interrupt line. In this case, both generate a trigger
<> 144:ef7eb2e8f9f7 788 * condition.
<> 144:ef7eb2e8f9f7 789 * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
<> 144:ef7eb2e8f9f7 790 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 791 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 792 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 793 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 794 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 795 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 796 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 797 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 798 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 799 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 800 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 801 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 802 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 803 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 804 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 805 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 806 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 807 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 808 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 809 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 810 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 811 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 812 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 813 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 814 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 815 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 816 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 817 * @retval None
<> 144:ef7eb2e8f9f7 818 */
<> 144:ef7eb2e8f9f7 819 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 CLEAR_BIT(EXTI->RTSR1, ExtiLine);
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /**
<> 144:ef7eb2e8f9f7 826 * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 827 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 828 * generated on these lines. If a rising edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 829 * line occurs during a write operation in the EXTI_RTSR register, the
<> 144:ef7eb2e8f9f7 830 * pending bit is not set.
<> 144:ef7eb2e8f9f7 831 * Rising and falling edge triggers can be set for
<> 144:ef7eb2e8f9f7 832 * the same interrupt line. In this case, both generate a trigger
<> 144:ef7eb2e8f9f7 833 * condition.
<> 144:ef7eb2e8f9f7 834 * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
<> 144:ef7eb2e8f9f7 835 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 836 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 837 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 838 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 839 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 840 * @retval None
<> 144:ef7eb2e8f9f7 841 */
<> 144:ef7eb2e8f9f7 842 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 CLEAR_BIT(EXTI->RTSR2, ExtiLine);
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /**
<> 144:ef7eb2e8f9f7 848 * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 849 * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
<> 144:ef7eb2e8f9f7 850 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 851 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 852 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 853 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 854 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 855 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 856 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 857 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 858 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 859 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 860 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 861 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 862 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 863 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 864 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 865 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 866 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 867 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 868 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 869 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 870 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 871 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 872 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 873 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 874 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 875 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 876 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 877 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 return (READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /**
<> 144:ef7eb2e8f9f7 885 * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 886 * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
<> 144:ef7eb2e8f9f7 887 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 888 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 889 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 890 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 891 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 892 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 895 {
<> 144:ef7eb2e8f9f7 896 return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /**
<> 144:ef7eb2e8f9f7 900 * @}
<> 144:ef7eb2e8f9f7 901 */
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
<> 144:ef7eb2e8f9f7 904 * @{
<> 144:ef7eb2e8f9f7 905 */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /**
<> 144:ef7eb2e8f9f7 908 * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 909 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 910 * generated on these lines. If a falling edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 911 * line occurs during a write operation in the EXTI_FTSR register, the
<> 144:ef7eb2e8f9f7 912 * pending bit is not set.
<> 144:ef7eb2e8f9f7 913 * Rising and falling edge triggers can be set for
<> 144:ef7eb2e8f9f7 914 * the same interrupt line. In this case, both generate a trigger
<> 144:ef7eb2e8f9f7 915 * condition.
<> 144:ef7eb2e8f9f7 916 * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
<> 144:ef7eb2e8f9f7 917 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 918 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 919 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 920 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 921 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 922 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 923 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 924 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 925 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 926 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 927 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 928 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 929 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 930 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 931 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 932 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 933 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 934 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 935 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 936 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 937 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 938 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 939 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 940 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 941 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 942 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 943 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 944 * @retval None
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 SET_BIT(EXTI->FTSR1, ExtiLine);
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /**
<> 144:ef7eb2e8f9f7 952 * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 953 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 954 * generated on these lines. If a Falling edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 955 * line occurs during a write operation in the EXTI_FTSR register, the
<> 144:ef7eb2e8f9f7 956 * pending bit is not set.
<> 144:ef7eb2e8f9f7 957 * Rising and falling edge triggers can be set for
<> 144:ef7eb2e8f9f7 958 * the same interrupt line. In this case, both generate a trigger
<> 144:ef7eb2e8f9f7 959 * condition.
<> 144:ef7eb2e8f9f7 960 * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
<> 144:ef7eb2e8f9f7 961 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 962 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 963 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 964 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 965 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 966 * @retval None
<> 144:ef7eb2e8f9f7 967 */
<> 144:ef7eb2e8f9f7 968 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 969 {
<> 144:ef7eb2e8f9f7 970 SET_BIT(EXTI->FTSR2, ExtiLine);
<> 144:ef7eb2e8f9f7 971 }
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /**
<> 144:ef7eb2e8f9f7 974 * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 975 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 976 * generated on these lines. If a Falling edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 977 * line occurs during a write operation in the EXTI_FTSR register, the
<> 144:ef7eb2e8f9f7 978 * pending bit is not set.
<> 144:ef7eb2e8f9f7 979 * Rising and falling edge triggers can be set for the same interrupt line.
<> 144:ef7eb2e8f9f7 980 * In this case, both generate a trigger condition.
<> 144:ef7eb2e8f9f7 981 * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
<> 144:ef7eb2e8f9f7 982 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 983 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 984 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 985 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 986 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 987 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 988 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 989 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 990 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 991 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 992 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 993 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 994 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 995 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 996 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 997 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 998 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 999 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 1000 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 1001 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 1002 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 1003 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 1004 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 1005 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 1006 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 1007 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 1008 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 1009 * @retval None
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1012 {
<> 144:ef7eb2e8f9f7 1013 CLEAR_BIT(EXTI->FTSR1, ExtiLine);
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /**
<> 144:ef7eb2e8f9f7 1017 * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 1018 * @note The configurable wakeup lines are edge-triggered. No glitch must be
<> 144:ef7eb2e8f9f7 1019 * generated on these lines. If a Falling edge on a configurable interrupt
<> 144:ef7eb2e8f9f7 1020 * line occurs during a write operation in the EXTI_FTSR register, the
<> 144:ef7eb2e8f9f7 1021 * pending bit is not set.
<> 144:ef7eb2e8f9f7 1022 * Rising and falling edge triggers can be set for the same interrupt line.
<> 144:ef7eb2e8f9f7 1023 * In this case, both generate a trigger condition.
<> 144:ef7eb2e8f9f7 1024 * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
<> 144:ef7eb2e8f9f7 1025 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1026 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 1027 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 1028 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 1029 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 1030 * @retval None
<> 144:ef7eb2e8f9f7 1031 */
<> 144:ef7eb2e8f9f7 1032 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 CLEAR_BIT(EXTI->FTSR2, ExtiLine);
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /**
<> 144:ef7eb2e8f9f7 1038 * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 1039 * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
<> 144:ef7eb2e8f9f7 1040 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1041 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 1042 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 1043 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 1044 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 1045 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 1046 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 1047 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 1048 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 1049 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 1050 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 1051 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 1052 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 1053 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 1054 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 1055 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 1056 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 1057 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 1058 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 1059 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 1060 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 1061 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 1062 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 1063 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 1064 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 1065 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 1066 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 1067 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 return (READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /**
<> 144:ef7eb2e8f9f7 1075 * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 1076 * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
<> 144:ef7eb2e8f9f7 1077 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1078 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 1079 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 1080 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 1081 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 1082 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 1083 */
<> 144:ef7eb2e8f9f7 1084 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1085 {
<> 144:ef7eb2e8f9f7 1086 return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 1087 }
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /**
<> 144:ef7eb2e8f9f7 1090 * @}
<> 144:ef7eb2e8f9f7 1091 */
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
<> 144:ef7eb2e8f9f7 1094 * @{
<> 144:ef7eb2e8f9f7 1095 */
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /**
<> 144:ef7eb2e8f9f7 1098 * @brief Generate a software Interrupt Event for Lines in range 0 to 31
AnnaBridge 167:e84263d55307 1099 * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to
AnnaBridge 167:e84263d55307 1100 * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
<> 144:ef7eb2e8f9f7 1101 * resulting in an interrupt request generation.
AnnaBridge 167:e84263d55307 1102 * This bit is cleared by clearing the corresponding bit in the EXTI_PR1
<> 144:ef7eb2e8f9f7 1103 * register (by writing a 1 into the bit)
<> 144:ef7eb2e8f9f7 1104 * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
<> 144:ef7eb2e8f9f7 1105 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1106 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 1107 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 1108 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 1109 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 1110 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 1111 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 1112 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 1113 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 1114 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 1115 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 1116 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 1117 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 1118 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 1119 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 1120 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 1121 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 1122 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 1123 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 1124 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 1125 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 1126 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 1127 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 1128 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 1129 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 1130 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 1131 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 1132 * @retval None
<> 144:ef7eb2e8f9f7 1133 */
<> 144:ef7eb2e8f9f7 1134 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1135 {
<> 144:ef7eb2e8f9f7 1136 SET_BIT(EXTI->SWIER1, ExtiLine);
<> 144:ef7eb2e8f9f7 1137 }
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /**
<> 144:ef7eb2e8f9f7 1140 * @brief Generate a software Interrupt Event for Lines in range 32 to 63
AnnaBridge 167:e84263d55307 1141 * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
AnnaBridge 167:e84263d55307 1142 * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
<> 144:ef7eb2e8f9f7 1143 * resulting in an interrupt request generation.
AnnaBridge 167:e84263d55307 1144 * This bit is cleared by clearing the corresponding bit in the EXTI_PR2
<> 144:ef7eb2e8f9f7 1145 * register (by writing a 1 into the bit)
<> 144:ef7eb2e8f9f7 1146 * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
<> 144:ef7eb2e8f9f7 1147 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1148 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 1149 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 1150 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 1151 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 1152 * @retval None
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 SET_BIT(EXTI->SWIER2, ExtiLine);
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /**
<> 144:ef7eb2e8f9f7 1160 * @}
<> 144:ef7eb2e8f9f7 1161 */
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
<> 144:ef7eb2e8f9f7 1164 * @{
<> 144:ef7eb2e8f9f7 1165 */
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /**
<> 144:ef7eb2e8f9f7 1168 * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 1169 * @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1170 * line. This bit is cleared by writing a 1 to the bit.
<> 144:ef7eb2e8f9f7 1171 * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31
<> 144:ef7eb2e8f9f7 1172 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1173 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 1174 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 1175 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 1176 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 1177 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 1178 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 1179 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 1180 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 1181 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 1182 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 1183 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 1184 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 1185 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 1186 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 1187 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 1188 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 1189 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 1190 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 1191 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 1192 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 1193 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 1194 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 1195 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 1196 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 1197 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 1198 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 1199 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 1200 */
<> 144:ef7eb2e8f9f7 1201 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1202 {
<> 144:ef7eb2e8f9f7 1203 return (READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 1204 }
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /**
<> 144:ef7eb2e8f9f7 1207 * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 1208 * @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1209 * line. This bit is cleared by writing a 1 to the bit.
<> 144:ef7eb2e8f9f7 1210 * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
<> 144:ef7eb2e8f9f7 1211 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1212 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 1213 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 1214 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 1215 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 1216 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 1217 */
<> 144:ef7eb2e8f9f7 1218 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1219 {
<> 144:ef7eb2e8f9f7 1220 return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));
<> 144:ef7eb2e8f9f7 1221 }
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /**
<> 144:ef7eb2e8f9f7 1224 * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 1225 * @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1226 * line. This bit is cleared by writing a 1 to the bit.
<> 144:ef7eb2e8f9f7 1227 * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31
<> 144:ef7eb2e8f9f7 1228 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1229 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 1230 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 1231 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 1232 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 1233 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 1234 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 1235 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 1236 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 1237 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 1238 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 1239 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 1240 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 1241 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 1242 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 1243 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 1244 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 1245 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 1246 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 1247 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 1248 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 1249 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 1250 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 1251 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 1252 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 1253 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 1254 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 1255 * @retval @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1256 */
<> 144:ef7eb2e8f9f7 1257 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1258 {
<> 144:ef7eb2e8f9f7 1259 return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /**
<> 144:ef7eb2e8f9f7 1264 * @brief Read ExtLine Combination Flag for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 1265 * @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1266 * line. This bit is cleared by writing a 1 to the bit.
<> 144:ef7eb2e8f9f7 1267 * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
<> 144:ef7eb2e8f9f7 1268 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1269 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 1270 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 1271 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 1272 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 1273 * @retval @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1274 */
<> 144:ef7eb2e8f9f7 1275 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1276 {
<> 144:ef7eb2e8f9f7 1277 return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
<> 144:ef7eb2e8f9f7 1278 }
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /**
<> 144:ef7eb2e8f9f7 1281 * @brief Clear ExtLine Flags for Lines in range 0 to 31
<> 144:ef7eb2e8f9f7 1282 * @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1283 * line. This bit is cleared by writing a 1 to the bit.
<> 144:ef7eb2e8f9f7 1284 * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31
<> 144:ef7eb2e8f9f7 1285 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1286 * @arg @ref LL_EXTI_LINE_0
<> 144:ef7eb2e8f9f7 1287 * @arg @ref LL_EXTI_LINE_1
<> 144:ef7eb2e8f9f7 1288 * @arg @ref LL_EXTI_LINE_2
<> 144:ef7eb2e8f9f7 1289 * @arg @ref LL_EXTI_LINE_3
<> 144:ef7eb2e8f9f7 1290 * @arg @ref LL_EXTI_LINE_4
<> 144:ef7eb2e8f9f7 1291 * @arg @ref LL_EXTI_LINE_5
<> 144:ef7eb2e8f9f7 1292 * @arg @ref LL_EXTI_LINE_6
<> 144:ef7eb2e8f9f7 1293 * @arg @ref LL_EXTI_LINE_7
<> 144:ef7eb2e8f9f7 1294 * @arg @ref LL_EXTI_LINE_8
<> 144:ef7eb2e8f9f7 1295 * @arg @ref LL_EXTI_LINE_9
<> 144:ef7eb2e8f9f7 1296 * @arg @ref LL_EXTI_LINE_10
<> 144:ef7eb2e8f9f7 1297 * @arg @ref LL_EXTI_LINE_11
<> 144:ef7eb2e8f9f7 1298 * @arg @ref LL_EXTI_LINE_12
<> 144:ef7eb2e8f9f7 1299 * @arg @ref LL_EXTI_LINE_13
<> 144:ef7eb2e8f9f7 1300 * @arg @ref LL_EXTI_LINE_14
<> 144:ef7eb2e8f9f7 1301 * @arg @ref LL_EXTI_LINE_15
<> 144:ef7eb2e8f9f7 1302 * @arg @ref LL_EXTI_LINE_16
<> 144:ef7eb2e8f9f7 1303 * @arg @ref LL_EXTI_LINE_18
<> 144:ef7eb2e8f9f7 1304 * @arg @ref LL_EXTI_LINE_19
<> 144:ef7eb2e8f9f7 1305 * @arg @ref LL_EXTI_LINE_20
<> 144:ef7eb2e8f9f7 1306 * @arg @ref LL_EXTI_LINE_21
<> 144:ef7eb2e8f9f7 1307 * @arg @ref LL_EXTI_LINE_22
<> 144:ef7eb2e8f9f7 1308 * @arg @ref LL_EXTI_LINE_29
<> 144:ef7eb2e8f9f7 1309 * @arg @ref LL_EXTI_LINE_30
<> 144:ef7eb2e8f9f7 1310 * @arg @ref LL_EXTI_LINE_31
<> 144:ef7eb2e8f9f7 1311 * @note Please check each device line mapping for EXTI Line availability
<> 144:ef7eb2e8f9f7 1312 * @retval None
<> 144:ef7eb2e8f9f7 1313 */
<> 144:ef7eb2e8f9f7 1314 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 WRITE_REG(EXTI->PR1, ExtiLine);
<> 144:ef7eb2e8f9f7 1317 }
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 /**
<> 144:ef7eb2e8f9f7 1320 * @brief Clear ExtLine Flags for Lines in range 32 to 63
<> 144:ef7eb2e8f9f7 1321 * @note This bit is set when the selected edge event arrives on the interrupt
<> 144:ef7eb2e8f9f7 1322 * line. This bit is cleared by writing a 1 to the bit.
<> 144:ef7eb2e8f9f7 1323 * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
<> 144:ef7eb2e8f9f7 1324 * @param ExtiLine This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 1325 * @arg @ref LL_EXTI_LINE_35
<> 144:ef7eb2e8f9f7 1326 * @arg @ref LL_EXTI_LINE_36
<> 144:ef7eb2e8f9f7 1327 * @arg @ref LL_EXTI_LINE_37
<> 144:ef7eb2e8f9f7 1328 * @arg @ref LL_EXTI_LINE_38
<> 144:ef7eb2e8f9f7 1329 * @retval None
<> 144:ef7eb2e8f9f7 1330 */
<> 144:ef7eb2e8f9f7 1331 __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
<> 144:ef7eb2e8f9f7 1332 {
<> 144:ef7eb2e8f9f7 1333 WRITE_REG(EXTI->PR2, ExtiLine);
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /**
<> 144:ef7eb2e8f9f7 1337 * @}
<> 144:ef7eb2e8f9f7 1338 */
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 1341 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 1342 * @{
<> 144:ef7eb2e8f9f7 1343 */
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
<> 144:ef7eb2e8f9f7 1346 uint32_t LL_EXTI_DeInit(void);
<> 144:ef7eb2e8f9f7 1347 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /**
<> 144:ef7eb2e8f9f7 1351 * @}
<> 144:ef7eb2e8f9f7 1352 */
<> 144:ef7eb2e8f9f7 1353 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /**
<> 144:ef7eb2e8f9f7 1356 * @}
<> 144:ef7eb2e8f9f7 1357 */
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /**
<> 144:ef7eb2e8f9f7 1360 * @}
<> 144:ef7eb2e8f9f7 1361 */
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363 #endif /* EXTI */
<> 144:ef7eb2e8f9f7 1364
<> 144:ef7eb2e8f9f7 1365 /**
<> 144:ef7eb2e8f9f7 1366 * @}
<> 144:ef7eb2e8f9f7 1367 */
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1370 }
<> 144:ef7eb2e8f9f7 1371 #endif
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 #endif /* __STM32L4xx_LL_EXTI_H */
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/