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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
181:57724642e740 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_dac.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief DAC LL module driver
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 167:e84263d55307 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #include "stm32l4xx_ll_dac.h"
<> 144:ef7eb2e8f9f7 39 #include "stm32l4xx_ll_bus.h"
<> 144:ef7eb2e8f9f7 40
AnnaBridge 167:e84263d55307 41 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 42 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 43 #else
<> 144:ef7eb2e8f9f7 44 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #if defined (DAC1)
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DAC_LL DAC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @addtogroup DAC_LL_Private_Macros
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
AnnaBridge 167:e84263d55307 66 #if defined(DAC_CHANNEL2_SUPPORT)
<> 144:ef7eb2e8f9f7 67 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
<> 144:ef7eb2e8f9f7 68 ( \
<> 144:ef7eb2e8f9f7 69 ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
<> 144:ef7eb2e8f9f7 70 || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
<> 144:ef7eb2e8f9f7 71 )
AnnaBridge 167:e84263d55307 72 #else
AnnaBridge 167:e84263d55307 73 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
AnnaBridge 167:e84263d55307 74 ( \
AnnaBridge 167:e84263d55307 75 ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
AnnaBridge 167:e84263d55307 76 )
AnnaBridge 167:e84263d55307 77 #endif /* DAC_CHANNEL2_SUPPORT */
<> 144:ef7eb2e8f9f7 78
AnnaBridge 181:57724642e740 79 #if defined (DAC_CR_TSEL1_3)
AnnaBridge 181:57724642e740 80 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
AnnaBridge 181:57724642e740 81 ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
AnnaBridge 181:57724642e740 82 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
AnnaBridge 181:57724642e740 83 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
AnnaBridge 181:57724642e740 84 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
AnnaBridge 181:57724642e740 85 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
AnnaBridge 181:57724642e740 86 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
AnnaBridge 181:57724642e740 87 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
AnnaBridge 181:57724642e740 88 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
AnnaBridge 181:57724642e740 89 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO) \
AnnaBridge 181:57724642e740 90 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO) \
AnnaBridge 181:57724642e740 91 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
AnnaBridge 181:57724642e740 92 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
AnnaBridge 181:57724642e740 93 )
AnnaBridge 181:57724642e740 94 #else
<> 144:ef7eb2e8f9f7 95 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
<> 144:ef7eb2e8f9f7 96 ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
<> 144:ef7eb2e8f9f7 97 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
<> 144:ef7eb2e8f9f7 98 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
<> 144:ef7eb2e8f9f7 99 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
<> 144:ef7eb2e8f9f7 100 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
<> 144:ef7eb2e8f9f7 101 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
<> 144:ef7eb2e8f9f7 102 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
<> 144:ef7eb2e8f9f7 103 || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
<> 144:ef7eb2e8f9f7 104 )
AnnaBridge 181:57724642e740 105 #endif /* DAC_CR_TSEL1_3 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
<> 144:ef7eb2e8f9f7 108 ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
<> 144:ef7eb2e8f9f7 109 || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
<> 144:ef7eb2e8f9f7 110 || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
<> 144:ef7eb2e8f9f7 111 )
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
<> 144:ef7eb2e8f9f7 114 ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
<> 144:ef7eb2e8f9f7 115 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
<> 144:ef7eb2e8f9f7 116 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
<> 144:ef7eb2e8f9f7 117 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
<> 144:ef7eb2e8f9f7 118 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
<> 144:ef7eb2e8f9f7 119 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
<> 144:ef7eb2e8f9f7 120 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
<> 144:ef7eb2e8f9f7 121 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
<> 144:ef7eb2e8f9f7 122 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
<> 144:ef7eb2e8f9f7 123 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
<> 144:ef7eb2e8f9f7 124 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
<> 144:ef7eb2e8f9f7 125 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
<> 144:ef7eb2e8f9f7 126 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
<> 144:ef7eb2e8f9f7 127 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
<> 144:ef7eb2e8f9f7 128 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
<> 144:ef7eb2e8f9f7 129 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
<> 144:ef7eb2e8f9f7 130 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
<> 144:ef7eb2e8f9f7 131 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
<> 144:ef7eb2e8f9f7 132 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
<> 144:ef7eb2e8f9f7 133 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
<> 144:ef7eb2e8f9f7 134 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
<> 144:ef7eb2e8f9f7 135 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
<> 144:ef7eb2e8f9f7 136 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
<> 144:ef7eb2e8f9f7 137 || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
<> 144:ef7eb2e8f9f7 138 )
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
<> 144:ef7eb2e8f9f7 141 ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
<> 144:ef7eb2e8f9f7 142 || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
<> 144:ef7eb2e8f9f7 143 )
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \
<> 144:ef7eb2e8f9f7 146 ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
<> 144:ef7eb2e8f9f7 147 || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
<> 144:ef7eb2e8f9f7 148 )
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \
<> 144:ef7eb2e8f9f7 151 ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
<> 144:ef7eb2e8f9f7 152 || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
<> 144:ef7eb2e8f9f7 153 )
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 163 /** @addtogroup DAC_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /** @addtogroup DAC_LL_EF_Init
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @brief De-initialize registers of the selected DAC instance
<> 144:ef7eb2e8f9f7 173 * to their default reset values.
<> 144:ef7eb2e8f9f7 174 * @param DACx DAC instance
<> 144:ef7eb2e8f9f7 175 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 176 * - SUCCESS: DAC registers are de-initialized
<> 144:ef7eb2e8f9f7 177 * - ERROR: not applicable
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 /* Check the parameters */
<> 144:ef7eb2e8f9f7 182 assert_param(IS_DAC_ALL_INSTANCE(DACx));
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Force reset of DAC clock */
<> 144:ef7eb2e8f9f7 185 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Release reset of DAC clock */
<> 144:ef7eb2e8f9f7 188 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 return SUCCESS;
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @brief Initialize some features of DAC instance.
<> 144:ef7eb2e8f9f7 195 * @note The setting of these parameters by function @ref LL_DAC_Init()
<> 144:ef7eb2e8f9f7 196 * is conditioned to DAC state:
<> 144:ef7eb2e8f9f7 197 * DAC instance must be disabled.
<> 144:ef7eb2e8f9f7 198 * @param DACx DAC instance
<> 144:ef7eb2e8f9f7 199 * @param DAC_Channel This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 200 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 167:e84263d55307 201 * @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge 167:e84263d55307 202 *
AnnaBridge 167:e84263d55307 203 * (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge 167:e84263d55307 204 * Refer to device datasheet for channels availability.
<> 144:ef7eb2e8f9f7 205 * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
<> 144:ef7eb2e8f9f7 206 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 207 * - SUCCESS: DAC registers are initialized
<> 144:ef7eb2e8f9f7 208 * - ERROR: DAC registers are not initialized
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Check the parameters */
<> 144:ef7eb2e8f9f7 215 assert_param(IS_DAC_ALL_INSTANCE(DACx));
<> 144:ef7eb2e8f9f7 216 assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
<> 144:ef7eb2e8f9f7 218 assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
<> 144:ef7eb2e8f9f7 220 assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
<> 144:ef7eb2e8f9f7 221 assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
<> 144:ef7eb2e8f9f7 222 if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Note: Hardware constraint (refer to description of this function) */
<> 144:ef7eb2e8f9f7 228 /* DAC instance must be disabled. */
<> 144:ef7eb2e8f9f7 229 if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 /* Configuration of DAC channel: */
<> 144:ef7eb2e8f9f7 232 /* - TriggerSource */
<> 144:ef7eb2e8f9f7 233 /* - WaveAutoGeneration */
<> 144:ef7eb2e8f9f7 234 /* - OutputBuffer */
<> 144:ef7eb2e8f9f7 235 /* - OutputConnection */
<> 144:ef7eb2e8f9f7 236 /* - OutputMode */
<> 144:ef7eb2e8f9f7 237 if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 MODIFY_REG(DACx->CR,
<> 144:ef7eb2e8f9f7 240 ( DAC_CR_TSEL1
<> 144:ef7eb2e8f9f7 241 | DAC_CR_WAVE1
<> 144:ef7eb2e8f9f7 242 | DAC_CR_MAMP1
<> 144:ef7eb2e8f9f7 243 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 144:ef7eb2e8f9f7 244 ,
<> 144:ef7eb2e8f9f7 245 ( DAC_InitStruct->TriggerSource
<> 144:ef7eb2e8f9f7 246 | DAC_InitStruct->WaveAutoGeneration
<> 144:ef7eb2e8f9f7 247 | DAC_InitStruct->WaveAutoGenerationConfig
<> 144:ef7eb2e8f9f7 248 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 144:ef7eb2e8f9f7 249 );
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 else
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 MODIFY_REG(DACx->CR,
<> 144:ef7eb2e8f9f7 254 ( DAC_CR_TSEL1
<> 144:ef7eb2e8f9f7 255 | DAC_CR_WAVE1
<> 144:ef7eb2e8f9f7 256 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 144:ef7eb2e8f9f7 257 ,
<> 144:ef7eb2e8f9f7 258 ( DAC_InitStruct->TriggerSource
<> 144:ef7eb2e8f9f7 259 | LL_DAC_WAVE_AUTO_GENERATION_NONE
<> 144:ef7eb2e8f9f7 260 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 144:ef7eb2e8f9f7 261 );
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 MODIFY_REG(DACx->MCR,
<> 144:ef7eb2e8f9f7 265 ( DAC_MCR_MODE1_1
<> 144:ef7eb2e8f9f7 266 | DAC_MCR_MODE1_0
<> 144:ef7eb2e8f9f7 267 | DAC_MCR_MODE1_2
<> 144:ef7eb2e8f9f7 268 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 144:ef7eb2e8f9f7 269 ,
<> 144:ef7eb2e8f9f7 270 ( DAC_InitStruct->OutputBuffer
<> 144:ef7eb2e8f9f7 271 | DAC_InitStruct->OutputConnection
<> 144:ef7eb2e8f9f7 272 | DAC_InitStruct->OutputMode
<> 144:ef7eb2e8f9f7 273 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 144:ef7eb2e8f9f7 274 );
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276 else
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Initialization error: DAC instance is not disabled. */
<> 144:ef7eb2e8f9f7 279 status = ERROR;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281 return status;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
<> 144:ef7eb2e8f9f7 286 * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
<> 144:ef7eb2e8f9f7 287 * whose fields will be set to default values.
<> 144:ef7eb2e8f9f7 288 * @retval None
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 /* Set DAC_InitStruct fields to default values */
<> 144:ef7eb2e8f9f7 293 DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
<> 144:ef7eb2e8f9f7 294 DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
<> 144:ef7eb2e8f9f7 295 /* Note: Parameter discarded if wave auto generation is disabled, */
<> 144:ef7eb2e8f9f7 296 /* set anyway to its default value. */
<> 144:ef7eb2e8f9f7 297 DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
<> 144:ef7eb2e8f9f7 298 DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
<> 144:ef7eb2e8f9f7 299 DAC_InitStruct->OutputConnection = LL_DAC_OUTPUT_CONNECT_GPIO;
<> 144:ef7eb2e8f9f7 300 DAC_InitStruct->OutputMode = LL_DAC_OUTPUT_MODE_NORMAL;
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @}
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 #endif /* DAC1 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @}
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/