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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 181:57724642e740

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_dfsdm.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief Header file of DFSDM HAL module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
AnnaBridge	167:e84263d55307	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
<>	144:ef7eb2e8f9f7	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	37	#ifndef __STM32L4xx_HAL_DFSDM_H
<>	144:ef7eb2e8f9f7	38	#define __STM32L4xx_HAL_DFSDM_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
AnnaBridge	167:e84263d55307	44	#if defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	167:e84263d55307	45	defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| \
AnnaBridge	181:57724642e740	46	defined(STM32L496xx) \|\| defined(STM32L4A6xx) \|\| \
AnnaBridge	181:57724642e740	47	defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	181:57724642e740	48
<>	144:ef7eb2e8f9f7	49	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	50	#include "stm32l4xx_hal_def.h"
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	53	* @{
<>	144:ef7eb2e8f9f7	54	*/
<>	144:ef7eb2e8f9f7	55
<>	144:ef7eb2e8f9f7	56	/** @addtogroup DFSDM
<>	144:ef7eb2e8f9f7	57	* @{
<>	144:ef7eb2e8f9f7	58	*/
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	61	/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
<>	144:ef7eb2e8f9f7	62	* @{
<>	144:ef7eb2e8f9f7	63	*/
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65	/**
<>	144:ef7eb2e8f9f7	66	* @brief HAL DFSDM Channel states definition
<>	144:ef7eb2e8f9f7	67	*/
<>	144:ef7eb2e8f9f7	68	typedef enum
<>	144:ef7eb2e8f9f7	69	{
<>	144:ef7eb2e8f9f7	70	HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /!< DFSDM channel not initialized /
<>	144:ef7eb2e8f9f7	71	HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /!< DFSDM channel initialized and ready for use /
<>	144:ef7eb2e8f9f7	72	HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /!< DFSDM channel state error /
<>	144:ef7eb2e8f9f7	73	}HAL_DFSDM_Channel_StateTypeDef;
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	/**
<>	144:ef7eb2e8f9f7	76	* @brief DFSDM channel output clock structure definition
<>	144:ef7eb2e8f9f7	77	*/
<>	144:ef7eb2e8f9f7	78	typedef struct
<>	144:ef7eb2e8f9f7	79	{
<>	144:ef7eb2e8f9f7	80	FunctionalState Activation; /!< Output clock enable/disable /
<>	144:ef7eb2e8f9f7	81	uint32_t Selection; /*!< Output clock is system clock or audio clock.
<>	144:ef7eb2e8f9f7	82	This parameter can be a value of @ref DFSDM_Channel_OuputClock */
<>	144:ef7eb2e8f9f7	83	uint32_t Divider; /*!< Output clock divider.
<>	144:ef7eb2e8f9f7	84	This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
<>	144:ef7eb2e8f9f7	85	}DFSDM_Channel_OutputClockTypeDef;
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	/**
<>	144:ef7eb2e8f9f7	88	* @brief DFSDM channel input structure definition
<>	144:ef7eb2e8f9f7	89	*/
<>	144:ef7eb2e8f9f7	90	typedef struct
<>	144:ef7eb2e8f9f7	91	{
AnnaBridge	167:e84263d55307	92	uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
AnnaBridge	167:e84263d55307	93	ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,
AnnaBridge	181:57724642e740	94	STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx,
AnnaBridge	181:57724642e740	95	STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products.
<>	144:ef7eb2e8f9f7	96	This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
<>	144:ef7eb2e8f9f7	97	uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
<>	144:ef7eb2e8f9f7	98	This parameter can be a value of @ref DFSDM_Channel_DataPacking */
<>	144:ef7eb2e8f9f7	99	uint32_t Pins; /*!< Input pins are taken from same or following channel.
<>	144:ef7eb2e8f9f7	100	This parameter can be a value of @ref DFSDM_Channel_InputPins */
<>	144:ef7eb2e8f9f7	101	}DFSDM_Channel_InputTypeDef;
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	/**
<>	144:ef7eb2e8f9f7	104	* @brief DFSDM channel serial interface structure definition
<>	144:ef7eb2e8f9f7	105	*/
<>	144:ef7eb2e8f9f7	106	typedef struct
<>	144:ef7eb2e8f9f7	107	{
<>	144:ef7eb2e8f9f7	108	uint32_t Type; /*!< SPI or Manchester modes.
<>	144:ef7eb2e8f9f7	109	This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
<>	144:ef7eb2e8f9f7	110	uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
<>	144:ef7eb2e8f9f7	111	This parameter can be a value of @ref DFSDM_Channel_SpiClock */
<>	144:ef7eb2e8f9f7	112	}DFSDM_Channel_SerialInterfaceTypeDef;
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	/**
<>	144:ef7eb2e8f9f7	115	* @brief DFSDM channel analog watchdog structure definition
<>	144:ef7eb2e8f9f7	116	*/
<>	144:ef7eb2e8f9f7	117	typedef struct
<>	144:ef7eb2e8f9f7	118	{
<>	144:ef7eb2e8f9f7	119	uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
<>	144:ef7eb2e8f9f7	120	This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
<>	144:ef7eb2e8f9f7	121	uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
<>	144:ef7eb2e8f9f7	122	This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
<>	144:ef7eb2e8f9f7	123	}DFSDM_Channel_AwdTypeDef;
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	/**
<>	144:ef7eb2e8f9f7	126	* @brief DFSDM channel init structure definition
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128	typedef struct
<>	144:ef7eb2e8f9f7	129	{
<>	144:ef7eb2e8f9f7	130	DFSDM_Channel_OutputClockTypeDef OutputClock; /!< DFSDM channel output clock parameters /
<>	144:ef7eb2e8f9f7	131	DFSDM_Channel_InputTypeDef Input; /!< DFSDM channel input parameters /
<>	144:ef7eb2e8f9f7	132	DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /!< DFSDM channel serial interface parameters /
<>	144:ef7eb2e8f9f7	133	DFSDM_Channel_AwdTypeDef Awd; /!< DFSDM channel analog watchdog parameters /
<>	144:ef7eb2e8f9f7	134	int32_t Offset; /*!< DFSDM channel offset.
<>	144:ef7eb2e8f9f7	135	This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
<>	144:ef7eb2e8f9f7	136	uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
<>	144:ef7eb2e8f9f7	137	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
<>	144:ef7eb2e8f9f7	138	}DFSDM_Channel_InitTypeDef;
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	/**
<>	144:ef7eb2e8f9f7	141	* @brief DFSDM channel handle structure definition
<>	144:ef7eb2e8f9f7	142	*/
<>	144:ef7eb2e8f9f7	143	typedef struct
<>	144:ef7eb2e8f9f7	144	{
<>	144:ef7eb2e8f9f7	145	DFSDM_Channel_TypeDef Instance; /!< DFSDM channel instance */
<>	144:ef7eb2e8f9f7	146	DFSDM_Channel_InitTypeDef Init; /!< DFSDM channel init parameters /
<>	144:ef7eb2e8f9f7	147	HAL_DFSDM_Channel_StateTypeDef State; /!< DFSDM channel state /
<>	144:ef7eb2e8f9f7	148	}DFSDM_Channel_HandleTypeDef;
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	/**
<>	144:ef7eb2e8f9f7	151	* @brief HAL DFSDM Filter states definition
<>	144:ef7eb2e8f9f7	152	*/
<>	144:ef7eb2e8f9f7	153	typedef enum
<>	144:ef7eb2e8f9f7	154	{
<>	144:ef7eb2e8f9f7	155	HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /!< DFSDM filter not initialized /
<>	144:ef7eb2e8f9f7	156	HAL_DFSDM_FILTER_STATE_READY = 0x01U, /!< DFSDM filter initialized and ready for use /
<>	144:ef7eb2e8f9f7	157	HAL_DFSDM_FILTER_STATE_REG = 0x02U, /!< DFSDM filter regular conversion in progress /
<>	144:ef7eb2e8f9f7	158	HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /!< DFSDM filter injected conversion in progress /
<>	144:ef7eb2e8f9f7	159	HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /!< DFSDM filter regular and injected conversions in progress /
<>	144:ef7eb2e8f9f7	160	HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /!< DFSDM filter state error /
<>	144:ef7eb2e8f9f7	161	}HAL_DFSDM_Filter_StateTypeDef;
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	/**
<>	144:ef7eb2e8f9f7	164	* @brief DFSDM filter regular conversion parameters structure definition
<>	144:ef7eb2e8f9f7	165	*/
<>	144:ef7eb2e8f9f7	166	typedef struct
<>	144:ef7eb2e8f9f7	167	{
<>	144:ef7eb2e8f9f7	168	uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
<>	144:ef7eb2e8f9f7	169	This parameter can be a value of @ref DFSDM_Filter_Trigger */
<>	144:ef7eb2e8f9f7	170	FunctionalState FastMode; /!< Enable/disable fast mode for regular conversion /
<>	144:ef7eb2e8f9f7	171	FunctionalState DmaMode; /!< Enable/disable DMA for regular conversion /
<>	144:ef7eb2e8f9f7	172	}DFSDM_Filter_RegularParamTypeDef;
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	/**
<>	144:ef7eb2e8f9f7	175	* @brief DFSDM filter injected conversion parameters structure definition
<>	144:ef7eb2e8f9f7	176	*/
<>	144:ef7eb2e8f9f7	177	typedef struct
<>	144:ef7eb2e8f9f7	178	{
<>	144:ef7eb2e8f9f7	179	uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
<>	144:ef7eb2e8f9f7	180	This parameter can be a value of @ref DFSDM_Filter_Trigger */
<>	144:ef7eb2e8f9f7	181	FunctionalState ScanMode; /!< Enable/disable scanning mode for injected conversion /
<>	144:ef7eb2e8f9f7	182	FunctionalState DmaMode; /!< Enable/disable DMA for injected conversion /
<>	144:ef7eb2e8f9f7	183	uint32_t ExtTrigger; /*!< External trigger.
<>	144:ef7eb2e8f9f7	184	This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
<>	144:ef7eb2e8f9f7	185	uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
<>	144:ef7eb2e8f9f7	186	This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
<>	144:ef7eb2e8f9f7	187	}DFSDM_Filter_InjectedParamTypeDef;
<>	144:ef7eb2e8f9f7	188
<>	144:ef7eb2e8f9f7	189	/**
<>	144:ef7eb2e8f9f7	190	* @brief DFSDM filter parameters structure definition
<>	144:ef7eb2e8f9f7	191	*/
<>	144:ef7eb2e8f9f7	192	typedef struct
<>	144:ef7eb2e8f9f7	193	{
<>	144:ef7eb2e8f9f7	194	uint32_t SincOrder; /*!< Sinc filter order.
<>	144:ef7eb2e8f9f7	195	This parameter can be a value of @ref DFSDM_Filter_SincOrder */
<>	144:ef7eb2e8f9f7	196	uint32_t Oversampling; /*!< Filter oversampling ratio.
<>	144:ef7eb2e8f9f7	197	This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
<>	144:ef7eb2e8f9f7	198	uint32_t IntOversampling; /*!< Integrator oversampling ratio.
<>	144:ef7eb2e8f9f7	199	This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
<>	144:ef7eb2e8f9f7	200	}DFSDM_Filter_FilterParamTypeDef;
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	/**
<>	144:ef7eb2e8f9f7	203	* @brief DFSDM filter init structure definition
<>	144:ef7eb2e8f9f7	204	*/
<>	144:ef7eb2e8f9f7	205	typedef struct
<>	144:ef7eb2e8f9f7	206	{
<>	144:ef7eb2e8f9f7	207	DFSDM_Filter_RegularParamTypeDef RegularParam; /!< DFSDM regular conversion parameters /
<>	144:ef7eb2e8f9f7	208	DFSDM_Filter_InjectedParamTypeDef InjectedParam; /!< DFSDM injected conversion parameters /
<>	144:ef7eb2e8f9f7	209	DFSDM_Filter_FilterParamTypeDef FilterParam; /!< DFSDM filter parameters /
<>	144:ef7eb2e8f9f7	210	}DFSDM_Filter_InitTypeDef;
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	/**
<>	144:ef7eb2e8f9f7	213	* @brief DFSDM filter handle structure definition
<>	144:ef7eb2e8f9f7	214	*/
<>	144:ef7eb2e8f9f7	215	typedef struct
<>	144:ef7eb2e8f9f7	216	{
<>	144:ef7eb2e8f9f7	217	DFSDM_Filter_TypeDef Instance; /!< DFSDM filter instance */
<>	144:ef7eb2e8f9f7	218	DFSDM_Filter_InitTypeDef Init; /!< DFSDM filter init parameters /
<>	144:ef7eb2e8f9f7	219	DMA_HandleTypeDef hdmaReg; /!< Pointer on DMA handler for regular conversions */
<>	144:ef7eb2e8f9f7	220	DMA_HandleTypeDef hdmaInj; /!< Pointer on DMA handler for injected conversions */
<>	144:ef7eb2e8f9f7	221	uint32_t RegularContMode; /!< Regular conversion continuous mode /
<>	144:ef7eb2e8f9f7	222	uint32_t RegularTrigger; /!< Trigger used for regular conversion /
<>	144:ef7eb2e8f9f7	223	uint32_t InjectedTrigger; /!< Trigger used for injected conversion /
<>	144:ef7eb2e8f9f7	224	uint32_t ExtTriggerEdge; /!< Rising, falling or both edges selected /
<>	144:ef7eb2e8f9f7	225	FunctionalState InjectedScanMode; /!< Injected scanning mode /
<>	144:ef7eb2e8f9f7	226	uint32_t InjectedChannelsNbr; /!< Number of channels in injected sequence /
<>	144:ef7eb2e8f9f7	227	uint32_t InjConvRemaining; /!< Injected conversions remaining /
<>	144:ef7eb2e8f9f7	228	HAL_DFSDM_Filter_StateTypeDef State; /!< DFSDM filter state /
<>	144:ef7eb2e8f9f7	229	uint32_t ErrorCode; /!< DFSDM filter error code /
<>	144:ef7eb2e8f9f7	230	}DFSDM_Filter_HandleTypeDef;
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/**
<>	144:ef7eb2e8f9f7	233	* @brief DFSDM filter analog watchdog parameters structure definition
<>	144:ef7eb2e8f9f7	234	*/
<>	144:ef7eb2e8f9f7	235	typedef struct
<>	144:ef7eb2e8f9f7	236	{
<>	144:ef7eb2e8f9f7	237	uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
<>	144:ef7eb2e8f9f7	238	This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
<>	144:ef7eb2e8f9f7	239	uint32_t Channel; /*!< Analog watchdog channel selection.
<>	144:ef7eb2e8f9f7	240	This parameter can be a values combination of @ref DFSDM_Channel_Selection */
<>	144:ef7eb2e8f9f7	241	int32_t HighThreshold; /*!< High threshold for the analog watchdog.
<>	144:ef7eb2e8f9f7	242	This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
<>	144:ef7eb2e8f9f7	243	int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
<>	144:ef7eb2e8f9f7	244	This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
<>	144:ef7eb2e8f9f7	245	uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
<>	144:ef7eb2e8f9f7	246	This parameter can be a values combination of @ref DFSDM_BreakSignals */
<>	144:ef7eb2e8f9f7	247	uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
<>	144:ef7eb2e8f9f7	248	This parameter can be a values combination of @ref DFSDM_BreakSignals */
<>	144:ef7eb2e8f9f7	249	}DFSDM_Filter_AwdParamTypeDef;
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/**
<>	144:ef7eb2e8f9f7	252	* @}
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254	/* End of exported types -----------------------------------------------------*/
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	257	/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
<>	144:ef7eb2e8f9f7	258	* @{
<>	144:ef7eb2e8f9f7	259	*/
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
<>	144:ef7eb2e8f9f7	262	* @{
<>	144:ef7eb2e8f9f7	263	*/
<>	144:ef7eb2e8f9f7	264	#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /!< Source for ouput clock is system clock /
<>	144:ef7eb2e8f9f7	265	#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /!< Source for ouput clock is audio clock /
<>	144:ef7eb2e8f9f7	266	/**
<>	144:ef7eb2e8f9f7	267	* @}
<>	144:ef7eb2e8f9f7	268	*/
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
<>	144:ef7eb2e8f9f7	271	* @{
<>	144:ef7eb2e8f9f7	272	*/
<>	144:ef7eb2e8f9f7	273	#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /!< Data are taken from external inputs /
AnnaBridge	167:e84263d55307	274	#if defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	181:57724642e740	275	defined(STM32L496xx) \|\| defined(STM32L4A6xx) \|\| \
AnnaBridge	181:57724642e740	276	defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	167:e84263d55307	277	#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /!< Data are taken from ADC output /
AnnaBridge	181:57724642e740	278	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx \|\| STM32L496xx \|\| STM32L4A6xx \|\| STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
<>	144:ef7eb2e8f9f7	279	#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /!< Data are taken from internal register /
<>	144:ef7eb2e8f9f7	280	/**
<>	144:ef7eb2e8f9f7	281	* @}
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
<>	144:ef7eb2e8f9f7	285	* @{
<>	144:ef7eb2e8f9f7	286	*/
<>	144:ef7eb2e8f9f7	287	#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /!< Standard data packing mode /
<>	144:ef7eb2e8f9f7	288	#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /!< Interleaved data packing mode /
<>	144:ef7eb2e8f9f7	289	#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /!< Dual data packing mode /
<>	144:ef7eb2e8f9f7	290	/**
<>	144:ef7eb2e8f9f7	291	* @}
<>	144:ef7eb2e8f9f7	292	*/
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
<>	144:ef7eb2e8f9f7	295	* @{
<>	144:ef7eb2e8f9f7	296	*/
<>	144:ef7eb2e8f9f7	297	#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /!< Input from pins on same channel /
<>	144:ef7eb2e8f9f7	298	#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /!< Input from pins on following channel /
<>	144:ef7eb2e8f9f7	299	/**
<>	144:ef7eb2e8f9f7	300	* @}
<>	144:ef7eb2e8f9f7	301	*/
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303	/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
<>	144:ef7eb2e8f9f7	304	* @{
<>	144:ef7eb2e8f9f7	305	*/
<>	144:ef7eb2e8f9f7	306	#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /!< SPI with rising edge /
<>	144:ef7eb2e8f9f7	307	#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /!< SPI with falling edge /
<>	144:ef7eb2e8f9f7	308	#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /!< Manchester with rising edge /
<>	144:ef7eb2e8f9f7	309	#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /!< Manchester with falling edge /
<>	144:ef7eb2e8f9f7	310	/**
<>	144:ef7eb2e8f9f7	311	* @}
<>	144:ef7eb2e8f9f7	312	*/
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
<>	144:ef7eb2e8f9f7	315	* @{
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317	#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /!< External SPI clock /
<>	144:ef7eb2e8f9f7	318	#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /!< Internal SPI clock /
<>	144:ef7eb2e8f9f7	319	#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /!< Internal SPI clock divided by 2, falling edge /
<>	144:ef7eb2e8f9f7	320	#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /!< Internal SPI clock divided by 2, rising edge /
<>	144:ef7eb2e8f9f7	321	/**
<>	144:ef7eb2e8f9f7	322	* @}
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
<>	144:ef7eb2e8f9f7	326	* @{
<>	144:ef7eb2e8f9f7	327	*/
<>	144:ef7eb2e8f9f7	328	#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /!< FastSinc filter type /
<>	144:ef7eb2e8f9f7	329	#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /!< Sinc 1 filter type /
<>	144:ef7eb2e8f9f7	330	#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /!< Sinc 2 filter type /
<>	144:ef7eb2e8f9f7	331	#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /!< Sinc 3 filter type /
<>	144:ef7eb2e8f9f7	332	/**
<>	144:ef7eb2e8f9f7	333	* @}
<>	144:ef7eb2e8f9f7	334	*/
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
<>	144:ef7eb2e8f9f7	337	* @{
<>	144:ef7eb2e8f9f7	338	*/
<>	144:ef7eb2e8f9f7	339	#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /!< Software trigger /
<>	144:ef7eb2e8f9f7	340	#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /!< Synchronous with DFSDM_FLT0 /
<>	144:ef7eb2e8f9f7	341	#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /!< External trigger (only for injected conversion) /
<>	144:ef7eb2e8f9f7	342	/**
<>	144:ef7eb2e8f9f7	343	* @}
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
<>	144:ef7eb2e8f9f7	347	* @{
<>	144:ef7eb2e8f9f7	348	*/
AnnaBridge	167:e84263d55307	349	#if defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx)
AnnaBridge	167:e84263d55307	350	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /!< For DFSDM filter 0, 1, 2 and 3 /
AnnaBridge	167:e84263d55307	351	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /!< For DFSDM filter 0, 1, 2 and 3 /
AnnaBridge	167:e84263d55307	352	#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /!< For DFSDM filter 0, 1, 2 and 3 /
AnnaBridge	167:e84263d55307	353	#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1) /!< For DFSDM filter 0, 1 and 2 /
AnnaBridge	167:e84263d55307	354	#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM filter 0 and 1 /
AnnaBridge	167:e84263d55307	355	#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM filter 0, 1, 2 and 3 /
AnnaBridge	167:e84263d55307	356	#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /!< For DFSDM filter 0, 1, 2 and 3 /
AnnaBridge	181:57724642e740	357	#elif defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	181:57724642e740	358	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	359	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	360	#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	361	#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1) /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	362	#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	363	#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	364	#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	365	#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1 \| \
AnnaBridge	181:57724642e740	366	DFSDM_FLTCR1_JEXTSEL_2) /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	367	#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	368	#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 \| DFSDM_FLTCR1_JEXTSEL_4) /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	369	#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_3 \| \
AnnaBridge	181:57724642e740	370	DFSDM_FLTCR1_JEXTSEL_4) /!< For all DFSDM filters /
AnnaBridge	181:57724642e740	371	#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 \| DFSDM_FLTCR1_JEXTSEL_3 \| \
AnnaBridge	181:57724642e740	372	DFSDM_FLTCR1_JEXTSEL_4) /!< For all DFSDM filters /
AnnaBridge	167:e84263d55307	373	#else
<>	144:ef7eb2e8f9f7	374	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /!< For DFSDM filter 0, 1, 2 and 3 /
<>	144:ef7eb2e8f9f7	375	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /!< For DFSDM filter 0, 1, 2 and 3 /
<>	144:ef7eb2e8f9f7	376	#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /!< For DFSDM filter 0, 1, 2 and 3 /
<>	144:ef7eb2e8f9f7	377	#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1) /!< For DFSDM filter 0, 1 and 2 /
<>	144:ef7eb2e8f9f7	378	#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1) /!< For DFSDM filter 3 /
<>	144:ef7eb2e8f9f7	379	#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /!< For DFSDM filter 0, 1 and 2 /
<>	144:ef7eb2e8f9f7	380	#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /!< For DFSDM filter 3 /
<>	144:ef7eb2e8f9f7	381	#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM filter 0 and 1 /
<>	144:ef7eb2e8f9f7	382	#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM filter 2 and 3 /
<>	144:ef7eb2e8f9f7	383	#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM filter 0, 1, 2 and 3 /
<>	144:ef7eb2e8f9f7	384	#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /!< For DFSDM filter 0, 1, 2 and 3 /
AnnaBridge	167:e84263d55307	385	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
<>	144:ef7eb2e8f9f7	386	/**
<>	144:ef7eb2e8f9f7	387	* @}
<>	144:ef7eb2e8f9f7	388	*/
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
<>	144:ef7eb2e8f9f7	391	* @{
<>	144:ef7eb2e8f9f7	392	*/
<>	144:ef7eb2e8f9f7	393	#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /!< External rising edge /
<>	144:ef7eb2e8f9f7	394	#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /!< External falling edge /
<>	144:ef7eb2e8f9f7	395	#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /!< External rising and falling edges /
<>	144:ef7eb2e8f9f7	396	/**
<>	144:ef7eb2e8f9f7	397	* @}
<>	144:ef7eb2e8f9f7	398	*/
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
<>	144:ef7eb2e8f9f7	401	* @{
<>	144:ef7eb2e8f9f7	402	*/
<>	144:ef7eb2e8f9f7	403	#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /!< FastSinc filter type /
<>	144:ef7eb2e8f9f7	404	#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /!< Sinc 1 filter type /
<>	144:ef7eb2e8f9f7	405	#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /!< Sinc 2 filter type /
<>	144:ef7eb2e8f9f7	406	#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 \| DFSDM_FLTFCR_FORD_1) /!< Sinc 3 filter type /
<>	144:ef7eb2e8f9f7	407	#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /!< Sinc 4 filter type /
<>	144:ef7eb2e8f9f7	408	#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 \| DFSDM_FLTFCR_FORD_2) /!< Sinc 5 filter type /
<>	144:ef7eb2e8f9f7	409	/**
<>	144:ef7eb2e8f9f7	410	* @}
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
<>	144:ef7eb2e8f9f7	414	* @{
<>	144:ef7eb2e8f9f7	415	*/
<>	144:ef7eb2e8f9f7	416	#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /!< From digital filter /
<>	144:ef7eb2e8f9f7	417	#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /!< From analog watchdog channel /
<>	144:ef7eb2e8f9f7	418	/**
<>	144:ef7eb2e8f9f7	419	* @}
<>	144:ef7eb2e8f9f7	420	*/
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
<>	144:ef7eb2e8f9f7	423	* @{
<>	144:ef7eb2e8f9f7	424	*/
<>	144:ef7eb2e8f9f7	425	#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
<>	144:ef7eb2e8f9f7	426	#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /!< Overrun occurs during regular conversion /
<>	144:ef7eb2e8f9f7	427	#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /!< Overrun occurs during injected conversion /
<>	144:ef7eb2e8f9f7	428	#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /!< DMA error occurs /
<>	144:ef7eb2e8f9f7	429	/**
<>	144:ef7eb2e8f9f7	430	* @}
<>	144:ef7eb2e8f9f7	431	*/
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	/** @defgroup DFSDM_BreakSignals DFSDM break signals
<>	144:ef7eb2e8f9f7	434	* @{
<>	144:ef7eb2e8f9f7	435	*/
<>	144:ef7eb2e8f9f7	436	#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /!< No break signal /
<>	144:ef7eb2e8f9f7	437	#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /!< Break signal 0 /
<>	144:ef7eb2e8f9f7	438	#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /!< Break signal 1 /
<>	144:ef7eb2e8f9f7	439	#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /!< Break signal 2 /
<>	144:ef7eb2e8f9f7	440	#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /!< Break signal 3 /
<>	144:ef7eb2e8f9f7	441	/**
<>	144:ef7eb2e8f9f7	442	* @}
<>	144:ef7eb2e8f9f7	443	*/
<>	144:ef7eb2e8f9f7	444
<>	144:ef7eb2e8f9f7	445	/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
<>	144:ef7eb2e8f9f7	446	* @{
<>	144:ef7eb2e8f9f7	447	*/
<>	144:ef7eb2e8f9f7	448	/* DFSDM Channels ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	449	/* The DFSDM channels are defined as follows:
<>	144:ef7eb2e8f9f7	450	- in 16-bit LSB the channel mask is set
<>	144:ef7eb2e8f9f7	451	- in 16-bit MSB the channel number is set
<>	144:ef7eb2e8f9f7	452	e.g. for channel 5 definition:
<>	144:ef7eb2e8f9f7	453	- the channel mask is 0x00000020 (bit 5 is set)
<>	144:ef7eb2e8f9f7	454	- the channel number 5 is 0x00050000
<>	144:ef7eb2e8f9f7	455	--> Consequently, channel 5 definition is 0x00000020 \| 0x00050000 = 0x00050020 */
AnnaBridge	167:e84263d55307	456	#if defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx)
AnnaBridge	167:e84263d55307	457	#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
AnnaBridge	167:e84263d55307	458	#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
AnnaBridge	167:e84263d55307	459	#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
AnnaBridge	167:e84263d55307	460	#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
AnnaBridge	181:57724642e740	461	#else
<>	144:ef7eb2e8f9f7	462	#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	463	#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
<>	144:ef7eb2e8f9f7	464	#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
<>	144:ef7eb2e8f9f7	465	#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
<>	144:ef7eb2e8f9f7	466	#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
<>	144:ef7eb2e8f9f7	467	#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
<>	144:ef7eb2e8f9f7	468	#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
<>	144:ef7eb2e8f9f7	469	#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
AnnaBridge	167:e84263d55307	470	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
<>	144:ef7eb2e8f9f7	471	/**
<>	144:ef7eb2e8f9f7	472	* @}
<>	144:ef7eb2e8f9f7	473	*/
<>	144:ef7eb2e8f9f7	474
<>	144:ef7eb2e8f9f7	475	/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
<>	144:ef7eb2e8f9f7	476	* @{
<>	144:ef7eb2e8f9f7	477	*/
<>	144:ef7eb2e8f9f7	478	#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /!< Conversion are not continuous /
<>	144:ef7eb2e8f9f7	479	#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /!< Conversion are continuous /
<>	144:ef7eb2e8f9f7	480	/**
<>	144:ef7eb2e8f9f7	481	* @}
<>	144:ef7eb2e8f9f7	482	*/
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484	/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
<>	144:ef7eb2e8f9f7	485	* @{
<>	144:ef7eb2e8f9f7	486	*/
<>	144:ef7eb2e8f9f7	487	#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /!< Analog watchdog high threshold /
<>	144:ef7eb2e8f9f7	488	#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /!< Analog watchdog low threshold /
<>	144:ef7eb2e8f9f7	489	/**
<>	144:ef7eb2e8f9f7	490	* @}
<>	144:ef7eb2e8f9f7	491	*/
<>	144:ef7eb2e8f9f7	492
<>	144:ef7eb2e8f9f7	493	/**
<>	144:ef7eb2e8f9f7	494	* @}
<>	144:ef7eb2e8f9f7	495	*/
<>	144:ef7eb2e8f9f7	496	/* End of exported constants -------------------------------------------------*/
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/* Exported macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	499	/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
<>	144:ef7eb2e8f9f7	500	* @{
<>	144:ef7eb2e8f9f7	501	*/
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/** @brief Reset DFSDM channel handle state.
AnnaBridge	181:57724642e740	504	* @param __HANDLE__ DFSDM channel handle.
<>	144:ef7eb2e8f9f7	505	* @retval None
<>	144:ef7eb2e8f9f7	506	*/
<>	144:ef7eb2e8f9f7	507	#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
<>	144:ef7eb2e8f9f7	508
<>	144:ef7eb2e8f9f7	509	/** @brief Reset DFSDM filter handle state.
AnnaBridge	181:57724642e740	510	* @param __HANDLE__ DFSDM filter handle.
<>	144:ef7eb2e8f9f7	511	* @retval None
<>	144:ef7eb2e8f9f7	512	*/
<>	144:ef7eb2e8f9f7	513	#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
<>	144:ef7eb2e8f9f7	514
<>	144:ef7eb2e8f9f7	515	/**
<>	144:ef7eb2e8f9f7	516	* @}
<>	144:ef7eb2e8f9f7	517	*/
<>	144:ef7eb2e8f9f7	518	/* End of exported macros ----------------------------------------------------*/
<>	144:ef7eb2e8f9f7	519
AnnaBridge	181:57724642e740	520	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	181:57724642e740	521	/* Include DFSDM HAL Extension module */
AnnaBridge	181:57724642e740	522	#include "stm32l4xx_hal_dfsdm_ex.h"
AnnaBridge	181:57724642e740	523	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	181:57724642e740	524
<>	144:ef7eb2e8f9f7	525	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	526	/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
<>	144:ef7eb2e8f9f7	527	* @{
<>	144:ef7eb2e8f9f7	528	*/
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	531	* @{
<>	144:ef7eb2e8f9f7	532	*/
<>	144:ef7eb2e8f9f7	533	/* Channel initialization and de-initialization functions *********************/
<>	144:ef7eb2e8f9f7	534	HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	535	HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	536	void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	537	void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	538	/**
<>	144:ef7eb2e8f9f7	539	* @}
<>	144:ef7eb2e8f9f7	540	*/
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
<>	144:ef7eb2e8f9f7	543	* @{
<>	144:ef7eb2e8f9f7	544	*/
<>	144:ef7eb2e8f9f7	545	/* Channel operation functions ************************************************/
<>	144:ef7eb2e8f9f7	546	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	547	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	548	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	549	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
<>	144:ef7eb2e8f9f7	552	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
<>	144:ef7eb2e8f9f7	553	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	554	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	555
<>	144:ef7eb2e8f9f7	556	int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	557	HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
<>	144:ef7eb2e8f9f7	558
<>	144:ef7eb2e8f9f7	559	HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	560	HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	563	void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	564	/**
<>	144:ef7eb2e8f9f7	565	* @}
<>	144:ef7eb2e8f9f7	566	*/
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
<>	144:ef7eb2e8f9f7	569	* @{
<>	144:ef7eb2e8f9f7	570	*/
<>	144:ef7eb2e8f9f7	571	/* Channel state function *****************************************************/
<>	144:ef7eb2e8f9f7	572	HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<>	144:ef7eb2e8f9f7	573	/**
<>	144:ef7eb2e8f9f7	574	* @}
<>	144:ef7eb2e8f9f7	575	*/
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	578	* @{
<>	144:ef7eb2e8f9f7	579	*/
<>	144:ef7eb2e8f9f7	580	/* Filter initialization and de-initialization functions *********************/
<>	144:ef7eb2e8f9f7	581	HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	582	HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	583	void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	584	void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	585	/**
<>	144:ef7eb2e8f9f7	586	* @}
<>	144:ef7eb2e8f9f7	587	*/
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
<>	144:ef7eb2e8f9f7	590	* @{
<>	144:ef7eb2e8f9f7	591	*/
<>	144:ef7eb2e8f9f7	592	/* Filter control functions *********************/
<>	144:ef7eb2e8f9f7	593	HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<>	144:ef7eb2e8f9f7	594	uint32_t Channel,
<>	144:ef7eb2e8f9f7	595	uint32_t ContinuousMode);
<>	144:ef7eb2e8f9f7	596	HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<>	144:ef7eb2e8f9f7	597	uint32_t Channel);
<>	144:ef7eb2e8f9f7	598	/**
<>	144:ef7eb2e8f9f7	599	* @}
<>	144:ef7eb2e8f9f7	600	*/
<>	144:ef7eb2e8f9f7	601
<>	144:ef7eb2e8f9f7	602	/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
<>	144:ef7eb2e8f9f7	603	* @{
<>	144:ef7eb2e8f9f7	604	*/
<>	144:ef7eb2e8f9f7	605	/* Filter operation functions *********************/
<>	144:ef7eb2e8f9f7	606	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	607	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	608	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int32_t pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	609	HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int16_t pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	610	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	611	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	612	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	613	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	614	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	615	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int32_t pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	616	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int16_t pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	617	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	618	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	619	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	620	HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<>	144:ef7eb2e8f9f7	621	DFSDM_Filter_AwdParamTypeDef* awdParam);
<>	144:ef7eb2e8f9f7	622	HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	623	HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
<>	144:ef7eb2e8f9f7	624	HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
<>	144:ef7eb2e8f9f7	627	int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
<>	144:ef7eb2e8f9f7	628	int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
<>	144:ef7eb2e8f9f7	629	int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
<>	144:ef7eb2e8f9f7	630	uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	635	HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	636
<>	144:ef7eb2e8f9f7	637	void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	638	void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	639	void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	640	void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	641	void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
<>	144:ef7eb2e8f9f7	642	void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	643	/**
<>	144:ef7eb2e8f9f7	644	* @}
<>	144:ef7eb2e8f9f7	645	*/
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
<>	144:ef7eb2e8f9f7	648	* @{
<>	144:ef7eb2e8f9f7	649	*/
<>	144:ef7eb2e8f9f7	650	/* Filter state functions *****************************************************/
<>	144:ef7eb2e8f9f7	651	HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	652	uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<>	144:ef7eb2e8f9f7	653	/**
<>	144:ef7eb2e8f9f7	654	* @}
<>	144:ef7eb2e8f9f7	655	*/
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657	/**
<>	144:ef7eb2e8f9f7	658	* @}
<>	144:ef7eb2e8f9f7	659	*/
<>	144:ef7eb2e8f9f7	660	/* End of exported functions -------------------------------------------------*/
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	663	/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
<>	144:ef7eb2e8f9f7	664	* @{
<>	144:ef7eb2e8f9f7	665	*/
<>	144:ef7eb2e8f9f7	666	#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) \|\| \
<>	144:ef7eb2e8f9f7	667	((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
<>	144:ef7eb2e8f9f7	668	#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
AnnaBridge	167:e84263d55307	669	#if defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	181:57724642e740	670	defined(STM32L496xx) \|\| defined(STM32L4A6xx) \|\| \
AnnaBridge	181:57724642e740	671	defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	167:e84263d55307	672	#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) \|\| \
AnnaBridge	167:e84263d55307	673	((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) \|\| \
AnnaBridge	167:e84263d55307	674	((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
AnnaBridge	167:e84263d55307	675	#else
<>	144:ef7eb2e8f9f7	676	#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) \|\| \
<>	144:ef7eb2e8f9f7	677	((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
AnnaBridge	181:57724642e740	678	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx \|\| */
AnnaBridge	181:57724642e740	679	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	181:57724642e740	680	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
<>	144:ef7eb2e8f9f7	681	#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) \|\| \
<>	144:ef7eb2e8f9f7	682	((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) \|\| \
<>	144:ef7eb2e8f9f7	683	((MODE) == DFSDM_CHANNEL_DUAL_MODE))
<>	144:ef7eb2e8f9f7	684	#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) \|\| \
<>	144:ef7eb2e8f9f7	685	((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
<>	144:ef7eb2e8f9f7	686	#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) \|\| \
<>	144:ef7eb2e8f9f7	687	((MODE) == DFSDM_CHANNEL_SPI_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	688	((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) \|\| \
<>	144:ef7eb2e8f9f7	689	((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
<>	144:ef7eb2e8f9f7	690	#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) \|\| \
<>	144:ef7eb2e8f9f7	691	((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) \|\| \
<>	144:ef7eb2e8f9f7	692	((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	693	((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
<>	144:ef7eb2e8f9f7	694	#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	695	((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	696	((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	697	((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
<>	144:ef7eb2e8f9f7	698	#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
<>	144:ef7eb2e8f9f7	699	#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
<>	144:ef7eb2e8f9f7	700	#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
<>	144:ef7eb2e8f9f7	701	#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
<>	144:ef7eb2e8f9f7	702	#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	703	((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
<>	144:ef7eb2e8f9f7	704	#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	705	((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	706	((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
AnnaBridge	167:e84263d55307	707	#if defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx)
AnnaBridge	167:e84263d55307	708	#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) \|\| \
AnnaBridge	167:e84263d55307	709	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) \|\| \
AnnaBridge	167:e84263d55307	710	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) \|\| \
AnnaBridge	167:e84263d55307	711	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) \|\| \
AnnaBridge	167:e84263d55307	712	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) \|\| \
AnnaBridge	167:e84263d55307	713	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) \|\| \
AnnaBridge	167:e84263d55307	714	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
AnnaBridge	181:57724642e740	715	#elif defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	181:57724642e740	716	#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) \|\| \
AnnaBridge	181:57724642e740	717	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) \|\| \
AnnaBridge	181:57724642e740	718	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) \|\| \
AnnaBridge	181:57724642e740	719	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) \|\| \
AnnaBridge	181:57724642e740	720	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) \|\| \
AnnaBridge	181:57724642e740	721	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) \|\| \
AnnaBridge	181:57724642e740	722	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) \|\| \
AnnaBridge	181:57724642e740	723	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) \|\| \
AnnaBridge	181:57724642e740	724	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) \|\| \
AnnaBridge	181:57724642e740	725	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) \|\| \
AnnaBridge	181:57724642e740	726	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) \|\| \
AnnaBridge	181:57724642e740	727	((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
AnnaBridge	167:e84263d55307	728	#else
<>	144:ef7eb2e8f9f7	729	#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	730	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	731	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	732	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	733	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	734	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	735	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) \|\| \
<>	144:ef7eb2e8f9f7	736	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	737	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	738	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) \|\| \
<>	144:ef7eb2e8f9f7	739	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
AnnaBridge	167:e84263d55307	740	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
<>	144:ef7eb2e8f9f7	741	#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) \|\| \
<>	144:ef7eb2e8f9f7	742	((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) \|\| \
<>	144:ef7eb2e8f9f7	743	((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
<>	144:ef7eb2e8f9f7	744	#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	745	((ORDER) == DFSDM_FILTER_SINC1_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	746	((ORDER) == DFSDM_FILTER_SINC2_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	747	((ORDER) == DFSDM_FILTER_SINC3_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	748	((ORDER) == DFSDM_FILTER_SINC4_ORDER) \|\| \
<>	144:ef7eb2e8f9f7	749	((ORDER) == DFSDM_FILTER_SINC5_ORDER))
<>	144:ef7eb2e8f9f7	750	#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
<>	144:ef7eb2e8f9f7	751	#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
<>	144:ef7eb2e8f9f7	752	#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) \|\| \
<>	144:ef7eb2e8f9f7	753	((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
<>	144:ef7eb2e8f9f7	754	#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
<>	144:ef7eb2e8f9f7	755	#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
AnnaBridge	167:e84263d55307	756	#if defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx)
AnnaBridge	167:e84263d55307	757	#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) \|\| \
AnnaBridge	167:e84263d55307	758	((CHANNEL) == DFSDM_CHANNEL_1) \|\| \
AnnaBridge	167:e84263d55307	759	((CHANNEL) == DFSDM_CHANNEL_2) \|\| \
AnnaBridge	167:e84263d55307	760	((CHANNEL) == DFSDM_CHANNEL_3))
AnnaBridge	167:e84263d55307	761	#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU))
AnnaBridge	181:57724642e740	762	#else
<>	144:ef7eb2e8f9f7	763	#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) \|\| \
<>	144:ef7eb2e8f9f7	764	((CHANNEL) == DFSDM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	765	((CHANNEL) == DFSDM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	766	((CHANNEL) == DFSDM_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	767	((CHANNEL) == DFSDM_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	768	((CHANNEL) == DFSDM_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	769	((CHANNEL) == DFSDM_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	770	((CHANNEL) == DFSDM_CHANNEL_7))
<>	144:ef7eb2e8f9f7	771	#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
AnnaBridge	167:e84263d55307	772	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
<>	144:ef7eb2e8f9f7	773	#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) \|\| \
<>	144:ef7eb2e8f9f7	774	((MODE) == DFSDM_CONTINUOUS_CONV_ON))
<>	144:ef7eb2e8f9f7	775	/**
<>	144:ef7eb2e8f9f7	776	* @}
<>	144:ef7eb2e8f9f7	777	*/
<>	144:ef7eb2e8f9f7	778	/* End of private macros -----------------------------------------------------*/
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/**
<>	144:ef7eb2e8f9f7	781	* @}
<>	144:ef7eb2e8f9f7	782	*/
<>	144:ef7eb2e8f9f7	783
<>	144:ef7eb2e8f9f7	784	/**
<>	144:ef7eb2e8f9f7	785	* @}
<>	144:ef7eb2e8f9f7	786	*/
AnnaBridge	181:57724642e740	787	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx \|\| */
AnnaBridge	181:57724642e740	788	/* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	181:57724642e740	789	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	181:57724642e740	790	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	181:57724642e740	791
<>	144:ef7eb2e8f9f7	792	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	793	}
<>	144:ef7eb2e8f9f7	794	#endif
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	#endif /* __STM32L4xx_HAL_DFSDM_H */
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/