mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 176:447f873cad2f 1 /* mbed Microcontroller Library
AnnaBridge 176:447f873cad2f 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 176:447f873cad2f 3 *
AnnaBridge 176:447f873cad2f 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 176:447f873cad2f 5 * you may not use this file except in compliance with the License.
AnnaBridge 176:447f873cad2f 6 * You may obtain a copy of the License at
AnnaBridge 176:447f873cad2f 7 *
AnnaBridge 176:447f873cad2f 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 176:447f873cad2f 9 *
AnnaBridge 176:447f873cad2f 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 176:447f873cad2f 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 176:447f873cad2f 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 176:447f873cad2f 13 * See the License for the specific language governing permissions and
AnnaBridge 176:447f873cad2f 14 * limitations under the License.
AnnaBridge 176:447f873cad2f 15 */
AnnaBridge 176:447f873cad2f 16
AnnaBridge 176:447f873cad2f 17 /**
AnnaBridge 176:447f873cad2f 18 * This file configures the system clock as follows:
AnnaBridge 176:447f873cad2f 19 *-----------------------------------------------------------------------------
AnnaBridge 176:447f873cad2f 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
AnnaBridge 176:447f873cad2f 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
AnnaBridge 176:447f873cad2f 22 * | 3- USE_PLL_HSI (internal 16 MHz)
AnnaBridge 176:447f873cad2f 23 * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
AnnaBridge 176:447f873cad2f 24 *-----------------------------------------------------------------------------
AnnaBridge 176:447f873cad2f 25 * SYSCLK(MHz) | 80
AnnaBridge 176:447f873cad2f 26 * AHBCLK (MHz) | 80
AnnaBridge 176:447f873cad2f 27 * APB1CLK (MHz) | 80
AnnaBridge 176:447f873cad2f 28 * APB2CLK (MHz) | 80
AnnaBridge 176:447f873cad2f 29 * USB capable | YES
AnnaBridge 176:447f873cad2f 30 *-----------------------------------------------------------------------------
AnnaBridge 176:447f873cad2f 31 **/
AnnaBridge 176:447f873cad2f 32
AnnaBridge 176:447f873cad2f 33 #include "stm32l4xx.h"
AnnaBridge 176:447f873cad2f 34 #include "nvic_addr.h"
AnnaBridge 187:0387e8f68319 35 #include "mbed_error.h"
AnnaBridge 176:447f873cad2f 36
AnnaBridge 176:447f873cad2f 37 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 176:447f873cad2f 38 Internal SRAM. */
AnnaBridge 176:447f873cad2f 39 /* #define VECT_TAB_SRAM */
AnnaBridge 176:447f873cad2f 40 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
AnnaBridge 176:447f873cad2f 41 This value must be a multiple of 0x200. */
AnnaBridge 176:447f873cad2f 42
AnnaBridge 176:447f873cad2f 43
AnnaBridge 176:447f873cad2f 44 // clock source is selected with CLOCK_SOURCE in json config
AnnaBridge 176:447f873cad2f 45 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
AnnaBridge 176:447f873cad2f 46 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
AnnaBridge 176:447f873cad2f 47 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 176:447f873cad2f 48 #define USE_PLL_MSI 0x1 // Use MSI internal clock
AnnaBridge 176:447f873cad2f 49
AnnaBridge 176:447f873cad2f 50 #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
AnnaBridge 176:447f873cad2f 51
AnnaBridge 176:447f873cad2f 52 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 176:447f873cad2f 53 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 176:447f873cad2f 54 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 176:447f873cad2f 55
AnnaBridge 176:447f873cad2f 56 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 176:447f873cad2f 57 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 176:447f873cad2f 58 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 176:447f873cad2f 59
AnnaBridge 176:447f873cad2f 60 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
AnnaBridge 176:447f873cad2f 61 uint8_t SetSysClock_PLL_MSI(void);
AnnaBridge 176:447f873cad2f 62 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
AnnaBridge 176:447f873cad2f 63
AnnaBridge 176:447f873cad2f 64
AnnaBridge 176:447f873cad2f 65 /**
AnnaBridge 176:447f873cad2f 66 * @brief Setup the microcontroller system.
AnnaBridge 176:447f873cad2f 67 * @param None
AnnaBridge 176:447f873cad2f 68 * @retval None
AnnaBridge 176:447f873cad2f 69 */
AnnaBridge 176:447f873cad2f 70
AnnaBridge 176:447f873cad2f 71 void SystemInit(void)
AnnaBridge 176:447f873cad2f 72 {
AnnaBridge 176:447f873cad2f 73 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 176:447f873cad2f 74 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 75 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
AnnaBridge 176:447f873cad2f 76 #endif
AnnaBridge 176:447f873cad2f 77 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 176:447f873cad2f 78 /* Set MSION bit */
AnnaBridge 176:447f873cad2f 79 RCC->CR |= RCC_CR_MSION;
AnnaBridge 176:447f873cad2f 80
AnnaBridge 176:447f873cad2f 81 /* Reset CFGR register */
AnnaBridge 176:447f873cad2f 82 RCC->CFGR = 0x00000000;
AnnaBridge 176:447f873cad2f 83
AnnaBridge 176:447f873cad2f 84 /* Reset HSEON, CSSON , HSION, and PLLON bits */
AnnaBridge 176:447f873cad2f 85 RCC->CR &= (uint32_t)0xEAF6FFFF;
AnnaBridge 176:447f873cad2f 86
AnnaBridge 176:447f873cad2f 87 /* Reset PLLCFGR register */
AnnaBridge 176:447f873cad2f 88 RCC->PLLCFGR = 0x00001000;
AnnaBridge 176:447f873cad2f 89
AnnaBridge 176:447f873cad2f 90 /* Reset HSEBYP bit */
AnnaBridge 176:447f873cad2f 91 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 176:447f873cad2f 92
AnnaBridge 176:447f873cad2f 93 /* Disable all interrupts */
AnnaBridge 176:447f873cad2f 94 RCC->CIER = 0x00000000;
AnnaBridge 176:447f873cad2f 95
AnnaBridge 176:447f873cad2f 96 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 176:447f873cad2f 97 #ifdef VECT_TAB_SRAM
AnnaBridge 176:447f873cad2f 98 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 176:447f873cad2f 99 #else
AnnaBridge 176:447f873cad2f 100 SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 176:447f873cad2f 101 #endif
AnnaBridge 176:447f873cad2f 102
AnnaBridge 176:447f873cad2f 103 }
AnnaBridge 176:447f873cad2f 104
AnnaBridge 176:447f873cad2f 105
AnnaBridge 176:447f873cad2f 106 /**
AnnaBridge 176:447f873cad2f 107 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 176:447f873cad2f 108 * AHB/APBx prescalers and Flash settings
AnnaBridge 176:447f873cad2f 109 * @note This function should be called only once the RCC clock configuration
AnnaBridge 176:447f873cad2f 110 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 176:447f873cad2f 111 * @param None
AnnaBridge 176:447f873cad2f 112 * @retval None
AnnaBridge 176:447f873cad2f 113 */
AnnaBridge 176:447f873cad2f 114
AnnaBridge 176:447f873cad2f 115 void SetSysClock(void)
AnnaBridge 176:447f873cad2f 116 {
AnnaBridge 176:447f873cad2f 117 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 176:447f873cad2f 118 /* 1- Try to start with HSE and external clock */
AnnaBridge 176:447f873cad2f 119 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 176:447f873cad2f 120 #endif
AnnaBridge 176:447f873cad2f 121 {
AnnaBridge 176:447f873cad2f 122 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 176:447f873cad2f 123 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 176:447f873cad2f 124 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 176:447f873cad2f 125 #endif
AnnaBridge 176:447f873cad2f 126 {
AnnaBridge 176:447f873cad2f 127 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 176:447f873cad2f 128 /* 3- If fail start with HSI clock */
AnnaBridge 187:0387e8f68319 129 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 176:447f873cad2f 130 #endif
AnnaBridge 176:447f873cad2f 131 {
AnnaBridge 176:447f873cad2f 132 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
AnnaBridge 176:447f873cad2f 133 /* 4- If fail start with MSI clock */
AnnaBridge 176:447f873cad2f 134 if (SetSysClock_PLL_MSI() == 0)
AnnaBridge 176:447f873cad2f 135 #endif
AnnaBridge 176:447f873cad2f 136 {
AnnaBridge 187:0387e8f68319 137 {
AnnaBridge 187:0387e8f68319 138 error("SetSysClock failed\n");
AnnaBridge 176:447f873cad2f 139 }
AnnaBridge 176:447f873cad2f 140 }
AnnaBridge 176:447f873cad2f 141 }
AnnaBridge 176:447f873cad2f 142 }
AnnaBridge 176:447f873cad2f 143 }
AnnaBridge 176:447f873cad2f 144
AnnaBridge 176:447f873cad2f 145 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 176:447f873cad2f 146 #if DEBUG_MCO == 1
AnnaBridge 176:447f873cad2f 147 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
AnnaBridge 176:447f873cad2f 148 #endif
AnnaBridge 176:447f873cad2f 149 }
AnnaBridge 176:447f873cad2f 150
AnnaBridge 176:447f873cad2f 151 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 176:447f873cad2f 152 /******************************************************************************/
AnnaBridge 176:447f873cad2f 153 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 176:447f873cad2f 154 /******************************************************************************/
AnnaBridge 176:447f873cad2f 155 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 176:447f873cad2f 156 {
AnnaBridge 176:447f873cad2f 157 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
AnnaBridge 176:447f873cad2f 158 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
AnnaBridge 176:447f873cad2f 159 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
AnnaBridge 176:447f873cad2f 160
AnnaBridge 176:447f873cad2f 161 // Used to gain time after DeepSleep in case HSI is used
AnnaBridge 176:447f873cad2f 162 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
AnnaBridge 176:447f873cad2f 163 return 0;
AnnaBridge 176:447f873cad2f 164 }
AnnaBridge 176:447f873cad2f 165
AnnaBridge 176:447f873cad2f 166 // Select MSI as system clock source to allow modification of the PLL configuration
AnnaBridge 176:447f873cad2f 167 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
AnnaBridge 176:447f873cad2f 168 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
AnnaBridge 176:447f873cad2f 169 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
AnnaBridge 176:447f873cad2f 170
AnnaBridge 176:447f873cad2f 171 // Enable HSE oscillator and activate PLL with HSE as source
AnnaBridge 176:447f873cad2f 172 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
AnnaBridge 176:447f873cad2f 173 if (bypass == 0) {
AnnaBridge 176:447f873cad2f 174 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
AnnaBridge 176:447f873cad2f 175 } else {
AnnaBridge 176:447f873cad2f 176 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
AnnaBridge 176:447f873cad2f 177 }
AnnaBridge 176:447f873cad2f 178 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
AnnaBridge 176:447f873cad2f 179 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
AnnaBridge 176:447f873cad2f 180 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 176:447f873cad2f 181 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
AnnaBridge 176:447f873cad2f 182 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
AnnaBridge 176:447f873cad2f 183 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
AnnaBridge 176:447f873cad2f 184 RCC_OscInitStruct.PLL.PLLQ = 2;
AnnaBridge 176:447f873cad2f 185 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
AnnaBridge 176:447f873cad2f 186
AnnaBridge 176:447f873cad2f 187 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 176:447f873cad2f 188 return 0; // FAIL
AnnaBridge 176:447f873cad2f 189 }
AnnaBridge 176:447f873cad2f 190
AnnaBridge 176:447f873cad2f 191 // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 176:447f873cad2f 192 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 176:447f873cad2f 193 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
AnnaBridge 176:447f873cad2f 194 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
AnnaBridge 176:447f873cad2f 195 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
AnnaBridge 176:447f873cad2f 196 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
AnnaBridge 176:447f873cad2f 197 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
AnnaBridge 176:447f873cad2f 198 return 0; // FAIL
AnnaBridge 176:447f873cad2f 199 }
AnnaBridge 176:447f873cad2f 200
AnnaBridge 176:447f873cad2f 201 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 176:447f873cad2f 202 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
AnnaBridge 176:447f873cad2f 203 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
AnnaBridge 176:447f873cad2f 204 RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
AnnaBridge 176:447f873cad2f 205 RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
AnnaBridge 176:447f873cad2f 206 RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
AnnaBridge 176:447f873cad2f 207 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
AnnaBridge 176:447f873cad2f 208 RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
AnnaBridge 176:447f873cad2f 209 RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
AnnaBridge 176:447f873cad2f 210 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
AnnaBridge 176:447f873cad2f 211 return 0; // FAIL
AnnaBridge 176:447f873cad2f 212 }
AnnaBridge 176:447f873cad2f 213
AnnaBridge 176:447f873cad2f 214 // Disable MSI Oscillator
AnnaBridge 176:447f873cad2f 215 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
AnnaBridge 176:447f873cad2f 216 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
AnnaBridge 176:447f873cad2f 217 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
AnnaBridge 176:447f873cad2f 218 HAL_RCC_OscConfig(&RCC_OscInitStruct);
AnnaBridge 176:447f873cad2f 219
AnnaBridge 176:447f873cad2f 220 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 176:447f873cad2f 221 #if DEBUG_MCO == 2
AnnaBridge 187:0387e8f68319 222 if (bypass == 0) {
AnnaBridge 187:0387e8f68319 223 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
AnnaBridge 187:0387e8f68319 224 } else {
AnnaBridge 187:0387e8f68319 225 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
AnnaBridge 187:0387e8f68319 226 }
AnnaBridge 176:447f873cad2f 227 #endif
AnnaBridge 176:447f873cad2f 228
AnnaBridge 176:447f873cad2f 229 return 1; // OK
AnnaBridge 176:447f873cad2f 230 }
AnnaBridge 176:447f873cad2f 231 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 176:447f873cad2f 232
AnnaBridge 176:447f873cad2f 233 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 176:447f873cad2f 234 /******************************************************************************/
AnnaBridge 176:447f873cad2f 235 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 176:447f873cad2f 236 /******************************************************************************/
AnnaBridge 176:447f873cad2f 237 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 176:447f873cad2f 238 {
AnnaBridge 176:447f873cad2f 239 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
AnnaBridge 176:447f873cad2f 240 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
AnnaBridge 176:447f873cad2f 241 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
AnnaBridge 176:447f873cad2f 242
AnnaBridge 176:447f873cad2f 243 // Select MSI as system clock source to allow modification of the PLL configuration
AnnaBridge 176:447f873cad2f 244 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
AnnaBridge 176:447f873cad2f 245 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
AnnaBridge 176:447f873cad2f 246 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
AnnaBridge 176:447f873cad2f 247
AnnaBridge 176:447f873cad2f 248 // Enable HSI oscillator and activate PLL with HSI as source
AnnaBridge 176:447f873cad2f 249 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 176:447f873cad2f 250 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 176:447f873cad2f 251 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 176:447f873cad2f 252 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 176:447f873cad2f 253 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 176:447f873cad2f 254 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
AnnaBridge 176:447f873cad2f 255 RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
AnnaBridge 176:447f873cad2f 256 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
AnnaBridge 176:447f873cad2f 257 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
AnnaBridge 176:447f873cad2f 258 RCC_OscInitStruct.PLL.PLLQ = 2;
AnnaBridge 176:447f873cad2f 259 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
AnnaBridge 176:447f873cad2f 260 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 176:447f873cad2f 261 return 0; // FAIL
AnnaBridge 176:447f873cad2f 262 }
AnnaBridge 176:447f873cad2f 263
AnnaBridge 176:447f873cad2f 264 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 176:447f873cad2f 265 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 176:447f873cad2f 266 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
AnnaBridge 176:447f873cad2f 267 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
AnnaBridge 176:447f873cad2f 268 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
AnnaBridge 176:447f873cad2f 269 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
AnnaBridge 176:447f873cad2f 270 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
AnnaBridge 176:447f873cad2f 271 return 0; // FAIL
AnnaBridge 176:447f873cad2f 272 }
AnnaBridge 176:447f873cad2f 273
AnnaBridge 176:447f873cad2f 274 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 176:447f873cad2f 275 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
AnnaBridge 176:447f873cad2f 276 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
AnnaBridge 176:447f873cad2f 277 RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
AnnaBridge 176:447f873cad2f 278 RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
AnnaBridge 176:447f873cad2f 279 RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
AnnaBridge 176:447f873cad2f 280 RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
AnnaBridge 176:447f873cad2f 281 RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
AnnaBridge 176:447f873cad2f 282 RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
AnnaBridge 176:447f873cad2f 283 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
AnnaBridge 176:447f873cad2f 284 return 0; // FAIL
AnnaBridge 176:447f873cad2f 285 }
AnnaBridge 176:447f873cad2f 286
AnnaBridge 176:447f873cad2f 287 // Disable MSI Oscillator
AnnaBridge 176:447f873cad2f 288 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
AnnaBridge 176:447f873cad2f 289 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
AnnaBridge 176:447f873cad2f 290 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
AnnaBridge 176:447f873cad2f 291 HAL_RCC_OscConfig(&RCC_OscInitStruct);
AnnaBridge 176:447f873cad2f 292
AnnaBridge 176:447f873cad2f 293 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 176:447f873cad2f 294 #if DEBUG_MCO == 3
AnnaBridge 176:447f873cad2f 295 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 176:447f873cad2f 296 #endif
AnnaBridge 176:447f873cad2f 297
AnnaBridge 176:447f873cad2f 298 return 1; // OK
AnnaBridge 176:447f873cad2f 299 }
AnnaBridge 176:447f873cad2f 300 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 176:447f873cad2f 301
AnnaBridge 176:447f873cad2f 302 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
AnnaBridge 176:447f873cad2f 303 /******************************************************************************/
AnnaBridge 176:447f873cad2f 304 /* PLL (clocked by MSI) used as System clock source */
AnnaBridge 176:447f873cad2f 305 /******************************************************************************/
AnnaBridge 176:447f873cad2f 306 uint8_t SetSysClock_PLL_MSI(void)
AnnaBridge 176:447f873cad2f 307 {
AnnaBridge 176:447f873cad2f 308 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
AnnaBridge 176:447f873cad2f 309 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
AnnaBridge 176:447f873cad2f 310 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
AnnaBridge 176:447f873cad2f 311
AnnaBridge 188:bcfe06ba3d64 312 #if MBED_CONF_TARGET_LSE_AVAILABLE
AnnaBridge 176:447f873cad2f 313 // Enable LSE Oscillator to automatically calibrate the MSI clock
AnnaBridge 176:447f873cad2f 314 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
AnnaBridge 176:447f873cad2f 315 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
AnnaBridge 176:447f873cad2f 316 RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
AnnaBridge 188:bcfe06ba3d64 317 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 188:bcfe06ba3d64 318 return 0; // FAIL
AnnaBridge 176:447f873cad2f 319 }
AnnaBridge 176:447f873cad2f 320
AnnaBridge 188:bcfe06ba3d64 321 /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
AnnaBridge 176:447f873cad2f 322 HAL_RCCEx_DisableLSECSS();
AnnaBridge 188:bcfe06ba3d64 323 #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
AnnaBridge 188:bcfe06ba3d64 324
AnnaBridge 176:447f873cad2f 325 /* Enable MSI Oscillator and activate PLL with MSI as source */
AnnaBridge 176:447f873cad2f 326 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 176:447f873cad2f 327 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
AnnaBridge 176:447f873cad2f 328 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 176:447f873cad2f 329 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
AnnaBridge 176:447f873cad2f 330
AnnaBridge 176:447f873cad2f 331 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
AnnaBridge 176:447f873cad2f 332 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
AnnaBridge 176:447f873cad2f 333 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 176:447f873cad2f 334 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
AnnaBridge 176:447f873cad2f 335 RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
AnnaBridge 176:447f873cad2f 336 RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
AnnaBridge 176:447f873cad2f 337 RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
AnnaBridge 176:447f873cad2f 338 RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
AnnaBridge 176:447f873cad2f 339 RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
AnnaBridge 176:447f873cad2f 340 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 176:447f873cad2f 341 return 0; // FAIL
AnnaBridge 176:447f873cad2f 342 }
AnnaBridge 188:bcfe06ba3d64 343
AnnaBridge 188:bcfe06ba3d64 344 #if MBED_CONF_TARGET_LSE_AVAILABLE
AnnaBridge 176:447f873cad2f 345 /* Enable MSI Auto-calibration through LSE */
AnnaBridge 176:447f873cad2f 346 HAL_RCCEx_EnableMSIPLLMode();
AnnaBridge 188:bcfe06ba3d64 347 #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
AnnaBridge 188:bcfe06ba3d64 348
AnnaBridge 176:447f873cad2f 349 /* Select MSI output as USB clock source */
AnnaBridge 176:447f873cad2f 350 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 176:447f873cad2f 351 PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
AnnaBridge 176:447f873cad2f 352 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 176:447f873cad2f 353 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 176:447f873cad2f 354 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 176:447f873cad2f 355 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
AnnaBridge 176:447f873cad2f 356 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
AnnaBridge 176:447f873cad2f 357 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
AnnaBridge 176:447f873cad2f 358 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
AnnaBridge 176:447f873cad2f 359 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
AnnaBridge 176:447f873cad2f 360 return 0; // FAIL
AnnaBridge 176:447f873cad2f 361 }
AnnaBridge 176:447f873cad2f 362
AnnaBridge 176:447f873cad2f 363 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 176:447f873cad2f 364 #if DEBUG_MCO == 4
AnnaBridge 176:447f873cad2f 365 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
AnnaBridge 176:447f873cad2f 366 #endif
AnnaBridge 176:447f873cad2f 367
AnnaBridge 176:447f873cad2f 368 return 1; // OK
AnnaBridge 176:447f873cad2f 369 }
AnnaBridge 176:447f873cad2f 370 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */