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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_nor.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_nor.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief NOR HAL module driver.
<> 149:156823d33999 6 * This file provides a generic firmware to drive NOR memories mounted
<> 149:156823d33999 7 * as external device.
<> 149:156823d33999 8 *
<> 149:156823d33999 9 @verbatim
<> 149:156823d33999 10 ==============================================================================
<> 149:156823d33999 11 ##### How to use this driver #####
<> 149:156823d33999 12 ==============================================================================
<> 149:156823d33999 13 [..]
<> 149:156823d33999 14 This driver is a generic layered driver which contains a set of APIs used to
<> 149:156823d33999 15 control NOR flash memories. It uses the FSMC layer functions to interface
<> 149:156823d33999 16 with NOR devices. This driver is used as follows:
<> 149:156823d33999 17
<> 149:156823d33999 18 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
<> 149:156823d33999 19 with control and timing parameters for both normal and extended mode.
<> 149:156823d33999 20
<> 149:156823d33999 21 (+) Read NOR flash memory manufacturer code and device IDs using the function
<> 149:156823d33999 22 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
<> 149:156823d33999 23 structure declared by the function caller.
<> 149:156823d33999 24
<> 149:156823d33999 25 (+) Access NOR flash memory by read/write data unit operations using the functions
<> 149:156823d33999 26 HAL_NOR_Read(), HAL_NOR_Program().
<> 149:156823d33999 27
<> 149:156823d33999 28 (+) Perform NOR flash erase block/chip operations using the functions
<> 149:156823d33999 29 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
<> 149:156823d33999 30
<> 149:156823d33999 31 (+) Read the NOR flash CFI (common flash interface) IDs using the function
<> 149:156823d33999 32 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
<> 149:156823d33999 33 structure declared by the function caller.
<> 149:156823d33999 34
<> 149:156823d33999 35 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
<> 149:156823d33999 36 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
<> 149:156823d33999 37
<> 149:156823d33999 38 (+) You can monitor the NOR device HAL state by calling the function
<> 149:156823d33999 39 HAL_NOR_GetState()
<> 149:156823d33999 40 [..]
<> 149:156823d33999 41 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
<> 149:156823d33999 42 If a NOR flash device contains different operations and/or implementations,
<> 149:156823d33999 43 it should be implemented separately.
<> 149:156823d33999 44
<> 149:156823d33999 45 *** NOR HAL driver macros list ***
<> 149:156823d33999 46 =============================================
<> 149:156823d33999 47 [..]
<> 149:156823d33999 48 Below the list of most used macros in NOR HAL driver.
<> 149:156823d33999 49
<> 149:156823d33999 50 (+) NOR_WRITE : NOR memory write data to specified address
<> 149:156823d33999 51
<> 149:156823d33999 52 @endverbatim
<> 149:156823d33999 53 ******************************************************************************
<> 149:156823d33999 54 * @attention
<> 149:156823d33999 55 *
AnnaBridge 184:08ed48f1de7f 56 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 57 *
<> 149:156823d33999 58 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 59 * are permitted provided that the following conditions are met:
<> 149:156823d33999 60 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 61 * this list of conditions and the following disclaimer.
<> 149:156823d33999 62 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 63 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 64 * and/or other materials provided with the distribution.
<> 149:156823d33999 65 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 66 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 67 * without specific prior written permission.
<> 149:156823d33999 68 *
<> 149:156823d33999 69 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 70 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 72 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 73 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 74 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 75 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 76 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 77 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 78 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 79 *
<> 149:156823d33999 80 ******************************************************************************
<> 149:156823d33999 81 */
<> 149:156823d33999 82
<> 149:156823d33999 83 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 84 #include "stm32l1xx_hal.h"
<> 149:156823d33999 85
<> 149:156823d33999 86 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 87 * @{
<> 149:156823d33999 88 */
<> 149:156823d33999 89
<> 149:156823d33999 90 #ifdef HAL_NOR_MODULE_ENABLED
<> 149:156823d33999 91 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
<> 149:156823d33999 92
<> 149:156823d33999 93 /** @defgroup NOR NOR
<> 149:156823d33999 94 * @brief NOR driver modules
<> 149:156823d33999 95 * @{
<> 149:156823d33999 96 */
<> 149:156823d33999 97 /* Private typedef -----------------------------------------------------------*/
<> 149:156823d33999 98 /* Private define ------------------------------------------------------------*/
<> 149:156823d33999 99 /** @defgroup NOR_Private_Constants NOR Private Constants
<> 149:156823d33999 100 * @{
<> 149:156823d33999 101 */
<> 149:156823d33999 102
<> 149:156823d33999 103 /* Constants to define address to set to write a command */
<> 149:156823d33999 104 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
<> 149:156823d33999 105 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
<> 149:156823d33999 106 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
<> 149:156823d33999 107 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
<> 149:156823d33999 108 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
<> 149:156823d33999 109 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
<> 149:156823d33999 110 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
<> 149:156823d33999 111
<> 149:156823d33999 112 /* Constants to define data to program a command */
<> 149:156823d33999 113 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
<> 149:156823d33999 114 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
<> 149:156823d33999 115 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
<> 149:156823d33999 116 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
<> 149:156823d33999 117 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
<> 149:156823d33999 118 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
<> 149:156823d33999 119 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
<> 149:156823d33999 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
<> 149:156823d33999 121 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
<> 149:156823d33999 122 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
<> 149:156823d33999 123
<> 149:156823d33999 124 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
<> 149:156823d33999 125 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
<> 149:156823d33999 126 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
<> 149:156823d33999 127
<> 149:156823d33999 128 /* Mask on NOR STATUS REGISTER */
<> 149:156823d33999 129 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
<> 149:156823d33999 130 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
<> 149:156823d33999 131
<> 149:156823d33999 132 /**
<> 149:156823d33999 133 * @}
<> 149:156823d33999 134 */
<> 149:156823d33999 135
<> 149:156823d33999 136 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 137 /** @defgroup NOR_Private_Macros NOR Private Macros
<> 149:156823d33999 138 * @{
<> 149:156823d33999 139 */
<> 149:156823d33999 140
<> 149:156823d33999 141 /**
<> 149:156823d33999 142 * @}
<> 149:156823d33999 143 */
<> 149:156823d33999 144
<> 149:156823d33999 145 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 146
<> 149:156823d33999 147 /** @defgroup NOR_Private_Variables NOR Private Variables
<> 149:156823d33999 148 * @{
<> 149:156823d33999 149 */
<> 149:156823d33999 150
<> 149:156823d33999 151 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 149:156823d33999 152
<> 149:156823d33999 153 /**
<> 149:156823d33999 154 * @}
<> 149:156823d33999 155 */
<> 149:156823d33999 156
<> 149:156823d33999 157 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 158 /* Private functions ---------------------------------------------------------*/
<> 149:156823d33999 159
<> 149:156823d33999 160 /** @defgroup NOR_Exported_Functions NOR Exported Functions
<> 149:156823d33999 161 * @{
<> 149:156823d33999 162 */
<> 149:156823d33999 163
<> 149:156823d33999 164 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 149:156823d33999 165 * @brief Initialization and Configuration functions
<> 149:156823d33999 166 *
<> 149:156823d33999 167 @verbatim
<> 149:156823d33999 168 ==============================================================================
<> 149:156823d33999 169 ##### NOR Initialization and de_initialization functions #####
<> 149:156823d33999 170 ==============================================================================
<> 149:156823d33999 171 [..]
<> 149:156823d33999 172 This section provides functions allowing to initialize/de-initialize
<> 149:156823d33999 173 the NOR memory
<> 149:156823d33999 174
<> 149:156823d33999 175 @endverbatim
<> 149:156823d33999 176 * @{
<> 149:156823d33999 177 */
<> 149:156823d33999 178
<> 149:156823d33999 179 /**
<> 149:156823d33999 180 * @brief Perform the NOR memory Initialization sequence
<> 149:156823d33999 181 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 182 * the configuration information for NOR module.
<> 149:156823d33999 183 * @param Timing: pointer to NOR control timing structure
<> 149:156823d33999 184 * @param ExtTiming: pointer to NOR extended mode timing structure
<> 149:156823d33999 185 * @retval HAL status
<> 149:156823d33999 186 */
<> 149:156823d33999 187 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 149:156823d33999 188 {
<> 149:156823d33999 189 /* Check the NOR handle parameter */
<> 149:156823d33999 190 if(hnor == NULL)
<> 149:156823d33999 191 {
<> 149:156823d33999 192 return HAL_ERROR;
<> 149:156823d33999 193 }
<> 149:156823d33999 194
<> 149:156823d33999 195 if(hnor->State == HAL_NOR_STATE_RESET)
<> 149:156823d33999 196 {
<> 149:156823d33999 197 /* Allocate lock resource and initialize it */
<> 149:156823d33999 198 hnor->Lock = HAL_UNLOCKED;
<> 149:156823d33999 199
<> 149:156823d33999 200 /* Initialize the low level hardware (MSP) */
<> 149:156823d33999 201 HAL_NOR_MspInit(hnor);
<> 149:156823d33999 202 }
<> 149:156823d33999 203
<> 149:156823d33999 204 /* Initialize NOR control Interface */
<> 149:156823d33999 205 FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
<> 149:156823d33999 206
<> 149:156823d33999 207 /* Initialize NOR timing Interface */
<> 149:156823d33999 208 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
<> 149:156823d33999 209
<> 149:156823d33999 210 /* Initialize NOR extended mode timing Interface */
<> 149:156823d33999 211 FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
<> 149:156823d33999 212
<> 149:156823d33999 213 /* Enable the NORSRAM device */
<> 149:156823d33999 214 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
<> 149:156823d33999 215
<> 149:156823d33999 216 /* Initialize NOR Memory Data Width*/
<> 149:156823d33999 217 if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
<> 149:156823d33999 218 {
<> 149:156823d33999 219 uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 149:156823d33999 220 }
<> 149:156823d33999 221 else
<> 149:156823d33999 222 {
<> 149:156823d33999 223 uwNORMemoryDataWidth = NOR_MEMORY_16B;
<> 149:156823d33999 224 }
<> 149:156823d33999 225
<> 149:156823d33999 226 /* Check the NOR controller state */
<> 149:156823d33999 227 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 228
<> 149:156823d33999 229 return HAL_OK;
<> 149:156823d33999 230 }
<> 149:156823d33999 231
<> 149:156823d33999 232 /**
<> 149:156823d33999 233 * @brief Perform NOR memory De-Initialization sequence
<> 149:156823d33999 234 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 235 * the configuration information for NOR module.
<> 149:156823d33999 236 * @retval HAL status
<> 149:156823d33999 237 */
<> 149:156823d33999 238 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
<> 149:156823d33999 239 {
<> 149:156823d33999 240 /* De-Initialize the low level hardware (MSP) */
<> 149:156823d33999 241 HAL_NOR_MspDeInit(hnor);
<> 149:156823d33999 242
<> 149:156823d33999 243 /* Configure the NOR registers with their reset values */
<> 149:156823d33999 244 FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
<> 149:156823d33999 245
<> 149:156823d33999 246 /* Update the NOR controller state */
<> 149:156823d33999 247 hnor->State = HAL_NOR_STATE_RESET;
<> 149:156823d33999 248
<> 149:156823d33999 249 /* Release Lock */
<> 149:156823d33999 250 __HAL_UNLOCK(hnor);
<> 149:156823d33999 251
<> 149:156823d33999 252 return HAL_OK;
<> 149:156823d33999 253 }
<> 149:156823d33999 254
<> 149:156823d33999 255 /**
<> 149:156823d33999 256 * @brief NOR MSP Init
<> 149:156823d33999 257 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 258 * the configuration information for NOR module.
<> 149:156823d33999 259 * @retval None
<> 149:156823d33999 260 */
<> 149:156823d33999 261 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
<> 149:156823d33999 262 {
<> 149:156823d33999 263 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 264 UNUSED(hnor);
<> 149:156823d33999 265
<> 149:156823d33999 266 /* NOTE : This function Should not be modified, when the callback is needed,
<> 149:156823d33999 267 the HAL_NOR_MspInit could be implemented in the user file
<> 149:156823d33999 268 */
<> 149:156823d33999 269 }
<> 149:156823d33999 270
<> 149:156823d33999 271 /**
<> 149:156823d33999 272 * @brief NOR MSP DeInit
<> 149:156823d33999 273 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 274 * the configuration information for NOR module.
<> 149:156823d33999 275 * @retval None
<> 149:156823d33999 276 */
<> 149:156823d33999 277 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
<> 149:156823d33999 278 {
<> 149:156823d33999 279 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 280 UNUSED(hnor);
<> 149:156823d33999 281
<> 149:156823d33999 282 /* NOTE : This function Should not be modified, when the callback is needed,
<> 149:156823d33999 283 the HAL_NOR_MspDeInit could be implemented in the user file
<> 149:156823d33999 284 */
<> 149:156823d33999 285 }
<> 149:156823d33999 286
<> 149:156823d33999 287 /**
<> 149:156823d33999 288 * @brief NOR MSP Wait fro Ready/Busy signal
<> 149:156823d33999 289 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 290 * the configuration information for NOR module.
<> 149:156823d33999 291 * @param Timeout: Maximum timeout value
<> 149:156823d33999 292 * @retval None
<> 149:156823d33999 293 */
<> 149:156823d33999 294 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
<> 149:156823d33999 295 {
<> 149:156823d33999 296 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 297 UNUSED(hnor);
<> 149:156823d33999 298 UNUSED(Timeout);
<> 149:156823d33999 299
<> 149:156823d33999 300 /* NOTE : This function Should not be modified, when the callback is needed,
<> 149:156823d33999 301 the HAL_NOR_MspWait could be implemented in the user file
<> 149:156823d33999 302 */
<> 149:156823d33999 303 }
<> 149:156823d33999 304
<> 149:156823d33999 305 /**
<> 149:156823d33999 306 * @}
<> 149:156823d33999 307 */
<> 149:156823d33999 308
<> 149:156823d33999 309 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
<> 149:156823d33999 310 * @brief Input Output and memory control functions
<> 149:156823d33999 311 *
<> 149:156823d33999 312 @verbatim
<> 149:156823d33999 313 ==============================================================================
<> 149:156823d33999 314 ##### NOR Input and Output functions #####
<> 149:156823d33999 315 ==============================================================================
<> 149:156823d33999 316 [..]
<> 149:156823d33999 317 This section provides functions allowing to use and control the NOR memory
<> 149:156823d33999 318
<> 149:156823d33999 319 @endverbatim
<> 149:156823d33999 320 * @{
<> 149:156823d33999 321 */
<> 149:156823d33999 322
<> 149:156823d33999 323 /**
<> 149:156823d33999 324 * @brief Read NOR flash IDs
<> 149:156823d33999 325 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 326 * the configuration information for NOR module.
<> 149:156823d33999 327 * @param pNOR_ID : pointer to NOR ID structure
<> 149:156823d33999 328 * @retval HAL status
<> 149:156823d33999 329 */
<> 149:156823d33999 330 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
<> 149:156823d33999 331 {
<> 149:156823d33999 332 uint32_t deviceaddress = 0;
<> 149:156823d33999 333
<> 149:156823d33999 334 /* Process Locked */
<> 149:156823d33999 335 __HAL_LOCK(hnor);
<> 149:156823d33999 336
<> 149:156823d33999 337 /* Check the NOR controller state */
<> 149:156823d33999 338 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 339 {
<> 149:156823d33999 340 return HAL_BUSY;
<> 149:156823d33999 341 }
<> 149:156823d33999 342
<> 149:156823d33999 343 /* Select the NOR device address */
<> 149:156823d33999 344 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 345 {
<> 149:156823d33999 346 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 347 }
<> 149:156823d33999 348 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 349 {
<> 149:156823d33999 350 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 351 }
<> 149:156823d33999 352 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 353 {
<> 149:156823d33999 354 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 355 }
<> 149:156823d33999 356 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 357 {
<> 149:156823d33999 358 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 359 }
<> 149:156823d33999 360
<> 149:156823d33999 361 /* Update the NOR controller state */
<> 149:156823d33999 362 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 363
<> 149:156823d33999 364 /* Send read ID command */
<> 149:156823d33999 365 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 149:156823d33999 366 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 149:156823d33999 367 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
<> 149:156823d33999 368
<> 149:156823d33999 369 /* Read the NOR IDs */
<> 149:156823d33999 370 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
<> 149:156823d33999 371 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
<> 149:156823d33999 372 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
<> 149:156823d33999 373 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
<> 149:156823d33999 374
<> 149:156823d33999 375 /* Check the NOR controller state */
<> 149:156823d33999 376 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 377
<> 149:156823d33999 378 /* Process unlocked */
<> 149:156823d33999 379 __HAL_UNLOCK(hnor);
<> 149:156823d33999 380
<> 149:156823d33999 381 return HAL_OK;
<> 149:156823d33999 382 }
<> 149:156823d33999 383
<> 149:156823d33999 384 /**
<> 149:156823d33999 385 * @brief Returns the NOR memory to Read mode.
<> 149:156823d33999 386 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 387 * the configuration information for NOR module.
<> 149:156823d33999 388 * @retval HAL status
<> 149:156823d33999 389 */
<> 149:156823d33999 390 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
<> 149:156823d33999 391 {
<> 149:156823d33999 392 uint32_t deviceaddress = 0;
<> 149:156823d33999 393
<> 149:156823d33999 394 /* Process Locked */
<> 149:156823d33999 395 __HAL_LOCK(hnor);
<> 149:156823d33999 396
<> 149:156823d33999 397 /* Check the NOR controller state */
<> 149:156823d33999 398 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 399 {
<> 149:156823d33999 400 return HAL_BUSY;
<> 149:156823d33999 401 }
<> 149:156823d33999 402
<> 149:156823d33999 403 /* Select the NOR device address */
<> 149:156823d33999 404 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 405 {
<> 149:156823d33999 406 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 407 }
<> 149:156823d33999 408 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 409 {
<> 149:156823d33999 410 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 411 }
<> 149:156823d33999 412 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 413 {
<> 149:156823d33999 414 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 415 }
<> 149:156823d33999 416 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 417 {
<> 149:156823d33999 418 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 419 }
<> 149:156823d33999 420
<> 149:156823d33999 421 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
<> 149:156823d33999 422
<> 149:156823d33999 423 /* Check the NOR controller state */
<> 149:156823d33999 424 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 425
<> 149:156823d33999 426 /* Process unlocked */
<> 149:156823d33999 427 __HAL_UNLOCK(hnor);
<> 149:156823d33999 428
<> 149:156823d33999 429 return HAL_OK;
<> 149:156823d33999 430 }
<> 149:156823d33999 431
<> 149:156823d33999 432 /**
<> 149:156823d33999 433 * @brief Read data from NOR memory
<> 149:156823d33999 434 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 435 * the configuration information for NOR module.
<> 149:156823d33999 436 * @param pAddress: pointer to Device address
<> 149:156823d33999 437 * @param pData : pointer to read data
<> 149:156823d33999 438 * @retval HAL status
<> 149:156823d33999 439 */
<> 149:156823d33999 440 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 149:156823d33999 441 {
<> 149:156823d33999 442 uint32_t deviceaddress = 0;
<> 149:156823d33999 443
<> 149:156823d33999 444 /* Process Locked */
<> 149:156823d33999 445 __HAL_LOCK(hnor);
<> 149:156823d33999 446
<> 149:156823d33999 447 /* Check the NOR controller state */
<> 149:156823d33999 448 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 449 {
<> 149:156823d33999 450 return HAL_BUSY;
<> 149:156823d33999 451 }
<> 149:156823d33999 452
<> 149:156823d33999 453 /* Select the NOR device address */
<> 149:156823d33999 454 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 455 {
<> 149:156823d33999 456 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 457 }
<> 149:156823d33999 458 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 459 {
<> 149:156823d33999 460 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 461 }
<> 149:156823d33999 462 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 463 {
<> 149:156823d33999 464 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 465 }
<> 149:156823d33999 466 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 467 {
<> 149:156823d33999 468 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 469 }
<> 149:156823d33999 470
<> 149:156823d33999 471 /* Update the NOR controller state */
<> 149:156823d33999 472 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 473
<> 149:156823d33999 474 /* Send read data command */
<> 149:156823d33999 475 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 149:156823d33999 476 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 149:156823d33999 477 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
<> 149:156823d33999 478
<> 149:156823d33999 479 /* Read the data */
<> 149:156823d33999 480 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
<> 149:156823d33999 481
<> 149:156823d33999 482 /* Check the NOR controller state */
<> 149:156823d33999 483 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 484
<> 149:156823d33999 485 /* Process unlocked */
<> 149:156823d33999 486 __HAL_UNLOCK(hnor);
<> 149:156823d33999 487
<> 149:156823d33999 488 return HAL_OK;
<> 149:156823d33999 489 }
<> 149:156823d33999 490
<> 149:156823d33999 491 /**
<> 149:156823d33999 492 * @brief Program data to NOR memory
<> 149:156823d33999 493 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 494 * the configuration information for NOR module.
<> 149:156823d33999 495 * @param pAddress: Device address
<> 149:156823d33999 496 * @param pData : pointer to the data to write
<> 149:156823d33999 497 * @retval HAL status
<> 149:156823d33999 498 */
<> 149:156823d33999 499 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 149:156823d33999 500 {
<> 149:156823d33999 501 uint32_t deviceaddress = 0;
<> 149:156823d33999 502
<> 149:156823d33999 503 /* Process Locked */
<> 149:156823d33999 504 __HAL_LOCK(hnor);
<> 149:156823d33999 505
<> 149:156823d33999 506 /* Check the NOR controller state */
<> 149:156823d33999 507 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 508 {
<> 149:156823d33999 509 return HAL_BUSY;
<> 149:156823d33999 510 }
<> 149:156823d33999 511
<> 149:156823d33999 512 /* Select the NOR device address */
<> 149:156823d33999 513 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 514 {
<> 149:156823d33999 515 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 516 }
<> 149:156823d33999 517 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 518 {
<> 149:156823d33999 519 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 520 }
<> 149:156823d33999 521 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 522 {
<> 149:156823d33999 523 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 524 }
<> 149:156823d33999 525 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 526 {
<> 149:156823d33999 527 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 528 }
<> 149:156823d33999 529
<> 149:156823d33999 530 /* Update the NOR controller state */
<> 149:156823d33999 531 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 532
<> 149:156823d33999 533 /* Send program data command */
<> 149:156823d33999 534 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 149:156823d33999 535 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 149:156823d33999 536 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
<> 149:156823d33999 537
<> 149:156823d33999 538 /* Write the data */
<> 149:156823d33999 539 NOR_WRITE(pAddress, *pData);
<> 149:156823d33999 540
<> 149:156823d33999 541 /* Check the NOR controller state */
<> 149:156823d33999 542 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 543
<> 149:156823d33999 544 /* Process unlocked */
<> 149:156823d33999 545 __HAL_UNLOCK(hnor);
<> 149:156823d33999 546
<> 149:156823d33999 547 return HAL_OK;
<> 149:156823d33999 548 }
<> 149:156823d33999 549
<> 149:156823d33999 550 /**
<> 149:156823d33999 551 * @brief Reads a block of data from the FSMC NOR memory.
<> 149:156823d33999 552 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 553 * the configuration information for NOR module.
<> 149:156823d33999 554 * @param uwAddress: NOR memory internal address to read from.
<> 149:156823d33999 555 * @param pData: pointer to the buffer that receives the data read from the
<> 149:156823d33999 556 * NOR memory.
<> 149:156823d33999 557 * @param uwBufferSize : number of Half word to read.
<> 149:156823d33999 558 * @retval HAL status
<> 149:156823d33999 559 */
<> 149:156823d33999 560 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 149:156823d33999 561 {
<> 149:156823d33999 562 uint32_t deviceaddress = 0;
<> 149:156823d33999 563
<> 149:156823d33999 564 /* Process Locked */
<> 149:156823d33999 565 __HAL_LOCK(hnor);
<> 149:156823d33999 566
<> 149:156823d33999 567 /* Check the NOR controller state */
<> 149:156823d33999 568 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 569 {
<> 149:156823d33999 570 return HAL_BUSY;
<> 149:156823d33999 571 }
<> 149:156823d33999 572
<> 149:156823d33999 573 /* Select the NOR device address */
<> 149:156823d33999 574 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 575 {
<> 149:156823d33999 576 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 577 }
<> 149:156823d33999 578 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 579 {
<> 149:156823d33999 580 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 581 }
<> 149:156823d33999 582 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 583 {
<> 149:156823d33999 584 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 585 }
<> 149:156823d33999 586 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 587 {
<> 149:156823d33999 588 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 589 }
<> 149:156823d33999 590
<> 149:156823d33999 591 /* Update the NOR controller state */
<> 149:156823d33999 592 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 593
<> 149:156823d33999 594 /* Send read data command */
<> 149:156823d33999 595 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 149:156823d33999 596 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 149:156823d33999 597 NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
<> 149:156823d33999 598
<> 149:156823d33999 599 /* Read buffer */
<> 149:156823d33999 600 while( uwBufferSize > 0)
<> 149:156823d33999 601 {
<> 149:156823d33999 602 *pData++ = *(__IO uint16_t *)uwAddress;
<> 149:156823d33999 603 uwAddress += 2;
<> 149:156823d33999 604 uwBufferSize--;
<> 149:156823d33999 605 }
<> 149:156823d33999 606
<> 149:156823d33999 607 /* Check the NOR controller state */
<> 149:156823d33999 608 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 609
<> 149:156823d33999 610 /* Process unlocked */
<> 149:156823d33999 611 __HAL_UNLOCK(hnor);
<> 149:156823d33999 612
<> 149:156823d33999 613 return HAL_OK;
<> 149:156823d33999 614 }
<> 149:156823d33999 615
<> 149:156823d33999 616 /**
<> 149:156823d33999 617 * @brief Writes a half-word buffer to the FSMC NOR memory. This function
<> 149:156823d33999 618 * must be used only with S29GL128P NOR memory.
<> 149:156823d33999 619 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 620 * the configuration information for NOR module.
<> 149:156823d33999 621 * @param uwAddress: NOR memory internal address from which the data
<> 149:156823d33999 622 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
<> 149:156823d33999 623 * 64 bytes boundary for example).
<> 149:156823d33999 624 * @param pData: pointer to source data buffer.
<> 149:156823d33999 625 * @param uwBufferSize: number of Half words to write.
<> 149:156823d33999 626 * @note The maximum buffer size allowed is NOR memory dependent
<> 149:156823d33999 627 * (can be 64 Bytes max for example).
<> 149:156823d33999 628 * @retval HAL status
<> 149:156823d33999 629 */
<> 149:156823d33999 630 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 149:156823d33999 631 {
<> 149:156823d33999 632 uint16_t * p_currentaddress = (uint16_t *)NULL;
<> 149:156823d33999 633 uint16_t * p_endaddress = (uint16_t *)NULL;
<> 149:156823d33999 634 uint32_t lastloadedaddress = 0, deviceaddress = 0;
<> 149:156823d33999 635
<> 149:156823d33999 636 /* Process Locked */
<> 149:156823d33999 637 __HAL_LOCK(hnor);
<> 149:156823d33999 638
<> 149:156823d33999 639 /* Check the NOR controller state */
<> 149:156823d33999 640 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 641 {
<> 149:156823d33999 642 return HAL_BUSY;
<> 149:156823d33999 643 }
<> 149:156823d33999 644
<> 149:156823d33999 645 /* Select the NOR device address */
<> 149:156823d33999 646 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 647 {
<> 149:156823d33999 648 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 649 }
<> 149:156823d33999 650 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 651 {
<> 149:156823d33999 652 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 653 }
<> 149:156823d33999 654 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 655 {
<> 149:156823d33999 656 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 657 }
<> 149:156823d33999 658 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 659 {
<> 149:156823d33999 660 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 661 }
<> 149:156823d33999 662
<> 149:156823d33999 663 /* Update the NOR controller state */
<> 149:156823d33999 664 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 665
<> 149:156823d33999 666 /* Initialize variables */
<> 149:156823d33999 667 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
<> 149:156823d33999 668 p_endaddress = p_currentaddress + (uwBufferSize-1);
<> 149:156823d33999 669 lastloadedaddress = (uint32_t)(uwAddress);
<> 149:156823d33999 670
<> 149:156823d33999 671 /* Issue unlock command sequence */
<> 149:156823d33999 672 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 149:156823d33999 673 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 149:156823d33999 674
<> 149:156823d33999 675 /* Write Buffer Load Command */
<> 149:156823d33999 676 NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
<> 149:156823d33999 677 NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
<> 149:156823d33999 678
<> 149:156823d33999 679 /* Load Data into NOR Buffer */
<> 149:156823d33999 680 while(p_currentaddress <= p_endaddress)
<> 149:156823d33999 681 {
<> 149:156823d33999 682 /* Store last loaded address & data value (for polling) */
<> 149:156823d33999 683 lastloadedaddress = (uint32_t)p_currentaddress;
<> 149:156823d33999 684
<> 149:156823d33999 685 NOR_WRITE(p_currentaddress, *pData++);
<> 149:156823d33999 686
<> 149:156823d33999 687 p_currentaddress++;
<> 149:156823d33999 688 }
<> 149:156823d33999 689
<> 149:156823d33999 690 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
<> 149:156823d33999 691
<> 149:156823d33999 692 /* Check the NOR controller state */
<> 149:156823d33999 693 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 694
<> 149:156823d33999 695 /* Process unlocked */
<> 149:156823d33999 696 __HAL_UNLOCK(hnor);
<> 149:156823d33999 697
<> 149:156823d33999 698 return HAL_OK;
<> 149:156823d33999 699
<> 149:156823d33999 700 }
<> 149:156823d33999 701
<> 149:156823d33999 702 /**
<> 149:156823d33999 703 * @brief Erase the specified block of the NOR memory
<> 149:156823d33999 704 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 705 * the configuration information for NOR module.
<> 149:156823d33999 706 * @param BlockAddress : Block to erase address
<> 149:156823d33999 707 * @param Address: Device address
<> 149:156823d33999 708 * @retval HAL status
<> 149:156823d33999 709 */
<> 149:156823d33999 710 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
<> 149:156823d33999 711 {
<> 149:156823d33999 712 uint32_t deviceaddress = 0;
<> 149:156823d33999 713
<> 149:156823d33999 714 /* Process Locked */
<> 149:156823d33999 715 __HAL_LOCK(hnor);
<> 149:156823d33999 716
<> 149:156823d33999 717 /* Check the NOR controller state */
<> 149:156823d33999 718 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 719 {
<> 149:156823d33999 720 return HAL_BUSY;
<> 149:156823d33999 721 }
<> 149:156823d33999 722
<> 149:156823d33999 723 /* Select the NOR device address */
<> 149:156823d33999 724 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 725 {
<> 149:156823d33999 726 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 727 }
<> 149:156823d33999 728 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 729 {
<> 149:156823d33999 730 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 731 }
<> 149:156823d33999 732 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 733 {
<> 149:156823d33999 734 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 735 }
<> 149:156823d33999 736 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 737 {
<> 149:156823d33999 738 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 739 }
<> 149:156823d33999 740
<> 149:156823d33999 741 /* Update the NOR controller state */
<> 149:156823d33999 742 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 743
<> 149:156823d33999 744 /* Send block erase command sequence */
<> 149:156823d33999 745 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 149:156823d33999 746 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 149:156823d33999 747 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 149:156823d33999 748 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 149:156823d33999 749 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 149:156823d33999 750 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
<> 149:156823d33999 751
<> 149:156823d33999 752 /* Check the NOR memory status and update the controller state */
<> 149:156823d33999 753 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 754
<> 149:156823d33999 755 /* Process unlocked */
<> 149:156823d33999 756 __HAL_UNLOCK(hnor);
<> 149:156823d33999 757
<> 149:156823d33999 758 return HAL_OK;
<> 149:156823d33999 759
<> 149:156823d33999 760 }
<> 149:156823d33999 761
<> 149:156823d33999 762 /**
<> 149:156823d33999 763 * @brief Erase the entire NOR chip.
<> 149:156823d33999 764 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 765 * the configuration information for NOR module.
<> 149:156823d33999 766 * @param Address : Device address
<> 149:156823d33999 767 * @retval HAL status
<> 149:156823d33999 768 */
<> 149:156823d33999 769 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
<> 149:156823d33999 770 {
<> 149:156823d33999 771 uint32_t deviceaddress = 0;
<> 149:156823d33999 772
<> 149:156823d33999 773 /* Process Locked */
<> 149:156823d33999 774 __HAL_LOCK(hnor);
<> 149:156823d33999 775
<> 149:156823d33999 776 /* Check the NOR controller state */
<> 149:156823d33999 777 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 778 {
<> 149:156823d33999 779 return HAL_BUSY;
<> 149:156823d33999 780 }
<> 149:156823d33999 781
<> 149:156823d33999 782 /* Select the NOR device address */
<> 149:156823d33999 783 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 784 {
<> 149:156823d33999 785 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 786 }
<> 149:156823d33999 787 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 788 {
<> 149:156823d33999 789 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 790 }
<> 149:156823d33999 791 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 792 {
<> 149:156823d33999 793 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 794 }
<> 149:156823d33999 795 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 796 {
<> 149:156823d33999 797 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 798 }
<> 149:156823d33999 799
<> 149:156823d33999 800 /* Update the NOR controller state */
<> 149:156823d33999 801 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 802
<> 149:156823d33999 803 /* Send NOR chip erase command sequence */
<> 149:156823d33999 804 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 149:156823d33999 805 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 149:156823d33999 806 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 149:156823d33999 807 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 149:156823d33999 808 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 149:156823d33999 809 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
<> 149:156823d33999 810
<> 149:156823d33999 811 /* Check the NOR memory status and update the controller state */
<> 149:156823d33999 812 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 813
<> 149:156823d33999 814 /* Process unlocked */
<> 149:156823d33999 815 __HAL_UNLOCK(hnor);
<> 149:156823d33999 816
<> 149:156823d33999 817 return HAL_OK;
<> 149:156823d33999 818 }
<> 149:156823d33999 819
<> 149:156823d33999 820 /**
<> 149:156823d33999 821 * @brief Read NOR flash CFI IDs
<> 149:156823d33999 822 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 823 * the configuration information for NOR module.
<> 149:156823d33999 824 * @param pNOR_CFI : pointer to NOR CFI IDs structure
<> 149:156823d33999 825 * @retval HAL status
<> 149:156823d33999 826 */
<> 149:156823d33999 827 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
<> 149:156823d33999 828 {
<> 149:156823d33999 829 uint32_t deviceaddress = 0;
<> 149:156823d33999 830
<> 149:156823d33999 831 /* Process Locked */
<> 149:156823d33999 832 __HAL_LOCK(hnor);
<> 149:156823d33999 833
<> 149:156823d33999 834 /* Check the NOR controller state */
<> 149:156823d33999 835 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 149:156823d33999 836 {
<> 149:156823d33999 837 return HAL_BUSY;
<> 149:156823d33999 838 }
<> 149:156823d33999 839
<> 149:156823d33999 840 /* Select the NOR device address */
<> 149:156823d33999 841 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 842 {
<> 149:156823d33999 843 deviceaddress = NOR_MEMORY_ADRESS1;
<> 149:156823d33999 844 }
<> 149:156823d33999 845 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 149:156823d33999 846 {
<> 149:156823d33999 847 deviceaddress = NOR_MEMORY_ADRESS2;
<> 149:156823d33999 848 }
<> 149:156823d33999 849 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 149:156823d33999 850 {
<> 149:156823d33999 851 deviceaddress = NOR_MEMORY_ADRESS3;
<> 149:156823d33999 852 }
<> 149:156823d33999 853 else /* FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 854 {
<> 149:156823d33999 855 deviceaddress = NOR_MEMORY_ADRESS4;
<> 149:156823d33999 856 }
<> 149:156823d33999 857
<> 149:156823d33999 858 /* Update the NOR controller state */
<> 149:156823d33999 859 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 860
<> 149:156823d33999 861 /* Send read CFI query command */
<> 149:156823d33999 862 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
<> 149:156823d33999 863
<> 149:156823d33999 864 /* read the NOR CFI information */
<> 149:156823d33999 865 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
<> 149:156823d33999 866 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
<> 149:156823d33999 867 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
<> 149:156823d33999 868 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
<> 149:156823d33999 869
<> 149:156823d33999 870 /* Check the NOR controller state */
<> 149:156823d33999 871 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 872
<> 149:156823d33999 873 /* Process unlocked */
<> 149:156823d33999 874 __HAL_UNLOCK(hnor);
<> 149:156823d33999 875
<> 149:156823d33999 876 return HAL_OK;
<> 149:156823d33999 877 }
<> 149:156823d33999 878
<> 149:156823d33999 879 /**
<> 149:156823d33999 880 * @}
<> 149:156823d33999 881 */
<> 149:156823d33999 882
<> 149:156823d33999 883 /** @defgroup NOR_Exported_Functions_Group3 Control functions
<> 149:156823d33999 884 * @brief management functions
<> 149:156823d33999 885 *
<> 149:156823d33999 886 @verbatim
<> 149:156823d33999 887 ==============================================================================
<> 149:156823d33999 888 ##### NOR Control functions #####
<> 149:156823d33999 889 ==============================================================================
<> 149:156823d33999 890 [..]
<> 149:156823d33999 891 This subsection provides a set of functions allowing to control dynamically
<> 149:156823d33999 892 the NOR interface.
<> 149:156823d33999 893
<> 149:156823d33999 894 @endverbatim
<> 149:156823d33999 895 * @{
<> 149:156823d33999 896 */
<> 149:156823d33999 897
<> 149:156823d33999 898 /**
<> 149:156823d33999 899 * @brief Enables dynamically NOR write operation.
<> 149:156823d33999 900 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 901 * the configuration information for NOR module.
<> 149:156823d33999 902 * @retval HAL status
<> 149:156823d33999 903 */
<> 149:156823d33999 904 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
<> 149:156823d33999 905 {
<> 149:156823d33999 906 /* Process Locked */
<> 149:156823d33999 907 __HAL_LOCK(hnor);
<> 149:156823d33999 908
<> 149:156823d33999 909 /* Enable write operation */
<> 149:156823d33999 910 FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
<> 149:156823d33999 911
<> 149:156823d33999 912 /* Update the NOR controller state */
<> 149:156823d33999 913 hnor->State = HAL_NOR_STATE_READY;
<> 149:156823d33999 914
<> 149:156823d33999 915 /* Process unlocked */
<> 149:156823d33999 916 __HAL_UNLOCK(hnor);
<> 149:156823d33999 917
<> 149:156823d33999 918 return HAL_OK;
<> 149:156823d33999 919 }
<> 149:156823d33999 920
<> 149:156823d33999 921 /**
<> 149:156823d33999 922 * @brief Disables dynamically NOR write operation.
<> 149:156823d33999 923 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 924 * the configuration information for NOR module.
<> 149:156823d33999 925 * @retval HAL status
<> 149:156823d33999 926 */
<> 149:156823d33999 927 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
<> 149:156823d33999 928 {
<> 149:156823d33999 929 /* Process Locked */
<> 149:156823d33999 930 __HAL_LOCK(hnor);
<> 149:156823d33999 931
<> 149:156823d33999 932 /* Update the SRAM controller state */
<> 149:156823d33999 933 hnor->State = HAL_NOR_STATE_BUSY;
<> 149:156823d33999 934
<> 149:156823d33999 935 /* Disable write operation */
<> 149:156823d33999 936 FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
<> 149:156823d33999 937
<> 149:156823d33999 938 /* Update the NOR controller state */
<> 149:156823d33999 939 hnor->State = HAL_NOR_STATE_PROTECTED;
<> 149:156823d33999 940
<> 149:156823d33999 941 /* Process unlocked */
<> 149:156823d33999 942 __HAL_UNLOCK(hnor);
<> 149:156823d33999 943
<> 149:156823d33999 944 return HAL_OK;
<> 149:156823d33999 945 }
<> 149:156823d33999 946
<> 149:156823d33999 947 /**
<> 149:156823d33999 948 * @}
<> 149:156823d33999 949 */
<> 149:156823d33999 950
<> 149:156823d33999 951 /** @defgroup NOR_Exported_Functions_Group4 State functions
<> 149:156823d33999 952 * @brief Peripheral State functions
<> 149:156823d33999 953 *
<> 149:156823d33999 954 @verbatim
<> 149:156823d33999 955 ==============================================================================
<> 149:156823d33999 956 ##### NOR State functions #####
<> 149:156823d33999 957 ==============================================================================
<> 149:156823d33999 958 [..]
<> 149:156823d33999 959 This subsection permits to get in run-time the status of the NOR controller
<> 149:156823d33999 960 and the data flow.
<> 149:156823d33999 961
<> 149:156823d33999 962 @endverbatim
<> 149:156823d33999 963 * @{
<> 149:156823d33999 964 */
<> 149:156823d33999 965
<> 149:156823d33999 966 /**
<> 149:156823d33999 967 * @brief return the NOR controller state
<> 149:156823d33999 968 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 969 * the configuration information for NOR module.
<> 149:156823d33999 970 * @retval NOR controller state
<> 149:156823d33999 971 */
<> 149:156823d33999 972 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
<> 149:156823d33999 973 {
<> 149:156823d33999 974 return hnor->State;
<> 149:156823d33999 975 }
<> 149:156823d33999 976
<> 149:156823d33999 977 /**
<> 149:156823d33999 978 * @brief Returns the NOR operation status.
<> 149:156823d33999 979 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 149:156823d33999 980 * the configuration information for NOR module.
<> 149:156823d33999 981 * @param Address: Device address
<> 149:156823d33999 982 * @param Timeout: NOR progamming Timeout
<> 149:156823d33999 983 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
<> 149:156823d33999 984 * or HAL_NOR_STATUS_TIMEOUT
<> 149:156823d33999 985 */
<> 149:156823d33999 986 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
<> 149:156823d33999 987 {
<> 149:156823d33999 988 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
<> 149:156823d33999 989 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
<> 149:156823d33999 990 uint32_t tickstart = 0;
<> 149:156823d33999 991
<> 149:156823d33999 992 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
<> 149:156823d33999 993 HAL_NOR_MspWait(hnor, Timeout);
<> 149:156823d33999 994
<> 149:156823d33999 995 /* Get tick */
<> 149:156823d33999 996 tickstart = HAL_GetTick();
<> 149:156823d33999 997 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
<> 149:156823d33999 998 {
<> 149:156823d33999 999 /* Check for the Timeout */
<> 149:156823d33999 1000 if(Timeout != HAL_MAX_DELAY)
<> 149:156823d33999 1001 {
<> 149:156823d33999 1002 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 149:156823d33999 1003 {
<> 149:156823d33999 1004 status = HAL_NOR_STATUS_TIMEOUT;
<> 149:156823d33999 1005 }
<> 149:156823d33999 1006 }
<> 149:156823d33999 1007
<> 149:156823d33999 1008 /* Read NOR status register (DQ6 and DQ5) */
<> 149:156823d33999 1009 tmp_sr1 = *(__IO uint16_t *)Address;
<> 149:156823d33999 1010 tmp_sr2 = *(__IO uint16_t *)Address;
<> 149:156823d33999 1011
<> 149:156823d33999 1012 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 149:156823d33999 1013 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 149:156823d33999 1014 {
<> 149:156823d33999 1015 return HAL_NOR_STATUS_SUCCESS;
<> 149:156823d33999 1016 }
<> 149:156823d33999 1017
<> 149:156823d33999 1018 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
<> 149:156823d33999 1019 {
<> 149:156823d33999 1020 status = HAL_NOR_STATUS_ONGOING;
<> 149:156823d33999 1021 }
<> 149:156823d33999 1022
<> 149:156823d33999 1023 tmp_sr1 = *(__IO uint16_t *)Address;
<> 149:156823d33999 1024 tmp_sr2 = *(__IO uint16_t *)Address;
<> 149:156823d33999 1025
<> 149:156823d33999 1026 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 149:156823d33999 1027 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 149:156823d33999 1028 {
<> 149:156823d33999 1029 return HAL_NOR_STATUS_SUCCESS;
<> 149:156823d33999 1030 }
<> 149:156823d33999 1031 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
<> 149:156823d33999 1032 {
<> 149:156823d33999 1033 return HAL_NOR_STATUS_ERROR;
<> 149:156823d33999 1034 }
<> 149:156823d33999 1035 }
<> 149:156823d33999 1036
<> 149:156823d33999 1037 /* Return the operation status */
<> 149:156823d33999 1038 return status;
<> 149:156823d33999 1039 }
<> 149:156823d33999 1040
<> 149:156823d33999 1041 /**
<> 149:156823d33999 1042 * @}
<> 149:156823d33999 1043 */
<> 149:156823d33999 1044
<> 149:156823d33999 1045 /**
<> 149:156823d33999 1046 * @}
<> 149:156823d33999 1047 */
<> 149:156823d33999 1048 /**
<> 149:156823d33999 1049 * @}
<> 149:156823d33999 1050 */
<> 149:156823d33999 1051 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
<> 149:156823d33999 1052 #endif /* HAL_NOR_MODULE_ENABLED */
<> 149:156823d33999 1053
<> 149:156823d33999 1054 /**
<> 149:156823d33999 1055 * @}
<> 149:156823d33999 1056 */
<> 149:156823d33999 1057
<> 149:156823d33999 1058 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/