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mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/stm32l152xe.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l152xe.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
<> 149:156823d33999 6 * This file contains all the peripheral register's definitions, bits
<> 149:156823d33999 7 * definitions and memory mapping for STM32L1xx devices.
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * This file contains:
<> 149:156823d33999 10 * - Data structures and the address mapping for all peripherals
<> 149:156823d33999 11 * - Peripheral's registers declarations and bits definition
<> 149:156823d33999 12 * - Macros to access peripheral’s registers hardware
<> 149:156823d33999 13 *
<> 149:156823d33999 14 ******************************************************************************
<> 149:156823d33999 15 * @attention
<> 149:156823d33999 16 *
AnnaBridge 184:08ed48f1de7f 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 18 *
<> 149:156823d33999 19 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 20 * are permitted provided that the following conditions are met:
<> 149:156823d33999 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 22 * this list of conditions and the following disclaimer.
<> 149:156823d33999 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 24 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 25 * and/or other materials provided with the distribution.
<> 149:156823d33999 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 27 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 28 * without specific prior written permission.
<> 149:156823d33999 29 *
<> 149:156823d33999 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 40 *
<> 149:156823d33999 41 ******************************************************************************
<> 149:156823d33999 42 */
<> 149:156823d33999 43
<> 149:156823d33999 44 /** @addtogroup CMSIS
<> 149:156823d33999 45 * @{
<> 149:156823d33999 46 */
<> 149:156823d33999 47
<> 149:156823d33999 48 /** @addtogroup stm32l152xe
<> 149:156823d33999 49 * @{
<> 149:156823d33999 50 */
<> 149:156823d33999 51
<> 149:156823d33999 52 #ifndef __STM32L152xE_H
<> 149:156823d33999 53 #define __STM32L152xE_H
<> 149:156823d33999 54
<> 149:156823d33999 55 #ifdef __cplusplus
<> 149:156823d33999 56 extern "C" {
<> 149:156823d33999 57 #endif
<> 149:156823d33999 58
<> 149:156823d33999 59
<> 149:156823d33999 60 /** @addtogroup Configuration_section_for_CMSIS
<> 149:156823d33999 61 * @{
<> 149:156823d33999 62 */
<> 149:156823d33999 63 /**
<> 149:156823d33999 64 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
<> 149:156823d33999 65 */
<> 149:156823d33999 66 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */
<> 149:156823d33999 67 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */
<> 149:156823d33999 68 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */
<> 149:156823d33999 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 149:156823d33999 70
<> 149:156823d33999 71 /**
<> 149:156823d33999 72 * @}
<> 149:156823d33999 73 */
<> 149:156823d33999 74
<> 149:156823d33999 75 /** @addtogroup Peripheral_interrupt_number_definition
<> 149:156823d33999 76 * @{
<> 149:156823d33999 77 */
<> 149:156823d33999 78
<> 149:156823d33999 79 /**
<> 149:156823d33999 80 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
<> 149:156823d33999 81 * in @ref Library_configuration_section
<> 149:156823d33999 82 */
<> 149:156823d33999 83
<> 149:156823d33999 84 /*!< Interrupt Number Definition */
<> 149:156823d33999 85 typedef enum
<> 149:156823d33999 86 {
<> 149:156823d33999 87 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
<> 149:156823d33999 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 149:156823d33999 89 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
<> 149:156823d33999 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
<> 149:156823d33999 91 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
<> 149:156823d33999 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
<> 149:156823d33999 93 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
<> 149:156823d33999 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
<> 149:156823d33999 95 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
<> 149:156823d33999 96 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
<> 149:156823d33999 97
<> 149:156823d33999 98 /****** STM32L specific Interrupt Numbers ***********************************************************/
<> 149:156823d33999 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 149:156823d33999 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 149:156823d33999 101 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 149:156823d33999 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
<> 149:156823d33999 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 149:156823d33999 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 149:156823d33999 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 149:156823d33999 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 149:156823d33999 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 149:156823d33999 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 149:156823d33999 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 149:156823d33999 110 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
<> 149:156823d33999 111 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
<> 149:156823d33999 112 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
<> 149:156823d33999 113 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
<> 149:156823d33999 114 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
<> 149:156823d33999 115 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
<> 149:156823d33999 116 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
<> 149:156823d33999 117 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
<> 149:156823d33999 118 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
<> 149:156823d33999 119 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
<> 149:156823d33999 120 DAC_IRQn = 21, /*!< DAC Interrupt */
<> 149:156823d33999 121 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
<> 149:156823d33999 122 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 149:156823d33999 123 LCD_IRQn = 24, /*!< LCD Interrupt */
<> 149:156823d33999 124 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
<> 149:156823d33999 125 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
<> 149:156823d33999 126 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
<> 149:156823d33999 127 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 149:156823d33999 128 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 149:156823d33999 129 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 149:156823d33999 130 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 149:156823d33999 131 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 149:156823d33999 132 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 149:156823d33999 133 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 149:156823d33999 134 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 149:156823d33999 135 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 149:156823d33999 136 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 149:156823d33999 137 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 149:156823d33999 138 USART3_IRQn = 39, /*!< USART3 global Interrupt */
<> 149:156823d33999 139 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 149:156823d33999 140 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
<> 149:156823d33999 141 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
<> 149:156823d33999 142 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
<> 149:156823d33999 143 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
<> 149:156823d33999 144 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
<> 149:156823d33999 145 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
<> 149:156823d33999 146 UART4_IRQn = 48, /*!< UART4 global Interrupt */
<> 149:156823d33999 147 UART5_IRQn = 49, /*!< UART5 global Interrupt */
<> 149:156823d33999 148 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
<> 149:156823d33999 149 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
<> 149:156823d33999 150 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
<> 149:156823d33999 151 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
<> 149:156823d33999 152 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
<> 149:156823d33999 153 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
<> 149:156823d33999 154 } IRQn_Type;
<> 149:156823d33999 155
<> 149:156823d33999 156 /**
<> 149:156823d33999 157 * @}
<> 149:156823d33999 158 */
<> 149:156823d33999 159
<> 149:156823d33999 160 #include "core_cm3.h"
<> 149:156823d33999 161 #include "system_stm32l1xx.h"
<> 149:156823d33999 162 #include <stdint.h>
<> 149:156823d33999 163
<> 149:156823d33999 164 /** @addtogroup Peripheral_registers_structures
<> 149:156823d33999 165 * @{
<> 149:156823d33999 166 */
<> 149:156823d33999 167
<> 149:156823d33999 168 /**
<> 149:156823d33999 169 * @brief Analog to Digital Converter
<> 149:156823d33999 170 */
<> 149:156823d33999 171
<> 149:156823d33999 172 typedef struct
<> 149:156823d33999 173 {
<> 149:156823d33999 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
<> 149:156823d33999 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 149:156823d33999 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 149:156823d33999 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 149:156823d33999 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 149:156823d33999 179 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
<> 149:156823d33999 180 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
<> 149:156823d33999 181 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
<> 149:156823d33999 182 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
<> 149:156823d33999 183 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
<> 149:156823d33999 184 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
<> 149:156823d33999 185 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
<> 149:156823d33999 186 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
<> 149:156823d33999 187 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
<> 149:156823d33999 188 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
<> 149:156823d33999 189 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
<> 149:156823d33999 190 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
<> 149:156823d33999 191 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
<> 149:156823d33999 192 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
<> 149:156823d33999 193 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
<> 149:156823d33999 194 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
<> 149:156823d33999 195 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
<> 149:156823d33999 196 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
<> 149:156823d33999 197 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
<> 149:156823d33999 198 } ADC_TypeDef;
<> 149:156823d33999 199
<> 149:156823d33999 200 typedef struct
<> 149:156823d33999 201 {
<> 149:156823d33999 202 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
<> 149:156823d33999 203 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 149:156823d33999 204 } ADC_Common_TypeDef;
<> 149:156823d33999 205
<> 149:156823d33999 206 /**
<> 149:156823d33999 207 * @brief Comparator
<> 149:156823d33999 208 */
<> 149:156823d33999 209
<> 149:156823d33999 210 typedef struct
<> 149:156823d33999 211 {
<> 149:156823d33999 212 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
<> 149:156823d33999 213 } COMP_TypeDef;
<> 149:156823d33999 214
<> 149:156823d33999 215 typedef struct
<> 149:156823d33999 216 {
<> 149:156823d33999 217 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
<> 149:156823d33999 218 } COMP_Common_TypeDef;
<> 149:156823d33999 219
<> 149:156823d33999 220 /**
<> 149:156823d33999 221 * @brief CRC calculation unit
<> 149:156823d33999 222 */
<> 149:156823d33999 223
<> 149:156823d33999 224 typedef struct
<> 149:156823d33999 225 {
<> 149:156823d33999 226 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 149:156823d33999 227 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 149:156823d33999 228 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
<> 149:156823d33999 229 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
<> 149:156823d33999 230 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 149:156823d33999 231 } CRC_TypeDef;
<> 149:156823d33999 232
<> 149:156823d33999 233 /**
<> 149:156823d33999 234 * @brief Digital to Analog Converter
<> 149:156823d33999 235 */
<> 149:156823d33999 236
<> 149:156823d33999 237 typedef struct
<> 149:156823d33999 238 {
<> 149:156823d33999 239 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 149:156823d33999 240 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 149:156823d33999 241 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 149:156823d33999 242 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 149:156823d33999 243 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 149:156823d33999 244 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 149:156823d33999 245 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 149:156823d33999 246 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 149:156823d33999 247 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 149:156823d33999 248 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 149:156823d33999 249 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 149:156823d33999 250 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 149:156823d33999 251 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 149:156823d33999 252 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 149:156823d33999 253 } DAC_TypeDef;
<> 149:156823d33999 254
<> 149:156823d33999 255 /**
<> 149:156823d33999 256 * @brief Debug MCU
<> 149:156823d33999 257 */
<> 149:156823d33999 258
<> 149:156823d33999 259 typedef struct
<> 149:156823d33999 260 {
<> 149:156823d33999 261 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 149:156823d33999 262 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 149:156823d33999 263 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 149:156823d33999 264 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 149:156823d33999 265 }DBGMCU_TypeDef;
<> 149:156823d33999 266
<> 149:156823d33999 267 /**
<> 149:156823d33999 268 * @brief DMA Controller
<> 149:156823d33999 269 */
<> 149:156823d33999 270
<> 149:156823d33999 271 typedef struct
<> 149:156823d33999 272 {
<> 149:156823d33999 273 __IO uint32_t CCR; /*!< DMA channel x configuration register */
<> 149:156823d33999 274 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
<> 149:156823d33999 275 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
<> 149:156823d33999 276 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
<> 149:156823d33999 277 } DMA_Channel_TypeDef;
<> 149:156823d33999 278
<> 149:156823d33999 279 typedef struct
<> 149:156823d33999 280 {
<> 149:156823d33999 281 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
<> 149:156823d33999 282 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
<> 149:156823d33999 283 } DMA_TypeDef;
<> 149:156823d33999 284
<> 149:156823d33999 285 /**
<> 149:156823d33999 286 * @brief External Interrupt/Event Controller
<> 149:156823d33999 287 */
<> 149:156823d33999 288
<> 149:156823d33999 289 typedef struct
<> 149:156823d33999 290 {
<> 149:156823d33999 291 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
<> 149:156823d33999 292 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
<> 149:156823d33999 293 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
<> 149:156823d33999 294 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
<> 149:156823d33999 295 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
<> 149:156823d33999 296 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
<> 149:156823d33999 297 } EXTI_TypeDef;
<> 149:156823d33999 298
<> 149:156823d33999 299 /**
<> 149:156823d33999 300 * @brief FLASH Registers
<> 149:156823d33999 301 */
<> 149:156823d33999 302 typedef struct
<> 149:156823d33999 303 {
<> 149:156823d33999 304 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
<> 149:156823d33999 305 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
<> 149:156823d33999 306 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
<> 149:156823d33999 307 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
<> 149:156823d33999 308 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
<> 149:156823d33999 309 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
<> 149:156823d33999 310 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
<> 149:156823d33999 311 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
<> 149:156823d33999 312 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
<> 149:156823d33999 313 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
<> 149:156823d33999 314 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
<> 149:156823d33999 315 __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */
<> 149:156823d33999 316 __IO uint32_t WRPR4; /*!< Write protection register 4, Address offset: 0x88 */
<> 149:156823d33999 317 } FLASH_TypeDef;
<> 149:156823d33999 318
<> 149:156823d33999 319 /**
<> 149:156823d33999 320 * @brief Option Bytes Registers
<> 149:156823d33999 321 */
<> 149:156823d33999 322 typedef struct
<> 149:156823d33999 323 {
<> 149:156823d33999 324 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
<> 149:156823d33999 325 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
<> 149:156823d33999 326 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
<> 149:156823d33999 327 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
<> 149:156823d33999 328 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
<> 149:156823d33999 329 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
<> 149:156823d33999 330 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
<> 149:156823d33999 331 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
<> 149:156823d33999 332 uint32_t RESERVED[24]; /*!< Reserved, 0x20 -> 0x7C */
<> 149:156823d33999 333 __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */
<> 149:156823d33999 334 __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */
<> 149:156823d33999 335 } OB_TypeDef;
<> 149:156823d33999 336
<> 149:156823d33999 337 /**
<> 149:156823d33999 338 * @brief Operational Amplifier (OPAMP)
<> 149:156823d33999 339 */
<> 149:156823d33999 340 typedef struct
<> 149:156823d33999 341 {
<> 149:156823d33999 342 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
<> 149:156823d33999 343 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
<> 149:156823d33999 344 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
<> 149:156823d33999 345 } OPAMP_TypeDef;
<> 149:156823d33999 346
<> 149:156823d33999 347 typedef struct
<> 149:156823d33999 348 {
<> 149:156823d33999 349 __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
<> 149:156823d33999 350 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */
<> 149:156823d33999 351 } OPAMP_Common_TypeDef;
<> 149:156823d33999 352
<> 149:156823d33999 353 /**
<> 149:156823d33999 354 * @brief General Purpose IO
<> 149:156823d33999 355 */
<> 149:156823d33999 356
<> 149:156823d33999 357 typedef struct
<> 149:156823d33999 358 {
<> 149:156823d33999 359 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 149:156823d33999 360 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 149:156823d33999 361 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 149:156823d33999 362 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 149:156823d33999 363 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 149:156823d33999 364 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 149:156823d33999 365 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
<> 149:156823d33999 366 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 149:156823d33999 367 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
<> 149:156823d33999 368 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
<> 149:156823d33999 369 } GPIO_TypeDef;
<> 149:156823d33999 370
<> 149:156823d33999 371 /**
<> 149:156823d33999 372 * @brief SysTem Configuration
<> 149:156823d33999 373 */
<> 149:156823d33999 374
<> 149:156823d33999 375 typedef struct
<> 149:156823d33999 376 {
<> 149:156823d33999 377 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 149:156823d33999 378 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 149:156823d33999 379 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 149:156823d33999 380 } SYSCFG_TypeDef;
<> 149:156823d33999 381
<> 149:156823d33999 382 /**
<> 149:156823d33999 383 * @brief Inter-integrated Circuit Interface
<> 149:156823d33999 384 */
<> 149:156823d33999 385
<> 149:156823d33999 386 typedef struct
<> 149:156823d33999 387 {
<> 149:156823d33999 388 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 149:156823d33999 389 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 149:156823d33999 390 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
<> 149:156823d33999 391 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
<> 149:156823d33999 392 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
<> 149:156823d33999 393 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
<> 149:156823d33999 394 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
<> 149:156823d33999 395 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
<> 149:156823d33999 396 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
<> 149:156823d33999 397 } I2C_TypeDef;
<> 149:156823d33999 398
<> 149:156823d33999 399 /**
<> 149:156823d33999 400 * @brief Independent WATCHDOG
<> 149:156823d33999 401 */
<> 149:156823d33999 402
<> 149:156823d33999 403 typedef struct
<> 149:156823d33999 404 {
<> 149:156823d33999 405 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
<> 149:156823d33999 406 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
<> 149:156823d33999 407 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
<> 149:156823d33999 408 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
<> 149:156823d33999 409 } IWDG_TypeDef;
<> 149:156823d33999 410
<> 149:156823d33999 411 /**
<> 149:156823d33999 412 * @brief LCD
<> 149:156823d33999 413 */
<> 149:156823d33999 414
<> 149:156823d33999 415 typedef struct
<> 149:156823d33999 416 {
<> 149:156823d33999 417 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
<> 149:156823d33999 418 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
<> 149:156823d33999 419 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
<> 149:156823d33999 420 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
<> 149:156823d33999 421 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
<> 149:156823d33999 422 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
<> 149:156823d33999 423 } LCD_TypeDef;
<> 149:156823d33999 424
<> 149:156823d33999 425 /**
<> 149:156823d33999 426 * @brief Power Control
<> 149:156823d33999 427 */
<> 149:156823d33999 428
<> 149:156823d33999 429 typedef struct
<> 149:156823d33999 430 {
<> 149:156823d33999 431 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 149:156823d33999 432 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 149:156823d33999 433 } PWR_TypeDef;
<> 149:156823d33999 434
<> 149:156823d33999 435 /**
<> 149:156823d33999 436 * @brief Reset and Clock Control
<> 149:156823d33999 437 */
<> 149:156823d33999 438
<> 149:156823d33999 439 typedef struct
<> 149:156823d33999 440 {
<> 149:156823d33999 441 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 149:156823d33999 442 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
<> 149:156823d33999 443 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
<> 149:156823d33999 444 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
<> 149:156823d33999 445 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
<> 149:156823d33999 446 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
<> 149:156823d33999 447 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
<> 149:156823d33999 448 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
<> 149:156823d33999 449 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
<> 149:156823d33999 450 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
<> 149:156823d33999 451 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
<> 149:156823d33999 452 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
<> 149:156823d33999 453 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
<> 149:156823d33999 454 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
<> 149:156823d33999 455 } RCC_TypeDef;
<> 149:156823d33999 456
<> 149:156823d33999 457 /**
<> 149:156823d33999 458 * @brief Routing Interface
<> 149:156823d33999 459 */
<> 149:156823d33999 460
<> 149:156823d33999 461 typedef struct
<> 149:156823d33999 462 {
<> 149:156823d33999 463 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
AnnaBridge 184:08ed48f1de7f 464 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
AnnaBridge 184:08ed48f1de7f 465 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
<> 149:156823d33999 466 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
AnnaBridge 184:08ed48f1de7f 467 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
AnnaBridge 184:08ed48f1de7f 468 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
AnnaBridge 184:08ed48f1de7f 469 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
AnnaBridge 184:08ed48f1de7f 470 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
AnnaBridge 184:08ed48f1de7f 471 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
AnnaBridge 184:08ed48f1de7f 472 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
AnnaBridge 184:08ed48f1de7f 473 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
AnnaBridge 184:08ed48f1de7f 474 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
AnnaBridge 184:08ed48f1de7f 475 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
AnnaBridge 184:08ed48f1de7f 476 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
AnnaBridge 184:08ed48f1de7f 477 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
AnnaBridge 184:08ed48f1de7f 478 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
AnnaBridge 184:08ed48f1de7f 479 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
AnnaBridge 184:08ed48f1de7f 480 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
AnnaBridge 184:08ed48f1de7f 481 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
AnnaBridge 184:08ed48f1de7f 482 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
AnnaBridge 184:08ed48f1de7f 483 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
AnnaBridge 184:08ed48f1de7f 484 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
<> 149:156823d33999 485 } RI_TypeDef;
<> 149:156823d33999 486
<> 149:156823d33999 487 /**
<> 149:156823d33999 488 * @brief Real-Time Clock
<> 149:156823d33999 489 */
<> 149:156823d33999 490 typedef struct
<> 149:156823d33999 491 {
<> 149:156823d33999 492 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 149:156823d33999 493 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 149:156823d33999 494 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 149:156823d33999 495 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 149:156823d33999 496 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 149:156823d33999 497 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 149:156823d33999 498 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
<> 149:156823d33999 499 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 149:156823d33999 500 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 149:156823d33999 501 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 149:156823d33999 502 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 149:156823d33999 503 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 149:156823d33999 504 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 149:156823d33999 505 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 149:156823d33999 506 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 149:156823d33999 507 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
<> 149:156823d33999 508 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 149:156823d33999 509 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 149:156823d33999 510 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 149:156823d33999 511 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 149:156823d33999 512 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
<> 149:156823d33999 513 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 149:156823d33999 514 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 149:156823d33999 515 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 149:156823d33999 516 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 149:156823d33999 517 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 149:156823d33999 518 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 149:156823d33999 519 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 149:156823d33999 520 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 149:156823d33999 521 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 149:156823d33999 522 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 149:156823d33999 523 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 149:156823d33999 524 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 149:156823d33999 525 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 149:156823d33999 526 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 149:156823d33999 527 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 149:156823d33999 528 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 149:156823d33999 529 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 149:156823d33999 530 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 149:156823d33999 531 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 149:156823d33999 532 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
<> 149:156823d33999 533 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
<> 149:156823d33999 534 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
<> 149:156823d33999 535 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
<> 149:156823d33999 536 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
<> 149:156823d33999 537 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
<> 149:156823d33999 538 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
<> 149:156823d33999 539 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
<> 149:156823d33999 540 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
<> 149:156823d33999 541 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
<> 149:156823d33999 542 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
<> 149:156823d33999 543 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
<> 149:156823d33999 544 } RTC_TypeDef;
<> 149:156823d33999 545
<> 149:156823d33999 546 /**
<> 149:156823d33999 547 * @brief Serial Peripheral Interface
<> 149:156823d33999 548 */
<> 149:156823d33999 549
<> 149:156823d33999 550 typedef struct
<> 149:156823d33999 551 {
<> 149:156823d33999 552 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 149:156823d33999 553 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
<> 149:156823d33999 554 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
<> 149:156823d33999 555 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 149:156823d33999 556 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 149:156823d33999 557 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
<> 149:156823d33999 558 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
<> 149:156823d33999 559 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 149:156823d33999 560 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 149:156823d33999 561 } SPI_TypeDef;
<> 149:156823d33999 562
<> 149:156823d33999 563 /**
<> 149:156823d33999 564 * @brief TIM
<> 149:156823d33999 565 */
<> 149:156823d33999 566 typedef struct
<> 149:156823d33999 567 {
<> 149:156823d33999 568 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 149:156823d33999 569 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 149:156823d33999 570 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
<> 149:156823d33999 571 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 149:156823d33999 572 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 149:156823d33999 573 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 149:156823d33999 574 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 149:156823d33999 575 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 149:156823d33999 576 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 149:156823d33999 577 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 149:156823d33999 578 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
<> 149:156823d33999 579 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 149:156823d33999 580 uint32_t RESERVED12; /*!< Reserved, 0x30 */
<> 149:156823d33999 581 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 149:156823d33999 582 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 149:156823d33999 583 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 149:156823d33999 584 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 149:156823d33999 585 uint32_t RESERVED17; /*!< Reserved, 0x44 */
<> 149:156823d33999 586 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 149:156823d33999 587 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 149:156823d33999 588 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 149:156823d33999 589 } TIM_TypeDef;
<> 149:156823d33999 590 /**
<> 149:156823d33999 591 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 149:156823d33999 592 */
<> 149:156823d33999 593
<> 149:156823d33999 594 typedef struct
<> 149:156823d33999 595 {
<> 149:156823d33999 596 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
<> 149:156823d33999 597 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
<> 149:156823d33999 598 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
<> 149:156823d33999 599 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
<> 149:156823d33999 600 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
<> 149:156823d33999 601 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
<> 149:156823d33999 602 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
<> 149:156823d33999 603 } USART_TypeDef;
<> 149:156823d33999 604
<> 149:156823d33999 605 /**
<> 149:156823d33999 606 * @brief Universal Serial Bus Full Speed Device
<> 149:156823d33999 607 */
<> 149:156823d33999 608
<> 149:156823d33999 609 typedef struct
<> 149:156823d33999 610 {
<> 149:156823d33999 611 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
<> 149:156823d33999 612 __IO uint16_t RESERVED0; /*!< Reserved */
<> 149:156823d33999 613 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
<> 149:156823d33999 614 __IO uint16_t RESERVED1; /*!< Reserved */
<> 149:156823d33999 615 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
<> 149:156823d33999 616 __IO uint16_t RESERVED2; /*!< Reserved */
<> 149:156823d33999 617 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
<> 149:156823d33999 618 __IO uint16_t RESERVED3; /*!< Reserved */
<> 149:156823d33999 619 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
<> 149:156823d33999 620 __IO uint16_t RESERVED4; /*!< Reserved */
<> 149:156823d33999 621 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
<> 149:156823d33999 622 __IO uint16_t RESERVED5; /*!< Reserved */
<> 149:156823d33999 623 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
<> 149:156823d33999 624 __IO uint16_t RESERVED6; /*!< Reserved */
<> 149:156823d33999 625 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
<> 149:156823d33999 626 __IO uint16_t RESERVED7[17]; /*!< Reserved */
<> 149:156823d33999 627 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
<> 149:156823d33999 628 __IO uint16_t RESERVED8; /*!< Reserved */
<> 149:156823d33999 629 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
<> 149:156823d33999 630 __IO uint16_t RESERVED9; /*!< Reserved */
<> 149:156823d33999 631 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
<> 149:156823d33999 632 __IO uint16_t RESERVEDA; /*!< Reserved */
<> 149:156823d33999 633 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
<> 149:156823d33999 634 __IO uint16_t RESERVEDB; /*!< Reserved */
<> 149:156823d33999 635 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
<> 149:156823d33999 636 __IO uint16_t RESERVEDC; /*!< Reserved */
<> 149:156823d33999 637 } USB_TypeDef;
<> 149:156823d33999 638
<> 149:156823d33999 639 /**
<> 149:156823d33999 640 * @brief Window WATCHDOG
<> 149:156823d33999 641 */
<> 149:156823d33999 642 typedef struct
<> 149:156823d33999 643 {
<> 149:156823d33999 644 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 149:156823d33999 645 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 149:156823d33999 646 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 149:156823d33999 647 } WWDG_TypeDef;
<> 149:156823d33999 648
<> 149:156823d33999 649 /**
<> 149:156823d33999 650 * @brief Universal Serial Bus Full Speed Device
<> 149:156823d33999 651 */
<> 149:156823d33999 652 /**
<> 149:156823d33999 653 * @}
<> 149:156823d33999 654 */
<> 149:156823d33999 655
<> 149:156823d33999 656 /** @addtogroup Peripheral_memory_map
<> 149:156823d33999 657 * @{
<> 149:156823d33999 658 */
<> 149:156823d33999 659
<> 149:156823d33999 660 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
<> 149:156823d33999 661 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */
<> 149:156823d33999 662 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
<> 149:156823d33999 663 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
<> 149:156823d33999 664 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
<> 149:156823d33999 665 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
<> 149:156823d33999 666 #define FLASH_BANK2_BASE ((uint32_t)0x08040000U) /*!< FLASH BANK2 base address in the alias region */
<> 149:156823d33999 667 #define FLASH_BANK1_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH BANK1 address */
<> 149:156823d33999 668 #define FLASH_BANK2_END ((uint32_t)0x0807FFFFU) /*!< Program end FLASH BANK2 address */
<> 149:156823d33999 669 #define FLASH_EEPROM_END ((uint32_t)0x08083FFFU) /*!< FLASH EEPROM end address (16KB) */
<> 149:156823d33999 670
<> 149:156823d33999 671 /*!< Peripheral memory map */
<> 149:156823d33999 672 #define APB1PERIPH_BASE PERIPH_BASE
<> 149:156823d33999 673 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 149:156823d33999 674 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 149:156823d33999 675
<> 149:156823d33999 676 /*!< APB1 peripherals */
<> 149:156823d33999 677 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
<> 149:156823d33999 678 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
<> 149:156823d33999 679 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
<> 149:156823d33999 680 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
<> 149:156823d33999 681 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
<> 149:156823d33999 682 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
<> 149:156823d33999 683 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400U)
<> 149:156823d33999 684 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
<> 149:156823d33999 685 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
<> 149:156823d33999 686 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
<> 149:156823d33999 687 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
<> 149:156823d33999 688 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
<> 149:156823d33999 689 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
<> 149:156823d33999 690 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
<> 149:156823d33999 691 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
<> 149:156823d33999 692 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
<> 149:156823d33999 693 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
<> 149:156823d33999 694 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
<> 149:156823d33999 695
<> 149:156823d33999 696 /* USB device FS */
<> 149:156823d33999 697 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
<> 149:156823d33999 698 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
<> 149:156823d33999 699
<> 149:156823d33999 700 /* USB device FS SRAM */
<> 149:156823d33999 701 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
<> 149:156823d33999 702 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
<> 149:156823d33999 703 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U)
<> 149:156823d33999 704 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U)
<> 149:156823d33999 705 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU)
<> 149:156823d33999 706
<> 149:156823d33999 707 /*!< APB2 peripherals */
<> 149:156823d33999 708 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
<> 149:156823d33999 709 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
<> 149:156823d33999 710 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U)
<> 149:156823d33999 711 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U)
<> 149:156823d33999 712 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U)
<> 149:156823d33999 713 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
<> 149:156823d33999 714 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U)
<> 149:156823d33999 715 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
<> 149:156823d33999 716 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
<> 149:156823d33999 717
<> 149:156823d33999 718 /*!< AHB peripherals */
<> 149:156823d33999 719 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U)
<> 149:156823d33999 720 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U)
<> 149:156823d33999 721 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U)
<> 149:156823d33999 722 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U)
<> 149:156823d33999 723 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U)
<> 149:156823d33999 724 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U)
<> 149:156823d33999 725 #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800U)
<> 149:156823d33999 726 #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00U)
<> 149:156823d33999 727 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
<> 149:156823d33999 728 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U)
<> 149:156823d33999 729 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */
<> 149:156823d33999 730 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
<> 149:156823d33999 731 #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
<> 149:156823d33999 732 #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
<> 149:156823d33999 733 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U)
<> 149:156823d33999 734 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
<> 149:156823d33999 735 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
<> 149:156823d33999 736 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
<> 149:156823d33999 737 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
<> 149:156823d33999 738 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
<> 149:156823d33999 739 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
<> 149:156823d33999 740 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
<> 149:156823d33999 741 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U)
<> 149:156823d33999 742 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U)
<> 149:156823d33999 743 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU)
<> 149:156823d33999 744 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U)
<> 149:156823d33999 745 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U)
<> 149:156823d33999 746 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U)
<> 149:156823d33999 747 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
<> 149:156823d33999 748
<> 149:156823d33999 749 /**
<> 149:156823d33999 750 * @}
<> 149:156823d33999 751 */
<> 149:156823d33999 752
<> 149:156823d33999 753 /** @addtogroup Peripheral_declaration
<> 149:156823d33999 754 * @{
<> 149:156823d33999 755 */
<> 149:156823d33999 756
<> 149:156823d33999 757 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 149:156823d33999 758 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 149:156823d33999 759 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 149:156823d33999 760 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 149:156823d33999 761 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 149:156823d33999 762 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 149:156823d33999 763 #define LCD ((LCD_TypeDef *) LCD_BASE)
<> 149:156823d33999 764 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 149:156823d33999 765 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 149:156823d33999 766 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 149:156823d33999 767 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 149:156823d33999 768 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 149:156823d33999 769 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 149:156823d33999 770 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 149:156823d33999 771 #define UART4 ((USART_TypeDef *) UART4_BASE)
<> 149:156823d33999 772 #define UART5 ((USART_TypeDef *) UART5_BASE)
<> 149:156823d33999 773 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 149:156823d33999 774 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 149:156823d33999 775 /* USB device FS */
<> 149:156823d33999 776 #define USB ((USB_TypeDef *) USB_BASE)
<> 149:156823d33999 777 /* USB device FS SRAM */
<> 149:156823d33999 778 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 149:156823d33999 779
<> 149:156823d33999 780 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
<> 149:156823d33999 781 /* Legacy define */
<> 149:156823d33999 782 #define DAC DAC1
<> 149:156823d33999 783
<> 149:156823d33999 784 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
<> 149:156823d33999 785 #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
<> 149:156823d33999 786 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
<> 149:156823d33999 787 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
<> 149:156823d33999 788
<> 149:156823d33999 789 #define RI ((RI_TypeDef *) RI_BASE)
<> 149:156823d33999 790
<> 149:156823d33999 791 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
<> 149:156823d33999 792 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
<> 149:156823d33999 793 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
<> 149:156823d33999 794 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE)
<> 149:156823d33999 795 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 149:156823d33999 796 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 149:156823d33999 797 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 149:156823d33999 798 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 149:156823d33999 799 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 149:156823d33999 800
<> 149:156823d33999 801 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 149:156823d33999 802 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
<> 149:156823d33999 803 /* Legacy defines */
<> 149:156823d33999 804 #define ADC ADC1_COMMON
<> 149:156823d33999 805
<> 149:156823d33999 806 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 149:156823d33999 807 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 149:156823d33999 808 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 149:156823d33999 809 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 149:156823d33999 810 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 149:156823d33999 811 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 149:156823d33999 812 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 149:156823d33999 813 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 149:156823d33999 814 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 149:156823d33999 815 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
<> 149:156823d33999 816 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 149:156823d33999 817 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 149:156823d33999 818 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 149:156823d33999 819 #define OB ((OB_TypeDef *) OB_BASE)
<> 149:156823d33999 820 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 149:156823d33999 821 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
<> 149:156823d33999 822 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
<> 149:156823d33999 823 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
<> 149:156823d33999 824 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
<> 149:156823d33999 825 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
<> 149:156823d33999 826 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
<> 149:156823d33999 827 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
<> 149:156823d33999 828 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 149:156823d33999 829 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
<> 149:156823d33999 830 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
<> 149:156823d33999 831 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
<> 149:156823d33999 832 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
<> 149:156823d33999 833 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
<> 149:156823d33999 834 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 149:156823d33999 835
<> 149:156823d33999 836 /**
<> 149:156823d33999 837 * @}
<> 149:156823d33999 838 */
<> 149:156823d33999 839
<> 149:156823d33999 840 /** @addtogroup Exported_constants
<> 149:156823d33999 841 * @{
<> 149:156823d33999 842 */
<> 149:156823d33999 843
<> 149:156823d33999 844 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 149:156823d33999 845 * @{
<> 149:156823d33999 846 */
<> 149:156823d33999 847
<> 149:156823d33999 848 /******************************************************************************/
<> 149:156823d33999 849 /* Peripheral Registers Bits Definition */
<> 149:156823d33999 850 /******************************************************************************/
<> 149:156823d33999 851 /******************************************************************************/
<> 149:156823d33999 852 /* */
<> 149:156823d33999 853 /* Analog to Digital Converter (ADC) */
<> 149:156823d33999 854 /* */
<> 149:156823d33999 855 /******************************************************************************/
<> 149:156823d33999 856
<> 149:156823d33999 857 /******************** Bit definition for ADC_SR register ********************/
<> 149:156823d33999 858 #define ADC_SR_AWD_Pos (0U)
<> 149:156823d33999 859 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
<> 149:156823d33999 860 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
<> 149:156823d33999 861 #define ADC_SR_EOCS_Pos (1U)
<> 149:156823d33999 862 #define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /*!< 0x00000002 */
<> 149:156823d33999 863 #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
<> 149:156823d33999 864 #define ADC_SR_JEOS_Pos (2U)
<> 149:156823d33999 865 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
<> 149:156823d33999 866 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
<> 149:156823d33999 867 #define ADC_SR_JSTRT_Pos (3U)
<> 149:156823d33999 868 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
<> 149:156823d33999 869 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
<> 149:156823d33999 870 #define ADC_SR_STRT_Pos (4U)
<> 149:156823d33999 871 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
<> 149:156823d33999 872 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
<> 149:156823d33999 873 #define ADC_SR_OVR_Pos (5U)
<> 149:156823d33999 874 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
<> 149:156823d33999 875 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */
<> 149:156823d33999 876 #define ADC_SR_ADONS_Pos (6U)
<> 149:156823d33999 877 #define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 878 #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */
<> 149:156823d33999 879 #define ADC_SR_RCNR_Pos (8U)
<> 149:156823d33999 880 #define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /*!< 0x00000100 */
<> 149:156823d33999 881 #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */
<> 149:156823d33999 882 #define ADC_SR_JCNR_Pos (9U)
<> 149:156823d33999 883 #define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /*!< 0x00000200 */
<> 149:156823d33999 884 #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */
<> 149:156823d33999 885
<> 149:156823d33999 886 /* Legacy defines */
<> 149:156823d33999 887 #define ADC_SR_EOC (ADC_SR_EOCS)
<> 149:156823d33999 888 #define ADC_SR_JEOC (ADC_SR_JEOS)
<> 149:156823d33999 889
<> 149:156823d33999 890 /******************* Bit definition for ADC_CR1 register ********************/
<> 149:156823d33999 891 #define ADC_CR1_AWDCH_Pos (0U)
<> 149:156823d33999 892 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
<> 149:156823d33999 893 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
<> 149:156823d33999 894 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
<> 149:156823d33999 895 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
<> 149:156823d33999 896 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
<> 149:156823d33999 897 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
<> 149:156823d33999 898 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
<> 149:156823d33999 899
<> 149:156823d33999 900 #define ADC_CR1_EOCSIE_Pos (5U)
<> 149:156823d33999 901 #define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */
<> 149:156823d33999 902 #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
<> 149:156823d33999 903 #define ADC_CR1_AWDIE_Pos (6U)
<> 149:156823d33999 904 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 905 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
<> 149:156823d33999 906 #define ADC_CR1_JEOSIE_Pos (7U)
<> 149:156823d33999 907 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 908 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
<> 149:156823d33999 909 #define ADC_CR1_SCAN_Pos (8U)
<> 149:156823d33999 910 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
<> 149:156823d33999 911 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
<> 149:156823d33999 912 #define ADC_CR1_AWDSGL_Pos (9U)
<> 149:156823d33999 913 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
<> 149:156823d33999 914 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
<> 149:156823d33999 915 #define ADC_CR1_JAUTO_Pos (10U)
<> 149:156823d33999 916 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
<> 149:156823d33999 917 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
<> 149:156823d33999 918 #define ADC_CR1_DISCEN_Pos (11U)
<> 149:156823d33999 919 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
<> 149:156823d33999 920 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
<> 149:156823d33999 921 #define ADC_CR1_JDISCEN_Pos (12U)
<> 149:156823d33999 922 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
<> 149:156823d33999 923 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
<> 149:156823d33999 924
<> 149:156823d33999 925 #define ADC_CR1_DISCNUM_Pos (13U)
<> 149:156823d33999 926 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
<> 149:156823d33999 927 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
<> 149:156823d33999 928 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
<> 149:156823d33999 929 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
<> 149:156823d33999 930 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
<> 149:156823d33999 931
<> 149:156823d33999 932 #define ADC_CR1_PDD_Pos (16U)
<> 149:156823d33999 933 #define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /*!< 0x00010000 */
<> 149:156823d33999 934 #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */
<> 149:156823d33999 935 #define ADC_CR1_PDI_Pos (17U)
<> 149:156823d33999 936 #define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /*!< 0x00020000 */
<> 149:156823d33999 937 #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */
<> 149:156823d33999 938
<> 149:156823d33999 939 #define ADC_CR1_JAWDEN_Pos (22U)
<> 149:156823d33999 940 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
<> 149:156823d33999 941 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
<> 149:156823d33999 942 #define ADC_CR1_AWDEN_Pos (23U)
<> 149:156823d33999 943 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
<> 149:156823d33999 944 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
<> 149:156823d33999 945
<> 149:156823d33999 946 #define ADC_CR1_RES_Pos (24U)
<> 149:156823d33999 947 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
<> 149:156823d33999 948 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */
<> 149:156823d33999 949 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
<> 149:156823d33999 950 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
<> 149:156823d33999 951
<> 149:156823d33999 952 #define ADC_CR1_OVRIE_Pos (26U)
<> 149:156823d33999 953 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
<> 149:156823d33999 954 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */
<> 149:156823d33999 955
<> 149:156823d33999 956 /* Legacy defines */
<> 149:156823d33999 957 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
<> 149:156823d33999 958 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
<> 149:156823d33999 959
<> 149:156823d33999 960 /******************* Bit definition for ADC_CR2 register ********************/
<> 149:156823d33999 961 #define ADC_CR2_ADON_Pos (0U)
<> 149:156823d33999 962 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
<> 149:156823d33999 963 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
<> 149:156823d33999 964 #define ADC_CR2_CONT_Pos (1U)
<> 149:156823d33999 965 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
<> 149:156823d33999 966 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
<> 149:156823d33999 967 #define ADC_CR2_CFG_Pos (2U)
<> 149:156823d33999 968 #define ADC_CR2_CFG_Msk (0x1U << ADC_CR2_CFG_Pos) /*!< 0x00000004 */
<> 149:156823d33999 969 #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */
<> 149:156823d33999 970
<> 149:156823d33999 971 #define ADC_CR2_DELS_Pos (4U)
<> 149:156823d33999 972 #define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /*!< 0x00000070 */
<> 149:156823d33999 973 #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */
<> 149:156823d33999 974 #define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /*!< 0x00000010 */
<> 149:156823d33999 975 #define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /*!< 0x00000020 */
<> 149:156823d33999 976 #define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 977
<> 149:156823d33999 978 #define ADC_CR2_DMA_Pos (8U)
<> 149:156823d33999 979 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
<> 149:156823d33999 980 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
<> 149:156823d33999 981 #define ADC_CR2_DDS_Pos (9U)
<> 149:156823d33999 982 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
<> 149:156823d33999 983 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */
<> 149:156823d33999 984 #define ADC_CR2_EOCS_Pos (10U)
<> 149:156823d33999 985 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
<> 149:156823d33999 986 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
<> 149:156823d33999 987 #define ADC_CR2_ALIGN_Pos (11U)
<> 149:156823d33999 988 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
<> 149:156823d33999 989 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
<> 149:156823d33999 990
<> 149:156823d33999 991 #define ADC_CR2_JEXTSEL_Pos (16U)
<> 149:156823d33999 992 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
<> 149:156823d33999 993 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
<> 149:156823d33999 994 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
<> 149:156823d33999 995 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
<> 149:156823d33999 996 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
<> 149:156823d33999 997 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
<> 149:156823d33999 998
<> 149:156823d33999 999 #define ADC_CR2_JEXTEN_Pos (20U)
<> 149:156823d33999 1000 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
<> 149:156823d33999 1001 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
<> 149:156823d33999 1002 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1003 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1004
<> 149:156823d33999 1005 #define ADC_CR2_JSWSTART_Pos (22U)
<> 149:156823d33999 1006 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1007 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
<> 149:156823d33999 1008
<> 149:156823d33999 1009 #define ADC_CR2_EXTSEL_Pos (24U)
<> 149:156823d33999 1010 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
<> 149:156823d33999 1011 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
<> 149:156823d33999 1012 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1013 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1014 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1015 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1016
<> 149:156823d33999 1017 #define ADC_CR2_EXTEN_Pos (28U)
<> 149:156823d33999 1018 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
<> 149:156823d33999 1019 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */
<> 149:156823d33999 1020 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1021 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1022
<> 149:156823d33999 1023 #define ADC_CR2_SWSTART_Pos (30U)
<> 149:156823d33999 1024 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
<> 149:156823d33999 1025 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
<> 149:156823d33999 1026
<> 149:156823d33999 1027 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 149:156823d33999 1028 #define ADC_SMPR1_SMP20_Pos (0U)
<> 149:156823d33999 1029 #define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */
<> 149:156823d33999 1030 #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */
<> 149:156823d33999 1031 #define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1032 #define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1033 #define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1034
<> 149:156823d33999 1035 #define ADC_SMPR1_SMP21_Pos (3U)
<> 149:156823d33999 1036 #define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */
<> 149:156823d33999 1037 #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */
<> 149:156823d33999 1038 #define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1039 #define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1040 #define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1041
<> 149:156823d33999 1042 #define ADC_SMPR1_SMP22_Pos (6U)
<> 149:156823d33999 1043 #define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */
<> 149:156823d33999 1044 #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */
<> 149:156823d33999 1045 #define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1046 #define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1047 #define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1048
<> 149:156823d33999 1049 #define ADC_SMPR1_SMP23_Pos (9U)
<> 149:156823d33999 1050 #define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */
<> 149:156823d33999 1051 #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */
<> 149:156823d33999 1052 #define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1053 #define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1054 #define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1055
<> 149:156823d33999 1056 #define ADC_SMPR1_SMP24_Pos (12U)
<> 149:156823d33999 1057 #define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */
<> 149:156823d33999 1058 #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */
<> 149:156823d33999 1059 #define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1060 #define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1061 #define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1062
<> 149:156823d33999 1063 #define ADC_SMPR1_SMP25_Pos (15U)
<> 149:156823d33999 1064 #define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */
<> 149:156823d33999 1065 #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */
<> 149:156823d33999 1066 #define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1067 #define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1068 #define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1069
<> 149:156823d33999 1070 #define ADC_SMPR1_SMP26_Pos (18U)
<> 149:156823d33999 1071 #define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */
<> 149:156823d33999 1072 #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */
<> 149:156823d33999 1073 #define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1074 #define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1075 #define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1076
<> 149:156823d33999 1077 #define ADC_SMPR1_SMP27_Pos (21U)
<> 149:156823d33999 1078 #define ADC_SMPR1_SMP27_Msk (0x7U << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */
<> 149:156823d33999 1079 #define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */
<> 149:156823d33999 1080 #define ADC_SMPR1_SMP27_0 (0x1U << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1081 #define ADC_SMPR1_SMP27_1 (0x2U << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1082 #define ADC_SMPR1_SMP27_2 (0x4U << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1083
<> 149:156823d33999 1084 #define ADC_SMPR1_SMP28_Pos (24U)
<> 149:156823d33999 1085 #define ADC_SMPR1_SMP28_Msk (0x7U << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */
<> 149:156823d33999 1086 #define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */
<> 149:156823d33999 1087 #define ADC_SMPR1_SMP28_0 (0x1U << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1088 #define ADC_SMPR1_SMP28_1 (0x2U << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1089 #define ADC_SMPR1_SMP28_2 (0x4U << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1090
<> 149:156823d33999 1091 #define ADC_SMPR1_SMP29_Pos (27U)
<> 149:156823d33999 1092 #define ADC_SMPR1_SMP29_Msk (0x7U << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */
<> 149:156823d33999 1093 #define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */
<> 149:156823d33999 1094 #define ADC_SMPR1_SMP29_0 (0x1U << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1095 #define ADC_SMPR1_SMP29_1 (0x2U << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1096 #define ADC_SMPR1_SMP29_2 (0x4U << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1097
<> 149:156823d33999 1098 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 149:156823d33999 1099 #define ADC_SMPR2_SMP10_Pos (0U)
<> 149:156823d33999 1100 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
<> 149:156823d33999 1101 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
<> 149:156823d33999 1102 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1103 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1104 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1105
<> 149:156823d33999 1106 #define ADC_SMPR2_SMP11_Pos (3U)
<> 149:156823d33999 1107 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
<> 149:156823d33999 1108 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
<> 149:156823d33999 1109 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1110 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1111 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1112
<> 149:156823d33999 1113 #define ADC_SMPR2_SMP12_Pos (6U)
<> 149:156823d33999 1114 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
<> 149:156823d33999 1115 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
<> 149:156823d33999 1116 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1117 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1118 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1119
<> 149:156823d33999 1120 #define ADC_SMPR2_SMP13_Pos (9U)
<> 149:156823d33999 1121 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
<> 149:156823d33999 1122 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
<> 149:156823d33999 1123 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1124 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1125 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1126
<> 149:156823d33999 1127 #define ADC_SMPR2_SMP14_Pos (12U)
<> 149:156823d33999 1128 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
<> 149:156823d33999 1129 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
<> 149:156823d33999 1130 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1131 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1132 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1133
<> 149:156823d33999 1134 #define ADC_SMPR2_SMP15_Pos (15U)
<> 149:156823d33999 1135 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
<> 149:156823d33999 1136 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */
<> 149:156823d33999 1137 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1138 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1139 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1140
<> 149:156823d33999 1141 #define ADC_SMPR2_SMP16_Pos (18U)
<> 149:156823d33999 1142 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
<> 149:156823d33999 1143 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
<> 149:156823d33999 1144 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1145 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1146 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1147
<> 149:156823d33999 1148 #define ADC_SMPR2_SMP17_Pos (21U)
<> 149:156823d33999 1149 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
<> 149:156823d33999 1150 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
<> 149:156823d33999 1151 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1152 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1153 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1154
<> 149:156823d33999 1155 #define ADC_SMPR2_SMP18_Pos (24U)
<> 149:156823d33999 1156 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
<> 149:156823d33999 1157 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
<> 149:156823d33999 1158 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1159 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1160 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1161
<> 149:156823d33999 1162 #define ADC_SMPR2_SMP19_Pos (27U)
<> 149:156823d33999 1163 #define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
<> 149:156823d33999 1164 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */
<> 149:156823d33999 1165 #define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1166 #define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1167 #define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1168
<> 149:156823d33999 1169 /****************** Bit definition for ADC_SMPR3 register *******************/
<> 149:156823d33999 1170 #define ADC_SMPR3_SMP0_Pos (0U)
<> 149:156823d33999 1171 #define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */
<> 149:156823d33999 1172 #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */
<> 149:156823d33999 1173 #define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1174 #define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1175 #define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1176
<> 149:156823d33999 1177 #define ADC_SMPR3_SMP1_Pos (3U)
<> 149:156823d33999 1178 #define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */
<> 149:156823d33999 1179 #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */
<> 149:156823d33999 1180 #define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1181 #define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1182 #define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1183
<> 149:156823d33999 1184 #define ADC_SMPR3_SMP2_Pos (6U)
<> 149:156823d33999 1185 #define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
<> 149:156823d33999 1186 #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */
<> 149:156823d33999 1187 #define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1188 #define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1189 #define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1190
<> 149:156823d33999 1191 #define ADC_SMPR3_SMP3_Pos (9U)
<> 149:156823d33999 1192 #define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */
<> 149:156823d33999 1193 #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */
<> 149:156823d33999 1194 #define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1195 #define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1196 #define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1197
<> 149:156823d33999 1198 #define ADC_SMPR3_SMP4_Pos (12U)
<> 149:156823d33999 1199 #define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */
<> 149:156823d33999 1200 #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */
<> 149:156823d33999 1201 #define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1202 #define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1203 #define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1204
<> 149:156823d33999 1205 #define ADC_SMPR3_SMP5_Pos (15U)
<> 149:156823d33999 1206 #define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */
<> 149:156823d33999 1207 #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */
<> 149:156823d33999 1208 #define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1209 #define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1210 #define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1211
<> 149:156823d33999 1212 #define ADC_SMPR3_SMP6_Pos (18U)
<> 149:156823d33999 1213 #define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */
<> 149:156823d33999 1214 #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */
<> 149:156823d33999 1215 #define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1216 #define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1217 #define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1218
<> 149:156823d33999 1219 #define ADC_SMPR3_SMP7_Pos (21U)
<> 149:156823d33999 1220 #define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */
<> 149:156823d33999 1221 #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */
<> 149:156823d33999 1222 #define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1223 #define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1224 #define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1225
<> 149:156823d33999 1226 #define ADC_SMPR3_SMP8_Pos (24U)
<> 149:156823d33999 1227 #define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */
<> 149:156823d33999 1228 #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */
<> 149:156823d33999 1229 #define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1230 #define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1231 #define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1232
<> 149:156823d33999 1233 #define ADC_SMPR3_SMP9_Pos (27U)
<> 149:156823d33999 1234 #define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */
<> 149:156823d33999 1235 #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */
<> 149:156823d33999 1236 #define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1237 #define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1238 #define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1239
<> 149:156823d33999 1240 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 149:156823d33999 1241 #define ADC_JOFR1_JOFFSET1_Pos (0U)
<> 149:156823d33999 1242 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1243 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
<> 149:156823d33999 1244
<> 149:156823d33999 1245 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 149:156823d33999 1246 #define ADC_JOFR2_JOFFSET2_Pos (0U)
<> 149:156823d33999 1247 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1248 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
<> 149:156823d33999 1249
<> 149:156823d33999 1250 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 149:156823d33999 1251 #define ADC_JOFR3_JOFFSET3_Pos (0U)
<> 149:156823d33999 1252 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1253 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
<> 149:156823d33999 1254
<> 149:156823d33999 1255 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 149:156823d33999 1256 #define ADC_JOFR4_JOFFSET4_Pos (0U)
<> 149:156823d33999 1257 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1258 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
<> 149:156823d33999 1259
<> 149:156823d33999 1260 /******************* Bit definition for ADC_HTR register ********************/
<> 149:156823d33999 1261 #define ADC_HTR_HT_Pos (0U)
<> 149:156823d33999 1262 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1263 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
<> 149:156823d33999 1264
<> 149:156823d33999 1265 /******************* Bit definition for ADC_LTR register ********************/
<> 149:156823d33999 1266 #define ADC_LTR_LT_Pos (0U)
<> 149:156823d33999 1267 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1268 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
<> 149:156823d33999 1269
<> 149:156823d33999 1270 /******************* Bit definition for ADC_SQR1 register *******************/
<> 149:156823d33999 1271 #define ADC_SQR1_L_Pos (20U)
<> 149:156823d33999 1272 #define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /*!< 0x01F00000 */
<> 149:156823d33999 1273 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
<> 149:156823d33999 1274 #define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1275 #define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1276 #define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1277 #define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1278 #define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1279
<> 149:156823d33999 1280 #define ADC_SQR1_SQ28_Pos (15U)
<> 149:156823d33999 1281 #define ADC_SQR1_SQ28_Msk (0x1FU << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1282 #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */
<> 149:156823d33999 1283 #define ADC_SQR1_SQ28_0 (0x01U << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1284 #define ADC_SQR1_SQ28_1 (0x02U << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1285 #define ADC_SQR1_SQ28_2 (0x04U << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1286 #define ADC_SQR1_SQ28_3 (0x08U << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1287 #define ADC_SQR1_SQ28_4 (0x10U << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1288
<> 149:156823d33999 1289 #define ADC_SQR1_SQ27_Pos (10U)
<> 149:156823d33999 1290 #define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1291 #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */
<> 149:156823d33999 1292 #define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1293 #define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1294 #define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1295 #define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1296 #define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1297
<> 149:156823d33999 1298 #define ADC_SQR1_SQ26_Pos (5U)
<> 149:156823d33999 1299 #define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1300 #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */
<> 149:156823d33999 1301 #define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1302 #define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1303 #define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1304 #define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1305 #define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1306
<> 149:156823d33999 1307 #define ADC_SQR1_SQ25_Pos (0U)
<> 149:156823d33999 1308 #define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1309 #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */
<> 149:156823d33999 1310 #define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1311 #define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1312 #define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1313 #define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1314 #define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1315
<> 149:156823d33999 1316 /******************* Bit definition for ADC_SQR2 register *******************/
<> 149:156823d33999 1317 #define ADC_SQR2_SQ19_Pos (0U)
<> 149:156823d33999 1318 #define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1319 #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */
<> 149:156823d33999 1320 #define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1321 #define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1322 #define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1323 #define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1324 #define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1325
<> 149:156823d33999 1326 #define ADC_SQR2_SQ20_Pos (5U)
<> 149:156823d33999 1327 #define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1328 #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */
<> 149:156823d33999 1329 #define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1330 #define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1331 #define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1332 #define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1333 #define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1334
<> 149:156823d33999 1335 #define ADC_SQR2_SQ21_Pos (10U)
<> 149:156823d33999 1336 #define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1337 #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */
<> 149:156823d33999 1338 #define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1339 #define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1340 #define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1341 #define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1342 #define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1343
<> 149:156823d33999 1344 #define ADC_SQR2_SQ22_Pos (15U)
<> 149:156823d33999 1345 #define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1346 #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */
<> 149:156823d33999 1347 #define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1348 #define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1349 #define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1350 #define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1351 #define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1352
<> 149:156823d33999 1353 #define ADC_SQR2_SQ23_Pos (20U)
<> 149:156823d33999 1354 #define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */
<> 149:156823d33999 1355 #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */
<> 149:156823d33999 1356 #define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1357 #define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1358 #define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1359 #define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1360 #define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1361
<> 149:156823d33999 1362 #define ADC_SQR2_SQ24_Pos (25U)
<> 149:156823d33999 1363 #define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */
<> 149:156823d33999 1364 #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */
<> 149:156823d33999 1365 #define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1366 #define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1367 #define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1368 #define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1369 #define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1370
<> 149:156823d33999 1371 /******************* Bit definition for ADC_SQR3 register *******************/
<> 149:156823d33999 1372 #define ADC_SQR3_SQ13_Pos (0U)
<> 149:156823d33999 1373 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1374 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
<> 149:156823d33999 1375 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1376 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1377 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1378 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1379 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1380
<> 149:156823d33999 1381 #define ADC_SQR3_SQ14_Pos (5U)
<> 149:156823d33999 1382 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1383 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
<> 149:156823d33999 1384 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1385 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1386 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1387 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1388 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1389
<> 149:156823d33999 1390 #define ADC_SQR3_SQ15_Pos (10U)
<> 149:156823d33999 1391 #define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1392 #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
<> 149:156823d33999 1393 #define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1394 #define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1395 #define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1396 #define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1397 #define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1398
<> 149:156823d33999 1399 #define ADC_SQR3_SQ16_Pos (15U)
<> 149:156823d33999 1400 #define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1401 #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
<> 149:156823d33999 1402 #define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1403 #define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1404 #define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1405 #define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1406 #define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1407
<> 149:156823d33999 1408 #define ADC_SQR3_SQ17_Pos (20U)
<> 149:156823d33999 1409 #define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */
<> 149:156823d33999 1410 #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */
<> 149:156823d33999 1411 #define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1412 #define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1413 #define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1414 #define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1415 #define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1416
<> 149:156823d33999 1417 #define ADC_SQR3_SQ18_Pos (25U)
<> 149:156823d33999 1418 #define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */
<> 149:156823d33999 1419 #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */
<> 149:156823d33999 1420 #define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1421 #define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1422 #define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1423 #define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1424 #define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1425
<> 149:156823d33999 1426 /******************* Bit definition for ADC_SQR4 register *******************/
<> 149:156823d33999 1427 #define ADC_SQR4_SQ7_Pos (0U)
<> 149:156823d33999 1428 #define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1429 #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
<> 149:156823d33999 1430 #define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1431 #define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1432 #define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1433 #define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1434 #define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1435
<> 149:156823d33999 1436 #define ADC_SQR4_SQ8_Pos (5U)
<> 149:156823d33999 1437 #define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1438 #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
<> 149:156823d33999 1439 #define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1440 #define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1441 #define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1442 #define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1443 #define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1444
<> 149:156823d33999 1445 #define ADC_SQR4_SQ9_Pos (10U)
<> 149:156823d33999 1446 #define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1447 #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
<> 149:156823d33999 1448 #define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1449 #define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1450 #define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1451 #define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1452 #define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1453
<> 149:156823d33999 1454 #define ADC_SQR4_SQ10_Pos (15U)
<> 149:156823d33999 1455 #define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1456 #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
<> 149:156823d33999 1457 #define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1458 #define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1459 #define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1460 #define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1461 #define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1462
<> 149:156823d33999 1463 #define ADC_SQR4_SQ11_Pos (20U)
<> 149:156823d33999 1464 #define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */
<> 149:156823d33999 1465 #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
<> 149:156823d33999 1466 #define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1467 #define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1468 #define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1469 #define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1470 #define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1471
<> 149:156823d33999 1472 #define ADC_SQR4_SQ12_Pos (25U)
<> 149:156823d33999 1473 #define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */
<> 149:156823d33999 1474 #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
<> 149:156823d33999 1475 #define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1476 #define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1477 #define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1478 #define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1479 #define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1480
<> 149:156823d33999 1481 /******************* Bit definition for ADC_SQR5 register *******************/
<> 149:156823d33999 1482 #define ADC_SQR5_SQ1_Pos (0U)
<> 149:156823d33999 1483 #define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1484 #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
<> 149:156823d33999 1485 #define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1486 #define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1487 #define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1488 #define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1489 #define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1490
<> 149:156823d33999 1491 #define ADC_SQR5_SQ2_Pos (5U)
<> 149:156823d33999 1492 #define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1493 #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
<> 149:156823d33999 1494 #define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1495 #define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1496 #define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1497 #define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1498 #define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1499
<> 149:156823d33999 1500 #define ADC_SQR5_SQ3_Pos (10U)
<> 149:156823d33999 1501 #define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1502 #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
<> 149:156823d33999 1503 #define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1504 #define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1505 #define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1506 #define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1507 #define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1508
<> 149:156823d33999 1509 #define ADC_SQR5_SQ4_Pos (15U)
<> 149:156823d33999 1510 #define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1511 #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
<> 149:156823d33999 1512 #define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1513 #define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1514 #define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1515 #define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1516 #define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1517
<> 149:156823d33999 1518 #define ADC_SQR5_SQ5_Pos (20U)
<> 149:156823d33999 1519 #define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */
<> 149:156823d33999 1520 #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
<> 149:156823d33999 1521 #define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1522 #define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1523 #define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1524 #define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1525 #define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1526
<> 149:156823d33999 1527 #define ADC_SQR5_SQ6_Pos (25U)
<> 149:156823d33999 1528 #define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */
<> 149:156823d33999 1529 #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
<> 149:156823d33999 1530 #define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1531 #define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1532 #define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1533 #define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1534 #define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1535
<> 149:156823d33999 1536
<> 149:156823d33999 1537 /******************* Bit definition for ADC_JSQR register *******************/
<> 149:156823d33999 1538 #define ADC_JSQR_JSQ1_Pos (0U)
<> 149:156823d33999 1539 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1540 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
<> 149:156823d33999 1541 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1542 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1543 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1544 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1545 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1546
<> 149:156823d33999 1547 #define ADC_JSQR_JSQ2_Pos (5U)
<> 149:156823d33999 1548 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1549 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
<> 149:156823d33999 1550 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1551 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1552 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1553 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1554 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1555
<> 149:156823d33999 1556 #define ADC_JSQR_JSQ3_Pos (10U)
<> 149:156823d33999 1557 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1558 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
<> 149:156823d33999 1559 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1560 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1561 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1562 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1563 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1564
<> 149:156823d33999 1565 #define ADC_JSQR_JSQ4_Pos (15U)
<> 149:156823d33999 1566 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1567 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
<> 149:156823d33999 1568 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1569 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1570 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1571 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1572 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1573
<> 149:156823d33999 1574 #define ADC_JSQR_JL_Pos (20U)
<> 149:156823d33999 1575 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
<> 149:156823d33999 1576 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
<> 149:156823d33999 1577 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1578 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1579
<> 149:156823d33999 1580 /******************* Bit definition for ADC_JDR1 register *******************/
<> 149:156823d33999 1581 #define ADC_JDR1_JDATA_Pos (0U)
<> 149:156823d33999 1582 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 1583 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
<> 149:156823d33999 1584
<> 149:156823d33999 1585 /******************* Bit definition for ADC_JDR2 register *******************/
<> 149:156823d33999 1586 #define ADC_JDR2_JDATA_Pos (0U)
<> 149:156823d33999 1587 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 1588 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
<> 149:156823d33999 1589
<> 149:156823d33999 1590 /******************* Bit definition for ADC_JDR3 register *******************/
<> 149:156823d33999 1591 #define ADC_JDR3_JDATA_Pos (0U)
<> 149:156823d33999 1592 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 1593 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
<> 149:156823d33999 1594
<> 149:156823d33999 1595 /******************* Bit definition for ADC_JDR4 register *******************/
<> 149:156823d33999 1596 #define ADC_JDR4_JDATA_Pos (0U)
<> 149:156823d33999 1597 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 1598 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
<> 149:156823d33999 1599
<> 149:156823d33999 1600 /******************** Bit definition for ADC_DR register ********************/
<> 149:156823d33999 1601 #define ADC_DR_DATA_Pos (0U)
<> 149:156823d33999 1602 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 1603 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
<> 149:156823d33999 1604
<> 149:156823d33999 1605 /****************** Bit definition for ADC_SMPR0 register *******************/
<> 149:156823d33999 1606 #define ADC_SMPR0_SMP30_Pos (0U)
<> 149:156823d33999 1607 #define ADC_SMPR0_SMP30_Msk (0x7U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */
<> 149:156823d33999 1608 #define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */
<> 149:156823d33999 1609 #define ADC_SMPR0_SMP30_0 (0x1U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1610 #define ADC_SMPR0_SMP30_1 (0x2U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1611 #define ADC_SMPR0_SMP30_2 (0x4U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1612
<> 149:156823d33999 1613 #define ADC_SMPR0_SMP31_Pos (3U)
<> 149:156823d33999 1614 #define ADC_SMPR0_SMP31_Msk (0x7U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */
<> 149:156823d33999 1615 #define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */
<> 149:156823d33999 1616 #define ADC_SMPR0_SMP31_0 (0x1U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1617 #define ADC_SMPR0_SMP31_1 (0x2U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1618 #define ADC_SMPR0_SMP31_2 (0x4U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1619
<> 149:156823d33999 1620 /******************* Bit definition for ADC_CSR register ********************/
<> 149:156823d33999 1621 #define ADC_CSR_AWD1_Pos (0U)
<> 149:156823d33999 1622 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1623 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */
<> 149:156823d33999 1624 #define ADC_CSR_EOCS1_Pos (1U)
<> 149:156823d33999 1625 #define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1626 #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
<> 149:156823d33999 1627 #define ADC_CSR_JEOS1_Pos (2U)
<> 149:156823d33999 1628 #define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1629 #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
<> 149:156823d33999 1630 #define ADC_CSR_JSTRT1_Pos (3U)
<> 149:156823d33999 1631 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1632 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */
<> 149:156823d33999 1633 #define ADC_CSR_STRT1_Pos (4U)
<> 149:156823d33999 1634 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1635 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */
<> 149:156823d33999 1636 #define ADC_CSR_OVR1_Pos (5U)
<> 149:156823d33999 1637 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1638 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */
<> 149:156823d33999 1639 #define ADC_CSR_ADONS1_Pos (6U)
<> 149:156823d33999 1640 #define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1641 #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */
<> 149:156823d33999 1642
<> 149:156823d33999 1643 /* Legacy defines */
<> 149:156823d33999 1644 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
<> 149:156823d33999 1645 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
<> 149:156823d33999 1646
<> 149:156823d33999 1647 /******************* Bit definition for ADC_CCR register ********************/
<> 149:156823d33999 1648 #define ADC_CCR_ADCPRE_Pos (16U)
<> 149:156823d33999 1649 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
<> 149:156823d33999 1650 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */
<> 149:156823d33999 1651 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1652 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1653 #define ADC_CCR_TSVREFE_Pos (23U)
<> 149:156823d33999 1654 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1655 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
<> 149:156823d33999 1656
<> 149:156823d33999 1657 /******************************************************************************/
<> 149:156823d33999 1658 /* */
<> 149:156823d33999 1659 /* Analog Comparators (COMP) */
<> 149:156823d33999 1660 /* */
<> 149:156823d33999 1661 /******************************************************************************/
<> 149:156823d33999 1662
<> 149:156823d33999 1663 /****************** Bit definition for COMP_CSR register ********************/
<> 149:156823d33999 1664 #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */
<> 149:156823d33999 1665 #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */
<> 149:156823d33999 1666 #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */
<> 149:156823d33999 1667 #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */
<> 149:156823d33999 1668 #define COMP_CSR_CMP1EN_Pos (4U)
<> 149:156823d33999 1669 #define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1670 #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */
<> 149:156823d33999 1671 #define COMP_CSR_CMP1OUT_Pos (7U)
<> 149:156823d33999 1672 #define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1673 #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */
<> 149:156823d33999 1674 #define COMP_CSR_SPEED_Pos (12U)
<> 149:156823d33999 1675 #define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1676 #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */
<> 149:156823d33999 1677 #define COMP_CSR_CMP2OUT_Pos (13U)
<> 149:156823d33999 1678 #define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1679 #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */
<> 149:156823d33999 1680
<> 149:156823d33999 1681 #define COMP_CSR_WNDWE_Pos (17U)
<> 149:156823d33999 1682 #define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1683 #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
<> 149:156823d33999 1684
<> 149:156823d33999 1685 #define COMP_CSR_INSEL_Pos (18U)
<> 149:156823d33999 1686 #define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
<> 149:156823d33999 1687 #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */
<> 149:156823d33999 1688 #define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1689 #define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1690 #define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1691 #define COMP_CSR_OUTSEL_Pos (21U)
<> 149:156823d33999 1692 #define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */
<> 149:156823d33999 1693 #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */
<> 149:156823d33999 1694 #define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1695 #define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1696 #define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1697
<> 149:156823d33999 1698 /* Bits present in COMP register but not related to comparator */
<> 149:156823d33999 1699 /* (or partially related to comparator, in addition to other peripherals) */
<> 149:156823d33999 1700 #define COMP_CSR_SW1_Pos (5U)
<> 149:156823d33999 1701 #define COMP_CSR_SW1_Msk (0x1U << COMP_CSR_SW1_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1702 #define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */
<> 149:156823d33999 1703 #define COMP_CSR_VREFOUTEN_Pos (16U)
<> 149:156823d33999 1704 #define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1705 #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */
<> 149:156823d33999 1706
<> 149:156823d33999 1707 #define COMP_CSR_FCH3_Pos (26U)
<> 149:156823d33999 1708 #define COMP_CSR_FCH3_Msk (0x1U << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1709 #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */
<> 149:156823d33999 1710 #define COMP_CSR_FCH8_Pos (27U)
<> 149:156823d33999 1711 #define COMP_CSR_FCH8_Msk (0x1U << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1712 #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */
<> 149:156823d33999 1713 #define COMP_CSR_RCH13_Pos (28U)
<> 149:156823d33999 1714 #define COMP_CSR_RCH13_Msk (0x1U << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1715 #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */
<> 149:156823d33999 1716
<> 149:156823d33999 1717 #define COMP_CSR_CAIE_Pos (29U)
<> 149:156823d33999 1718 #define COMP_CSR_CAIE_Msk (0x1U << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1719 #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */
<> 149:156823d33999 1720 #define COMP_CSR_CAIF_Pos (30U)
<> 149:156823d33999 1721 #define COMP_CSR_CAIF_Msk (0x1U << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */
<> 149:156823d33999 1722 #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */
<> 149:156823d33999 1723 #define COMP_CSR_TSUSP_Pos (31U)
<> 149:156823d33999 1724 #define COMP_CSR_TSUSP_Msk (0x1U << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */
<> 149:156823d33999 1725 #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */
<> 149:156823d33999 1726
<> 149:156823d33999 1727 /******************************************************************************/
<> 149:156823d33999 1728 /* */
<> 149:156823d33999 1729 /* Operational Amplifier (OPAMP) */
<> 149:156823d33999 1730 /* */
<> 149:156823d33999 1731 /******************************************************************************/
<> 149:156823d33999 1732 /******************* Bit definition for OPAMP_CSR register ******************/
<> 149:156823d33999 1733 #define OPAMP_CSR_OPA1PD_Pos (0U)
<> 149:156823d33999 1734 #define OPAMP_CSR_OPA1PD_Msk (0x1U << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1735 #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */
<> 149:156823d33999 1736 #define OPAMP_CSR_S3SEL1_Pos (1U)
<> 149:156823d33999 1737 #define OPAMP_CSR_S3SEL1_Msk (0x1U << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1738 #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */
<> 149:156823d33999 1739 #define OPAMP_CSR_S4SEL1_Pos (2U)
<> 149:156823d33999 1740 #define OPAMP_CSR_S4SEL1_Msk (0x1U << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1741 #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */
<> 149:156823d33999 1742 #define OPAMP_CSR_S5SEL1_Pos (3U)
<> 149:156823d33999 1743 #define OPAMP_CSR_S5SEL1_Msk (0x1U << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1744 #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */
<> 149:156823d33999 1745 #define OPAMP_CSR_S6SEL1_Pos (4U)
<> 149:156823d33999 1746 #define OPAMP_CSR_S6SEL1_Msk (0x1U << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1747 #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */
<> 149:156823d33999 1748 #define OPAMP_CSR_OPA1CAL_L_Pos (5U)
<> 149:156823d33999 1749 #define OPAMP_CSR_OPA1CAL_L_Msk (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1750 #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */
<> 149:156823d33999 1751 #define OPAMP_CSR_OPA1CAL_H_Pos (6U)
<> 149:156823d33999 1752 #define OPAMP_CSR_OPA1CAL_H_Msk (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1753 #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */
<> 149:156823d33999 1754 #define OPAMP_CSR_OPA1LPM_Pos (7U)
<> 149:156823d33999 1755 #define OPAMP_CSR_OPA1LPM_Msk (0x1U << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1756 #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */
<> 149:156823d33999 1757 #define OPAMP_CSR_OPA2PD_Pos (8U)
<> 149:156823d33999 1758 #define OPAMP_CSR_OPA2PD_Msk (0x1U << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1759 #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */
<> 149:156823d33999 1760 #define OPAMP_CSR_S3SEL2_Pos (9U)
<> 149:156823d33999 1761 #define OPAMP_CSR_S3SEL2_Msk (0x1U << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1762 #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */
<> 149:156823d33999 1763 #define OPAMP_CSR_S4SEL2_Pos (10U)
<> 149:156823d33999 1764 #define OPAMP_CSR_S4SEL2_Msk (0x1U << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1765 #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */
<> 149:156823d33999 1766 #define OPAMP_CSR_S5SEL2_Pos (11U)
<> 149:156823d33999 1767 #define OPAMP_CSR_S5SEL2_Msk (0x1U << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1768 #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */
<> 149:156823d33999 1769 #define OPAMP_CSR_S6SEL2_Pos (12U)
<> 149:156823d33999 1770 #define OPAMP_CSR_S6SEL2_Msk (0x1U << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1771 #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */
<> 149:156823d33999 1772 #define OPAMP_CSR_OPA2CAL_L_Pos (13U)
<> 149:156823d33999 1773 #define OPAMP_CSR_OPA2CAL_L_Msk (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1774 #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */
<> 149:156823d33999 1775 #define OPAMP_CSR_OPA2CAL_H_Pos (14U)
<> 149:156823d33999 1776 #define OPAMP_CSR_OPA2CAL_H_Msk (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
<> 149:156823d33999 1777 #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */
<> 149:156823d33999 1778 #define OPAMP_CSR_OPA2LPM_Pos (15U)
<> 149:156823d33999 1779 #define OPAMP_CSR_OPA2LPM_Msk (0x1U << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */
<> 149:156823d33999 1780 #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */
<> 149:156823d33999 1781 #define OPAMP_CSR_ANAWSEL1_Pos (24U)
<> 149:156823d33999 1782 #define OPAMP_CSR_ANAWSEL1_Msk (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1783 #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */
<> 149:156823d33999 1784 #define OPAMP_CSR_ANAWSEL2_Pos (25U)
<> 149:156823d33999 1785 #define OPAMP_CSR_ANAWSEL2_Msk (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1786 #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */
<> 149:156823d33999 1787 #define OPAMP_CSR_S7SEL2_Pos (27U)
<> 149:156823d33999 1788 #define OPAMP_CSR_S7SEL2_Msk (0x1U << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1789 #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */
<> 149:156823d33999 1790 #define OPAMP_CSR_AOP_RANGE_Pos (28U)
<> 149:156823d33999 1791 #define OPAMP_CSR_AOP_RANGE_Msk (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1792 #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
<> 149:156823d33999 1793 #define OPAMP_CSR_OPA1CALOUT_Pos (29U)
<> 149:156823d33999 1794 #define OPAMP_CSR_OPA1CALOUT_Msk (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1795 #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */
<> 149:156823d33999 1796 #define OPAMP_CSR_OPA2CALOUT_Pos (30U)
<> 149:156823d33999 1797 #define OPAMP_CSR_OPA2CALOUT_Msk (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
<> 149:156823d33999 1798 #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */
<> 149:156823d33999 1799
<> 149:156823d33999 1800 /******************* Bit definition for OPAMP_OTR register ******************/
<> 149:156823d33999 1801 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)
<> 149:156823d33999 1802 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1803 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
<> 149:156823d33999 1804 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)
<> 149:156823d33999 1805 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1806 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
<> 149:156823d33999 1807 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)
<> 149:156823d33999 1808 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1809 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
<> 149:156823d33999 1810 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)
<> 149:156823d33999 1811 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1812 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
<> 149:156823d33999 1813 #define OPAMP_OTR_OT_USER_Pos (31U)
<> 149:156823d33999 1814 #define OPAMP_OTR_OT_USER_Msk (0x1U << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */
<> 149:156823d33999 1815 #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */
<> 149:156823d33999 1816
<> 149:156823d33999 1817 /******************* Bit definition for OPAMP_LPOTR register ****************/
<> 149:156823d33999 1818 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)
<> 149:156823d33999 1819 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
<> 149:156823d33999 1820 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
<> 149:156823d33999 1821 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)
<> 149:156823d33999 1822 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
<> 149:156823d33999 1823 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
<> 149:156823d33999 1824 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)
<> 149:156823d33999 1825 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 1826 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
<> 149:156823d33999 1827 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)
<> 149:156823d33999 1828 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
<> 149:156823d33999 1829 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
<> 149:156823d33999 1830
<> 149:156823d33999 1831 /******************************************************************************/
<> 149:156823d33999 1832 /* */
<> 149:156823d33999 1833 /* CRC calculation unit (CRC) */
<> 149:156823d33999 1834 /* */
<> 149:156823d33999 1835 /******************************************************************************/
<> 149:156823d33999 1836
<> 149:156823d33999 1837 /******************* Bit definition for CRC_DR register *********************/
<> 149:156823d33999 1838 #define CRC_DR_DR_Pos (0U)
<> 149:156823d33999 1839 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 1840 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 149:156823d33999 1841
<> 149:156823d33999 1842 /******************* Bit definition for CRC_IDR register ********************/
<> 149:156823d33999 1843 #define CRC_IDR_IDR_Pos (0U)
<> 149:156823d33999 1844 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
<> 149:156823d33999 1845 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
<> 149:156823d33999 1846
<> 149:156823d33999 1847 /******************** Bit definition for CRC_CR register ********************/
<> 149:156823d33999 1848 #define CRC_CR_RESET_Pos (0U)
<> 149:156823d33999 1849 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1850 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
<> 149:156823d33999 1851
<> 149:156823d33999 1852 /******************************************************************************/
<> 149:156823d33999 1853 /* */
<> 149:156823d33999 1854 /* Digital to Analog Converter (DAC) */
<> 149:156823d33999 1855 /* */
<> 149:156823d33999 1856 /******************************************************************************/
<> 149:156823d33999 1857
<> 149:156823d33999 1858 /******************** Bit definition for DAC_CR register ********************/
<> 149:156823d33999 1859 #define DAC_CR_EN1_Pos (0U)
<> 149:156823d33999 1860 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1861 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
<> 149:156823d33999 1862 #define DAC_CR_BOFF1_Pos (1U)
<> 149:156823d33999 1863 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1864 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
<> 149:156823d33999 1865 #define DAC_CR_TEN1_Pos (2U)
<> 149:156823d33999 1866 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 1867 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
<> 149:156823d33999 1868
<> 149:156823d33999 1869 #define DAC_CR_TSEL1_Pos (3U)
<> 149:156823d33999 1870 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
<> 149:156823d33999 1871 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 149:156823d33999 1872 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 1873 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
<> 149:156823d33999 1874 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
<> 149:156823d33999 1875
<> 149:156823d33999 1876 #define DAC_CR_WAVE1_Pos (6U)
<> 149:156823d33999 1877 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
<> 149:156823d33999 1878 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 149:156823d33999 1879 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
<> 149:156823d33999 1880 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
<> 149:156823d33999 1881
<> 149:156823d33999 1882 #define DAC_CR_MAMP1_Pos (8U)
<> 149:156823d33999 1883 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 1884 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 149:156823d33999 1885 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
<> 149:156823d33999 1886 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
<> 149:156823d33999 1887 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
<> 149:156823d33999 1888 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
<> 149:156823d33999 1889
<> 149:156823d33999 1890 #define DAC_CR_DMAEN1_Pos (12U)
<> 149:156823d33999 1891 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
<> 149:156823d33999 1892 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
<> 149:156823d33999 1893 #define DAC_CR_DMAUDRIE1_Pos (13U)
<> 149:156823d33999 1894 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
<> 149:156823d33999 1895 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */
<> 149:156823d33999 1896 #define DAC_CR_EN2_Pos (16U)
<> 149:156823d33999 1897 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
<> 149:156823d33999 1898 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
<> 149:156823d33999 1899 #define DAC_CR_BOFF2_Pos (17U)
<> 149:156823d33999 1900 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
<> 149:156823d33999 1901 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
<> 149:156823d33999 1902 #define DAC_CR_TEN2_Pos (18U)
<> 149:156823d33999 1903 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
<> 149:156823d33999 1904 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
<> 149:156823d33999 1905
<> 149:156823d33999 1906 #define DAC_CR_TSEL2_Pos (19U)
<> 149:156823d33999 1907 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
<> 149:156823d33999 1908 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 149:156823d33999 1909 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
<> 149:156823d33999 1910 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
<> 149:156823d33999 1911 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
<> 149:156823d33999 1912
<> 149:156823d33999 1913 #define DAC_CR_WAVE2_Pos (22U)
<> 149:156823d33999 1914 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
<> 149:156823d33999 1915 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 149:156823d33999 1916 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
<> 149:156823d33999 1917 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
<> 149:156823d33999 1918
<> 149:156823d33999 1919 #define DAC_CR_MAMP2_Pos (24U)
<> 149:156823d33999 1920 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
<> 149:156823d33999 1921 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 149:156823d33999 1922 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
<> 149:156823d33999 1923 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
<> 149:156823d33999 1924 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
<> 149:156823d33999 1925 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
<> 149:156823d33999 1926
<> 149:156823d33999 1927 #define DAC_CR_DMAEN2_Pos (28U)
<> 149:156823d33999 1928 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
<> 149:156823d33999 1929 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
<> 149:156823d33999 1930 #define DAC_CR_DMAUDRIE2_Pos (29U)
<> 149:156823d33999 1931 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
<> 149:156823d33999 1932 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
<> 149:156823d33999 1933 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 149:156823d33999 1934 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
<> 149:156823d33999 1935 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
<> 149:156823d33999 1936 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
<> 149:156823d33999 1937 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
<> 149:156823d33999 1938 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
<> 149:156823d33999 1939 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
<> 149:156823d33999 1940
<> 149:156823d33999 1941 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 149:156823d33999 1942 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
<> 149:156823d33999 1943 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1944 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 149:156823d33999 1945
<> 149:156823d33999 1946 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 149:156823d33999 1947 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
<> 149:156823d33999 1948 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 149:156823d33999 1949 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 149:156823d33999 1950
<> 149:156823d33999 1951 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 149:156823d33999 1952 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
<> 149:156823d33999 1953 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
<> 149:156823d33999 1954 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 149:156823d33999 1955
<> 149:156823d33999 1956 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 149:156823d33999 1957 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
<> 149:156823d33999 1958 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1959 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 149:156823d33999 1960
<> 149:156823d33999 1961 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 149:156823d33999 1962 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
<> 149:156823d33999 1963 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
<> 149:156823d33999 1964 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 149:156823d33999 1965
<> 149:156823d33999 1966 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 149:156823d33999 1967 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
<> 149:156823d33999 1968 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
<> 149:156823d33999 1969 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 149:156823d33999 1970
<> 149:156823d33999 1971 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 149:156823d33999 1972 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
<> 149:156823d33999 1973 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1974 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 149:156823d33999 1975 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
<> 149:156823d33999 1976 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
<> 149:156823d33999 1977 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 149:156823d33999 1978
<> 149:156823d33999 1979 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 149:156823d33999 1980 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
<> 149:156823d33999 1981 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 149:156823d33999 1982 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 149:156823d33999 1983 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
<> 149:156823d33999 1984 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
<> 149:156823d33999 1985 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 149:156823d33999 1986
<> 149:156823d33999 1987 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 149:156823d33999 1988 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
<> 149:156823d33999 1989 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
<> 149:156823d33999 1990 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 149:156823d33999 1991 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
<> 149:156823d33999 1992 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
<> 149:156823d33999 1993 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 149:156823d33999 1994
<> 149:156823d33999 1995 /******************* Bit definition for DAC_DOR1 register *******************/
<> 149:156823d33999 1996 #define DAC_DOR1_DACC1DOR_Pos (0U)
<> 149:156823d33999 1997 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 1998 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
<> 149:156823d33999 1999
<> 149:156823d33999 2000 /******************* Bit definition for DAC_DOR2 register *******************/
<> 149:156823d33999 2001 #define DAC_DOR2_DACC2DOR_Pos (0U)
<> 149:156823d33999 2002 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 2003 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
<> 149:156823d33999 2004
<> 149:156823d33999 2005 /******************** Bit definition for DAC_SR register ********************/
<> 149:156823d33999 2006 #define DAC_SR_DMAUDR1_Pos (13U)
<> 149:156823d33999 2007 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2008 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
<> 149:156823d33999 2009 #define DAC_SR_DMAUDR2_Pos (29U)
<> 149:156823d33999 2010 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
<> 149:156823d33999 2011 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
<> 149:156823d33999 2012
<> 149:156823d33999 2013 /******************************************************************************/
<> 149:156823d33999 2014 /* */
<> 149:156823d33999 2015 /* Debug MCU (DBGMCU) */
<> 149:156823d33999 2016 /* */
<> 149:156823d33999 2017 /******************************************************************************/
<> 149:156823d33999 2018
<> 149:156823d33999 2019 /**************** Bit definition for DBGMCU_IDCODE register *****************/
<> 149:156823d33999 2020 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
<> 149:156823d33999 2021 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 2022 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
<> 149:156823d33999 2023
<> 149:156823d33999 2024 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
<> 149:156823d33999 2025 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
<> 149:156823d33999 2026 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
<> 149:156823d33999 2027 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2028 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2029 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2030 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2031 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2032 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2033 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2034 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2035 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
<> 149:156823d33999 2036 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
<> 149:156823d33999 2037 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
<> 149:156823d33999 2038 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
<> 149:156823d33999 2039 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
<> 149:156823d33999 2040 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
<> 149:156823d33999 2041 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
<> 149:156823d33999 2042 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
<> 149:156823d33999 2043
<> 149:156823d33999 2044 /****************** Bit definition for DBGMCU_CR register *******************/
<> 149:156823d33999 2045 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
<> 149:156823d33999 2046 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2047 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
<> 149:156823d33999 2048 #define DBGMCU_CR_DBG_STOP_Pos (1U)
<> 149:156823d33999 2049 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2050 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
<> 149:156823d33999 2051 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
<> 149:156823d33999 2052 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2053 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
<> 149:156823d33999 2054 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
<> 149:156823d33999 2055 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2056 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
<> 149:156823d33999 2057
<> 149:156823d33999 2058 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
<> 149:156823d33999 2059 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
<> 149:156823d33999 2060 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
<> 149:156823d33999 2061 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2062 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2063
<> 149:156823d33999 2064 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
<> 149:156823d33999 2065
<> 149:156823d33999 2066 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
<> 149:156823d33999 2067 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2068 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
<> 149:156823d33999 2069 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
<> 149:156823d33999 2070 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2071 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
<> 149:156823d33999 2072 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
<> 149:156823d33999 2073 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2074 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
<> 149:156823d33999 2075 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
<> 149:156823d33999 2076 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2077 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
<> 149:156823d33999 2078 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
<> 149:156823d33999 2079 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2080 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
<> 149:156823d33999 2081 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
<> 149:156823d33999 2082 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2083 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
<> 149:156823d33999 2084 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
<> 149:156823d33999 2085 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2086 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
<> 149:156823d33999 2087 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
<> 149:156823d33999 2088 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2089 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
<> 149:156823d33999 2090 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
<> 149:156823d33999 2091 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2092 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
<> 149:156823d33999 2093 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
<> 149:156823d33999 2094 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2095 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
<> 149:156823d33999 2096 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
<> 149:156823d33999 2097 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2098 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
<> 149:156823d33999 2099
<> 149:156823d33999 2100 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
<> 149:156823d33999 2101
<> 149:156823d33999 2102 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U)
<> 149:156823d33999 2103 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2104 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
<> 149:156823d33999 2105 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U)
<> 149:156823d33999 2106 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2107 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
<> 149:156823d33999 2108 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U)
<> 149:156823d33999 2109 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2110 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
<> 149:156823d33999 2111
<> 149:156823d33999 2112 /******************************************************************************/
<> 149:156823d33999 2113 /* */
<> 149:156823d33999 2114 /* DMA Controller (DMA) */
<> 149:156823d33999 2115 /* */
<> 149:156823d33999 2116 /******************************************************************************/
<> 149:156823d33999 2117
<> 149:156823d33999 2118 /******************* Bit definition for DMA_ISR register ********************/
<> 149:156823d33999 2119 #define DMA_ISR_GIF1_Pos (0U)
<> 149:156823d33999 2120 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2121 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
<> 149:156823d33999 2122 #define DMA_ISR_TCIF1_Pos (1U)
<> 149:156823d33999 2123 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2124 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
<> 149:156823d33999 2125 #define DMA_ISR_HTIF1_Pos (2U)
<> 149:156823d33999 2126 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2127 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
<> 149:156823d33999 2128 #define DMA_ISR_TEIF1_Pos (3U)
<> 149:156823d33999 2129 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2130 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
<> 149:156823d33999 2131 #define DMA_ISR_GIF2_Pos (4U)
<> 149:156823d33999 2132 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2133 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
<> 149:156823d33999 2134 #define DMA_ISR_TCIF2_Pos (5U)
<> 149:156823d33999 2135 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2136 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
<> 149:156823d33999 2137 #define DMA_ISR_HTIF2_Pos (6U)
<> 149:156823d33999 2138 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2139 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
<> 149:156823d33999 2140 #define DMA_ISR_TEIF2_Pos (7U)
<> 149:156823d33999 2141 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2142 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
<> 149:156823d33999 2143 #define DMA_ISR_GIF3_Pos (8U)
<> 149:156823d33999 2144 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2145 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
<> 149:156823d33999 2146 #define DMA_ISR_TCIF3_Pos (9U)
<> 149:156823d33999 2147 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2148 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
<> 149:156823d33999 2149 #define DMA_ISR_HTIF3_Pos (10U)
<> 149:156823d33999 2150 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2151 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
<> 149:156823d33999 2152 #define DMA_ISR_TEIF3_Pos (11U)
<> 149:156823d33999 2153 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2154 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
<> 149:156823d33999 2155 #define DMA_ISR_GIF4_Pos (12U)
<> 149:156823d33999 2156 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2157 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
<> 149:156823d33999 2158 #define DMA_ISR_TCIF4_Pos (13U)
<> 149:156823d33999 2159 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2160 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
<> 149:156823d33999 2161 #define DMA_ISR_HTIF4_Pos (14U)
<> 149:156823d33999 2162 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2163 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
<> 149:156823d33999 2164 #define DMA_ISR_TEIF4_Pos (15U)
<> 149:156823d33999 2165 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
<> 149:156823d33999 2166 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
<> 149:156823d33999 2167 #define DMA_ISR_GIF5_Pos (16U)
<> 149:156823d33999 2168 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2169 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
<> 149:156823d33999 2170 #define DMA_ISR_TCIF5_Pos (17U)
<> 149:156823d33999 2171 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2172 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
<> 149:156823d33999 2173 #define DMA_ISR_HTIF5_Pos (18U)
<> 149:156823d33999 2174 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2175 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
<> 149:156823d33999 2176 #define DMA_ISR_TEIF5_Pos (19U)
<> 149:156823d33999 2177 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2178 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
<> 149:156823d33999 2179 #define DMA_ISR_GIF6_Pos (20U)
<> 149:156823d33999 2180 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2181 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
<> 149:156823d33999 2182 #define DMA_ISR_TCIF6_Pos (21U)
<> 149:156823d33999 2183 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2184 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
<> 149:156823d33999 2185 #define DMA_ISR_HTIF6_Pos (22U)
<> 149:156823d33999 2186 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2187 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
<> 149:156823d33999 2188 #define DMA_ISR_TEIF6_Pos (23U)
<> 149:156823d33999 2189 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2190 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
<> 149:156823d33999 2191 #define DMA_ISR_GIF7_Pos (24U)
<> 149:156823d33999 2192 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
<> 149:156823d33999 2193 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
<> 149:156823d33999 2194 #define DMA_ISR_TCIF7_Pos (25U)
<> 149:156823d33999 2195 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
<> 149:156823d33999 2196 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
<> 149:156823d33999 2197 #define DMA_ISR_HTIF7_Pos (26U)
<> 149:156823d33999 2198 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
<> 149:156823d33999 2199 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
<> 149:156823d33999 2200 #define DMA_ISR_TEIF7_Pos (27U)
<> 149:156823d33999 2201 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
<> 149:156823d33999 2202 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
<> 149:156823d33999 2203
<> 149:156823d33999 2204 /******************* Bit definition for DMA_IFCR register *******************/
<> 149:156823d33999 2205 #define DMA_IFCR_CGIF1_Pos (0U)
<> 149:156823d33999 2206 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2207 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
<> 149:156823d33999 2208 #define DMA_IFCR_CTCIF1_Pos (1U)
<> 149:156823d33999 2209 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2210 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
<> 149:156823d33999 2211 #define DMA_IFCR_CHTIF1_Pos (2U)
<> 149:156823d33999 2212 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2213 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
<> 149:156823d33999 2214 #define DMA_IFCR_CTEIF1_Pos (3U)
<> 149:156823d33999 2215 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2216 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
<> 149:156823d33999 2217 #define DMA_IFCR_CGIF2_Pos (4U)
<> 149:156823d33999 2218 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2219 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
<> 149:156823d33999 2220 #define DMA_IFCR_CTCIF2_Pos (5U)
<> 149:156823d33999 2221 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2222 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
<> 149:156823d33999 2223 #define DMA_IFCR_CHTIF2_Pos (6U)
<> 149:156823d33999 2224 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2225 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
<> 149:156823d33999 2226 #define DMA_IFCR_CTEIF2_Pos (7U)
<> 149:156823d33999 2227 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2228 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
<> 149:156823d33999 2229 #define DMA_IFCR_CGIF3_Pos (8U)
<> 149:156823d33999 2230 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2231 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
<> 149:156823d33999 2232 #define DMA_IFCR_CTCIF3_Pos (9U)
<> 149:156823d33999 2233 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2234 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
<> 149:156823d33999 2235 #define DMA_IFCR_CHTIF3_Pos (10U)
<> 149:156823d33999 2236 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2237 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
<> 149:156823d33999 2238 #define DMA_IFCR_CTEIF3_Pos (11U)
<> 149:156823d33999 2239 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2240 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
<> 149:156823d33999 2241 #define DMA_IFCR_CGIF4_Pos (12U)
<> 149:156823d33999 2242 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2243 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
<> 149:156823d33999 2244 #define DMA_IFCR_CTCIF4_Pos (13U)
<> 149:156823d33999 2245 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2246 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
<> 149:156823d33999 2247 #define DMA_IFCR_CHTIF4_Pos (14U)
<> 149:156823d33999 2248 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2249 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
<> 149:156823d33999 2250 #define DMA_IFCR_CTEIF4_Pos (15U)
<> 149:156823d33999 2251 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
<> 149:156823d33999 2252 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
<> 149:156823d33999 2253 #define DMA_IFCR_CGIF5_Pos (16U)
<> 149:156823d33999 2254 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2255 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
<> 149:156823d33999 2256 #define DMA_IFCR_CTCIF5_Pos (17U)
<> 149:156823d33999 2257 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2258 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
<> 149:156823d33999 2259 #define DMA_IFCR_CHTIF5_Pos (18U)
<> 149:156823d33999 2260 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2261 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
<> 149:156823d33999 2262 #define DMA_IFCR_CTEIF5_Pos (19U)
<> 149:156823d33999 2263 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2264 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
<> 149:156823d33999 2265 #define DMA_IFCR_CGIF6_Pos (20U)
<> 149:156823d33999 2266 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2267 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
<> 149:156823d33999 2268 #define DMA_IFCR_CTCIF6_Pos (21U)
<> 149:156823d33999 2269 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2270 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
<> 149:156823d33999 2271 #define DMA_IFCR_CHTIF6_Pos (22U)
<> 149:156823d33999 2272 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2273 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
<> 149:156823d33999 2274 #define DMA_IFCR_CTEIF6_Pos (23U)
<> 149:156823d33999 2275 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2276 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
<> 149:156823d33999 2277 #define DMA_IFCR_CGIF7_Pos (24U)
<> 149:156823d33999 2278 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
<> 149:156823d33999 2279 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
<> 149:156823d33999 2280 #define DMA_IFCR_CTCIF7_Pos (25U)
<> 149:156823d33999 2281 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
<> 149:156823d33999 2282 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
<> 149:156823d33999 2283 #define DMA_IFCR_CHTIF7_Pos (26U)
<> 149:156823d33999 2284 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
<> 149:156823d33999 2285 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
<> 149:156823d33999 2286 #define DMA_IFCR_CTEIF7_Pos (27U)
<> 149:156823d33999 2287 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
<> 149:156823d33999 2288 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
<> 149:156823d33999 2289
<> 149:156823d33999 2290 /******************* Bit definition for DMA_CCR register *******************/
<> 149:156823d33999 2291 #define DMA_CCR_EN_Pos (0U)
<> 149:156823d33999 2292 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2293 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/
<> 149:156823d33999 2294 #define DMA_CCR_TCIE_Pos (1U)
<> 149:156823d33999 2295 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2296 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 149:156823d33999 2297 #define DMA_CCR_HTIE_Pos (2U)
<> 149:156823d33999 2298 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2299 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
<> 149:156823d33999 2300 #define DMA_CCR_TEIE_Pos (3U)
<> 149:156823d33999 2301 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2302 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
<> 149:156823d33999 2303 #define DMA_CCR_DIR_Pos (4U)
<> 149:156823d33999 2304 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2305 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
<> 149:156823d33999 2306 #define DMA_CCR_CIRC_Pos (5U)
<> 149:156823d33999 2307 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2308 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
<> 149:156823d33999 2309 #define DMA_CCR_PINC_Pos (6U)
<> 149:156823d33999 2310 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2311 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
<> 149:156823d33999 2312 #define DMA_CCR_MINC_Pos (7U)
<> 149:156823d33999 2313 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2314 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
<> 149:156823d33999 2315
<> 149:156823d33999 2316 #define DMA_CCR_PSIZE_Pos (8U)
<> 149:156823d33999 2317 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
<> 149:156823d33999 2318 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
<> 149:156823d33999 2319 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2320 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2321
<> 149:156823d33999 2322 #define DMA_CCR_MSIZE_Pos (10U)
<> 149:156823d33999 2323 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
<> 149:156823d33999 2324 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
<> 149:156823d33999 2325 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2326 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2327
<> 149:156823d33999 2328 #define DMA_CCR_PL_Pos (12U)
<> 149:156823d33999 2329 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
<> 149:156823d33999 2330 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
<> 149:156823d33999 2331 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2332 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2333
<> 149:156823d33999 2334 #define DMA_CCR_MEM2MEM_Pos (14U)
<> 149:156823d33999 2335 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2336 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
<> 149:156823d33999 2337
<> 149:156823d33999 2338 /****************** Bit definition generic for DMA_CNDTR register *******************/
<> 149:156823d33999 2339 #define DMA_CNDTR_NDT_Pos (0U)
<> 149:156823d33999 2340 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2341 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2342
<> 149:156823d33999 2343 /****************** Bit definition for DMA_CNDTR1 register ******************/
<> 149:156823d33999 2344 #define DMA_CNDTR1_NDT_Pos (0U)
<> 149:156823d33999 2345 #define DMA_CNDTR1_NDT_Msk (0xFFFFU << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2346 #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2347
<> 149:156823d33999 2348 /****************** Bit definition for DMA_CNDTR2 register ******************/
<> 149:156823d33999 2349 #define DMA_CNDTR2_NDT_Pos (0U)
<> 149:156823d33999 2350 #define DMA_CNDTR2_NDT_Msk (0xFFFFU << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2351 #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2352
<> 149:156823d33999 2353 /****************** Bit definition for DMA_CNDTR3 register ******************/
<> 149:156823d33999 2354 #define DMA_CNDTR3_NDT_Pos (0U)
<> 149:156823d33999 2355 #define DMA_CNDTR3_NDT_Msk (0xFFFFU << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2356 #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2357
<> 149:156823d33999 2358 /****************** Bit definition for DMA_CNDTR4 register ******************/
<> 149:156823d33999 2359 #define DMA_CNDTR4_NDT_Pos (0U)
<> 149:156823d33999 2360 #define DMA_CNDTR4_NDT_Msk (0xFFFFU << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2361 #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2362
<> 149:156823d33999 2363 /****************** Bit definition for DMA_CNDTR5 register ******************/
<> 149:156823d33999 2364 #define DMA_CNDTR5_NDT_Pos (0U)
<> 149:156823d33999 2365 #define DMA_CNDTR5_NDT_Msk (0xFFFFU << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2366 #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2367
<> 149:156823d33999 2368 /****************** Bit definition for DMA_CNDTR6 register ******************/
<> 149:156823d33999 2369 #define DMA_CNDTR6_NDT_Pos (0U)
<> 149:156823d33999 2370 #define DMA_CNDTR6_NDT_Msk (0xFFFFU << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2371 #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2372
<> 149:156823d33999 2373 /****************** Bit definition for DMA_CNDTR7 register ******************/
<> 149:156823d33999 2374 #define DMA_CNDTR7_NDT_Pos (0U)
<> 149:156823d33999 2375 #define DMA_CNDTR7_NDT_Msk (0xFFFFU << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 2376 #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */
<> 149:156823d33999 2377
<> 149:156823d33999 2378 /****************** Bit definition generic for DMA_CPAR register ********************/
<> 149:156823d33999 2379 #define DMA_CPAR_PA_Pos (0U)
<> 149:156823d33999 2380 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2381 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2382
<> 149:156823d33999 2383 /****************** Bit definition for DMA_CPAR1 register *******************/
<> 149:156823d33999 2384 #define DMA_CPAR1_PA_Pos (0U)
<> 149:156823d33999 2385 #define DMA_CPAR1_PA_Msk (0xFFFFFFFFU << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2386 #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2387
<> 149:156823d33999 2388 /****************** Bit definition for DMA_CPAR2 register *******************/
<> 149:156823d33999 2389 #define DMA_CPAR2_PA_Pos (0U)
<> 149:156823d33999 2390 #define DMA_CPAR2_PA_Msk (0xFFFFFFFFU << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2391 #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2392
<> 149:156823d33999 2393 /****************** Bit definition for DMA_CPAR3 register *******************/
<> 149:156823d33999 2394 #define DMA_CPAR3_PA_Pos (0U)
<> 149:156823d33999 2395 #define DMA_CPAR3_PA_Msk (0xFFFFFFFFU << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2396 #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2397
<> 149:156823d33999 2398
<> 149:156823d33999 2399 /****************** Bit definition for DMA_CPAR4 register *******************/
<> 149:156823d33999 2400 #define DMA_CPAR4_PA_Pos (0U)
<> 149:156823d33999 2401 #define DMA_CPAR4_PA_Msk (0xFFFFFFFFU << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2402 #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2403
<> 149:156823d33999 2404 /****************** Bit definition for DMA_CPAR5 register *******************/
<> 149:156823d33999 2405 #define DMA_CPAR5_PA_Pos (0U)
<> 149:156823d33999 2406 #define DMA_CPAR5_PA_Msk (0xFFFFFFFFU << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2407 #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2408
<> 149:156823d33999 2409 /****************** Bit definition for DMA_CPAR6 register *******************/
<> 149:156823d33999 2410 #define DMA_CPAR6_PA_Pos (0U)
<> 149:156823d33999 2411 #define DMA_CPAR6_PA_Msk (0xFFFFFFFFU << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2412 #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2413
<> 149:156823d33999 2414
<> 149:156823d33999 2415 /****************** Bit definition for DMA_CPAR7 register *******************/
<> 149:156823d33999 2416 #define DMA_CPAR7_PA_Pos (0U)
<> 149:156823d33999 2417 #define DMA_CPAR7_PA_Msk (0xFFFFFFFFU << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2418 #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */
<> 149:156823d33999 2419
<> 149:156823d33999 2420 /****************** Bit definition generic for DMA_CMAR register ********************/
<> 149:156823d33999 2421 #define DMA_CMAR_MA_Pos (0U)
<> 149:156823d33999 2422 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2423 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2424
<> 149:156823d33999 2425 /****************** Bit definition for DMA_CMAR1 register *******************/
<> 149:156823d33999 2426 #define DMA_CMAR1_MA_Pos (0U)
<> 149:156823d33999 2427 #define DMA_CMAR1_MA_Msk (0xFFFFFFFFU << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2428 #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2429
<> 149:156823d33999 2430 /****************** Bit definition for DMA_CMAR2 register *******************/
<> 149:156823d33999 2431 #define DMA_CMAR2_MA_Pos (0U)
<> 149:156823d33999 2432 #define DMA_CMAR2_MA_Msk (0xFFFFFFFFU << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2433 #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2434
<> 149:156823d33999 2435 /****************** Bit definition for DMA_CMAR3 register *******************/
<> 149:156823d33999 2436 #define DMA_CMAR3_MA_Pos (0U)
<> 149:156823d33999 2437 #define DMA_CMAR3_MA_Msk (0xFFFFFFFFU << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2438 #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2439
<> 149:156823d33999 2440
<> 149:156823d33999 2441 /****************** Bit definition for DMA_CMAR4 register *******************/
<> 149:156823d33999 2442 #define DMA_CMAR4_MA_Pos (0U)
<> 149:156823d33999 2443 #define DMA_CMAR4_MA_Msk (0xFFFFFFFFU << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2444 #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2445
<> 149:156823d33999 2446 /****************** Bit definition for DMA_CMAR5 register *******************/
<> 149:156823d33999 2447 #define DMA_CMAR5_MA_Pos (0U)
<> 149:156823d33999 2448 #define DMA_CMAR5_MA_Msk (0xFFFFFFFFU << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2449 #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2450
<> 149:156823d33999 2451 /****************** Bit definition for DMA_CMAR6 register *******************/
<> 149:156823d33999 2452 #define DMA_CMAR6_MA_Pos (0U)
<> 149:156823d33999 2453 #define DMA_CMAR6_MA_Msk (0xFFFFFFFFU << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2454 #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2455
<> 149:156823d33999 2456 /****************** Bit definition for DMA_CMAR7 register *******************/
<> 149:156823d33999 2457 #define DMA_CMAR7_MA_Pos (0U)
<> 149:156823d33999 2458 #define DMA_CMAR7_MA_Msk (0xFFFFFFFFU << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 2459 #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */
<> 149:156823d33999 2460
<> 149:156823d33999 2461 /******************************************************************************/
<> 149:156823d33999 2462 /* */
<> 149:156823d33999 2463 /* External Interrupt/Event Controller (EXTI) */
<> 149:156823d33999 2464 /* */
<> 149:156823d33999 2465 /******************************************************************************/
<> 149:156823d33999 2466
<> 149:156823d33999 2467 /******************* Bit definition for EXTI_IMR register *******************/
<> 149:156823d33999 2468 #define EXTI_IMR_MR0_Pos (0U)
<> 149:156823d33999 2469 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2470 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
<> 149:156823d33999 2471 #define EXTI_IMR_MR1_Pos (1U)
<> 149:156823d33999 2472 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2473 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
<> 149:156823d33999 2474 #define EXTI_IMR_MR2_Pos (2U)
<> 149:156823d33999 2475 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2476 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
<> 149:156823d33999 2477 #define EXTI_IMR_MR3_Pos (3U)
<> 149:156823d33999 2478 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2479 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
<> 149:156823d33999 2480 #define EXTI_IMR_MR4_Pos (4U)
<> 149:156823d33999 2481 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2482 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
<> 149:156823d33999 2483 #define EXTI_IMR_MR5_Pos (5U)
<> 149:156823d33999 2484 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2485 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
<> 149:156823d33999 2486 #define EXTI_IMR_MR6_Pos (6U)
<> 149:156823d33999 2487 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2488 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
<> 149:156823d33999 2489 #define EXTI_IMR_MR7_Pos (7U)
<> 149:156823d33999 2490 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2491 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
<> 149:156823d33999 2492 #define EXTI_IMR_MR8_Pos (8U)
<> 149:156823d33999 2493 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2494 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
<> 149:156823d33999 2495 #define EXTI_IMR_MR9_Pos (9U)
<> 149:156823d33999 2496 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2497 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
<> 149:156823d33999 2498 #define EXTI_IMR_MR10_Pos (10U)
<> 149:156823d33999 2499 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2500 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
<> 149:156823d33999 2501 #define EXTI_IMR_MR11_Pos (11U)
<> 149:156823d33999 2502 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2503 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
<> 149:156823d33999 2504 #define EXTI_IMR_MR12_Pos (12U)
<> 149:156823d33999 2505 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2506 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
<> 149:156823d33999 2507 #define EXTI_IMR_MR13_Pos (13U)
<> 149:156823d33999 2508 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2509 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
<> 149:156823d33999 2510 #define EXTI_IMR_MR14_Pos (14U)
<> 149:156823d33999 2511 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2512 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
<> 149:156823d33999 2513 #define EXTI_IMR_MR15_Pos (15U)
<> 149:156823d33999 2514 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 2515 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
<> 149:156823d33999 2516 #define EXTI_IMR_MR16_Pos (16U)
<> 149:156823d33999 2517 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2518 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
<> 149:156823d33999 2519 #define EXTI_IMR_MR17_Pos (17U)
<> 149:156823d33999 2520 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2521 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
<> 149:156823d33999 2522 #define EXTI_IMR_MR18_Pos (18U)
<> 149:156823d33999 2523 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2524 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
<> 149:156823d33999 2525 #define EXTI_IMR_MR19_Pos (19U)
<> 149:156823d33999 2526 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2527 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
<> 149:156823d33999 2528 #define EXTI_IMR_MR20_Pos (20U)
<> 149:156823d33999 2529 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2530 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
<> 149:156823d33999 2531 #define EXTI_IMR_MR21_Pos (21U)
<> 149:156823d33999 2532 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2533 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
<> 149:156823d33999 2534 #define EXTI_IMR_MR22_Pos (22U)
<> 149:156823d33999 2535 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2536 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
<> 149:156823d33999 2537 #define EXTI_IMR_MR23_Pos (23U)
<> 149:156823d33999 2538 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2539 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
<> 149:156823d33999 2540
<> 149:156823d33999 2541 /* References Defines */
<> 149:156823d33999 2542 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 149:156823d33999 2543 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 149:156823d33999 2544 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 149:156823d33999 2545 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 149:156823d33999 2546 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 149:156823d33999 2547 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 149:156823d33999 2548 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 149:156823d33999 2549 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 149:156823d33999 2550 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 149:156823d33999 2551 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 149:156823d33999 2552 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 149:156823d33999 2553 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 149:156823d33999 2554 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 149:156823d33999 2555 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 149:156823d33999 2556 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 149:156823d33999 2557 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 149:156823d33999 2558 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 149:156823d33999 2559 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 149:156823d33999 2560 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 149:156823d33999 2561 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 149:156823d33999 2562 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 149:156823d33999 2563 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 149:156823d33999 2564 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 149:156823d33999 2565 /* Category 3, 4 & 5 */
<> 149:156823d33999 2566 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 149:156823d33999 2567 #define EXTI_IMR_IM_Pos (0U)
<> 149:156823d33999 2568 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
<> 149:156823d33999 2569 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
<> 149:156823d33999 2570
<> 149:156823d33999 2571 /******************* Bit definition for EXTI_EMR register *******************/
<> 149:156823d33999 2572 #define EXTI_EMR_MR0_Pos (0U)
<> 149:156823d33999 2573 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2574 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
<> 149:156823d33999 2575 #define EXTI_EMR_MR1_Pos (1U)
<> 149:156823d33999 2576 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2577 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
<> 149:156823d33999 2578 #define EXTI_EMR_MR2_Pos (2U)
<> 149:156823d33999 2579 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2580 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
<> 149:156823d33999 2581 #define EXTI_EMR_MR3_Pos (3U)
<> 149:156823d33999 2582 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2583 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
<> 149:156823d33999 2584 #define EXTI_EMR_MR4_Pos (4U)
<> 149:156823d33999 2585 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2586 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
<> 149:156823d33999 2587 #define EXTI_EMR_MR5_Pos (5U)
<> 149:156823d33999 2588 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2589 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
<> 149:156823d33999 2590 #define EXTI_EMR_MR6_Pos (6U)
<> 149:156823d33999 2591 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2592 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
<> 149:156823d33999 2593 #define EXTI_EMR_MR7_Pos (7U)
<> 149:156823d33999 2594 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2595 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
<> 149:156823d33999 2596 #define EXTI_EMR_MR8_Pos (8U)
<> 149:156823d33999 2597 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2598 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
<> 149:156823d33999 2599 #define EXTI_EMR_MR9_Pos (9U)
<> 149:156823d33999 2600 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2601 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
<> 149:156823d33999 2602 #define EXTI_EMR_MR10_Pos (10U)
<> 149:156823d33999 2603 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2604 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
<> 149:156823d33999 2605 #define EXTI_EMR_MR11_Pos (11U)
<> 149:156823d33999 2606 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2607 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
<> 149:156823d33999 2608 #define EXTI_EMR_MR12_Pos (12U)
<> 149:156823d33999 2609 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2610 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
<> 149:156823d33999 2611 #define EXTI_EMR_MR13_Pos (13U)
<> 149:156823d33999 2612 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2613 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
<> 149:156823d33999 2614 #define EXTI_EMR_MR14_Pos (14U)
<> 149:156823d33999 2615 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2616 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
<> 149:156823d33999 2617 #define EXTI_EMR_MR15_Pos (15U)
<> 149:156823d33999 2618 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 2619 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
<> 149:156823d33999 2620 #define EXTI_EMR_MR16_Pos (16U)
<> 149:156823d33999 2621 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2622 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
<> 149:156823d33999 2623 #define EXTI_EMR_MR17_Pos (17U)
<> 149:156823d33999 2624 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2625 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
<> 149:156823d33999 2626 #define EXTI_EMR_MR18_Pos (18U)
<> 149:156823d33999 2627 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2628 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
<> 149:156823d33999 2629 #define EXTI_EMR_MR19_Pos (19U)
<> 149:156823d33999 2630 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2631 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
<> 149:156823d33999 2632 #define EXTI_EMR_MR20_Pos (20U)
<> 149:156823d33999 2633 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2634 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
<> 149:156823d33999 2635 #define EXTI_EMR_MR21_Pos (21U)
<> 149:156823d33999 2636 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2637 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
<> 149:156823d33999 2638 #define EXTI_EMR_MR22_Pos (22U)
<> 149:156823d33999 2639 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2640 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
<> 149:156823d33999 2641 #define EXTI_EMR_MR23_Pos (23U)
<> 149:156823d33999 2642 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2643 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
<> 149:156823d33999 2644
<> 149:156823d33999 2645 /* References Defines */
<> 149:156823d33999 2646 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 149:156823d33999 2647 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 149:156823d33999 2648 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 149:156823d33999 2649 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 149:156823d33999 2650 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 149:156823d33999 2651 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 149:156823d33999 2652 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 149:156823d33999 2653 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 149:156823d33999 2654 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 149:156823d33999 2655 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 149:156823d33999 2656 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 149:156823d33999 2657 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 149:156823d33999 2658 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 149:156823d33999 2659 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 149:156823d33999 2660 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 149:156823d33999 2661 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 149:156823d33999 2662 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 149:156823d33999 2663 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 149:156823d33999 2664 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 149:156823d33999 2665 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 149:156823d33999 2666 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 149:156823d33999 2667 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 149:156823d33999 2668 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 149:156823d33999 2669 #define EXTI_EMR_EM23 EXTI_EMR_MR23
<> 149:156823d33999 2670
<> 149:156823d33999 2671 /****************** Bit definition for EXTI_RTSR register *******************/
<> 149:156823d33999 2672 #define EXTI_RTSR_TR0_Pos (0U)
<> 149:156823d33999 2673 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2674 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
<> 149:156823d33999 2675 #define EXTI_RTSR_TR1_Pos (1U)
<> 149:156823d33999 2676 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2677 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
<> 149:156823d33999 2678 #define EXTI_RTSR_TR2_Pos (2U)
<> 149:156823d33999 2679 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2680 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
<> 149:156823d33999 2681 #define EXTI_RTSR_TR3_Pos (3U)
<> 149:156823d33999 2682 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2683 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
<> 149:156823d33999 2684 #define EXTI_RTSR_TR4_Pos (4U)
<> 149:156823d33999 2685 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2686 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
<> 149:156823d33999 2687 #define EXTI_RTSR_TR5_Pos (5U)
<> 149:156823d33999 2688 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2689 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
<> 149:156823d33999 2690 #define EXTI_RTSR_TR6_Pos (6U)
<> 149:156823d33999 2691 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2692 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
<> 149:156823d33999 2693 #define EXTI_RTSR_TR7_Pos (7U)
<> 149:156823d33999 2694 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2695 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
<> 149:156823d33999 2696 #define EXTI_RTSR_TR8_Pos (8U)
<> 149:156823d33999 2697 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2698 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
<> 149:156823d33999 2699 #define EXTI_RTSR_TR9_Pos (9U)
<> 149:156823d33999 2700 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2701 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
<> 149:156823d33999 2702 #define EXTI_RTSR_TR10_Pos (10U)
<> 149:156823d33999 2703 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2704 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
<> 149:156823d33999 2705 #define EXTI_RTSR_TR11_Pos (11U)
<> 149:156823d33999 2706 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2707 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
<> 149:156823d33999 2708 #define EXTI_RTSR_TR12_Pos (12U)
<> 149:156823d33999 2709 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2710 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
<> 149:156823d33999 2711 #define EXTI_RTSR_TR13_Pos (13U)
<> 149:156823d33999 2712 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2713 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
<> 149:156823d33999 2714 #define EXTI_RTSR_TR14_Pos (14U)
<> 149:156823d33999 2715 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2716 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
<> 149:156823d33999 2717 #define EXTI_RTSR_TR15_Pos (15U)
<> 149:156823d33999 2718 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 2719 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
<> 149:156823d33999 2720 #define EXTI_RTSR_TR16_Pos (16U)
<> 149:156823d33999 2721 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2722 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
<> 149:156823d33999 2723 #define EXTI_RTSR_TR17_Pos (17U)
<> 149:156823d33999 2724 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2725 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
<> 149:156823d33999 2726 #define EXTI_RTSR_TR18_Pos (18U)
<> 149:156823d33999 2727 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2728 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
<> 149:156823d33999 2729 #define EXTI_RTSR_TR19_Pos (19U)
<> 149:156823d33999 2730 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2731 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
<> 149:156823d33999 2732 #define EXTI_RTSR_TR20_Pos (20U)
<> 149:156823d33999 2733 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2734 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
<> 149:156823d33999 2735 #define EXTI_RTSR_TR21_Pos (21U)
<> 149:156823d33999 2736 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2737 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
<> 149:156823d33999 2738 #define EXTI_RTSR_TR22_Pos (22U)
<> 149:156823d33999 2739 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2740 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 149:156823d33999 2741 #define EXTI_RTSR_TR23_Pos (23U)
<> 149:156823d33999 2742 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2743 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
<> 149:156823d33999 2744
<> 149:156823d33999 2745 /* References Defines */
<> 149:156823d33999 2746 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
<> 149:156823d33999 2747 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
<> 149:156823d33999 2748 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
<> 149:156823d33999 2749 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
<> 149:156823d33999 2750 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
<> 149:156823d33999 2751 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
<> 149:156823d33999 2752 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
<> 149:156823d33999 2753 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
<> 149:156823d33999 2754 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
<> 149:156823d33999 2755 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
<> 149:156823d33999 2756 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
<> 149:156823d33999 2757 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
<> 149:156823d33999 2758 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
<> 149:156823d33999 2759 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
<> 149:156823d33999 2760 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
<> 149:156823d33999 2761 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
<> 149:156823d33999 2762 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
<> 149:156823d33999 2763 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
<> 149:156823d33999 2764 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
<> 149:156823d33999 2765 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
<> 149:156823d33999 2766 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
<> 149:156823d33999 2767 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
<> 149:156823d33999 2768 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
<> 149:156823d33999 2769 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
<> 149:156823d33999 2770
<> 149:156823d33999 2771 /****************** Bit definition for EXTI_FTSR register *******************/
<> 149:156823d33999 2772 #define EXTI_FTSR_TR0_Pos (0U)
<> 149:156823d33999 2773 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2774 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
<> 149:156823d33999 2775 #define EXTI_FTSR_TR1_Pos (1U)
<> 149:156823d33999 2776 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2777 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
<> 149:156823d33999 2778 #define EXTI_FTSR_TR2_Pos (2U)
<> 149:156823d33999 2779 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2780 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
<> 149:156823d33999 2781 #define EXTI_FTSR_TR3_Pos (3U)
<> 149:156823d33999 2782 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2783 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
<> 149:156823d33999 2784 #define EXTI_FTSR_TR4_Pos (4U)
<> 149:156823d33999 2785 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2786 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
<> 149:156823d33999 2787 #define EXTI_FTSR_TR5_Pos (5U)
<> 149:156823d33999 2788 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2789 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
<> 149:156823d33999 2790 #define EXTI_FTSR_TR6_Pos (6U)
<> 149:156823d33999 2791 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2792 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
<> 149:156823d33999 2793 #define EXTI_FTSR_TR7_Pos (7U)
<> 149:156823d33999 2794 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2795 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
<> 149:156823d33999 2796 #define EXTI_FTSR_TR8_Pos (8U)
<> 149:156823d33999 2797 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2798 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
<> 149:156823d33999 2799 #define EXTI_FTSR_TR9_Pos (9U)
<> 149:156823d33999 2800 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2801 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
<> 149:156823d33999 2802 #define EXTI_FTSR_TR10_Pos (10U)
<> 149:156823d33999 2803 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2804 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
<> 149:156823d33999 2805 #define EXTI_FTSR_TR11_Pos (11U)
<> 149:156823d33999 2806 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2807 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
<> 149:156823d33999 2808 #define EXTI_FTSR_TR12_Pos (12U)
<> 149:156823d33999 2809 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2810 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
<> 149:156823d33999 2811 #define EXTI_FTSR_TR13_Pos (13U)
<> 149:156823d33999 2812 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2813 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
<> 149:156823d33999 2814 #define EXTI_FTSR_TR14_Pos (14U)
<> 149:156823d33999 2815 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2816 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
<> 149:156823d33999 2817 #define EXTI_FTSR_TR15_Pos (15U)
<> 149:156823d33999 2818 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 2819 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
<> 149:156823d33999 2820 #define EXTI_FTSR_TR16_Pos (16U)
<> 149:156823d33999 2821 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2822 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
<> 149:156823d33999 2823 #define EXTI_FTSR_TR17_Pos (17U)
<> 149:156823d33999 2824 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2825 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
<> 149:156823d33999 2826 #define EXTI_FTSR_TR18_Pos (18U)
<> 149:156823d33999 2827 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2828 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
<> 149:156823d33999 2829 #define EXTI_FTSR_TR19_Pos (19U)
<> 149:156823d33999 2830 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2831 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
<> 149:156823d33999 2832 #define EXTI_FTSR_TR20_Pos (20U)
<> 149:156823d33999 2833 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2834 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
<> 149:156823d33999 2835 #define EXTI_FTSR_TR21_Pos (21U)
<> 149:156823d33999 2836 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2837 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
<> 149:156823d33999 2838 #define EXTI_FTSR_TR22_Pos (22U)
<> 149:156823d33999 2839 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2840 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 149:156823d33999 2841 #define EXTI_FTSR_TR23_Pos (23U)
<> 149:156823d33999 2842 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2843 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
<> 149:156823d33999 2844
<> 149:156823d33999 2845 /* References Defines */
<> 149:156823d33999 2846 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
<> 149:156823d33999 2847 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
<> 149:156823d33999 2848 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
<> 149:156823d33999 2849 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
<> 149:156823d33999 2850 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
<> 149:156823d33999 2851 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
<> 149:156823d33999 2852 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
<> 149:156823d33999 2853 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
<> 149:156823d33999 2854 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
<> 149:156823d33999 2855 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
<> 149:156823d33999 2856 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
<> 149:156823d33999 2857 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
<> 149:156823d33999 2858 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
<> 149:156823d33999 2859 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
<> 149:156823d33999 2860 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
<> 149:156823d33999 2861 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
<> 149:156823d33999 2862 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
<> 149:156823d33999 2863 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
<> 149:156823d33999 2864 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
<> 149:156823d33999 2865 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
<> 149:156823d33999 2866 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
<> 149:156823d33999 2867 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
<> 149:156823d33999 2868 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
<> 149:156823d33999 2869 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
<> 149:156823d33999 2870
<> 149:156823d33999 2871 /****************** Bit definition for EXTI_SWIER register ******************/
<> 149:156823d33999 2872 #define EXTI_SWIER_SWIER0_Pos (0U)
<> 149:156823d33999 2873 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2874 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
<> 149:156823d33999 2875 #define EXTI_SWIER_SWIER1_Pos (1U)
<> 149:156823d33999 2876 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2877 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
<> 149:156823d33999 2878 #define EXTI_SWIER_SWIER2_Pos (2U)
<> 149:156823d33999 2879 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2880 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
<> 149:156823d33999 2881 #define EXTI_SWIER_SWIER3_Pos (3U)
<> 149:156823d33999 2882 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2883 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
<> 149:156823d33999 2884 #define EXTI_SWIER_SWIER4_Pos (4U)
<> 149:156823d33999 2885 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2886 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
<> 149:156823d33999 2887 #define EXTI_SWIER_SWIER5_Pos (5U)
<> 149:156823d33999 2888 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2889 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
<> 149:156823d33999 2890 #define EXTI_SWIER_SWIER6_Pos (6U)
<> 149:156823d33999 2891 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2892 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
<> 149:156823d33999 2893 #define EXTI_SWIER_SWIER7_Pos (7U)
<> 149:156823d33999 2894 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2895 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
<> 149:156823d33999 2896 #define EXTI_SWIER_SWIER8_Pos (8U)
<> 149:156823d33999 2897 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2898 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
<> 149:156823d33999 2899 #define EXTI_SWIER_SWIER9_Pos (9U)
<> 149:156823d33999 2900 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 2901 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
<> 149:156823d33999 2902 #define EXTI_SWIER_SWIER10_Pos (10U)
<> 149:156823d33999 2903 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
<> 149:156823d33999 2904 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
<> 149:156823d33999 2905 #define EXTI_SWIER_SWIER11_Pos (11U)
<> 149:156823d33999 2906 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
<> 149:156823d33999 2907 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
<> 149:156823d33999 2908 #define EXTI_SWIER_SWIER12_Pos (12U)
<> 149:156823d33999 2909 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
<> 149:156823d33999 2910 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
<> 149:156823d33999 2911 #define EXTI_SWIER_SWIER13_Pos (13U)
<> 149:156823d33999 2912 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
<> 149:156823d33999 2913 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
<> 149:156823d33999 2914 #define EXTI_SWIER_SWIER14_Pos (14U)
<> 149:156823d33999 2915 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 2916 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
<> 149:156823d33999 2917 #define EXTI_SWIER_SWIER15_Pos (15U)
<> 149:156823d33999 2918 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 2919 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
<> 149:156823d33999 2920 #define EXTI_SWIER_SWIER16_Pos (16U)
<> 149:156823d33999 2921 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
<> 149:156823d33999 2922 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
<> 149:156823d33999 2923 #define EXTI_SWIER_SWIER17_Pos (17U)
<> 149:156823d33999 2924 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
<> 149:156823d33999 2925 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
<> 149:156823d33999 2926 #define EXTI_SWIER_SWIER18_Pos (18U)
<> 149:156823d33999 2927 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
<> 149:156823d33999 2928 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
<> 149:156823d33999 2929 #define EXTI_SWIER_SWIER19_Pos (19U)
<> 149:156823d33999 2930 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
<> 149:156823d33999 2931 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
<> 149:156823d33999 2932 #define EXTI_SWIER_SWIER20_Pos (20U)
<> 149:156823d33999 2933 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
<> 149:156823d33999 2934 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
<> 149:156823d33999 2935 #define EXTI_SWIER_SWIER21_Pos (21U)
<> 149:156823d33999 2936 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
<> 149:156823d33999 2937 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
<> 149:156823d33999 2938 #define EXTI_SWIER_SWIER22_Pos (22U)
<> 149:156823d33999 2939 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
<> 149:156823d33999 2940 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
<> 149:156823d33999 2941 #define EXTI_SWIER_SWIER23_Pos (23U)
<> 149:156823d33999 2942 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
<> 149:156823d33999 2943 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
<> 149:156823d33999 2944
<> 149:156823d33999 2945 /* References Defines */
<> 149:156823d33999 2946 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
<> 149:156823d33999 2947 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
<> 149:156823d33999 2948 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
<> 149:156823d33999 2949 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
<> 149:156823d33999 2950 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
<> 149:156823d33999 2951 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
<> 149:156823d33999 2952 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
<> 149:156823d33999 2953 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
<> 149:156823d33999 2954 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
<> 149:156823d33999 2955 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
<> 149:156823d33999 2956 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
<> 149:156823d33999 2957 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
<> 149:156823d33999 2958 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
<> 149:156823d33999 2959 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
<> 149:156823d33999 2960 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
<> 149:156823d33999 2961 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
<> 149:156823d33999 2962 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
<> 149:156823d33999 2963 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
<> 149:156823d33999 2964 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
<> 149:156823d33999 2965 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
<> 149:156823d33999 2966 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
<> 149:156823d33999 2967 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
<> 149:156823d33999 2968 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
<> 149:156823d33999 2969 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
<> 149:156823d33999 2970
<> 149:156823d33999 2971 /******************* Bit definition for EXTI_PR register ********************/
<> 149:156823d33999 2972 #define EXTI_PR_PR0_Pos (0U)
<> 149:156823d33999 2973 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 2974 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
<> 149:156823d33999 2975 #define EXTI_PR_PR1_Pos (1U)
<> 149:156823d33999 2976 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 2977 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
<> 149:156823d33999 2978 #define EXTI_PR_PR2_Pos (2U)
<> 149:156823d33999 2979 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 2980 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
<> 149:156823d33999 2981 #define EXTI_PR_PR3_Pos (3U)
<> 149:156823d33999 2982 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 2983 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
<> 149:156823d33999 2984 #define EXTI_PR_PR4_Pos (4U)
<> 149:156823d33999 2985 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 2986 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
<> 149:156823d33999 2987 #define EXTI_PR_PR5_Pos (5U)
<> 149:156823d33999 2988 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 2989 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
<> 149:156823d33999 2990 #define EXTI_PR_PR6_Pos (6U)
<> 149:156823d33999 2991 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 2992 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
<> 149:156823d33999 2993 #define EXTI_PR_PR7_Pos (7U)
<> 149:156823d33999 2994 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 2995 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
<> 149:156823d33999 2996 #define EXTI_PR_PR8_Pos (8U)
<> 149:156823d33999 2997 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 2998 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
<> 149:156823d33999 2999 #define EXTI_PR_PR9_Pos (9U)
<> 149:156823d33999 3000 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3001 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
<> 149:156823d33999 3002 #define EXTI_PR_PR10_Pos (10U)
<> 149:156823d33999 3003 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3004 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
<> 149:156823d33999 3005 #define EXTI_PR_PR11_Pos (11U)
<> 149:156823d33999 3006 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3007 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
<> 149:156823d33999 3008 #define EXTI_PR_PR12_Pos (12U)
<> 149:156823d33999 3009 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3010 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
<> 149:156823d33999 3011 #define EXTI_PR_PR13_Pos (13U)
<> 149:156823d33999 3012 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
<> 149:156823d33999 3013 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
<> 149:156823d33999 3014 #define EXTI_PR_PR14_Pos (14U)
<> 149:156823d33999 3015 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 3016 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
<> 149:156823d33999 3017 #define EXTI_PR_PR15_Pos (15U)
<> 149:156823d33999 3018 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3019 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
<> 149:156823d33999 3020 #define EXTI_PR_PR16_Pos (16U)
<> 149:156823d33999 3021 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
<> 149:156823d33999 3022 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
<> 149:156823d33999 3023 #define EXTI_PR_PR17_Pos (17U)
<> 149:156823d33999 3024 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
<> 149:156823d33999 3025 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
<> 149:156823d33999 3026 #define EXTI_PR_PR18_Pos (18U)
<> 149:156823d33999 3027 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
<> 149:156823d33999 3028 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
<> 149:156823d33999 3029 #define EXTI_PR_PR19_Pos (19U)
<> 149:156823d33999 3030 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
<> 149:156823d33999 3031 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
<> 149:156823d33999 3032 #define EXTI_PR_PR20_Pos (20U)
<> 149:156823d33999 3033 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
<> 149:156823d33999 3034 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
<> 149:156823d33999 3035 #define EXTI_PR_PR21_Pos (21U)
<> 149:156823d33999 3036 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
<> 149:156823d33999 3037 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
<> 149:156823d33999 3038 #define EXTI_PR_PR22_Pos (22U)
<> 149:156823d33999 3039 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
<> 149:156823d33999 3040 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
<> 149:156823d33999 3041 #define EXTI_PR_PR23_Pos (23U)
<> 149:156823d33999 3042 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
<> 149:156823d33999 3043 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
<> 149:156823d33999 3044
<> 149:156823d33999 3045 /* References Defines */
<> 149:156823d33999 3046 #define EXTI_PR_PIF0 EXTI_PR_PR0
<> 149:156823d33999 3047 #define EXTI_PR_PIF1 EXTI_PR_PR1
<> 149:156823d33999 3048 #define EXTI_PR_PIF2 EXTI_PR_PR2
<> 149:156823d33999 3049 #define EXTI_PR_PIF3 EXTI_PR_PR3
<> 149:156823d33999 3050 #define EXTI_PR_PIF4 EXTI_PR_PR4
<> 149:156823d33999 3051 #define EXTI_PR_PIF5 EXTI_PR_PR5
<> 149:156823d33999 3052 #define EXTI_PR_PIF6 EXTI_PR_PR6
<> 149:156823d33999 3053 #define EXTI_PR_PIF7 EXTI_PR_PR7
<> 149:156823d33999 3054 #define EXTI_PR_PIF8 EXTI_PR_PR8
<> 149:156823d33999 3055 #define EXTI_PR_PIF9 EXTI_PR_PR9
<> 149:156823d33999 3056 #define EXTI_PR_PIF10 EXTI_PR_PR10
<> 149:156823d33999 3057 #define EXTI_PR_PIF11 EXTI_PR_PR11
<> 149:156823d33999 3058 #define EXTI_PR_PIF12 EXTI_PR_PR12
<> 149:156823d33999 3059 #define EXTI_PR_PIF13 EXTI_PR_PR13
<> 149:156823d33999 3060 #define EXTI_PR_PIF14 EXTI_PR_PR14
<> 149:156823d33999 3061 #define EXTI_PR_PIF15 EXTI_PR_PR15
<> 149:156823d33999 3062 #define EXTI_PR_PIF16 EXTI_PR_PR16
<> 149:156823d33999 3063 #define EXTI_PR_PIF17 EXTI_PR_PR17
<> 149:156823d33999 3064 #define EXTI_PR_PIF18 EXTI_PR_PR18
<> 149:156823d33999 3065 #define EXTI_PR_PIF19 EXTI_PR_PR19
<> 149:156823d33999 3066 #define EXTI_PR_PIF20 EXTI_PR_PR20
<> 149:156823d33999 3067 #define EXTI_PR_PIF21 EXTI_PR_PR21
<> 149:156823d33999 3068 #define EXTI_PR_PIF22 EXTI_PR_PR22
<> 149:156823d33999 3069 #define EXTI_PR_PIF23 EXTI_PR_PR23
<> 149:156823d33999 3070
<> 149:156823d33999 3071 /******************************************************************************/
<> 149:156823d33999 3072 /* */
<> 149:156823d33999 3073 /* FLASH, DATA EEPROM and Option Bytes Registers */
<> 149:156823d33999 3074 /* (FLASH, DATA_EEPROM, OB) */
<> 149:156823d33999 3075 /* */
<> 149:156823d33999 3076 /******************************************************************************/
<> 149:156823d33999 3077
<> 149:156823d33999 3078 /******************* Bit definition for FLASH_ACR register ******************/
<> 149:156823d33999 3079 #define FLASH_ACR_LATENCY_Pos (0U)
<> 149:156823d33999 3080 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3081 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
<> 149:156823d33999 3082 #define FLASH_ACR_PRFTEN_Pos (1U)
<> 149:156823d33999 3083 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3084 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
<> 149:156823d33999 3085 #define FLASH_ACR_ACC64_Pos (2U)
<> 149:156823d33999 3086 #define FLASH_ACR_ACC64_Msk (0x1U << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3087 #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */
<> 149:156823d33999 3088 #define FLASH_ACR_SLEEP_PD_Pos (3U)
<> 149:156823d33999 3089 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3090 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
<> 149:156823d33999 3091 #define FLASH_ACR_RUN_PD_Pos (4U)
<> 149:156823d33999 3092 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3093 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
<> 149:156823d33999 3094
<> 149:156823d33999 3095 /******************* Bit definition for FLASH_PECR register ******************/
<> 149:156823d33999 3096 #define FLASH_PECR_PELOCK_Pos (0U)
<> 149:156823d33999 3097 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3098 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
<> 149:156823d33999 3099 #define FLASH_PECR_PRGLOCK_Pos (1U)
<> 149:156823d33999 3100 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3101 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
<> 149:156823d33999 3102 #define FLASH_PECR_OPTLOCK_Pos (2U)
<> 149:156823d33999 3103 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3104 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
<> 149:156823d33999 3105 #define FLASH_PECR_PROG_Pos (3U)
<> 149:156823d33999 3106 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3107 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
<> 149:156823d33999 3108 #define FLASH_PECR_DATA_Pos (4U)
<> 149:156823d33999 3109 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3110 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
<> 149:156823d33999 3111 #define FLASH_PECR_FTDW_Pos (8U)
<> 149:156823d33999 3112 #define FLASH_PECR_FTDW_Msk (0x1U << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3113 #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
<> 149:156823d33999 3114 #define FLASH_PECR_ERASE_Pos (9U)
<> 149:156823d33999 3115 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3116 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
<> 149:156823d33999 3117 #define FLASH_PECR_FPRG_Pos (10U)
<> 149:156823d33999 3118 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3119 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
<> 149:156823d33999 3120 #define FLASH_PECR_PARALLBANK_Pos (15U)
<> 149:156823d33999 3121 #define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3122 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
<> 149:156823d33999 3123 #define FLASH_PECR_EOPIE_Pos (16U)
<> 149:156823d33999 3124 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
<> 149:156823d33999 3125 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
<> 149:156823d33999 3126 #define FLASH_PECR_ERRIE_Pos (17U)
<> 149:156823d33999 3127 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
<> 149:156823d33999 3128 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
<> 149:156823d33999 3129 #define FLASH_PECR_OBL_LAUNCH_Pos (18U)
<> 149:156823d33999 3130 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
<> 149:156823d33999 3131 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
<> 149:156823d33999 3132
<> 149:156823d33999 3133 /****************** Bit definition for FLASH_PDKEYR register ******************/
<> 149:156823d33999 3134 #define FLASH_PDKEYR_PDKEYR_Pos (0U)
<> 149:156823d33999 3135 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3136 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
<> 149:156823d33999 3137
<> 149:156823d33999 3138 /****************** Bit definition for FLASH_PEKEYR register ******************/
<> 149:156823d33999 3139 #define FLASH_PEKEYR_PEKEYR_Pos (0U)
<> 149:156823d33999 3140 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3141 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
<> 149:156823d33999 3142
<> 149:156823d33999 3143 /****************** Bit definition for FLASH_PRGKEYR register ******************/
<> 149:156823d33999 3144 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
<> 149:156823d33999 3145 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3146 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
<> 149:156823d33999 3147
<> 149:156823d33999 3148 /****************** Bit definition for FLASH_OPTKEYR register ******************/
<> 149:156823d33999 3149 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
<> 149:156823d33999 3150 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3151 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
<> 149:156823d33999 3152
<> 149:156823d33999 3153 /****************** Bit definition for FLASH_SR register *******************/
<> 149:156823d33999 3154 #define FLASH_SR_BSY_Pos (0U)
<> 149:156823d33999 3155 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3156 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
<> 149:156823d33999 3157 #define FLASH_SR_EOP_Pos (1U)
<> 149:156823d33999 3158 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3159 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
<> 149:156823d33999 3160 #define FLASH_SR_ENDHV_Pos (2U)
<> 149:156823d33999 3161 #define FLASH_SR_ENDHV_Msk (0x1U << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3162 #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */
<> 149:156823d33999 3163 #define FLASH_SR_READY_Pos (3U)
<> 149:156823d33999 3164 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3165 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
<> 149:156823d33999 3166
<> 149:156823d33999 3167 #define FLASH_SR_WRPERR_Pos (8U)
<> 149:156823d33999 3168 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3169 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */
<> 149:156823d33999 3170 #define FLASH_SR_PGAERR_Pos (9U)
<> 149:156823d33999 3171 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3172 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
<> 149:156823d33999 3173 #define FLASH_SR_SIZERR_Pos (10U)
<> 149:156823d33999 3174 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3175 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
<> 149:156823d33999 3176 #define FLASH_SR_OPTVERR_Pos (11U)
<> 149:156823d33999 3177 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3178 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */
<> 149:156823d33999 3179 #define FLASH_SR_OPTVERRUSR_Pos (12U)
<> 149:156823d33999 3180 #define FLASH_SR_OPTVERRUSR_Msk (0x1U << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3181 #define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */
<> 149:156823d33999 3182
<> 149:156823d33999 3183 /****************** Bit definition for FLASH_OBR register *******************/
<> 149:156823d33999 3184 #define FLASH_OBR_RDPRT_Pos (0U)
<> 149:156823d33999 3185 #define FLASH_OBR_RDPRT_Msk (0xFFU << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */
<> 149:156823d33999 3186 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */
<> 149:156823d33999 3187 #define FLASH_OBR_BOR_LEV_Pos (16U)
<> 149:156823d33999 3188 #define FLASH_OBR_BOR_LEV_Msk (0xFU << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */
<> 149:156823d33999 3189 #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
<> 149:156823d33999 3190 #define FLASH_OBR_USER_Pos (20U)
<> 149:156823d33999 3191 #define FLASH_OBR_USER_Msk (0xFU << FLASH_OBR_USER_Pos) /*!< 0x00F00000 */
<> 149:156823d33999 3192 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
<> 149:156823d33999 3193 #define FLASH_OBR_IWDG_SW_Pos (20U)
<> 149:156823d33999 3194 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */
<> 149:156823d33999 3195 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */
<> 149:156823d33999 3196 #define FLASH_OBR_nRST_STOP_Pos (21U)
<> 149:156823d33999 3197 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
<> 149:156823d33999 3198 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
<> 149:156823d33999 3199 #define FLASH_OBR_nRST_STDBY_Pos (22U)
<> 149:156823d33999 3200 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
<> 149:156823d33999 3201 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
<> 149:156823d33999 3202 #define FLASH_OBR_nRST_BFB2_Pos (23U)
<> 149:156823d33999 3203 #define FLASH_OBR_nRST_BFB2_Msk (0x1U << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
<> 149:156823d33999 3204 #define FLASH_OBR_nRST_BFB2 FLASH_OBR_nRST_BFB2_Msk /*!< BFB2 */
<> 149:156823d33999 3205
<> 149:156823d33999 3206 /****************** Bit definition for FLASH_WRPR register ******************/
<> 149:156823d33999 3207 #define FLASH_WRPR1_WRP_Pos (0U)
<> 149:156823d33999 3208 #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3209 #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */
<> 149:156823d33999 3210 #define FLASH_WRPR2_WRP_Pos (0U)
<> 149:156823d33999 3211 #define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3212 #define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */
<> 149:156823d33999 3213 #define FLASH_WRPR3_WRP_Pos (0U)
<> 149:156823d33999 3214 #define FLASH_WRPR3_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3215 #define FLASH_WRPR3_WRP FLASH_WRPR3_WRP_Msk /*!< Write Protect sectors 64 to 95 */
<> 149:156823d33999 3216 #define FLASH_WRPR4_WRP_Pos (0U)
<> 149:156823d33999 3217 #define FLASH_WRPR4_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR4_WRP_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 3218 #define FLASH_WRPR4_WRP FLASH_WRPR4_WRP_Msk /*!< Write Protect sectors 96 to 127 */
<> 149:156823d33999 3219
<> 149:156823d33999 3220 /******************************************************************************/
<> 149:156823d33999 3221 /* */
<> 149:156823d33999 3222 /* General Purpose I/O */
<> 149:156823d33999 3223 /* */
<> 149:156823d33999 3224 /******************************************************************************/
<> 149:156823d33999 3225 /****************** Bits definition for GPIO_MODER register *****************/
<> 149:156823d33999 3226 #define GPIO_MODER_MODER0_Pos (0U)
<> 149:156823d33999 3227 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
<> 149:156823d33999 3228 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
<> 149:156823d33999 3229 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3230 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3231
<> 149:156823d33999 3232 #define GPIO_MODER_MODER1_Pos (2U)
<> 149:156823d33999 3233 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
<> 149:156823d33999 3234 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
<> 149:156823d33999 3235 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3236 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3237
<> 149:156823d33999 3238 #define GPIO_MODER_MODER2_Pos (4U)
<> 149:156823d33999 3239 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
<> 149:156823d33999 3240 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
<> 149:156823d33999 3241 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3242 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3243
<> 149:156823d33999 3244 #define GPIO_MODER_MODER3_Pos (6U)
<> 149:156823d33999 3245 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
<> 149:156823d33999 3246 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
<> 149:156823d33999 3247 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3248 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3249
<> 149:156823d33999 3250 #define GPIO_MODER_MODER4_Pos (8U)
<> 149:156823d33999 3251 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
<> 149:156823d33999 3252 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
<> 149:156823d33999 3253 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3254 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3255
<> 149:156823d33999 3256 #define GPIO_MODER_MODER5_Pos (10U)
<> 149:156823d33999 3257 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
<> 149:156823d33999 3258 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
<> 149:156823d33999 3259 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3260 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3261
<> 149:156823d33999 3262 #define GPIO_MODER_MODER6_Pos (12U)
<> 149:156823d33999 3263 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
<> 149:156823d33999 3264 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
<> 149:156823d33999 3265 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3266 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
<> 149:156823d33999 3267
<> 149:156823d33999 3268 #define GPIO_MODER_MODER7_Pos (14U)
<> 149:156823d33999 3269 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
<> 149:156823d33999 3270 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
<> 149:156823d33999 3271 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
<> 149:156823d33999 3272 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3273
<> 149:156823d33999 3274 #define GPIO_MODER_MODER8_Pos (16U)
<> 149:156823d33999 3275 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
<> 149:156823d33999 3276 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
<> 149:156823d33999 3277 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
<> 149:156823d33999 3278 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
<> 149:156823d33999 3279
<> 149:156823d33999 3280 #define GPIO_MODER_MODER9_Pos (18U)
<> 149:156823d33999 3281 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
<> 149:156823d33999 3282 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
<> 149:156823d33999 3283 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
<> 149:156823d33999 3284 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
<> 149:156823d33999 3285
<> 149:156823d33999 3286 #define GPIO_MODER_MODER10_Pos (20U)
<> 149:156823d33999 3287 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
<> 149:156823d33999 3288 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
<> 149:156823d33999 3289 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
<> 149:156823d33999 3290 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
<> 149:156823d33999 3291
<> 149:156823d33999 3292 #define GPIO_MODER_MODER11_Pos (22U)
<> 149:156823d33999 3293 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
<> 149:156823d33999 3294 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
<> 149:156823d33999 3295 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
<> 149:156823d33999 3296 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
<> 149:156823d33999 3297
<> 149:156823d33999 3298 #define GPIO_MODER_MODER12_Pos (24U)
<> 149:156823d33999 3299 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
<> 149:156823d33999 3300 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
<> 149:156823d33999 3301 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
<> 149:156823d33999 3302 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
<> 149:156823d33999 3303
<> 149:156823d33999 3304 #define GPIO_MODER_MODER13_Pos (26U)
<> 149:156823d33999 3305 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
<> 149:156823d33999 3306 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
<> 149:156823d33999 3307 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
<> 149:156823d33999 3308 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
<> 149:156823d33999 3309
<> 149:156823d33999 3310 #define GPIO_MODER_MODER14_Pos (28U)
<> 149:156823d33999 3311 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
<> 149:156823d33999 3312 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
<> 149:156823d33999 3313 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
<> 149:156823d33999 3314 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
<> 149:156823d33999 3315
<> 149:156823d33999 3316 #define GPIO_MODER_MODER15_Pos (30U)
<> 149:156823d33999 3317 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
<> 149:156823d33999 3318 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
<> 149:156823d33999 3319 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
<> 149:156823d33999 3320 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
<> 149:156823d33999 3321
<> 149:156823d33999 3322 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 149:156823d33999 3323 #define GPIO_OTYPER_OT_0 (0x00000001U)
<> 149:156823d33999 3324 #define GPIO_OTYPER_OT_1 (0x00000002U)
<> 149:156823d33999 3325 #define GPIO_OTYPER_OT_2 (0x00000004U)
<> 149:156823d33999 3326 #define GPIO_OTYPER_OT_3 (0x00000008U)
<> 149:156823d33999 3327 #define GPIO_OTYPER_OT_4 (0x00000010U)
<> 149:156823d33999 3328 #define GPIO_OTYPER_OT_5 (0x00000020U)
<> 149:156823d33999 3329 #define GPIO_OTYPER_OT_6 (0x00000040U)
<> 149:156823d33999 3330 #define GPIO_OTYPER_OT_7 (0x00000080U)
<> 149:156823d33999 3331 #define GPIO_OTYPER_OT_8 (0x00000100U)
<> 149:156823d33999 3332 #define GPIO_OTYPER_OT_9 (0x00000200U)
<> 149:156823d33999 3333 #define GPIO_OTYPER_OT_10 (0x00000400U)
<> 149:156823d33999 3334 #define GPIO_OTYPER_OT_11 (0x00000800U)
<> 149:156823d33999 3335 #define GPIO_OTYPER_OT_12 (0x00001000U)
<> 149:156823d33999 3336 #define GPIO_OTYPER_OT_13 (0x00002000U)
<> 149:156823d33999 3337 #define GPIO_OTYPER_OT_14 (0x00004000U)
<> 149:156823d33999 3338 #define GPIO_OTYPER_OT_15 (0x00008000U)
<> 149:156823d33999 3339
<> 149:156823d33999 3340 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 149:156823d33999 3341 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
<> 149:156823d33999 3342 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
<> 149:156823d33999 3343 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
<> 149:156823d33999 3344 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3345 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3346
<> 149:156823d33999 3347 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
<> 149:156823d33999 3348 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
<> 149:156823d33999 3349 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
<> 149:156823d33999 3350 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3351 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3352
<> 149:156823d33999 3353 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
<> 149:156823d33999 3354 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
<> 149:156823d33999 3355 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
<> 149:156823d33999 3356 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3357 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3358
<> 149:156823d33999 3359 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
<> 149:156823d33999 3360 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
<> 149:156823d33999 3361 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
<> 149:156823d33999 3362 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3363 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3364
<> 149:156823d33999 3365 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
<> 149:156823d33999 3366 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
<> 149:156823d33999 3367 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
<> 149:156823d33999 3368 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3369 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3370
<> 149:156823d33999 3371 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
<> 149:156823d33999 3372 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
<> 149:156823d33999 3373 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
<> 149:156823d33999 3374 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3375 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3376
<> 149:156823d33999 3377 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
<> 149:156823d33999 3378 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
<> 149:156823d33999 3379 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
<> 149:156823d33999 3380 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3381 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
<> 149:156823d33999 3382
<> 149:156823d33999 3383 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
<> 149:156823d33999 3384 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
<> 149:156823d33999 3385 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
<> 149:156823d33999 3386 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
<> 149:156823d33999 3387 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3388
<> 149:156823d33999 3389 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
<> 149:156823d33999 3390 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
<> 149:156823d33999 3391 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
<> 149:156823d33999 3392 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
<> 149:156823d33999 3393 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
<> 149:156823d33999 3394
<> 149:156823d33999 3395 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
<> 149:156823d33999 3396 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
<> 149:156823d33999 3397 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
<> 149:156823d33999 3398 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
<> 149:156823d33999 3399 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
<> 149:156823d33999 3400
<> 149:156823d33999 3401 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
<> 149:156823d33999 3402 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
<> 149:156823d33999 3403 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
<> 149:156823d33999 3404 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
<> 149:156823d33999 3405 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
<> 149:156823d33999 3406
<> 149:156823d33999 3407 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
<> 149:156823d33999 3408 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
<> 149:156823d33999 3409 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
<> 149:156823d33999 3410 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
<> 149:156823d33999 3411 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
<> 149:156823d33999 3412
<> 149:156823d33999 3413 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
<> 149:156823d33999 3414 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
<> 149:156823d33999 3415 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
<> 149:156823d33999 3416 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
<> 149:156823d33999 3417 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
<> 149:156823d33999 3418
<> 149:156823d33999 3419 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
<> 149:156823d33999 3420 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
<> 149:156823d33999 3421 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
<> 149:156823d33999 3422 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
<> 149:156823d33999 3423 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
<> 149:156823d33999 3424
<> 149:156823d33999 3425 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
<> 149:156823d33999 3426 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
<> 149:156823d33999 3427 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
<> 149:156823d33999 3428 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
<> 149:156823d33999 3429 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
<> 149:156823d33999 3430
<> 149:156823d33999 3431 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
<> 149:156823d33999 3432 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
<> 149:156823d33999 3433 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
<> 149:156823d33999 3434 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
<> 149:156823d33999 3435 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
<> 149:156823d33999 3436
<> 149:156823d33999 3437 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 149:156823d33999 3438 #define GPIO_PUPDR_PUPDR0_Pos (0U)
<> 149:156823d33999 3439 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
<> 149:156823d33999 3440 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
<> 149:156823d33999 3441 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3442 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3443
<> 149:156823d33999 3444 #define GPIO_PUPDR_PUPDR1_Pos (2U)
<> 149:156823d33999 3445 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
<> 149:156823d33999 3446 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
<> 149:156823d33999 3447 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3448 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3449
<> 149:156823d33999 3450 #define GPIO_PUPDR_PUPDR2_Pos (4U)
<> 149:156823d33999 3451 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
<> 149:156823d33999 3452 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
<> 149:156823d33999 3453 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3454 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3455
<> 149:156823d33999 3456 #define GPIO_PUPDR_PUPDR3_Pos (6U)
<> 149:156823d33999 3457 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
<> 149:156823d33999 3458 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
<> 149:156823d33999 3459 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3460 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3461
<> 149:156823d33999 3462 #define GPIO_PUPDR_PUPDR4_Pos (8U)
<> 149:156823d33999 3463 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
<> 149:156823d33999 3464 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
<> 149:156823d33999 3465 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3466 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3467
<> 149:156823d33999 3468 #define GPIO_PUPDR_PUPDR5_Pos (10U)
<> 149:156823d33999 3469 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
<> 149:156823d33999 3470 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
<> 149:156823d33999 3471 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3472 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3473
<> 149:156823d33999 3474 #define GPIO_PUPDR_PUPDR6_Pos (12U)
<> 149:156823d33999 3475 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
<> 149:156823d33999 3476 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
<> 149:156823d33999 3477 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3478 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
<> 149:156823d33999 3479
<> 149:156823d33999 3480 #define GPIO_PUPDR_PUPDR7_Pos (14U)
<> 149:156823d33999 3481 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
<> 149:156823d33999 3482 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
<> 149:156823d33999 3483 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
<> 149:156823d33999 3484 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3485
<> 149:156823d33999 3486 #define GPIO_PUPDR_PUPDR8_Pos (16U)
<> 149:156823d33999 3487 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
<> 149:156823d33999 3488 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
<> 149:156823d33999 3489 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
<> 149:156823d33999 3490 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
<> 149:156823d33999 3491
<> 149:156823d33999 3492 #define GPIO_PUPDR_PUPDR9_Pos (18U)
<> 149:156823d33999 3493 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
<> 149:156823d33999 3494 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
<> 149:156823d33999 3495 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
<> 149:156823d33999 3496 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
<> 149:156823d33999 3497
<> 149:156823d33999 3498 #define GPIO_PUPDR_PUPDR10_Pos (20U)
<> 149:156823d33999 3499 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
<> 149:156823d33999 3500 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
<> 149:156823d33999 3501 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
<> 149:156823d33999 3502 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
<> 149:156823d33999 3503
<> 149:156823d33999 3504 #define GPIO_PUPDR_PUPDR11_Pos (22U)
<> 149:156823d33999 3505 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
<> 149:156823d33999 3506 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
<> 149:156823d33999 3507 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
<> 149:156823d33999 3508 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
<> 149:156823d33999 3509
<> 149:156823d33999 3510 #define GPIO_PUPDR_PUPDR12_Pos (24U)
<> 149:156823d33999 3511 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
<> 149:156823d33999 3512 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
<> 149:156823d33999 3513 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
<> 149:156823d33999 3514 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
<> 149:156823d33999 3515
<> 149:156823d33999 3516 #define GPIO_PUPDR_PUPDR13_Pos (26U)
<> 149:156823d33999 3517 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
<> 149:156823d33999 3518 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
<> 149:156823d33999 3519 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
<> 149:156823d33999 3520 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
<> 149:156823d33999 3521
<> 149:156823d33999 3522 #define GPIO_PUPDR_PUPDR14_Pos (28U)
<> 149:156823d33999 3523 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
<> 149:156823d33999 3524 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
<> 149:156823d33999 3525 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
<> 149:156823d33999 3526 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
<> 149:156823d33999 3527 #define GPIO_PUPDR_PUPDR15_Pos (30U)
<> 149:156823d33999 3528 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
<> 149:156823d33999 3529 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
<> 149:156823d33999 3530 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
<> 149:156823d33999 3531 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
<> 149:156823d33999 3532
<> 149:156823d33999 3533 /****************** Bits definition for GPIO_IDR register *******************/
<> 149:156823d33999 3534 #define GPIO_IDR_IDR_0 (0x00000001U)
<> 149:156823d33999 3535 #define GPIO_IDR_IDR_1 (0x00000002U)
<> 149:156823d33999 3536 #define GPIO_IDR_IDR_2 (0x00000004U)
<> 149:156823d33999 3537 #define GPIO_IDR_IDR_3 (0x00000008U)
<> 149:156823d33999 3538 #define GPIO_IDR_IDR_4 (0x00000010U)
<> 149:156823d33999 3539 #define GPIO_IDR_IDR_5 (0x00000020U)
<> 149:156823d33999 3540 #define GPIO_IDR_IDR_6 (0x00000040U)
<> 149:156823d33999 3541 #define GPIO_IDR_IDR_7 (0x00000080U)
<> 149:156823d33999 3542 #define GPIO_IDR_IDR_8 (0x00000100U)
<> 149:156823d33999 3543 #define GPIO_IDR_IDR_9 (0x00000200U)
<> 149:156823d33999 3544 #define GPIO_IDR_IDR_10 (0x00000400U)
<> 149:156823d33999 3545 #define GPIO_IDR_IDR_11 (0x00000800U)
<> 149:156823d33999 3546 #define GPIO_IDR_IDR_12 (0x00001000U)
<> 149:156823d33999 3547 #define GPIO_IDR_IDR_13 (0x00002000U)
<> 149:156823d33999 3548 #define GPIO_IDR_IDR_14 (0x00004000U)
<> 149:156823d33999 3549 #define GPIO_IDR_IDR_15 (0x00008000U)
<> 149:156823d33999 3550
<> 149:156823d33999 3551 /****************** Bits definition for GPIO_ODR register *******************/
<> 149:156823d33999 3552 #define GPIO_ODR_ODR_0 (0x00000001U)
<> 149:156823d33999 3553 #define GPIO_ODR_ODR_1 (0x00000002U)
<> 149:156823d33999 3554 #define GPIO_ODR_ODR_2 (0x00000004U)
<> 149:156823d33999 3555 #define GPIO_ODR_ODR_3 (0x00000008U)
<> 149:156823d33999 3556 #define GPIO_ODR_ODR_4 (0x00000010U)
<> 149:156823d33999 3557 #define GPIO_ODR_ODR_5 (0x00000020U)
<> 149:156823d33999 3558 #define GPIO_ODR_ODR_6 (0x00000040U)
<> 149:156823d33999 3559 #define GPIO_ODR_ODR_7 (0x00000080U)
<> 149:156823d33999 3560 #define GPIO_ODR_ODR_8 (0x00000100U)
<> 149:156823d33999 3561 #define GPIO_ODR_ODR_9 (0x00000200U)
<> 149:156823d33999 3562 #define GPIO_ODR_ODR_10 (0x00000400U)
<> 149:156823d33999 3563 #define GPIO_ODR_ODR_11 (0x00000800U)
<> 149:156823d33999 3564 #define GPIO_ODR_ODR_12 (0x00001000U)
<> 149:156823d33999 3565 #define GPIO_ODR_ODR_13 (0x00002000U)
<> 149:156823d33999 3566 #define GPIO_ODR_ODR_14 (0x00004000U)
<> 149:156823d33999 3567 #define GPIO_ODR_ODR_15 (0x00008000U)
<> 149:156823d33999 3568
<> 149:156823d33999 3569 /****************** Bits definition for GPIO_BSRR register ******************/
<> 149:156823d33999 3570 #define GPIO_BSRR_BS_0 (0x00000001U)
<> 149:156823d33999 3571 #define GPIO_BSRR_BS_1 (0x00000002U)
<> 149:156823d33999 3572 #define GPIO_BSRR_BS_2 (0x00000004U)
<> 149:156823d33999 3573 #define GPIO_BSRR_BS_3 (0x00000008U)
<> 149:156823d33999 3574 #define GPIO_BSRR_BS_4 (0x00000010U)
<> 149:156823d33999 3575 #define GPIO_BSRR_BS_5 (0x00000020U)
<> 149:156823d33999 3576 #define GPIO_BSRR_BS_6 (0x00000040U)
<> 149:156823d33999 3577 #define GPIO_BSRR_BS_7 (0x00000080U)
<> 149:156823d33999 3578 #define GPIO_BSRR_BS_8 (0x00000100U)
<> 149:156823d33999 3579 #define GPIO_BSRR_BS_9 (0x00000200U)
<> 149:156823d33999 3580 #define GPIO_BSRR_BS_10 (0x00000400U)
<> 149:156823d33999 3581 #define GPIO_BSRR_BS_11 (0x00000800U)
<> 149:156823d33999 3582 #define GPIO_BSRR_BS_12 (0x00001000U)
<> 149:156823d33999 3583 #define GPIO_BSRR_BS_13 (0x00002000U)
<> 149:156823d33999 3584 #define GPIO_BSRR_BS_14 (0x00004000U)
<> 149:156823d33999 3585 #define GPIO_BSRR_BS_15 (0x00008000U)
<> 149:156823d33999 3586 #define GPIO_BSRR_BR_0 (0x00010000U)
<> 149:156823d33999 3587 #define GPIO_BSRR_BR_1 (0x00020000U)
<> 149:156823d33999 3588 #define GPIO_BSRR_BR_2 (0x00040000U)
<> 149:156823d33999 3589 #define GPIO_BSRR_BR_3 (0x00080000U)
<> 149:156823d33999 3590 #define GPIO_BSRR_BR_4 (0x00100000U)
<> 149:156823d33999 3591 #define GPIO_BSRR_BR_5 (0x00200000U)
<> 149:156823d33999 3592 #define GPIO_BSRR_BR_6 (0x00400000U)
<> 149:156823d33999 3593 #define GPIO_BSRR_BR_7 (0x00800000U)
<> 149:156823d33999 3594 #define GPIO_BSRR_BR_8 (0x01000000U)
<> 149:156823d33999 3595 #define GPIO_BSRR_BR_9 (0x02000000U)
<> 149:156823d33999 3596 #define GPIO_BSRR_BR_10 (0x04000000U)
<> 149:156823d33999 3597 #define GPIO_BSRR_BR_11 (0x08000000U)
<> 149:156823d33999 3598 #define GPIO_BSRR_BR_12 (0x10000000U)
<> 149:156823d33999 3599 #define GPIO_BSRR_BR_13 (0x20000000U)
<> 149:156823d33999 3600 #define GPIO_BSRR_BR_14 (0x40000000U)
<> 149:156823d33999 3601 #define GPIO_BSRR_BR_15 (0x80000000U)
<> 149:156823d33999 3602
<> 149:156823d33999 3603 /****************** Bit definition for GPIO_LCKR register ********************/
<> 149:156823d33999 3604 #define GPIO_LCKR_LCK0_Pos (0U)
<> 149:156823d33999 3605 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3606 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
<> 149:156823d33999 3607 #define GPIO_LCKR_LCK1_Pos (1U)
<> 149:156823d33999 3608 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3609 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
<> 149:156823d33999 3610 #define GPIO_LCKR_LCK2_Pos (2U)
<> 149:156823d33999 3611 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3612 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
<> 149:156823d33999 3613 #define GPIO_LCKR_LCK3_Pos (3U)
<> 149:156823d33999 3614 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3615 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
<> 149:156823d33999 3616 #define GPIO_LCKR_LCK4_Pos (4U)
<> 149:156823d33999 3617 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3618 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
<> 149:156823d33999 3619 #define GPIO_LCKR_LCK5_Pos (5U)
<> 149:156823d33999 3620 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3621 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
<> 149:156823d33999 3622 #define GPIO_LCKR_LCK6_Pos (6U)
<> 149:156823d33999 3623 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3624 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
<> 149:156823d33999 3625 #define GPIO_LCKR_LCK7_Pos (7U)
<> 149:156823d33999 3626 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3627 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
<> 149:156823d33999 3628 #define GPIO_LCKR_LCK8_Pos (8U)
<> 149:156823d33999 3629 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3630 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
<> 149:156823d33999 3631 #define GPIO_LCKR_LCK9_Pos (9U)
<> 149:156823d33999 3632 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3633 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
<> 149:156823d33999 3634 #define GPIO_LCKR_LCK10_Pos (10U)
<> 149:156823d33999 3635 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3636 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
<> 149:156823d33999 3637 #define GPIO_LCKR_LCK11_Pos (11U)
<> 149:156823d33999 3638 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3639 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
<> 149:156823d33999 3640 #define GPIO_LCKR_LCK12_Pos (12U)
<> 149:156823d33999 3641 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3642 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
<> 149:156823d33999 3643 #define GPIO_LCKR_LCK13_Pos (13U)
<> 149:156823d33999 3644 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
<> 149:156823d33999 3645 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
<> 149:156823d33999 3646 #define GPIO_LCKR_LCK14_Pos (14U)
<> 149:156823d33999 3647 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
<> 149:156823d33999 3648 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
<> 149:156823d33999 3649 #define GPIO_LCKR_LCK15_Pos (15U)
<> 149:156823d33999 3650 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3651 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
<> 149:156823d33999 3652 #define GPIO_LCKR_LCKK_Pos (16U)
<> 149:156823d33999 3653 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
<> 149:156823d33999 3654 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
<> 149:156823d33999 3655
<> 149:156823d33999 3656 /****************** Bit definition for GPIO_AFRL register ********************/
AnnaBridge 184:08ed48f1de7f 3657 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 184:08ed48f1de7f 3658 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 184:08ed48f1de7f 3659 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 184:08ed48f1de7f 3660 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 184:08ed48f1de7f 3661 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 184:08ed48f1de7f 3662 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 184:08ed48f1de7f 3663 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 184:08ed48f1de7f 3664 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 184:08ed48f1de7f 3665 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 184:08ed48f1de7f 3666 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 184:08ed48f1de7f 3667 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 184:08ed48f1de7f 3668 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 184:08ed48f1de7f 3669 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 184:08ed48f1de7f 3670 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 184:08ed48f1de7f 3671 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 184:08ed48f1de7f 3672 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 184:08ed48f1de7f 3673 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 184:08ed48f1de7f 3674 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 184:08ed48f1de7f 3675 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 184:08ed48f1de7f 3676 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 184:08ed48f1de7f 3677 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 184:08ed48f1de7f 3678 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 184:08ed48f1de7f 3679 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 184:08ed48f1de7f 3680 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
<> 149:156823d33999 3681
<> 149:156823d33999 3682 /****************** Bit definition for GPIO_AFRH register ********************/
AnnaBridge 184:08ed48f1de7f 3683 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 184:08ed48f1de7f 3684 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 184:08ed48f1de7f 3685 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 184:08ed48f1de7f 3686 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 184:08ed48f1de7f 3687 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 184:08ed48f1de7f 3688 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 184:08ed48f1de7f 3689 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 184:08ed48f1de7f 3690 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 184:08ed48f1de7f 3691 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 184:08ed48f1de7f 3692 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 184:08ed48f1de7f 3693 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 184:08ed48f1de7f 3694 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 184:08ed48f1de7f 3695 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 184:08ed48f1de7f 3696 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 184:08ed48f1de7f 3697 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 184:08ed48f1de7f 3698 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 184:08ed48f1de7f 3699 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 184:08ed48f1de7f 3700 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 184:08ed48f1de7f 3701 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 184:08ed48f1de7f 3702 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 184:08ed48f1de7f 3703 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 184:08ed48f1de7f 3704 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 184:08ed48f1de7f 3705 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 184:08ed48f1de7f 3706 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
<> 149:156823d33999 3707
<> 149:156823d33999 3708 /****************** Bit definition for GPIO_BRR register *********************/
<> 149:156823d33999 3709 #define GPIO_BRR_BR_0 (0x00000001U)
<> 149:156823d33999 3710 #define GPIO_BRR_BR_1 (0x00000002U)
<> 149:156823d33999 3711 #define GPIO_BRR_BR_2 (0x00000004U)
<> 149:156823d33999 3712 #define GPIO_BRR_BR_3 (0x00000008U)
<> 149:156823d33999 3713 #define GPIO_BRR_BR_4 (0x00000010U)
<> 149:156823d33999 3714 #define GPIO_BRR_BR_5 (0x00000020U)
<> 149:156823d33999 3715 #define GPIO_BRR_BR_6 (0x00000040U)
<> 149:156823d33999 3716 #define GPIO_BRR_BR_7 (0x00000080U)
<> 149:156823d33999 3717 #define GPIO_BRR_BR_8 (0x00000100U)
<> 149:156823d33999 3718 #define GPIO_BRR_BR_9 (0x00000200U)
<> 149:156823d33999 3719 #define GPIO_BRR_BR_10 (0x00000400U)
<> 149:156823d33999 3720 #define GPIO_BRR_BR_11 (0x00000800U)
<> 149:156823d33999 3721 #define GPIO_BRR_BR_12 (0x00001000U)
<> 149:156823d33999 3722 #define GPIO_BRR_BR_13 (0x00002000U)
<> 149:156823d33999 3723 #define GPIO_BRR_BR_14 (0x00004000U)
<> 149:156823d33999 3724 #define GPIO_BRR_BR_15 (0x00008000U)
<> 149:156823d33999 3725
<> 149:156823d33999 3726 /******************************************************************************/
<> 149:156823d33999 3727 /* */
<> 149:156823d33999 3728 /* Inter-integrated Circuit Interface (I2C) */
<> 149:156823d33999 3729 /* */
<> 149:156823d33999 3730 /******************************************************************************/
<> 149:156823d33999 3731
<> 149:156823d33999 3732 /******************* Bit definition for I2C_CR1 register ********************/
<> 149:156823d33999 3733 #define I2C_CR1_PE_Pos (0U)
<> 149:156823d33999 3734 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3735 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
<> 149:156823d33999 3736 #define I2C_CR1_SMBUS_Pos (1U)
<> 149:156823d33999 3737 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3738 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
<> 149:156823d33999 3739 #define I2C_CR1_SMBTYPE_Pos (3U)
<> 149:156823d33999 3740 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3741 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
<> 149:156823d33999 3742 #define I2C_CR1_ENARP_Pos (4U)
<> 149:156823d33999 3743 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3744 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
<> 149:156823d33999 3745 #define I2C_CR1_ENPEC_Pos (5U)
<> 149:156823d33999 3746 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3747 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
<> 149:156823d33999 3748 #define I2C_CR1_ENGC_Pos (6U)
<> 149:156823d33999 3749 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3750 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
<> 149:156823d33999 3751 #define I2C_CR1_NOSTRETCH_Pos (7U)
<> 149:156823d33999 3752 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3753 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
<> 149:156823d33999 3754 #define I2C_CR1_START_Pos (8U)
<> 149:156823d33999 3755 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3756 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
<> 149:156823d33999 3757 #define I2C_CR1_STOP_Pos (9U)
<> 149:156823d33999 3758 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3759 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
<> 149:156823d33999 3760 #define I2C_CR1_ACK_Pos (10U)
<> 149:156823d33999 3761 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3762 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
<> 149:156823d33999 3763 #define I2C_CR1_POS_Pos (11U)
<> 149:156823d33999 3764 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3765 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
<> 149:156823d33999 3766 #define I2C_CR1_PEC_Pos (12U)
<> 149:156823d33999 3767 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3768 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
<> 149:156823d33999 3769 #define I2C_CR1_ALERT_Pos (13U)
<> 149:156823d33999 3770 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
<> 149:156823d33999 3771 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
<> 149:156823d33999 3772 #define I2C_CR1_SWRST_Pos (15U)
<> 149:156823d33999 3773 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3774 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
<> 149:156823d33999 3775
<> 149:156823d33999 3776 /******************* Bit definition for I2C_CR2 register ********************/
<> 149:156823d33999 3777 #define I2C_CR2_FREQ_Pos (0U)
<> 149:156823d33999 3778 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
<> 149:156823d33999 3779 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
<> 149:156823d33999 3780 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3781 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3782 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3783 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3784 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3785 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3786
<> 149:156823d33999 3787 #define I2C_CR2_ITERREN_Pos (8U)
<> 149:156823d33999 3788 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3789 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
<> 149:156823d33999 3790 #define I2C_CR2_ITEVTEN_Pos (9U)
<> 149:156823d33999 3791 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3792 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
<> 149:156823d33999 3793 #define I2C_CR2_ITBUFEN_Pos (10U)
<> 149:156823d33999 3794 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3795 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
<> 149:156823d33999 3796 #define I2C_CR2_DMAEN_Pos (11U)
<> 149:156823d33999 3797 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3798 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
<> 149:156823d33999 3799 #define I2C_CR2_LAST_Pos (12U)
<> 149:156823d33999 3800 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3801 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
<> 149:156823d33999 3802
<> 149:156823d33999 3803 /******************* Bit definition for I2C_OAR1 register *******************/
<> 149:156823d33999 3804 #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */
<> 149:156823d33999 3805 #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */
<> 149:156823d33999 3806
<> 149:156823d33999 3807 #define I2C_OAR1_ADD0_Pos (0U)
<> 149:156823d33999 3808 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3809 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
<> 149:156823d33999 3810 #define I2C_OAR1_ADD1_Pos (1U)
<> 149:156823d33999 3811 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3812 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
<> 149:156823d33999 3813 #define I2C_OAR1_ADD2_Pos (2U)
<> 149:156823d33999 3814 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3815 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
<> 149:156823d33999 3816 #define I2C_OAR1_ADD3_Pos (3U)
<> 149:156823d33999 3817 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3818 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
<> 149:156823d33999 3819 #define I2C_OAR1_ADD4_Pos (4U)
<> 149:156823d33999 3820 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3821 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
<> 149:156823d33999 3822 #define I2C_OAR1_ADD5_Pos (5U)
<> 149:156823d33999 3823 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3824 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
<> 149:156823d33999 3825 #define I2C_OAR1_ADD6_Pos (6U)
<> 149:156823d33999 3826 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3827 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
<> 149:156823d33999 3828 #define I2C_OAR1_ADD7_Pos (7U)
<> 149:156823d33999 3829 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3830 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
<> 149:156823d33999 3831 #define I2C_OAR1_ADD8_Pos (8U)
<> 149:156823d33999 3832 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3833 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
<> 149:156823d33999 3834 #define I2C_OAR1_ADD9_Pos (9U)
<> 149:156823d33999 3835 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3836 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
<> 149:156823d33999 3837
<> 149:156823d33999 3838 #define I2C_OAR1_ADDMODE_Pos (15U)
<> 149:156823d33999 3839 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3840 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
<> 149:156823d33999 3841
<> 149:156823d33999 3842 /******************* Bit definition for I2C_OAR2 register *******************/
<> 149:156823d33999 3843 #define I2C_OAR2_ENDUAL_Pos (0U)
<> 149:156823d33999 3844 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3845 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
<> 149:156823d33999 3846 #define I2C_OAR2_ADD2_Pos (1U)
<> 149:156823d33999 3847 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
<> 149:156823d33999 3848 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
<> 149:156823d33999 3849
<> 149:156823d33999 3850 /******************** Bit definition for I2C_DR register ********************/
<> 149:156823d33999 3851 #define I2C_DR_DR_Pos (0U)
<> 149:156823d33999 3852 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
<> 149:156823d33999 3853 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
<> 149:156823d33999 3854
<> 149:156823d33999 3855 /******************* Bit definition for I2C_SR1 register ********************/
<> 149:156823d33999 3856 #define I2C_SR1_SB_Pos (0U)
<> 149:156823d33999 3857 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3858 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
<> 149:156823d33999 3859 #define I2C_SR1_ADDR_Pos (1U)
<> 149:156823d33999 3860 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3861 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
<> 149:156823d33999 3862 #define I2C_SR1_BTF_Pos (2U)
<> 149:156823d33999 3863 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3864 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
<> 149:156823d33999 3865 #define I2C_SR1_ADD10_Pos (3U)
<> 149:156823d33999 3866 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3867 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
<> 149:156823d33999 3868 #define I2C_SR1_STOPF_Pos (4U)
<> 149:156823d33999 3869 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3870 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
<> 149:156823d33999 3871 #define I2C_SR1_RXNE_Pos (6U)
<> 149:156823d33999 3872 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3873 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
<> 149:156823d33999 3874 #define I2C_SR1_TXE_Pos (7U)
<> 149:156823d33999 3875 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3876 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
<> 149:156823d33999 3877 #define I2C_SR1_BERR_Pos (8U)
<> 149:156823d33999 3878 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
<> 149:156823d33999 3879 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
<> 149:156823d33999 3880 #define I2C_SR1_ARLO_Pos (9U)
<> 149:156823d33999 3881 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
<> 149:156823d33999 3882 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
<> 149:156823d33999 3883 #define I2C_SR1_AF_Pos (10U)
<> 149:156823d33999 3884 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
<> 149:156823d33999 3885 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
<> 149:156823d33999 3886 #define I2C_SR1_OVR_Pos (11U)
<> 149:156823d33999 3887 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
<> 149:156823d33999 3888 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
<> 149:156823d33999 3889 #define I2C_SR1_PECERR_Pos (12U)
<> 149:156823d33999 3890 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
<> 149:156823d33999 3891 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
<> 149:156823d33999 3892 #define I2C_SR1_TIMEOUT_Pos (14U)
<> 149:156823d33999 3893 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
<> 149:156823d33999 3894 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
<> 149:156823d33999 3895 #define I2C_SR1_SMBALERT_Pos (15U)
<> 149:156823d33999 3896 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3897 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
<> 149:156823d33999 3898
<> 149:156823d33999 3899 /******************* Bit definition for I2C_SR2 register ********************/
<> 149:156823d33999 3900 #define I2C_SR2_MSL_Pos (0U)
<> 149:156823d33999 3901 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3902 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
<> 149:156823d33999 3903 #define I2C_SR2_BUSY_Pos (1U)
<> 149:156823d33999 3904 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3905 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
<> 149:156823d33999 3906 #define I2C_SR2_TRA_Pos (2U)
<> 149:156823d33999 3907 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3908 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
<> 149:156823d33999 3909 #define I2C_SR2_GENCALL_Pos (4U)
<> 149:156823d33999 3910 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3911 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
<> 149:156823d33999 3912 #define I2C_SR2_SMBDEFAULT_Pos (5U)
<> 149:156823d33999 3913 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3914 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
<> 149:156823d33999 3915 #define I2C_SR2_SMBHOST_Pos (6U)
<> 149:156823d33999 3916 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3917 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
<> 149:156823d33999 3918 #define I2C_SR2_DUALF_Pos (7U)
<> 149:156823d33999 3919 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
<> 149:156823d33999 3920 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
<> 149:156823d33999 3921 #define I2C_SR2_PEC_Pos (8U)
<> 149:156823d33999 3922 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
<> 149:156823d33999 3923 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
<> 149:156823d33999 3924
<> 149:156823d33999 3925 /******************* Bit definition for I2C_CCR register ********************/
<> 149:156823d33999 3926 #define I2C_CCR_CCR_Pos (0U)
<> 149:156823d33999 3927 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 3928 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
<> 149:156823d33999 3929 #define I2C_CCR_DUTY_Pos (14U)
<> 149:156823d33999 3930 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
<> 149:156823d33999 3931 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
<> 149:156823d33999 3932 #define I2C_CCR_FS_Pos (15U)
<> 149:156823d33999 3933 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
<> 149:156823d33999 3934 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
<> 149:156823d33999 3935
<> 149:156823d33999 3936 /****************** Bit definition for I2C_TRISE register *******************/
<> 149:156823d33999 3937 #define I2C_TRISE_TRISE_Pos (0U)
<> 149:156823d33999 3938 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
<> 149:156823d33999 3939 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
<> 149:156823d33999 3940
<> 149:156823d33999 3941 /******************************************************************************/
<> 149:156823d33999 3942 /* */
<> 149:156823d33999 3943 /* Independent WATCHDOG (IWDG) */
<> 149:156823d33999 3944 /* */
<> 149:156823d33999 3945 /******************************************************************************/
<> 149:156823d33999 3946
<> 149:156823d33999 3947 /******************* Bit definition for IWDG_KR register ********************/
<> 149:156823d33999 3948 #define IWDG_KR_KEY_Pos (0U)
<> 149:156823d33999 3949 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 3950 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
<> 149:156823d33999 3951
<> 149:156823d33999 3952 /******************* Bit definition for IWDG_PR register ********************/
<> 149:156823d33999 3953 #define IWDG_PR_PR_Pos (0U)
<> 149:156823d33999 3954 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
<> 149:156823d33999 3955 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
<> 149:156823d33999 3956 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3957 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3958 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3959
<> 149:156823d33999 3960 /******************* Bit definition for IWDG_RLR register *******************/
<> 149:156823d33999 3961 #define IWDG_RLR_RL_Pos (0U)
<> 149:156823d33999 3962 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
<> 149:156823d33999 3963 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
<> 149:156823d33999 3964
<> 149:156823d33999 3965 /******************* Bit definition for IWDG_SR register ********************/
<> 149:156823d33999 3966 #define IWDG_SR_PVU_Pos (0U)
<> 149:156823d33999 3967 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3968 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
<> 149:156823d33999 3969 #define IWDG_SR_RVU_Pos (1U)
<> 149:156823d33999 3970 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3971 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
<> 149:156823d33999 3972
<> 149:156823d33999 3973 /******************************************************************************/
<> 149:156823d33999 3974 /* */
<> 149:156823d33999 3975 /* LCD Controller (LCD) */
<> 149:156823d33999 3976 /* */
<> 149:156823d33999 3977 /******************************************************************************/
<> 149:156823d33999 3978
<> 149:156823d33999 3979 /******************* Bit definition for LCD_CR register *********************/
<> 149:156823d33999 3980 #define LCD_CR_LCDEN_Pos (0U)
<> 149:156823d33999 3981 #define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 3982 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
<> 149:156823d33999 3983 #define LCD_CR_VSEL_Pos (1U)
<> 149:156823d33999 3984 #define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
<> 149:156823d33999 3985 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
<> 149:156823d33999 3986
<> 149:156823d33999 3987 #define LCD_CR_DUTY_Pos (2U)
<> 149:156823d33999 3988 #define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
<> 149:156823d33999 3989 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
<> 149:156823d33999 3990 #define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
<> 149:156823d33999 3991 #define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
<> 149:156823d33999 3992 #define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
<> 149:156823d33999 3993
<> 149:156823d33999 3994 #define LCD_CR_BIAS_Pos (5U)
<> 149:156823d33999 3995 #define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
<> 149:156823d33999 3996 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
<> 149:156823d33999 3997 #define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
<> 149:156823d33999 3998 #define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 3999
<> 149:156823d33999 4000 #define LCD_CR_MUX_SEG_Pos (7U)
<> 149:156823d33999 4001 #define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4002 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
<> 149:156823d33999 4003
<> 149:156823d33999 4004 /******************* Bit definition for LCD_FCR register ********************/
<> 149:156823d33999 4005 #define LCD_FCR_HD_Pos (0U)
<> 149:156823d33999 4006 #define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4007 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
<> 149:156823d33999 4008 #define LCD_FCR_SOFIE_Pos (1U)
<> 149:156823d33999 4009 #define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4010 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
<> 149:156823d33999 4011 #define LCD_FCR_UDDIE_Pos (3U)
<> 149:156823d33999 4012 #define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4013 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
<> 149:156823d33999 4014
<> 149:156823d33999 4015 #define LCD_FCR_PON_Pos (4U)
<> 149:156823d33999 4016 #define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
<> 149:156823d33999 4017 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
<> 149:156823d33999 4018 #define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4019 #define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4020 #define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
<> 149:156823d33999 4021
<> 149:156823d33999 4022 #define LCD_FCR_DEAD_Pos (7U)
<> 149:156823d33999 4023 #define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
<> 149:156823d33999 4024 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
<> 149:156823d33999 4025 #define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4026 #define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
<> 149:156823d33999 4027 #define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4028
<> 149:156823d33999 4029 #define LCD_FCR_CC_Pos (10U)
<> 149:156823d33999 4030 #define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
<> 149:156823d33999 4031 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
<> 149:156823d33999 4032 #define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
<> 149:156823d33999 4033 #define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4034 #define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4035
<> 149:156823d33999 4036 #define LCD_FCR_BLINKF_Pos (13U)
<> 149:156823d33999 4037 #define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
<> 149:156823d33999 4038 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
<> 149:156823d33999 4039 #define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
<> 149:156823d33999 4040 #define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4041 #define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4042
<> 149:156823d33999 4043 #define LCD_FCR_BLINK_Pos (16U)
<> 149:156823d33999 4044 #define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
<> 149:156823d33999 4045 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
<> 149:156823d33999 4046 #define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4047 #define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4048
<> 149:156823d33999 4049 #define LCD_FCR_DIV_Pos (18U)
<> 149:156823d33999 4050 #define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
<> 149:156823d33999 4051 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
<> 149:156823d33999 4052 #define LCD_FCR_PS_Pos (22U)
<> 149:156823d33999 4053 #define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
<> 149:156823d33999 4054 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
<> 149:156823d33999 4055
<> 149:156823d33999 4056 /******************* Bit definition for LCD_SR register *********************/
<> 149:156823d33999 4057 #define LCD_SR_ENS_Pos (0U)
<> 149:156823d33999 4058 #define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4059 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
<> 149:156823d33999 4060 #define LCD_SR_SOF_Pos (1U)
<> 149:156823d33999 4061 #define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4062 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
<> 149:156823d33999 4063 #define LCD_SR_UDR_Pos (2U)
<> 149:156823d33999 4064 #define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4065 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
<> 149:156823d33999 4066 #define LCD_SR_UDD_Pos (3U)
<> 149:156823d33999 4067 #define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4068 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
<> 149:156823d33999 4069 #define LCD_SR_RDY_Pos (4U)
<> 149:156823d33999 4070 #define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4071 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
<> 149:156823d33999 4072 #define LCD_SR_FCRSR_Pos (5U)
<> 149:156823d33999 4073 #define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4074 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
<> 149:156823d33999 4075
<> 149:156823d33999 4076 /******************* Bit definition for LCD_CLR register ********************/
<> 149:156823d33999 4077 #define LCD_CLR_SOFC_Pos (1U)
<> 149:156823d33999 4078 #define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4079 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
<> 149:156823d33999 4080 #define LCD_CLR_UDDC_Pos (3U)
<> 149:156823d33999 4081 #define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4082 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
<> 149:156823d33999 4083
<> 149:156823d33999 4084 /******************* Bit definition for LCD_RAM register ********************/
<> 149:156823d33999 4085 #define LCD_RAM_SEGMENT_DATA_Pos (0U)
<> 149:156823d33999 4086 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 4087 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
<> 149:156823d33999 4088
<> 149:156823d33999 4089 /******************************************************************************/
<> 149:156823d33999 4090 /* */
<> 149:156823d33999 4091 /* Power Control (PWR) */
<> 149:156823d33999 4092 /* */
<> 149:156823d33999 4093 /******************************************************************************/
<> 149:156823d33999 4094
<> 149:156823d33999 4095 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
<> 149:156823d33999 4096
<> 149:156823d33999 4097 /******************** Bit definition for PWR_CR register ********************/
<> 149:156823d33999 4098 #define PWR_CR_LPSDSR_Pos (0U)
<> 149:156823d33999 4099 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4100 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
<> 149:156823d33999 4101 #define PWR_CR_PDDS_Pos (1U)
<> 149:156823d33999 4102 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4103 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
<> 149:156823d33999 4104 #define PWR_CR_CWUF_Pos (2U)
<> 149:156823d33999 4105 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4106 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
<> 149:156823d33999 4107 #define PWR_CR_CSBF_Pos (3U)
<> 149:156823d33999 4108 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4109 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
<> 149:156823d33999 4110 #define PWR_CR_PVDE_Pos (4U)
<> 149:156823d33999 4111 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4112 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
<> 149:156823d33999 4113
<> 149:156823d33999 4114 #define PWR_CR_PLS_Pos (5U)
<> 149:156823d33999 4115 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
<> 149:156823d33999 4116 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
<> 149:156823d33999 4117 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4118 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 4119 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4120
<> 149:156823d33999 4121 /*!< PVD level configuration */
<> 149:156823d33999 4122 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
<> 149:156823d33999 4123 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
<> 149:156823d33999 4124 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
<> 149:156823d33999 4125 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
<> 149:156823d33999 4126 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
<> 149:156823d33999 4127 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
<> 149:156823d33999 4128 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
<> 149:156823d33999 4129 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
<> 149:156823d33999 4130
<> 149:156823d33999 4131 #define PWR_CR_DBP_Pos (8U)
<> 149:156823d33999 4132 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
<> 149:156823d33999 4133 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
<> 149:156823d33999 4134 #define PWR_CR_ULP_Pos (9U)
<> 149:156823d33999 4135 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4136 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
<> 149:156823d33999 4137 #define PWR_CR_FWU_Pos (10U)
<> 149:156823d33999 4138 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
<> 149:156823d33999 4139 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
<> 149:156823d33999 4140
<> 149:156823d33999 4141 #define PWR_CR_VOS_Pos (11U)
<> 149:156823d33999 4142 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
<> 149:156823d33999 4143 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
<> 149:156823d33999 4144 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4145 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4146 #define PWR_CR_LPRUN_Pos (14U)
<> 149:156823d33999 4147 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4148 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
<> 149:156823d33999 4149
<> 149:156823d33999 4150 /******************* Bit definition for PWR_CSR register ********************/
<> 149:156823d33999 4151 #define PWR_CSR_WUF_Pos (0U)
<> 149:156823d33999 4152 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4153 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
<> 149:156823d33999 4154 #define PWR_CSR_SBF_Pos (1U)
<> 149:156823d33999 4155 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4156 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
<> 149:156823d33999 4157 #define PWR_CSR_PVDO_Pos (2U)
<> 149:156823d33999 4158 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4159 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
<> 149:156823d33999 4160 #define PWR_CSR_VREFINTRDYF_Pos (3U)
<> 149:156823d33999 4161 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4162 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
<> 149:156823d33999 4163 #define PWR_CSR_VOSF_Pos (4U)
<> 149:156823d33999 4164 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4165 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
<> 149:156823d33999 4166 #define PWR_CSR_REGLPF_Pos (5U)
<> 149:156823d33999 4167 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4168 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
<> 149:156823d33999 4169
<> 149:156823d33999 4170 #define PWR_CSR_EWUP1_Pos (8U)
<> 149:156823d33999 4171 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
<> 149:156823d33999 4172 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
<> 149:156823d33999 4173 #define PWR_CSR_EWUP2_Pos (9U)
<> 149:156823d33999 4174 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4175 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
<> 149:156823d33999 4176 #define PWR_CSR_EWUP3_Pos (10U)
<> 149:156823d33999 4177 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
<> 149:156823d33999 4178 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
<> 149:156823d33999 4179
<> 149:156823d33999 4180 /******************************************************************************/
<> 149:156823d33999 4181 /* */
<> 149:156823d33999 4182 /* Reset and Clock Control (RCC) */
<> 149:156823d33999 4183 /* */
<> 149:156823d33999 4184 /******************************************************************************/
<> 149:156823d33999 4185 /*
<> 149:156823d33999 4186 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 149:156823d33999 4187 */
<> 149:156823d33999 4188 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
<> 149:156823d33999 4189
<> 149:156823d33999 4190 /******************** Bit definition for RCC_CR register ********************/
<> 149:156823d33999 4191 #define RCC_CR_HSION_Pos (0U)
<> 149:156823d33999 4192 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4193 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
<> 149:156823d33999 4194 #define RCC_CR_HSIRDY_Pos (1U)
<> 149:156823d33999 4195 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4196 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
<> 149:156823d33999 4197
<> 149:156823d33999 4198 #define RCC_CR_MSION_Pos (8U)
<> 149:156823d33999 4199 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
<> 149:156823d33999 4200 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
<> 149:156823d33999 4201 #define RCC_CR_MSIRDY_Pos (9U)
<> 149:156823d33999 4202 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4203 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
<> 149:156823d33999 4204
<> 149:156823d33999 4205 #define RCC_CR_HSEON_Pos (16U)
<> 149:156823d33999 4206 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4207 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
<> 149:156823d33999 4208 #define RCC_CR_HSERDY_Pos (17U)
<> 149:156823d33999 4209 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4210 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
<> 149:156823d33999 4211 #define RCC_CR_HSEBYP_Pos (18U)
<> 149:156823d33999 4212 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
<> 149:156823d33999 4213 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
<> 149:156823d33999 4214
<> 149:156823d33999 4215 #define RCC_CR_PLLON_Pos (24U)
<> 149:156823d33999 4216 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
<> 149:156823d33999 4217 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
<> 149:156823d33999 4218 #define RCC_CR_PLLRDY_Pos (25U)
<> 149:156823d33999 4219 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
<> 149:156823d33999 4220 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
<> 149:156823d33999 4221 #define RCC_CR_CSSON_Pos (28U)
<> 149:156823d33999 4222 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x10000000 */
<> 149:156823d33999 4223 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
<> 149:156823d33999 4224
<> 149:156823d33999 4225 #define RCC_CR_RTCPRE_Pos (29U)
<> 149:156823d33999 4226 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */
<> 149:156823d33999 4227 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD Prescaler */
<> 149:156823d33999 4228 #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */
<> 149:156823d33999 4229 #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */
<> 149:156823d33999 4230
<> 149:156823d33999 4231 /******************** Bit definition for RCC_ICSCR register *****************/
<> 149:156823d33999 4232 #define RCC_ICSCR_HSICAL_Pos (0U)
<> 149:156823d33999 4233 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
<> 149:156823d33999 4234 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
<> 149:156823d33999 4235 #define RCC_ICSCR_HSITRIM_Pos (8U)
<> 149:156823d33999 4236 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
<> 149:156823d33999 4237 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
<> 149:156823d33999 4238
<> 149:156823d33999 4239 #define RCC_ICSCR_MSIRANGE_Pos (13U)
<> 149:156823d33999 4240 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
<> 149:156823d33999 4241 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
<> 149:156823d33999 4242 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
<> 149:156823d33999 4243 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
<> 149:156823d33999 4244 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4245 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
<> 149:156823d33999 4246 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4247 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
<> 149:156823d33999 4248 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
<> 149:156823d33999 4249 #define RCC_ICSCR_MSICAL_Pos (16U)
<> 149:156823d33999 4250 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
<> 149:156823d33999 4251 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
<> 149:156823d33999 4252 #define RCC_ICSCR_MSITRIM_Pos (24U)
<> 149:156823d33999 4253 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
<> 149:156823d33999 4254 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
<> 149:156823d33999 4255
<> 149:156823d33999 4256 /******************** Bit definition for RCC_CFGR register ******************/
<> 149:156823d33999 4257 #define RCC_CFGR_SW_Pos (0U)
<> 149:156823d33999 4258 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
<> 149:156823d33999 4259 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
<> 149:156823d33999 4260 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4261 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4262
<> 149:156823d33999 4263 /*!< SW configuration */
<> 149:156823d33999 4264 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
<> 149:156823d33999 4265 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
<> 149:156823d33999 4266 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
<> 149:156823d33999 4267 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
<> 149:156823d33999 4268
<> 149:156823d33999 4269 #define RCC_CFGR_SWS_Pos (2U)
<> 149:156823d33999 4270 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
<> 149:156823d33999 4271 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 149:156823d33999 4272 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4273 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4274
<> 149:156823d33999 4275 /*!< SWS configuration */
<> 149:156823d33999 4276 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
<> 149:156823d33999 4277 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
<> 149:156823d33999 4278 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
<> 149:156823d33999 4279 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
<> 149:156823d33999 4280
<> 149:156823d33999 4281 #define RCC_CFGR_HPRE_Pos (4U)
<> 149:156823d33999 4282 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 4283 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
<> 149:156823d33999 4284 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4285 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4286 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 4287 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4288
<> 149:156823d33999 4289 /*!< HPRE configuration */
<> 149:156823d33999 4290 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
<> 149:156823d33999 4291 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
<> 149:156823d33999 4292 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
<> 149:156823d33999 4293 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
<> 149:156823d33999 4294 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
<> 149:156823d33999 4295 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
<> 149:156823d33999 4296 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
<> 149:156823d33999 4297 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
<> 149:156823d33999 4298 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
<> 149:156823d33999 4299
<> 149:156823d33999 4300 #define RCC_CFGR_PPRE1_Pos (8U)
<> 149:156823d33999 4301 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
<> 149:156823d33999 4302 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 149:156823d33999 4303 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
<> 149:156823d33999 4304 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4305 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
<> 149:156823d33999 4306
<> 149:156823d33999 4307 /*!< PPRE1 configuration */
<> 149:156823d33999 4308 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 149:156823d33999 4309 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
<> 149:156823d33999 4310 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
<> 149:156823d33999 4311 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
<> 149:156823d33999 4312 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
<> 149:156823d33999 4313
<> 149:156823d33999 4314 #define RCC_CFGR_PPRE2_Pos (11U)
<> 149:156823d33999 4315 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
<> 149:156823d33999 4316 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 149:156823d33999 4317 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4318 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4319 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
<> 149:156823d33999 4320
<> 149:156823d33999 4321 /*!< PPRE2 configuration */
<> 149:156823d33999 4322 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 149:156823d33999 4323 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
<> 149:156823d33999 4324 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
<> 149:156823d33999 4325 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
<> 149:156823d33999 4326 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
<> 149:156823d33999 4327
<> 149:156823d33999 4328 /*!< PLL entry clock source*/
<> 149:156823d33999 4329 #define RCC_CFGR_PLLSRC_Pos (16U)
<> 149:156823d33999 4330 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4331 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
<> 149:156823d33999 4332
<> 149:156823d33999 4333 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
<> 149:156823d33999 4334 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
<> 149:156823d33999 4335
<> 149:156823d33999 4336
<> 149:156823d33999 4337 /*!< PLLMUL configuration */
<> 149:156823d33999 4338 #define RCC_CFGR_PLLMUL_Pos (18U)
<> 149:156823d33999 4339 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
<> 149:156823d33999 4340 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
<> 149:156823d33999 4341 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
<> 149:156823d33999 4342 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
<> 149:156823d33999 4343 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
<> 149:156823d33999 4344 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
<> 149:156823d33999 4345
<> 149:156823d33999 4346 /*!< PLLMUL configuration */
<> 149:156823d33999 4347 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
<> 149:156823d33999 4348 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
<> 149:156823d33999 4349 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
<> 149:156823d33999 4350 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
<> 149:156823d33999 4351 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
<> 149:156823d33999 4352 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
<> 149:156823d33999 4353 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
<> 149:156823d33999 4354 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
<> 149:156823d33999 4355 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
<> 149:156823d33999 4356
<> 149:156823d33999 4357 /*!< PLLDIV configuration */
<> 149:156823d33999 4358 #define RCC_CFGR_PLLDIV_Pos (22U)
<> 149:156823d33999 4359 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
<> 149:156823d33999 4360 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
<> 149:156823d33999 4361 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4362 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
<> 149:156823d33999 4363
<> 149:156823d33999 4364
<> 149:156823d33999 4365 /*!< PLLDIV configuration */
<> 149:156823d33999 4366 #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */
<> 149:156823d33999 4367 #define RCC_CFGR_PLLDIV2_Pos (22U)
<> 149:156823d33999 4368 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4369 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
<> 149:156823d33999 4370 #define RCC_CFGR_PLLDIV3_Pos (23U)
<> 149:156823d33999 4371 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
<> 149:156823d33999 4372 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
<> 149:156823d33999 4373 #define RCC_CFGR_PLLDIV4_Pos (22U)
<> 149:156823d33999 4374 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
<> 149:156823d33999 4375 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
<> 149:156823d33999 4376
<> 149:156823d33999 4377
<> 149:156823d33999 4378 #define RCC_CFGR_MCOSEL_Pos (24U)
<> 149:156823d33999 4379 #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
<> 149:156823d33999 4380 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
<> 149:156823d33999 4381 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
<> 149:156823d33999 4382 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
<> 149:156823d33999 4383 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
<> 149:156823d33999 4384
<> 149:156823d33999 4385 /*!< MCO configuration */
<> 149:156823d33999 4386 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 149:156823d33999 4387 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
<> 149:156823d33999 4388 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
<> 149:156823d33999 4389 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */
<> 149:156823d33999 4390 #define RCC_CFGR_MCOSEL_HSI_Pos (25U)
<> 149:156823d33999 4391 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
<> 149:156823d33999 4392 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
<> 149:156823d33999 4393 #define RCC_CFGR_MCOSEL_MSI_Pos (24U)
<> 149:156823d33999 4394 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
<> 149:156823d33999 4395 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
<> 149:156823d33999 4396 #define RCC_CFGR_MCOSEL_HSE_Pos (26U)
<> 149:156823d33999 4397 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
<> 149:156823d33999 4398 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
<> 149:156823d33999 4399 #define RCC_CFGR_MCOSEL_PLL_Pos (24U)
<> 149:156823d33999 4400 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
<> 149:156823d33999 4401 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
<> 149:156823d33999 4402 #define RCC_CFGR_MCOSEL_LSI_Pos (25U)
<> 149:156823d33999 4403 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
<> 149:156823d33999 4404 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
<> 149:156823d33999 4405 #define RCC_CFGR_MCOSEL_LSE_Pos (24U)
<> 149:156823d33999 4406 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
<> 149:156823d33999 4407 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
<> 149:156823d33999 4408
<> 149:156823d33999 4409 #define RCC_CFGR_MCOPRE_Pos (28U)
<> 149:156823d33999 4410 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
<> 149:156823d33999 4411 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
<> 149:156823d33999 4412 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
<> 149:156823d33999 4413 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
<> 149:156823d33999 4414 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
<> 149:156823d33999 4415
<> 149:156823d33999 4416 /*!< MCO Prescaler configuration */
<> 149:156823d33999 4417 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
<> 149:156823d33999 4418 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
<> 149:156823d33999 4419 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
<> 149:156823d33999 4420 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
<> 149:156823d33999 4421 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
<> 149:156823d33999 4422
<> 149:156823d33999 4423 /* Legacy aliases */
<> 149:156823d33999 4424 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1
<> 149:156823d33999 4425 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
<> 149:156823d33999 4426 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4
<> 149:156823d33999 4427 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8
<> 149:156823d33999 4428 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16
<> 149:156823d33999 4429 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
<> 149:156823d33999 4430 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
<> 149:156823d33999 4431 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
<> 149:156823d33999 4432 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
<> 149:156823d33999 4433 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
<> 149:156823d33999 4434 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
<> 149:156823d33999 4435 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
<> 149:156823d33999 4436 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
<> 149:156823d33999 4437
<> 149:156823d33999 4438 /*!<****************** Bit definition for RCC_CIR register ********************/
<> 149:156823d33999 4439 #define RCC_CIR_LSIRDYF_Pos (0U)
<> 149:156823d33999 4440 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4441 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
<> 149:156823d33999 4442 #define RCC_CIR_LSERDYF_Pos (1U)
<> 149:156823d33999 4443 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4444 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
<> 149:156823d33999 4445 #define RCC_CIR_HSIRDYF_Pos (2U)
<> 149:156823d33999 4446 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4447 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
<> 149:156823d33999 4448 #define RCC_CIR_HSERDYF_Pos (3U)
<> 149:156823d33999 4449 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4450 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
<> 149:156823d33999 4451 #define RCC_CIR_PLLRDYF_Pos (4U)
<> 149:156823d33999 4452 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4453 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
<> 149:156823d33999 4454 #define RCC_CIR_MSIRDYF_Pos (5U)
<> 149:156823d33999 4455 #define RCC_CIR_MSIRDYF_Msk (0x1U << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4456 #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
<> 149:156823d33999 4457 #define RCC_CIR_LSECSSF_Pos (6U)
<> 149:156823d33999 4458 #define RCC_CIR_LSECSSF_Msk (0x1U << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */
<> 149:156823d33999 4459 #define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */
<> 149:156823d33999 4460 #define RCC_CIR_CSSF_Pos (7U)
<> 149:156823d33999 4461 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4462 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
<> 149:156823d33999 4463
<> 149:156823d33999 4464 #define RCC_CIR_LSIRDYIE_Pos (8U)
<> 149:156823d33999 4465 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 4466 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
<> 149:156823d33999 4467 #define RCC_CIR_LSERDYIE_Pos (9U)
<> 149:156823d33999 4468 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4469 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
<> 149:156823d33999 4470 #define RCC_CIR_HSIRDYIE_Pos (10U)
<> 149:156823d33999 4471 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 4472 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
<> 149:156823d33999 4473 #define RCC_CIR_HSERDYIE_Pos (11U)
<> 149:156823d33999 4474 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4475 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
<> 149:156823d33999 4476 #define RCC_CIR_PLLRDYIE_Pos (12U)
<> 149:156823d33999 4477 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4478 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
<> 149:156823d33999 4479 #define RCC_CIR_MSIRDYIE_Pos (13U)
<> 149:156823d33999 4480 #define RCC_CIR_MSIRDYIE_Msk (0x1U << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */
<> 149:156823d33999 4481 #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
<> 149:156823d33999 4482 #define RCC_CIR_LSECSSIE_Pos (14U)
<> 149:156823d33999 4483 #define RCC_CIR_LSECSSIE_Msk (0x1U << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4484 #define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */
<> 149:156823d33999 4485
<> 149:156823d33999 4486 #define RCC_CIR_LSIRDYC_Pos (16U)
<> 149:156823d33999 4487 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4488 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
<> 149:156823d33999 4489 #define RCC_CIR_LSERDYC_Pos (17U)
<> 149:156823d33999 4490 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4491 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
<> 149:156823d33999 4492 #define RCC_CIR_HSIRDYC_Pos (18U)
<> 149:156823d33999 4493 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
<> 149:156823d33999 4494 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
<> 149:156823d33999 4495 #define RCC_CIR_HSERDYC_Pos (19U)
<> 149:156823d33999 4496 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
<> 149:156823d33999 4497 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
<> 149:156823d33999 4498 #define RCC_CIR_PLLRDYC_Pos (20U)
<> 149:156823d33999 4499 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
<> 149:156823d33999 4500 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
<> 149:156823d33999 4501 #define RCC_CIR_MSIRDYC_Pos (21U)
<> 149:156823d33999 4502 #define RCC_CIR_MSIRDYC_Msk (0x1U << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */
<> 149:156823d33999 4503 #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
<> 149:156823d33999 4504 #define RCC_CIR_LSECSSC_Pos (22U)
<> 149:156823d33999 4505 #define RCC_CIR_LSECSSC_Msk (0x1U << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4506 #define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */
<> 149:156823d33999 4507 #define RCC_CIR_CSSC_Pos (23U)
<> 149:156823d33999 4508 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
<> 149:156823d33999 4509 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
<> 149:156823d33999 4510
<> 149:156823d33999 4511 /***************** Bit definition for RCC_AHBRSTR register ******************/
<> 149:156823d33999 4512 #define RCC_AHBRSTR_GPIOARST_Pos (0U)
<> 149:156823d33999 4513 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4514 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */
<> 149:156823d33999 4515 #define RCC_AHBRSTR_GPIOBRST_Pos (1U)
<> 149:156823d33999 4516 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4517 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */
<> 149:156823d33999 4518 #define RCC_AHBRSTR_GPIOCRST_Pos (2U)
<> 149:156823d33999 4519 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4520 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */
<> 149:156823d33999 4521 #define RCC_AHBRSTR_GPIODRST_Pos (3U)
<> 149:156823d33999 4522 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4523 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */
<> 149:156823d33999 4524 #define RCC_AHBRSTR_GPIOERST_Pos (4U)
<> 149:156823d33999 4525 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4526 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */
<> 149:156823d33999 4527 #define RCC_AHBRSTR_GPIOHRST_Pos (5U)
<> 149:156823d33999 4528 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4529 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */
<> 149:156823d33999 4530 #define RCC_AHBRSTR_GPIOFRST_Pos (6U)
<> 149:156823d33999 4531 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
<> 149:156823d33999 4532 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIO port F reset */
<> 149:156823d33999 4533 #define RCC_AHBRSTR_GPIOGRST_Pos (7U)
<> 149:156823d33999 4534 #define RCC_AHBRSTR_GPIOGRST_Msk (0x1U << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4535 #define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIO port G reset */
<> 149:156823d33999 4536 #define RCC_AHBRSTR_CRCRST_Pos (12U)
<> 149:156823d33999 4537 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4538 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
<> 149:156823d33999 4539 #define RCC_AHBRSTR_FLITFRST_Pos (15U)
<> 149:156823d33999 4540 #define RCC_AHBRSTR_FLITFRST_Msk (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4541 #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */
<> 149:156823d33999 4542 #define RCC_AHBRSTR_DMA1RST_Pos (24U)
<> 149:156823d33999 4543 #define RCC_AHBRSTR_DMA1RST_Msk (0x1U << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */
<> 149:156823d33999 4544 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */
<> 149:156823d33999 4545 #define RCC_AHBRSTR_DMA2RST_Pos (25U)
<> 149:156823d33999 4546 #define RCC_AHBRSTR_DMA2RST_Msk (0x1U << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */
<> 149:156823d33999 4547 #define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */
<> 149:156823d33999 4548
<> 149:156823d33999 4549 /***************** Bit definition for RCC_APB2RSTR register *****************/
<> 149:156823d33999 4550 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
<> 149:156823d33999 4551 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4552 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */
<> 149:156823d33999 4553 #define RCC_APB2RSTR_TIM9RST_Pos (2U)
<> 149:156823d33999 4554 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4555 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */
<> 149:156823d33999 4556 #define RCC_APB2RSTR_TIM10RST_Pos (3U)
<> 149:156823d33999 4557 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4558 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */
<> 149:156823d33999 4559 #define RCC_APB2RSTR_TIM11RST_Pos (4U)
<> 149:156823d33999 4560 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4561 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */
<> 149:156823d33999 4562 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
<> 149:156823d33999 4563 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4564 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */
<> 149:156823d33999 4565 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
<> 149:156823d33999 4566 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4567 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
<> 149:156823d33999 4568 #define RCC_APB2RSTR_USART1RST_Pos (14U)
<> 149:156823d33999 4569 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4570 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
<> 149:156823d33999 4571
<> 149:156823d33999 4572 /***************** Bit definition for RCC_APB1RSTR register *****************/
<> 149:156823d33999 4573 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
<> 149:156823d33999 4574 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4575 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
<> 149:156823d33999 4576 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
<> 149:156823d33999 4577 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4578 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
<> 149:156823d33999 4579 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
<> 149:156823d33999 4580 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4581 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
<> 149:156823d33999 4582 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
<> 149:156823d33999 4583 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4584 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
<> 149:156823d33999 4585 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
<> 149:156823d33999 4586 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4587 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
<> 149:156823d33999 4588 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
<> 149:156823d33999 4589 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4590 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
<> 149:156823d33999 4591 #define RCC_APB1RSTR_LCDRST_Pos (9U)
<> 149:156823d33999 4592 #define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4593 #define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */
<> 149:156823d33999 4594 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
<> 149:156823d33999 4595 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4596 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
<> 149:156823d33999 4597 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
<> 149:156823d33999 4598 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4599 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
<> 149:156823d33999 4600 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
<> 149:156823d33999 4601 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4602 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
<> 149:156823d33999 4603 #define RCC_APB1RSTR_USART2RST_Pos (17U)
<> 149:156823d33999 4604 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4605 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
<> 149:156823d33999 4606 #define RCC_APB1RSTR_USART3RST_Pos (18U)
<> 149:156823d33999 4607 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
<> 149:156823d33999 4608 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
<> 149:156823d33999 4609 #define RCC_APB1RSTR_UART4RST_Pos (19U)
<> 149:156823d33999 4610 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
<> 149:156823d33999 4611 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
<> 149:156823d33999 4612 #define RCC_APB1RSTR_UART5RST_Pos (20U)
<> 149:156823d33999 4613 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
<> 149:156823d33999 4614 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
<> 149:156823d33999 4615 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
<> 149:156823d33999 4616 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
<> 149:156823d33999 4617 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
<> 149:156823d33999 4618 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
<> 149:156823d33999 4619 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4620 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
<> 149:156823d33999 4621 #define RCC_APB1RSTR_USBRST_Pos (23U)
<> 149:156823d33999 4622 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
<> 149:156823d33999 4623 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
<> 149:156823d33999 4624 #define RCC_APB1RSTR_PWRRST_Pos (28U)
<> 149:156823d33999 4625 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
<> 149:156823d33999 4626 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
<> 149:156823d33999 4627 #define RCC_APB1RSTR_DACRST_Pos (29U)
<> 149:156823d33999 4628 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
<> 149:156823d33999 4629 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
<> 149:156823d33999 4630 #define RCC_APB1RSTR_COMPRST_Pos (31U)
<> 149:156823d33999 4631 #define RCC_APB1RSTR_COMPRST_Msk (0x1U << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
<> 149:156823d33999 4632 #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */
<> 149:156823d33999 4633
<> 149:156823d33999 4634 /****************** Bit definition for RCC_AHBENR register ******************/
<> 149:156823d33999 4635 #define RCC_AHBENR_GPIOAEN_Pos (0U)
<> 149:156823d33999 4636 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4637 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */
<> 149:156823d33999 4638 #define RCC_AHBENR_GPIOBEN_Pos (1U)
<> 149:156823d33999 4639 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4640 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */
<> 149:156823d33999 4641 #define RCC_AHBENR_GPIOCEN_Pos (2U)
<> 149:156823d33999 4642 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4643 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */
<> 149:156823d33999 4644 #define RCC_AHBENR_GPIODEN_Pos (3U)
<> 149:156823d33999 4645 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4646 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */
<> 149:156823d33999 4647 #define RCC_AHBENR_GPIOEEN_Pos (4U)
<> 149:156823d33999 4648 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4649 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */
<> 149:156823d33999 4650 #define RCC_AHBENR_GPIOHEN_Pos (5U)
<> 149:156823d33999 4651 #define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4652 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */
<> 149:156823d33999 4653 #define RCC_AHBENR_GPIOFEN_Pos (6U)
<> 149:156823d33999 4654 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00000040 */
<> 149:156823d33999 4655 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIO port F clock enable */
<> 149:156823d33999 4656 #define RCC_AHBENR_GPIOGEN_Pos (7U)
<> 149:156823d33999 4657 #define RCC_AHBENR_GPIOGEN_Msk (0x1U << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4658 #define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIO port G clock enable */
<> 149:156823d33999 4659 #define RCC_AHBENR_CRCEN_Pos (12U)
<> 149:156823d33999 4660 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4661 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
<> 149:156823d33999 4662 #define RCC_AHBENR_FLITFEN_Pos (15U)
<> 149:156823d33999 4663 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4664 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when
<> 149:156823d33999 4665 the Flash memory is in power down mode) */
<> 149:156823d33999 4666 #define RCC_AHBENR_DMA1EN_Pos (24U)
<> 149:156823d33999 4667 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */
<> 149:156823d33999 4668 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
<> 149:156823d33999 4669 #define RCC_AHBENR_DMA2EN_Pos (25U)
<> 149:156823d33999 4670 #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */
<> 149:156823d33999 4671 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
<> 149:156823d33999 4672
<> 149:156823d33999 4673 /****************** Bit definition for RCC_APB2ENR register *****************/
<> 149:156823d33999 4674 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
<> 149:156823d33999 4675 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4676 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */
<> 149:156823d33999 4677 #define RCC_APB2ENR_TIM9EN_Pos (2U)
<> 149:156823d33999 4678 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4679 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */
<> 149:156823d33999 4680 #define RCC_APB2ENR_TIM10EN_Pos (3U)
<> 149:156823d33999 4681 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4682 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */
<> 149:156823d33999 4683 #define RCC_APB2ENR_TIM11EN_Pos (4U)
<> 149:156823d33999 4684 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4685 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */
<> 149:156823d33999 4686 #define RCC_APB2ENR_ADC1EN_Pos (9U)
<> 149:156823d33999 4687 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4688 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */
<> 149:156823d33999 4689 #define RCC_APB2ENR_SPI1EN_Pos (12U)
<> 149:156823d33999 4690 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4691 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
<> 149:156823d33999 4692 #define RCC_APB2ENR_USART1EN_Pos (14U)
<> 149:156823d33999 4693 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4694 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
<> 149:156823d33999 4695
<> 149:156823d33999 4696 /***************** Bit definition for RCC_APB1ENR register ******************/
<> 149:156823d33999 4697 #define RCC_APB1ENR_TIM2EN_Pos (0U)
<> 149:156823d33999 4698 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4699 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
<> 149:156823d33999 4700 #define RCC_APB1ENR_TIM3EN_Pos (1U)
<> 149:156823d33999 4701 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4702 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
<> 149:156823d33999 4703 #define RCC_APB1ENR_TIM4EN_Pos (2U)
<> 149:156823d33999 4704 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4705 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
<> 149:156823d33999 4706 #define RCC_APB1ENR_TIM5EN_Pos (3U)
<> 149:156823d33999 4707 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4708 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
<> 149:156823d33999 4709 #define RCC_APB1ENR_TIM6EN_Pos (4U)
<> 149:156823d33999 4710 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4711 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
<> 149:156823d33999 4712 #define RCC_APB1ENR_TIM7EN_Pos (5U)
<> 149:156823d33999 4713 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4714 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
<> 149:156823d33999 4715 #define RCC_APB1ENR_LCDEN_Pos (9U)
<> 149:156823d33999 4716 #define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4717 #define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */
<> 149:156823d33999 4718 #define RCC_APB1ENR_WWDGEN_Pos (11U)
<> 149:156823d33999 4719 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4720 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
<> 149:156823d33999 4721 #define RCC_APB1ENR_SPI2EN_Pos (14U)
<> 149:156823d33999 4722 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4723 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
<> 149:156823d33999 4724 #define RCC_APB1ENR_SPI3EN_Pos (15U)
<> 149:156823d33999 4725 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4726 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
<> 149:156823d33999 4727 #define RCC_APB1ENR_USART2EN_Pos (17U)
<> 149:156823d33999 4728 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4729 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
<> 149:156823d33999 4730 #define RCC_APB1ENR_USART3EN_Pos (18U)
<> 149:156823d33999 4731 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
<> 149:156823d33999 4732 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
<> 149:156823d33999 4733 #define RCC_APB1ENR_UART4EN_Pos (19U)
<> 149:156823d33999 4734 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
<> 149:156823d33999 4735 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
<> 149:156823d33999 4736 #define RCC_APB1ENR_UART5EN_Pos (20U)
<> 149:156823d33999 4737 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
<> 149:156823d33999 4738 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
<> 149:156823d33999 4739 #define RCC_APB1ENR_I2C1EN_Pos (21U)
<> 149:156823d33999 4740 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
<> 149:156823d33999 4741 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
<> 149:156823d33999 4742 #define RCC_APB1ENR_I2C2EN_Pos (22U)
<> 149:156823d33999 4743 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4744 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
<> 149:156823d33999 4745 #define RCC_APB1ENR_USBEN_Pos (23U)
<> 149:156823d33999 4746 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
<> 149:156823d33999 4747 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
<> 149:156823d33999 4748 #define RCC_APB1ENR_PWREN_Pos (28U)
<> 149:156823d33999 4749 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
<> 149:156823d33999 4750 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
<> 149:156823d33999 4751 #define RCC_APB1ENR_DACEN_Pos (29U)
<> 149:156823d33999 4752 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
<> 149:156823d33999 4753 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
<> 149:156823d33999 4754 #define RCC_APB1ENR_COMPEN_Pos (31U)
<> 149:156823d33999 4755 #define RCC_APB1ENR_COMPEN_Msk (0x1U << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */
<> 149:156823d33999 4756 #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */
<> 149:156823d33999 4757
<> 149:156823d33999 4758 /****************** Bit definition for RCC_AHBLPENR register ****************/
<> 149:156823d33999 4759 #define RCC_AHBLPENR_GPIOALPEN_Pos (0U)
<> 149:156823d33999 4760 #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4761 #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */
<> 149:156823d33999 4762 #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U)
<> 149:156823d33999 4763 #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4764 #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */
<> 149:156823d33999 4765 #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U)
<> 149:156823d33999 4766 #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4767 #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */
<> 149:156823d33999 4768 #define RCC_AHBLPENR_GPIODLPEN_Pos (3U)
<> 149:156823d33999 4769 #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4770 #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */
<> 149:156823d33999 4771 #define RCC_AHBLPENR_GPIOELPEN_Pos (4U)
<> 149:156823d33999 4772 #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4773 #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */
<> 149:156823d33999 4774 #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U)
<> 149:156823d33999 4775 #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4776 #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */
<> 149:156823d33999 4777 #define RCC_AHBLPENR_GPIOFLPEN_Pos (6U)
<> 149:156823d33999 4778 #define RCC_AHBLPENR_GPIOFLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
<> 149:156823d33999 4779 #define RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOFLPEN_Msk /*!< GPIO port F clock enabled in sleep mode */
<> 149:156823d33999 4780 #define RCC_AHBLPENR_GPIOGLPEN_Pos (7U)
<> 149:156823d33999 4781 #define RCC_AHBLPENR_GPIOGLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
<> 149:156823d33999 4782 #define RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_GPIOGLPEN_Msk /*!< GPIO port G clock enabled in sleep mode */
<> 149:156823d33999 4783 #define RCC_AHBLPENR_CRCLPEN_Pos (12U)
<> 149:156823d33999 4784 #define RCC_AHBLPENR_CRCLPEN_Msk (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4785 #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */
<> 149:156823d33999 4786 #define RCC_AHBLPENR_FLITFLPEN_Pos (15U)
<> 149:156823d33999 4787 #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4788 #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode
<> 149:156823d33999 4789 (has effect only when the Flash memory is
<> 149:156823d33999 4790 in power down mode) */
<> 149:156823d33999 4791 #define RCC_AHBLPENR_SRAMLPEN_Pos (16U)
<> 149:156823d33999 4792 #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4793 #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */
<> 149:156823d33999 4794 #define RCC_AHBLPENR_DMA1LPEN_Pos (24U)
<> 149:156823d33999 4795 #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
<> 149:156823d33999 4796 #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */
<> 149:156823d33999 4797 #define RCC_AHBLPENR_DMA2LPEN_Pos (25U)
<> 149:156823d33999 4798 #define RCC_AHBLPENR_DMA2LPEN_Msk (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
<> 149:156823d33999 4799 #define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */
<> 149:156823d33999 4800
<> 149:156823d33999 4801 /****************** Bit definition for RCC_APB2LPENR register ***************/
<> 149:156823d33999 4802 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U)
<> 149:156823d33999 4803 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4804 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */
<> 149:156823d33999 4805 #define RCC_APB2LPENR_TIM9LPEN_Pos (2U)
<> 149:156823d33999 4806 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4807 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */
<> 149:156823d33999 4808 #define RCC_APB2LPENR_TIM10LPEN_Pos (3U)
<> 149:156823d33999 4809 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4810 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */
<> 149:156823d33999 4811 #define RCC_APB2LPENR_TIM11LPEN_Pos (4U)
<> 149:156823d33999 4812 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4813 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */
<> 149:156823d33999 4814 #define RCC_APB2LPENR_ADC1LPEN_Pos (9U)
<> 149:156823d33999 4815 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4816 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */
<> 149:156823d33999 4817 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
<> 149:156823d33999 4818 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4819 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */
<> 149:156823d33999 4820 #define RCC_APB2LPENR_USART1LPEN_Pos (14U)
<> 149:156823d33999 4821 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4822 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */
<> 149:156823d33999 4823
<> 149:156823d33999 4824 /***************** Bit definition for RCC_APB1LPENR register ****************/
<> 149:156823d33999 4825 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
<> 149:156823d33999 4826 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4827 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */
<> 149:156823d33999 4828 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
<> 149:156823d33999 4829 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4830 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */
<> 149:156823d33999 4831 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
<> 149:156823d33999 4832 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
<> 149:156823d33999 4833 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */
<> 149:156823d33999 4834 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
<> 149:156823d33999 4835 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
<> 149:156823d33999 4836 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */
<> 149:156823d33999 4837 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
<> 149:156823d33999 4838 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
<> 149:156823d33999 4839 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */
<> 149:156823d33999 4840 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
<> 149:156823d33999 4841 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
<> 149:156823d33999 4842 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */
<> 149:156823d33999 4843 #define RCC_APB1LPENR_LCDLPEN_Pos (9U)
<> 149:156823d33999 4844 #define RCC_APB1LPENR_LCDLPEN_Msk (0x1U << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4845 #define RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_LCDLPEN_Msk /*!< LCD clock enabled in sleep mode */
<> 149:156823d33999 4846 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
<> 149:156823d33999 4847 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4848 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
<> 149:156823d33999 4849 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
<> 149:156823d33999 4850 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4851 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */
<> 149:156823d33999 4852 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
<> 149:156823d33999 4853 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
<> 149:156823d33999 4854 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */
<> 149:156823d33999 4855 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
<> 149:156823d33999 4856 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4857 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */
<> 149:156823d33999 4858 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
<> 149:156823d33999 4859 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
<> 149:156823d33999 4860 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */
<> 149:156823d33999 4861 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
<> 149:156823d33999 4862 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
<> 149:156823d33999 4863 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk /*!< UART 4 clock enabled in sleep mode */
<> 149:156823d33999 4864 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
<> 149:156823d33999 4865 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
<> 149:156823d33999 4866 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk /*!< UART 5 clock enabled in sleep mode */
<> 149:156823d33999 4867 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
<> 149:156823d33999 4868 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
<> 149:156823d33999 4869 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */
<> 149:156823d33999 4870 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
<> 149:156823d33999 4871 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4872 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */
<> 149:156823d33999 4873 #define RCC_APB1LPENR_USBLPEN_Pos (23U)
<> 149:156823d33999 4874 #define RCC_APB1LPENR_USBLPEN_Msk (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
<> 149:156823d33999 4875 #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */
<> 149:156823d33999 4876 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
<> 149:156823d33999 4877 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
<> 149:156823d33999 4878 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */
<> 149:156823d33999 4879 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
<> 149:156823d33999 4880 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
<> 149:156823d33999 4881 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */
<> 149:156823d33999 4882 #define RCC_APB1LPENR_COMPLPEN_Pos (31U)
<> 149:156823d33999 4883 #define RCC_APB1LPENR_COMPLPEN_Msk (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
<> 149:156823d33999 4884 #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/
<> 149:156823d33999 4885
<> 149:156823d33999 4886 /******************* Bit definition for RCC_CSR register ********************/
<> 149:156823d33999 4887 #define RCC_CSR_LSION_Pos (0U)
<> 149:156823d33999 4888 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
<> 149:156823d33999 4889 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
<> 149:156823d33999 4890 #define RCC_CSR_LSIRDY_Pos (1U)
<> 149:156823d33999 4891 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
<> 149:156823d33999 4892 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
<> 149:156823d33999 4893
<> 149:156823d33999 4894 #define RCC_CSR_LSEON_Pos (8U)
<> 149:156823d33999 4895 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
<> 149:156823d33999 4896 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
<> 149:156823d33999 4897 #define RCC_CSR_LSERDY_Pos (9U)
<> 149:156823d33999 4898 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
<> 149:156823d33999 4899 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
<> 149:156823d33999 4900 #define RCC_CSR_LSEBYP_Pos (10U)
<> 149:156823d33999 4901 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
<> 149:156823d33999 4902 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
<> 149:156823d33999 4903
<> 149:156823d33999 4904 #define RCC_CSR_LSECSSON_Pos (11U)
<> 149:156823d33999 4905 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */
<> 149:156823d33999 4906 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
<> 149:156823d33999 4907 #define RCC_CSR_LSECSSD_Pos (12U)
<> 149:156823d33999 4908 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4909 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
<> 149:156823d33999 4910
<> 149:156823d33999 4911 #define RCC_CSR_RTCSEL_Pos (16U)
<> 149:156823d33999 4912 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
<> 149:156823d33999 4913 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
<> 149:156823d33999 4914 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4915 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4916
<> 149:156823d33999 4917 /*!< RTC congiguration */
<> 149:156823d33999 4918 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 149:156823d33999 4919 #define RCC_CSR_RTCSEL_LSE_Pos (16U)
<> 149:156823d33999 4920 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4921 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
<> 149:156823d33999 4922 #define RCC_CSR_RTCSEL_LSI_Pos (17U)
<> 149:156823d33999 4923 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4924 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
<> 149:156823d33999 4925 #define RCC_CSR_RTCSEL_HSE_Pos (16U)
<> 149:156823d33999 4926 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
<> 149:156823d33999 4927 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
<> 149:156823d33999 4928
<> 149:156823d33999 4929 #define RCC_CSR_RTCEN_Pos (22U)
<> 149:156823d33999 4930 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4931 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
<> 149:156823d33999 4932 #define RCC_CSR_RTCRST_Pos (23U)
<> 149:156823d33999 4933 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */
<> 149:156823d33999 4934 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */
<> 149:156823d33999 4935
<> 149:156823d33999 4936 #define RCC_CSR_RMVF_Pos (24U)
<> 149:156823d33999 4937 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
<> 149:156823d33999 4938 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
<> 149:156823d33999 4939 #define RCC_CSR_OBLRSTF_Pos (25U)
<> 149:156823d33999 4940 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
<> 149:156823d33999 4941 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */
<> 149:156823d33999 4942 #define RCC_CSR_PINRSTF_Pos (26U)
<> 149:156823d33999 4943 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
<> 149:156823d33999 4944 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
<> 149:156823d33999 4945 #define RCC_CSR_PORRSTF_Pos (27U)
<> 149:156823d33999 4946 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
<> 149:156823d33999 4947 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
<> 149:156823d33999 4948 #define RCC_CSR_SFTRSTF_Pos (28U)
<> 149:156823d33999 4949 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
<> 149:156823d33999 4950 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
<> 149:156823d33999 4951 #define RCC_CSR_IWDGRSTF_Pos (29U)
<> 149:156823d33999 4952 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
<> 149:156823d33999 4953 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
<> 149:156823d33999 4954 #define RCC_CSR_WWDGRSTF_Pos (30U)
<> 149:156823d33999 4955 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
<> 149:156823d33999 4956 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
<> 149:156823d33999 4957 #define RCC_CSR_LPWRRSTF_Pos (31U)
<> 149:156823d33999 4958 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
<> 149:156823d33999 4959 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
<> 149:156823d33999 4960
<> 149:156823d33999 4961 /******************************************************************************/
<> 149:156823d33999 4962 /* */
<> 149:156823d33999 4963 /* Real-Time Clock (RTC) */
<> 149:156823d33999 4964 /* */
<> 149:156823d33999 4965 /******************************************************************************/
<> 149:156823d33999 4966 /*
<> 149:156823d33999 4967 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 149:156823d33999 4968 */
<> 149:156823d33999 4969 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
<> 149:156823d33999 4970 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
<> 149:156823d33999 4971 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
<> 149:156823d33999 4972 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
<> 149:156823d33999 4973 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
<> 149:156823d33999 4974 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */
<> 149:156823d33999 4975 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */
<> 149:156823d33999 4976
<> 149:156823d33999 4977 /******************** Bits definition for RTC_TR register *******************/
<> 149:156823d33999 4978 #define RTC_TR_PM_Pos (22U)
<> 149:156823d33999 4979 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
<> 149:156823d33999 4980 #define RTC_TR_PM RTC_TR_PM_Msk
<> 149:156823d33999 4981 #define RTC_TR_HT_Pos (20U)
<> 149:156823d33999 4982 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
<> 149:156823d33999 4983 #define RTC_TR_HT RTC_TR_HT_Msk
<> 149:156823d33999 4984 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
<> 149:156823d33999 4985 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
<> 149:156823d33999 4986 #define RTC_TR_HU_Pos (16U)
<> 149:156823d33999 4987 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
<> 149:156823d33999 4988 #define RTC_TR_HU RTC_TR_HU_Msk
<> 149:156823d33999 4989 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
<> 149:156823d33999 4990 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
<> 149:156823d33999 4991 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
<> 149:156823d33999 4992 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
<> 149:156823d33999 4993 #define RTC_TR_MNT_Pos (12U)
<> 149:156823d33999 4994 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
<> 149:156823d33999 4995 #define RTC_TR_MNT RTC_TR_MNT_Msk
<> 149:156823d33999 4996 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 4997 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
<> 149:156823d33999 4998 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
<> 149:156823d33999 4999 #define RTC_TR_MNU_Pos (8U)
<> 149:156823d33999 5000 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5001 #define RTC_TR_MNU RTC_TR_MNU_Msk
<> 149:156823d33999 5002 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5003 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5004 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5005 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5006 #define RTC_TR_ST_Pos (4U)
<> 149:156823d33999 5007 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
<> 149:156823d33999 5008 #define RTC_TR_ST RTC_TR_ST_Msk
<> 149:156823d33999 5009 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5010 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5011 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5012 #define RTC_TR_SU_Pos (0U)
<> 149:156823d33999 5013 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5014 #define RTC_TR_SU RTC_TR_SU_Msk
<> 149:156823d33999 5015 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5016 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5017 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5018 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5019
<> 149:156823d33999 5020 /******************** Bits definition for RTC_DR register *******************/
<> 149:156823d33999 5021 #define RTC_DR_YT_Pos (20U)
<> 149:156823d33999 5022 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
<> 149:156823d33999 5023 #define RTC_DR_YT RTC_DR_YT_Msk
<> 149:156823d33999 5024 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
<> 149:156823d33999 5025 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
<> 149:156823d33999 5026 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
<> 149:156823d33999 5027 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
<> 149:156823d33999 5028 #define RTC_DR_YU_Pos (16U)
<> 149:156823d33999 5029 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
<> 149:156823d33999 5030 #define RTC_DR_YU RTC_DR_YU_Msk
<> 149:156823d33999 5031 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
<> 149:156823d33999 5032 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
<> 149:156823d33999 5033 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
<> 149:156823d33999 5034 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
<> 149:156823d33999 5035 #define RTC_DR_WDU_Pos (13U)
<> 149:156823d33999 5036 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
<> 149:156823d33999 5037 #define RTC_DR_WDU RTC_DR_WDU_Msk
<> 149:156823d33999 5038 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5039 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5040 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5041 #define RTC_DR_MT_Pos (12U)
<> 149:156823d33999 5042 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5043 #define RTC_DR_MT RTC_DR_MT_Msk
<> 149:156823d33999 5044 #define RTC_DR_MU_Pos (8U)
<> 149:156823d33999 5045 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5046 #define RTC_DR_MU RTC_DR_MU_Msk
<> 149:156823d33999 5047 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5048 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5049 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5050 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5051 #define RTC_DR_DT_Pos (4U)
<> 149:156823d33999 5052 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
<> 149:156823d33999 5053 #define RTC_DR_DT RTC_DR_DT_Msk
<> 149:156823d33999 5054 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5055 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5056 #define RTC_DR_DU_Pos (0U)
<> 149:156823d33999 5057 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5058 #define RTC_DR_DU RTC_DR_DU_Msk
<> 149:156823d33999 5059 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5060 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5061 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5062 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5063
<> 149:156823d33999 5064 /******************** Bits definition for RTC_CR register *******************/
<> 149:156823d33999 5065 #define RTC_CR_COE_Pos (23U)
<> 149:156823d33999 5066 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
<> 149:156823d33999 5067 #define RTC_CR_COE RTC_CR_COE_Msk
<> 149:156823d33999 5068 #define RTC_CR_OSEL_Pos (21U)
<> 149:156823d33999 5069 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
<> 149:156823d33999 5070 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
<> 149:156823d33999 5071 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
<> 149:156823d33999 5072 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
<> 149:156823d33999 5073 #define RTC_CR_POL_Pos (20U)
<> 149:156823d33999 5074 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
<> 149:156823d33999 5075 #define RTC_CR_POL RTC_CR_POL_Msk
<> 149:156823d33999 5076 #define RTC_CR_COSEL_Pos (19U)
<> 149:156823d33999 5077 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
<> 149:156823d33999 5078 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 184:08ed48f1de7f 5079 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 184:08ed48f1de7f 5080 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 184:08ed48f1de7f 5081 #define RTC_CR_BKP RTC_CR_BKP_Msk
<> 149:156823d33999 5082 #define RTC_CR_SUB1H_Pos (17U)
<> 149:156823d33999 5083 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
<> 149:156823d33999 5084 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
<> 149:156823d33999 5085 #define RTC_CR_ADD1H_Pos (16U)
<> 149:156823d33999 5086 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
<> 149:156823d33999 5087 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
<> 149:156823d33999 5088 #define RTC_CR_TSIE_Pos (15U)
<> 149:156823d33999 5089 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5090 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
<> 149:156823d33999 5091 #define RTC_CR_WUTIE_Pos (14U)
<> 149:156823d33999 5092 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5093 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
<> 149:156823d33999 5094 #define RTC_CR_ALRBIE_Pos (13U)
<> 149:156823d33999 5095 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5096 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
<> 149:156823d33999 5097 #define RTC_CR_ALRAIE_Pos (12U)
<> 149:156823d33999 5098 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5099 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
<> 149:156823d33999 5100 #define RTC_CR_TSE_Pos (11U)
<> 149:156823d33999 5101 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5102 #define RTC_CR_TSE RTC_CR_TSE_Msk
<> 149:156823d33999 5103 #define RTC_CR_WUTE_Pos (10U)
<> 149:156823d33999 5104 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5105 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
<> 149:156823d33999 5106 #define RTC_CR_ALRBE_Pos (9U)
<> 149:156823d33999 5107 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5108 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
<> 149:156823d33999 5109 #define RTC_CR_ALRAE_Pos (8U)
<> 149:156823d33999 5110 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5111 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
<> 149:156823d33999 5112 #define RTC_CR_DCE_Pos (7U)
<> 149:156823d33999 5113 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5114 #define RTC_CR_DCE RTC_CR_DCE_Msk
<> 149:156823d33999 5115 #define RTC_CR_FMT_Pos (6U)
<> 149:156823d33999 5116 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5117 #define RTC_CR_FMT RTC_CR_FMT_Msk
<> 149:156823d33999 5118 #define RTC_CR_BYPSHAD_Pos (5U)
<> 149:156823d33999 5119 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5120 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
<> 149:156823d33999 5121 #define RTC_CR_REFCKON_Pos (4U)
<> 149:156823d33999 5122 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5123 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
<> 149:156823d33999 5124 #define RTC_CR_TSEDGE_Pos (3U)
<> 149:156823d33999 5125 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5126 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
<> 149:156823d33999 5127 #define RTC_CR_WUCKSEL_Pos (0U)
<> 149:156823d33999 5128 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
<> 149:156823d33999 5129 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
<> 149:156823d33999 5130 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5131 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5132 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5133
AnnaBridge 184:08ed48f1de7f 5134 /* Legacy defines */
AnnaBridge 184:08ed48f1de7f 5135 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
AnnaBridge 184:08ed48f1de7f 5136 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
AnnaBridge 184:08ed48f1de7f 5137 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 184:08ed48f1de7f 5138
<> 149:156823d33999 5139 /******************** Bits definition for RTC_ISR register ******************/
<> 149:156823d33999 5140 #define RTC_ISR_RECALPF_Pos (16U)
<> 149:156823d33999 5141 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
<> 149:156823d33999 5142 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
<> 149:156823d33999 5143 #define RTC_ISR_TAMP3F_Pos (15U)
<> 149:156823d33999 5144 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5145 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
<> 149:156823d33999 5146 #define RTC_ISR_TAMP2F_Pos (14U)
<> 149:156823d33999 5147 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5148 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
<> 149:156823d33999 5149 #define RTC_ISR_TAMP1F_Pos (13U)
<> 149:156823d33999 5150 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5151 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
<> 149:156823d33999 5152 #define RTC_ISR_TSOVF_Pos (12U)
<> 149:156823d33999 5153 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5154 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
<> 149:156823d33999 5155 #define RTC_ISR_TSF_Pos (11U)
<> 149:156823d33999 5156 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5157 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
<> 149:156823d33999 5158 #define RTC_ISR_WUTF_Pos (10U)
<> 149:156823d33999 5159 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5160 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
<> 149:156823d33999 5161 #define RTC_ISR_ALRBF_Pos (9U)
<> 149:156823d33999 5162 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5163 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
<> 149:156823d33999 5164 #define RTC_ISR_ALRAF_Pos (8U)
<> 149:156823d33999 5165 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5166 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
<> 149:156823d33999 5167 #define RTC_ISR_INIT_Pos (7U)
<> 149:156823d33999 5168 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5169 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
<> 149:156823d33999 5170 #define RTC_ISR_INITF_Pos (6U)
<> 149:156823d33999 5171 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5172 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
<> 149:156823d33999 5173 #define RTC_ISR_RSF_Pos (5U)
<> 149:156823d33999 5174 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5175 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
<> 149:156823d33999 5176 #define RTC_ISR_INITS_Pos (4U)
<> 149:156823d33999 5177 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5178 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
<> 149:156823d33999 5179 #define RTC_ISR_SHPF_Pos (3U)
<> 149:156823d33999 5180 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5181 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
<> 149:156823d33999 5182 #define RTC_ISR_WUTWF_Pos (2U)
<> 149:156823d33999 5183 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5184 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
<> 149:156823d33999 5185 #define RTC_ISR_ALRBWF_Pos (1U)
<> 149:156823d33999 5186 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5187 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
<> 149:156823d33999 5188 #define RTC_ISR_ALRAWF_Pos (0U)
<> 149:156823d33999 5189 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5190 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 149:156823d33999 5191
<> 149:156823d33999 5192 /******************** Bits definition for RTC_PRER register *****************/
<> 149:156823d33999 5193 #define RTC_PRER_PREDIV_A_Pos (16U)
<> 149:156823d33999 5194 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
<> 149:156823d33999 5195 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
<> 149:156823d33999 5196 #define RTC_PRER_PREDIV_S_Pos (0U)
<> 149:156823d33999 5197 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
<> 149:156823d33999 5198 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 149:156823d33999 5199
<> 149:156823d33999 5200 /******************** Bits definition for RTC_WUTR register *****************/
<> 149:156823d33999 5201 #define RTC_WUTR_WUT_Pos (0U)
<> 149:156823d33999 5202 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 5203 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 149:156823d33999 5204
<> 149:156823d33999 5205 /******************** Bits definition for RTC_CALIBR register ***************/
<> 149:156823d33999 5206 #define RTC_CALIBR_DCS_Pos (7U)
<> 149:156823d33999 5207 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5208 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
<> 149:156823d33999 5209 #define RTC_CALIBR_DC_Pos (0U)
<> 149:156823d33999 5210 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
<> 149:156823d33999 5211 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
<> 149:156823d33999 5212
<> 149:156823d33999 5213 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 149:156823d33999 5214 #define RTC_ALRMAR_MSK4_Pos (31U)
<> 149:156823d33999 5215 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
<> 149:156823d33999 5216 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
<> 149:156823d33999 5217 #define RTC_ALRMAR_WDSEL_Pos (30U)
<> 149:156823d33999 5218 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
<> 149:156823d33999 5219 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
<> 149:156823d33999 5220 #define RTC_ALRMAR_DT_Pos (28U)
<> 149:156823d33999 5221 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
<> 149:156823d33999 5222 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
<> 149:156823d33999 5223 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
<> 149:156823d33999 5224 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
<> 149:156823d33999 5225 #define RTC_ALRMAR_DU_Pos (24U)
<> 149:156823d33999 5226 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
<> 149:156823d33999 5227 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
<> 149:156823d33999 5228 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
<> 149:156823d33999 5229 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
<> 149:156823d33999 5230 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
<> 149:156823d33999 5231 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
<> 149:156823d33999 5232 #define RTC_ALRMAR_MSK3_Pos (23U)
<> 149:156823d33999 5233 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
<> 149:156823d33999 5234 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
<> 149:156823d33999 5235 #define RTC_ALRMAR_PM_Pos (22U)
<> 149:156823d33999 5236 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
<> 149:156823d33999 5237 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
<> 149:156823d33999 5238 #define RTC_ALRMAR_HT_Pos (20U)
<> 149:156823d33999 5239 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
<> 149:156823d33999 5240 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
<> 149:156823d33999 5241 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
<> 149:156823d33999 5242 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
<> 149:156823d33999 5243 #define RTC_ALRMAR_HU_Pos (16U)
<> 149:156823d33999 5244 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
<> 149:156823d33999 5245 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
<> 149:156823d33999 5246 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
<> 149:156823d33999 5247 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
<> 149:156823d33999 5248 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
<> 149:156823d33999 5249 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
<> 149:156823d33999 5250 #define RTC_ALRMAR_MSK2_Pos (15U)
<> 149:156823d33999 5251 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5252 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
<> 149:156823d33999 5253 #define RTC_ALRMAR_MNT_Pos (12U)
<> 149:156823d33999 5254 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
<> 149:156823d33999 5255 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
<> 149:156823d33999 5256 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5257 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5258 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5259 #define RTC_ALRMAR_MNU_Pos (8U)
<> 149:156823d33999 5260 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5261 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
<> 149:156823d33999 5262 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5263 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5264 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5265 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5266 #define RTC_ALRMAR_MSK1_Pos (7U)
<> 149:156823d33999 5267 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5268 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
<> 149:156823d33999 5269 #define RTC_ALRMAR_ST_Pos (4U)
<> 149:156823d33999 5270 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
<> 149:156823d33999 5271 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
<> 149:156823d33999 5272 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5273 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5274 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5275 #define RTC_ALRMAR_SU_Pos (0U)
<> 149:156823d33999 5276 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5277 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
<> 149:156823d33999 5278 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5279 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5280 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5281 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5282
<> 149:156823d33999 5283 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 149:156823d33999 5284 #define RTC_ALRMBR_MSK4_Pos (31U)
<> 149:156823d33999 5285 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
<> 149:156823d33999 5286 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
<> 149:156823d33999 5287 #define RTC_ALRMBR_WDSEL_Pos (30U)
<> 149:156823d33999 5288 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
<> 149:156823d33999 5289 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
<> 149:156823d33999 5290 #define RTC_ALRMBR_DT_Pos (28U)
<> 149:156823d33999 5291 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
<> 149:156823d33999 5292 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
<> 149:156823d33999 5293 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
<> 149:156823d33999 5294 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
<> 149:156823d33999 5295 #define RTC_ALRMBR_DU_Pos (24U)
<> 149:156823d33999 5296 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
<> 149:156823d33999 5297 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
<> 149:156823d33999 5298 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
<> 149:156823d33999 5299 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
<> 149:156823d33999 5300 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
<> 149:156823d33999 5301 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
<> 149:156823d33999 5302 #define RTC_ALRMBR_MSK3_Pos (23U)
<> 149:156823d33999 5303 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
<> 149:156823d33999 5304 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
<> 149:156823d33999 5305 #define RTC_ALRMBR_PM_Pos (22U)
<> 149:156823d33999 5306 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
<> 149:156823d33999 5307 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
<> 149:156823d33999 5308 #define RTC_ALRMBR_HT_Pos (20U)
<> 149:156823d33999 5309 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
<> 149:156823d33999 5310 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
<> 149:156823d33999 5311 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
<> 149:156823d33999 5312 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
<> 149:156823d33999 5313 #define RTC_ALRMBR_HU_Pos (16U)
<> 149:156823d33999 5314 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
<> 149:156823d33999 5315 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
<> 149:156823d33999 5316 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
<> 149:156823d33999 5317 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
<> 149:156823d33999 5318 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
<> 149:156823d33999 5319 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
<> 149:156823d33999 5320 #define RTC_ALRMBR_MSK2_Pos (15U)
<> 149:156823d33999 5321 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5322 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
<> 149:156823d33999 5323 #define RTC_ALRMBR_MNT_Pos (12U)
<> 149:156823d33999 5324 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
<> 149:156823d33999 5325 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
<> 149:156823d33999 5326 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5327 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5328 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5329 #define RTC_ALRMBR_MNU_Pos (8U)
<> 149:156823d33999 5330 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5331 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
<> 149:156823d33999 5332 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5333 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5334 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5335 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5336 #define RTC_ALRMBR_MSK1_Pos (7U)
<> 149:156823d33999 5337 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5338 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
<> 149:156823d33999 5339 #define RTC_ALRMBR_ST_Pos (4U)
<> 149:156823d33999 5340 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
<> 149:156823d33999 5341 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
<> 149:156823d33999 5342 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5343 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5344 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5345 #define RTC_ALRMBR_SU_Pos (0U)
<> 149:156823d33999 5346 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5347 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
<> 149:156823d33999 5348 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5349 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5350 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5351 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5352
<> 149:156823d33999 5353 /******************** Bits definition for RTC_WPR register ******************/
<> 149:156823d33999 5354 #define RTC_WPR_KEY_Pos (0U)
<> 149:156823d33999 5355 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
<> 149:156823d33999 5356 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 149:156823d33999 5357
<> 149:156823d33999 5358 /******************** Bits definition for RTC_SSR register ******************/
<> 149:156823d33999 5359 #define RTC_SSR_SS_Pos (0U)
<> 149:156823d33999 5360 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 5361 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 149:156823d33999 5362
<> 149:156823d33999 5363 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 149:156823d33999 5364 #define RTC_SHIFTR_SUBFS_Pos (0U)
<> 149:156823d33999 5365 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
<> 149:156823d33999 5366 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
<> 149:156823d33999 5367 #define RTC_SHIFTR_ADD1S_Pos (31U)
<> 149:156823d33999 5368 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
<> 149:156823d33999 5369 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 149:156823d33999 5370
<> 149:156823d33999 5371 /******************** Bits definition for RTC_TSTR register *****************/
<> 149:156823d33999 5372 #define RTC_TSTR_PM_Pos (22U)
<> 149:156823d33999 5373 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
<> 149:156823d33999 5374 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
<> 149:156823d33999 5375 #define RTC_TSTR_HT_Pos (20U)
<> 149:156823d33999 5376 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
<> 149:156823d33999 5377 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
<> 149:156823d33999 5378 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
<> 149:156823d33999 5379 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
<> 149:156823d33999 5380 #define RTC_TSTR_HU_Pos (16U)
<> 149:156823d33999 5381 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
<> 149:156823d33999 5382 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
<> 149:156823d33999 5383 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
<> 149:156823d33999 5384 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
<> 149:156823d33999 5385 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
<> 149:156823d33999 5386 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
<> 149:156823d33999 5387 #define RTC_TSTR_MNT_Pos (12U)
<> 149:156823d33999 5388 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
<> 149:156823d33999 5389 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
<> 149:156823d33999 5390 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5391 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5392 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5393 #define RTC_TSTR_MNU_Pos (8U)
<> 149:156823d33999 5394 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5395 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
<> 149:156823d33999 5396 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5397 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5398 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5399 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5400 #define RTC_TSTR_ST_Pos (4U)
<> 149:156823d33999 5401 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
<> 149:156823d33999 5402 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
<> 149:156823d33999 5403 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5404 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5405 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5406 #define RTC_TSTR_SU_Pos (0U)
<> 149:156823d33999 5407 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5408 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
<> 149:156823d33999 5409 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5410 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5411 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5412 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5413
<> 149:156823d33999 5414 /******************** Bits definition for RTC_TSDR register *****************/
<> 149:156823d33999 5415 #define RTC_TSDR_WDU_Pos (13U)
<> 149:156823d33999 5416 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
<> 149:156823d33999 5417 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
<> 149:156823d33999 5418 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5419 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5420 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5421 #define RTC_TSDR_MT_Pos (12U)
<> 149:156823d33999 5422 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5423 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
<> 149:156823d33999 5424 #define RTC_TSDR_MU_Pos (8U)
<> 149:156823d33999 5425 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5426 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
<> 149:156823d33999 5427 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5428 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5429 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5430 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5431 #define RTC_TSDR_DT_Pos (4U)
<> 149:156823d33999 5432 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
<> 149:156823d33999 5433 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
<> 149:156823d33999 5434 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5435 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5436 #define RTC_TSDR_DU_Pos (0U)
<> 149:156823d33999 5437 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5438 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
<> 149:156823d33999 5439 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5440 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5441 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5442 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5443
<> 149:156823d33999 5444 /******************** Bits definition for RTC_TSSSR register ****************/
<> 149:156823d33999 5445 #define RTC_TSSSR_SS_Pos (0U)
<> 149:156823d33999 5446 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 5447 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 149:156823d33999 5448
<> 149:156823d33999 5449 /******************** Bits definition for RTC_CAL register *****************/
<> 149:156823d33999 5450 #define RTC_CALR_CALP_Pos (15U)
<> 149:156823d33999 5451 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5452 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
<> 149:156823d33999 5453 #define RTC_CALR_CALW8_Pos (14U)
<> 149:156823d33999 5454 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5455 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
<> 149:156823d33999 5456 #define RTC_CALR_CALW16_Pos (13U)
<> 149:156823d33999 5457 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5458 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
<> 149:156823d33999 5459 #define RTC_CALR_CALM_Pos (0U)
<> 149:156823d33999 5460 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
<> 149:156823d33999 5461 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
<> 149:156823d33999 5462 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5463 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5464 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5465 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5466 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5467 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5468 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5469 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5470 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5471
<> 149:156823d33999 5472 /******************** Bits definition for RTC_TAFCR register ****************/
<> 149:156823d33999 5473 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
<> 149:156823d33999 5474 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
<> 149:156823d33999 5475 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
<> 149:156823d33999 5476 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
<> 149:156823d33999 5477 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5478 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
<> 149:156823d33999 5479 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
<> 149:156823d33999 5480 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
<> 149:156823d33999 5481 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
<> 149:156823d33999 5482 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5483 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5484 #define RTC_TAFCR_TAMPFLT_Pos (11U)
<> 149:156823d33999 5485 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
<> 149:156823d33999 5486 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
<> 149:156823d33999 5487 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5488 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5489 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
<> 149:156823d33999 5490 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
<> 149:156823d33999 5491 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
<> 149:156823d33999 5492 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5493 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5494 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5495 #define RTC_TAFCR_TAMPTS_Pos (7U)
<> 149:156823d33999 5496 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5497 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
<> 149:156823d33999 5498 #define RTC_TAFCR_TAMP3TRG_Pos (6U)
<> 149:156823d33999 5499 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5500 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
<> 149:156823d33999 5501 #define RTC_TAFCR_TAMP3E_Pos (5U)
<> 149:156823d33999 5502 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5503 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
<> 149:156823d33999 5504 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
<> 149:156823d33999 5505 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5506 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
<> 149:156823d33999 5507 #define RTC_TAFCR_TAMP2E_Pos (3U)
<> 149:156823d33999 5508 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5509 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
<> 149:156823d33999 5510 #define RTC_TAFCR_TAMPIE_Pos (2U)
<> 149:156823d33999 5511 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5512 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
<> 149:156823d33999 5513 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
<> 149:156823d33999 5514 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5515 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
<> 149:156823d33999 5516 #define RTC_TAFCR_TAMP1E_Pos (0U)
<> 149:156823d33999 5517 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5518 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
<> 149:156823d33999 5519
<> 149:156823d33999 5520 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 149:156823d33999 5521 #define RTC_ALRMASSR_MASKSS_Pos (24U)
<> 149:156823d33999 5522 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 149:156823d33999 5523 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
<> 149:156823d33999 5524 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
<> 149:156823d33999 5525 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
<> 149:156823d33999 5526 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
<> 149:156823d33999 5527 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
<> 149:156823d33999 5528 #define RTC_ALRMASSR_SS_Pos (0U)
<> 149:156823d33999 5529 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
<> 149:156823d33999 5530 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 149:156823d33999 5531
<> 149:156823d33999 5532 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 149:156823d33999 5533 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
<> 149:156823d33999 5534 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 149:156823d33999 5535 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
<> 149:156823d33999 5536 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
<> 149:156823d33999 5537 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
<> 149:156823d33999 5538 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
<> 149:156823d33999 5539 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
<> 149:156823d33999 5540 #define RTC_ALRMBSSR_SS_Pos (0U)
<> 149:156823d33999 5541 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
<> 149:156823d33999 5542 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
<> 149:156823d33999 5543
<> 149:156823d33999 5544 /******************** Bits definition for RTC_BKP0R register ****************/
<> 149:156823d33999 5545 #define RTC_BKP0R_Pos (0U)
<> 149:156823d33999 5546 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5547 #define RTC_BKP0R RTC_BKP0R_Msk
<> 149:156823d33999 5548
<> 149:156823d33999 5549 /******************** Bits definition for RTC_BKP1R register ****************/
<> 149:156823d33999 5550 #define RTC_BKP1R_Pos (0U)
<> 149:156823d33999 5551 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5552 #define RTC_BKP1R RTC_BKP1R_Msk
<> 149:156823d33999 5553
<> 149:156823d33999 5554 /******************** Bits definition for RTC_BKP2R register ****************/
<> 149:156823d33999 5555 #define RTC_BKP2R_Pos (0U)
<> 149:156823d33999 5556 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5557 #define RTC_BKP2R RTC_BKP2R_Msk
<> 149:156823d33999 5558
<> 149:156823d33999 5559 /******************** Bits definition for RTC_BKP3R register ****************/
<> 149:156823d33999 5560 #define RTC_BKP3R_Pos (0U)
<> 149:156823d33999 5561 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5562 #define RTC_BKP3R RTC_BKP3R_Msk
<> 149:156823d33999 5563
<> 149:156823d33999 5564 /******************** Bits definition for RTC_BKP4R register ****************/
<> 149:156823d33999 5565 #define RTC_BKP4R_Pos (0U)
<> 149:156823d33999 5566 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5567 #define RTC_BKP4R RTC_BKP4R_Msk
<> 149:156823d33999 5568
<> 149:156823d33999 5569 /******************** Bits definition for RTC_BKP5R register ****************/
<> 149:156823d33999 5570 #define RTC_BKP5R_Pos (0U)
<> 149:156823d33999 5571 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5572 #define RTC_BKP5R RTC_BKP5R_Msk
<> 149:156823d33999 5573
<> 149:156823d33999 5574 /******************** Bits definition for RTC_BKP6R register ****************/
<> 149:156823d33999 5575 #define RTC_BKP6R_Pos (0U)
<> 149:156823d33999 5576 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5577 #define RTC_BKP6R RTC_BKP6R_Msk
<> 149:156823d33999 5578
<> 149:156823d33999 5579 /******************** Bits definition for RTC_BKP7R register ****************/
<> 149:156823d33999 5580 #define RTC_BKP7R_Pos (0U)
<> 149:156823d33999 5581 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5582 #define RTC_BKP7R RTC_BKP7R_Msk
<> 149:156823d33999 5583
<> 149:156823d33999 5584 /******************** Bits definition for RTC_BKP8R register ****************/
<> 149:156823d33999 5585 #define RTC_BKP8R_Pos (0U)
<> 149:156823d33999 5586 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5587 #define RTC_BKP8R RTC_BKP8R_Msk
<> 149:156823d33999 5588
<> 149:156823d33999 5589 /******************** Bits definition for RTC_BKP9R register ****************/
<> 149:156823d33999 5590 #define RTC_BKP9R_Pos (0U)
<> 149:156823d33999 5591 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5592 #define RTC_BKP9R RTC_BKP9R_Msk
<> 149:156823d33999 5593
<> 149:156823d33999 5594 /******************** Bits definition for RTC_BKP10R register ***************/
<> 149:156823d33999 5595 #define RTC_BKP10R_Pos (0U)
<> 149:156823d33999 5596 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5597 #define RTC_BKP10R RTC_BKP10R_Msk
<> 149:156823d33999 5598
<> 149:156823d33999 5599 /******************** Bits definition for RTC_BKP11R register ***************/
<> 149:156823d33999 5600 #define RTC_BKP11R_Pos (0U)
<> 149:156823d33999 5601 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5602 #define RTC_BKP11R RTC_BKP11R_Msk
<> 149:156823d33999 5603
<> 149:156823d33999 5604 /******************** Bits definition for RTC_BKP12R register ***************/
<> 149:156823d33999 5605 #define RTC_BKP12R_Pos (0U)
<> 149:156823d33999 5606 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5607 #define RTC_BKP12R RTC_BKP12R_Msk
<> 149:156823d33999 5608
<> 149:156823d33999 5609 /******************** Bits definition for RTC_BKP13R register ***************/
<> 149:156823d33999 5610 #define RTC_BKP13R_Pos (0U)
<> 149:156823d33999 5611 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5612 #define RTC_BKP13R RTC_BKP13R_Msk
<> 149:156823d33999 5613
<> 149:156823d33999 5614 /******************** Bits definition for RTC_BKP14R register ***************/
<> 149:156823d33999 5615 #define RTC_BKP14R_Pos (0U)
<> 149:156823d33999 5616 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5617 #define RTC_BKP14R RTC_BKP14R_Msk
<> 149:156823d33999 5618
<> 149:156823d33999 5619 /******************** Bits definition for RTC_BKP15R register ***************/
<> 149:156823d33999 5620 #define RTC_BKP15R_Pos (0U)
<> 149:156823d33999 5621 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5622 #define RTC_BKP15R RTC_BKP15R_Msk
<> 149:156823d33999 5623
<> 149:156823d33999 5624 /******************** Bits definition for RTC_BKP16R register ***************/
<> 149:156823d33999 5625 #define RTC_BKP16R_Pos (0U)
<> 149:156823d33999 5626 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5627 #define RTC_BKP16R RTC_BKP16R_Msk
<> 149:156823d33999 5628
<> 149:156823d33999 5629 /******************** Bits definition for RTC_BKP17R register ***************/
<> 149:156823d33999 5630 #define RTC_BKP17R_Pos (0U)
<> 149:156823d33999 5631 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5632 #define RTC_BKP17R RTC_BKP17R_Msk
<> 149:156823d33999 5633
<> 149:156823d33999 5634 /******************** Bits definition for RTC_BKP18R register ***************/
<> 149:156823d33999 5635 #define RTC_BKP18R_Pos (0U)
<> 149:156823d33999 5636 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5637 #define RTC_BKP18R RTC_BKP18R_Msk
<> 149:156823d33999 5638
<> 149:156823d33999 5639 /******************** Bits definition for RTC_BKP19R register ***************/
<> 149:156823d33999 5640 #define RTC_BKP19R_Pos (0U)
<> 149:156823d33999 5641 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5642 #define RTC_BKP19R RTC_BKP19R_Msk
<> 149:156823d33999 5643
<> 149:156823d33999 5644 /******************** Bits definition for RTC_BKP20R register ***************/
<> 149:156823d33999 5645 #define RTC_BKP20R_Pos (0U)
<> 149:156823d33999 5646 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5647 #define RTC_BKP20R RTC_BKP20R_Msk
<> 149:156823d33999 5648
<> 149:156823d33999 5649 /******************** Bits definition for RTC_BKP21R register ***************/
<> 149:156823d33999 5650 #define RTC_BKP21R_Pos (0U)
<> 149:156823d33999 5651 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5652 #define RTC_BKP21R RTC_BKP21R_Msk
<> 149:156823d33999 5653
<> 149:156823d33999 5654 /******************** Bits definition for RTC_BKP22R register ***************/
<> 149:156823d33999 5655 #define RTC_BKP22R_Pos (0U)
<> 149:156823d33999 5656 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5657 #define RTC_BKP22R RTC_BKP22R_Msk
<> 149:156823d33999 5658
<> 149:156823d33999 5659 /******************** Bits definition for RTC_BKP23R register ***************/
<> 149:156823d33999 5660 #define RTC_BKP23R_Pos (0U)
<> 149:156823d33999 5661 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5662 #define RTC_BKP23R RTC_BKP23R_Msk
<> 149:156823d33999 5663
<> 149:156823d33999 5664 /******************** Bits definition for RTC_BKP24R register ***************/
<> 149:156823d33999 5665 #define RTC_BKP24R_Pos (0U)
<> 149:156823d33999 5666 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5667 #define RTC_BKP24R RTC_BKP24R_Msk
<> 149:156823d33999 5668
<> 149:156823d33999 5669 /******************** Bits definition for RTC_BKP25R register ***************/
<> 149:156823d33999 5670 #define RTC_BKP25R_Pos (0U)
<> 149:156823d33999 5671 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5672 #define RTC_BKP25R RTC_BKP25R_Msk
<> 149:156823d33999 5673
<> 149:156823d33999 5674 /******************** Bits definition for RTC_BKP26R register ***************/
<> 149:156823d33999 5675 #define RTC_BKP26R_Pos (0U)
<> 149:156823d33999 5676 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5677 #define RTC_BKP26R RTC_BKP26R_Msk
<> 149:156823d33999 5678
<> 149:156823d33999 5679 /******************** Bits definition for RTC_BKP27R register ***************/
<> 149:156823d33999 5680 #define RTC_BKP27R_Pos (0U)
<> 149:156823d33999 5681 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5682 #define RTC_BKP27R RTC_BKP27R_Msk
<> 149:156823d33999 5683
<> 149:156823d33999 5684 /******************** Bits definition for RTC_BKP28R register ***************/
<> 149:156823d33999 5685 #define RTC_BKP28R_Pos (0U)
<> 149:156823d33999 5686 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5687 #define RTC_BKP28R RTC_BKP28R_Msk
<> 149:156823d33999 5688
<> 149:156823d33999 5689 /******************** Bits definition for RTC_BKP29R register ***************/
<> 149:156823d33999 5690 #define RTC_BKP29R_Pos (0U)
<> 149:156823d33999 5691 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5692 #define RTC_BKP29R RTC_BKP29R_Msk
<> 149:156823d33999 5693
<> 149:156823d33999 5694 /******************** Bits definition for RTC_BKP30R register ***************/
<> 149:156823d33999 5695 #define RTC_BKP30R_Pos (0U)
<> 149:156823d33999 5696 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5697 #define RTC_BKP30R RTC_BKP30R_Msk
<> 149:156823d33999 5698
<> 149:156823d33999 5699 /******************** Bits definition for RTC_BKP31R register ***************/
<> 149:156823d33999 5700 #define RTC_BKP31R_Pos (0U)
<> 149:156823d33999 5701 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 5702 #define RTC_BKP31R RTC_BKP31R_Msk
<> 149:156823d33999 5703
<> 149:156823d33999 5704 /******************** Number of backup registers ******************************/
<> 149:156823d33999 5705 #define RTC_BKP_NUMBER 32
<> 149:156823d33999 5706
<> 149:156823d33999 5707 /******************************************************************************/
<> 149:156823d33999 5708 /* */
<> 149:156823d33999 5709 /* Serial Peripheral Interface (SPI) */
<> 149:156823d33999 5710 /* */
<> 149:156823d33999 5711 /******************************************************************************/
<> 149:156823d33999 5712
<> 149:156823d33999 5713 /*
<> 149:156823d33999 5714 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 149:156823d33999 5715 */
<> 149:156823d33999 5716 #define SPI_I2S_SUPPORT
<> 149:156823d33999 5717
<> 149:156823d33999 5718 /******************* Bit definition for SPI_CR1 register ********************/
<> 149:156823d33999 5719 #define SPI_CR1_CPHA_Pos (0U)
<> 149:156823d33999 5720 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5721 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
<> 149:156823d33999 5722 #define SPI_CR1_CPOL_Pos (1U)
<> 149:156823d33999 5723 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5724 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
<> 149:156823d33999 5725 #define SPI_CR1_MSTR_Pos (2U)
<> 149:156823d33999 5726 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5727 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
<> 149:156823d33999 5728
<> 149:156823d33999 5729 #define SPI_CR1_BR_Pos (3U)
<> 149:156823d33999 5730 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
<> 149:156823d33999 5731 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
<> 149:156823d33999 5732 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5733 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5734 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5735
<> 149:156823d33999 5736 #define SPI_CR1_SPE_Pos (6U)
<> 149:156823d33999 5737 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5738 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
<> 149:156823d33999 5739 #define SPI_CR1_LSBFIRST_Pos (7U)
<> 149:156823d33999 5740 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5741 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
<> 149:156823d33999 5742 #define SPI_CR1_SSI_Pos (8U)
<> 149:156823d33999 5743 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5744 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
<> 149:156823d33999 5745 #define SPI_CR1_SSM_Pos (9U)
<> 149:156823d33999 5746 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5747 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
<> 149:156823d33999 5748 #define SPI_CR1_RXONLY_Pos (10U)
<> 149:156823d33999 5749 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5750 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
<> 149:156823d33999 5751 #define SPI_CR1_DFF_Pos (11U)
<> 149:156823d33999 5752 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5753 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
<> 149:156823d33999 5754 #define SPI_CR1_CRCNEXT_Pos (12U)
<> 149:156823d33999 5755 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
<> 149:156823d33999 5756 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
<> 149:156823d33999 5757 #define SPI_CR1_CRCEN_Pos (13U)
<> 149:156823d33999 5758 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
<> 149:156823d33999 5759 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
<> 149:156823d33999 5760 #define SPI_CR1_BIDIOE_Pos (14U)
<> 149:156823d33999 5761 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 5762 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
<> 149:156823d33999 5763 #define SPI_CR1_BIDIMODE_Pos (15U)
<> 149:156823d33999 5764 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 5765 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
<> 149:156823d33999 5766
<> 149:156823d33999 5767 /******************* Bit definition for SPI_CR2 register ********************/
<> 149:156823d33999 5768 #define SPI_CR2_RXDMAEN_Pos (0U)
<> 149:156823d33999 5769 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5770 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
<> 149:156823d33999 5771 #define SPI_CR2_TXDMAEN_Pos (1U)
<> 149:156823d33999 5772 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5773 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
<> 149:156823d33999 5774 #define SPI_CR2_SSOE_Pos (2U)
<> 149:156823d33999 5775 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5776 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
<> 149:156823d33999 5777 #define SPI_CR2_FRF_Pos (4U)
<> 149:156823d33999 5778 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5779 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */
<> 149:156823d33999 5780 #define SPI_CR2_ERRIE_Pos (5U)
<> 149:156823d33999 5781 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5782 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
<> 149:156823d33999 5783 #define SPI_CR2_RXNEIE_Pos (6U)
<> 149:156823d33999 5784 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5785 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
<> 149:156823d33999 5786 #define SPI_CR2_TXEIE_Pos (7U)
<> 149:156823d33999 5787 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5788 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
<> 149:156823d33999 5789
<> 149:156823d33999 5790 /******************** Bit definition for SPI_SR register ********************/
<> 149:156823d33999 5791 #define SPI_SR_RXNE_Pos (0U)
<> 149:156823d33999 5792 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5793 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
<> 149:156823d33999 5794 #define SPI_SR_TXE_Pos (1U)
<> 149:156823d33999 5795 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5796 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
<> 149:156823d33999 5797 #define SPI_SR_CHSIDE_Pos (2U)
<> 149:156823d33999 5798 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5799 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
<> 149:156823d33999 5800 #define SPI_SR_UDR_Pos (3U)
<> 149:156823d33999 5801 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5802 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
<> 149:156823d33999 5803 #define SPI_SR_CRCERR_Pos (4U)
<> 149:156823d33999 5804 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5805 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
<> 149:156823d33999 5806 #define SPI_SR_MODF_Pos (5U)
<> 149:156823d33999 5807 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5808 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
<> 149:156823d33999 5809 #define SPI_SR_OVR_Pos (6U)
<> 149:156823d33999 5810 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
<> 149:156823d33999 5811 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
<> 149:156823d33999 5812 #define SPI_SR_BSY_Pos (7U)
<> 149:156823d33999 5813 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5814 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
<> 149:156823d33999 5815 #define SPI_SR_FRE_Pos (8U)
<> 149:156823d33999 5816 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5817 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
<> 149:156823d33999 5818
<> 149:156823d33999 5819 /******************** Bit definition for SPI_DR register ********************/
<> 149:156823d33999 5820 #define SPI_DR_DR_Pos (0U)
<> 149:156823d33999 5821 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 5822 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
<> 149:156823d33999 5823
<> 149:156823d33999 5824 /******************* Bit definition for SPI_CRCPR register ******************/
<> 149:156823d33999 5825 #define SPI_CRCPR_CRCPOLY_Pos (0U)
<> 149:156823d33999 5826 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 5827 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
<> 149:156823d33999 5828
<> 149:156823d33999 5829 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 149:156823d33999 5830 #define SPI_RXCRCR_RXCRC_Pos (0U)
<> 149:156823d33999 5831 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 5832 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
<> 149:156823d33999 5833
<> 149:156823d33999 5834 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 149:156823d33999 5835 #define SPI_TXCRCR_TXCRC_Pos (0U)
<> 149:156823d33999 5836 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 5837 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
<> 149:156823d33999 5838
<> 149:156823d33999 5839 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 149:156823d33999 5840 #define SPI_I2SCFGR_CHLEN_Pos (0U)
<> 149:156823d33999 5841 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5842 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
<> 149:156823d33999 5843
<> 149:156823d33999 5844 #define SPI_I2SCFGR_DATLEN_Pos (1U)
<> 149:156823d33999 5845 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
<> 149:156823d33999 5846 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 149:156823d33999 5847 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5848 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5849
<> 149:156823d33999 5850 #define SPI_I2SCFGR_CKPOL_Pos (3U)
<> 149:156823d33999 5851 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5852 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
<> 149:156823d33999 5853
<> 149:156823d33999 5854 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
<> 149:156823d33999 5855 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
<> 149:156823d33999 5856 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 149:156823d33999 5857 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5858 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5859
<> 149:156823d33999 5860 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
<> 149:156823d33999 5861 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
<> 149:156823d33999 5862 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
<> 149:156823d33999 5863
<> 149:156823d33999 5864 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
<> 149:156823d33999 5865 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
<> 149:156823d33999 5866 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 149:156823d33999 5867 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5868 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5869
<> 149:156823d33999 5870 #define SPI_I2SCFGR_I2SE_Pos (10U)
<> 149:156823d33999 5871 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 5872 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
<> 149:156823d33999 5873 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
<> 149:156823d33999 5874 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
<> 149:156823d33999 5875 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
<> 149:156823d33999 5876
<> 149:156823d33999 5877 /****************** Bit definition for SPI_I2SPR register *******************/
<> 149:156823d33999 5878 #define SPI_I2SPR_I2SDIV_Pos (0U)
<> 149:156823d33999 5879 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
<> 149:156823d33999 5880 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
<> 149:156823d33999 5881 #define SPI_I2SPR_ODD_Pos (8U)
<> 149:156823d33999 5882 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5883 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
<> 149:156823d33999 5884 #define SPI_I2SPR_MCKOE_Pos (9U)
<> 149:156823d33999 5885 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5886 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
<> 149:156823d33999 5887
<> 149:156823d33999 5888 /******************************************************************************/
<> 149:156823d33999 5889 /* */
<> 149:156823d33999 5890 /* System Configuration (SYSCFG) */
<> 149:156823d33999 5891 /* */
<> 149:156823d33999 5892 /******************************************************************************/
<> 149:156823d33999 5893 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
<> 149:156823d33999 5894 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
<> 149:156823d33999 5895 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
<> 149:156823d33999 5896 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
<> 149:156823d33999 5897 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5898 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5899 #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U)
<> 149:156823d33999 5900 #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */
<> 149:156823d33999 5901 #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */
<> 149:156823d33999 5902 #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 5903 #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 5904
<> 149:156823d33999 5905 /***************** Bit definition for SYSCFG_PMC register *******************/
<> 149:156823d33999 5906 #define SYSCFG_PMC_USB_PU_Pos (0U)
<> 149:156823d33999 5907 #define SYSCFG_PMC_USB_PU_Msk (0x1U << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */
<> 149:156823d33999 5908 #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */
<> 149:156823d33999 5909 #define SYSCFG_PMC_LCD_CAPA_Pos (1U)
<> 149:156823d33999 5910 #define SYSCFG_PMC_LCD_CAPA_Msk (0x1FU << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x0000003E */
<> 149:156823d33999 5911 #define SYSCFG_PMC_LCD_CAPA SYSCFG_PMC_LCD_CAPA_Msk /*!< LCD_CAPA decoupling capacitance connection */
<> 149:156823d33999 5912 #define SYSCFG_PMC_LCD_CAPA_0 (0x01U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 5913 #define SYSCFG_PMC_LCD_CAPA_1 (0x02U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 5914 #define SYSCFG_PMC_LCD_CAPA_2 (0x04U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 5915 #define SYSCFG_PMC_LCD_CAPA_3 (0x08U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 5916 #define SYSCFG_PMC_LCD_CAPA_4 (0x10U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000020 */
<> 149:156823d33999 5917
<> 149:156823d33999 5918 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 149:156823d33999 5919 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
<> 149:156823d33999 5920 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5921 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
<> 149:156823d33999 5922 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
<> 149:156823d33999 5923 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 5924 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
<> 149:156823d33999 5925 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
<> 149:156823d33999 5926 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5927 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
<> 149:156823d33999 5928 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
<> 149:156823d33999 5929 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
<> 149:156823d33999 5930 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
<> 149:156823d33999 5931
<> 149:156823d33999 5932 /**
<> 149:156823d33999 5933 * @brief EXTI0 configuration
<> 149:156823d33999 5934 */
<> 149:156823d33999 5935 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
<> 149:156823d33999 5936 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
<> 149:156823d33999 5937 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
<> 149:156823d33999 5938 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
<> 149:156823d33999 5939 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
<> 149:156823d33999 5940 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
<> 149:156823d33999 5941 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
<> 149:156823d33999 5942 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
<> 149:156823d33999 5943
<> 149:156823d33999 5944 /**
<> 149:156823d33999 5945 * @brief EXTI1 configuration
<> 149:156823d33999 5946 */
<> 149:156823d33999 5947 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
<> 149:156823d33999 5948 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
<> 149:156823d33999 5949 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
<> 149:156823d33999 5950 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
<> 149:156823d33999 5951 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
<> 149:156823d33999 5952 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
<> 149:156823d33999 5953 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
<> 149:156823d33999 5954 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
<> 149:156823d33999 5955
<> 149:156823d33999 5956 /**
<> 149:156823d33999 5957 * @brief EXTI2 configuration
<> 149:156823d33999 5958 */
<> 149:156823d33999 5959 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
<> 149:156823d33999 5960 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
<> 149:156823d33999 5961 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
<> 149:156823d33999 5962 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
<> 149:156823d33999 5963 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
<> 149:156823d33999 5964 #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
<> 149:156823d33999 5965 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
<> 149:156823d33999 5966 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
<> 149:156823d33999 5967
<> 149:156823d33999 5968 /**
<> 149:156823d33999 5969 * @brief EXTI3 configuration
<> 149:156823d33999 5970 */
<> 149:156823d33999 5971 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
<> 149:156823d33999 5972 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
<> 149:156823d33999 5973 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
<> 149:156823d33999 5974 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
<> 149:156823d33999 5975 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
<> 149:156823d33999 5976 #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
<> 149:156823d33999 5977 #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
<> 149:156823d33999 5978
<> 149:156823d33999 5979 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
<> 149:156823d33999 5980 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
<> 149:156823d33999 5981 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
<> 149:156823d33999 5982 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
<> 149:156823d33999 5983 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
<> 149:156823d33999 5984 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 5985 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
<> 149:156823d33999 5986 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
<> 149:156823d33999 5987 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 5988 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
<> 149:156823d33999 5989 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
<> 149:156823d33999 5990 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
<> 149:156823d33999 5991 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
<> 149:156823d33999 5992
<> 149:156823d33999 5993 /**
<> 149:156823d33999 5994 * @brief EXTI4 configuration
<> 149:156823d33999 5995 */
<> 149:156823d33999 5996 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
<> 149:156823d33999 5997 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
<> 149:156823d33999 5998 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
<> 149:156823d33999 5999 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
<> 149:156823d33999 6000 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
<> 149:156823d33999 6001 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
<> 149:156823d33999 6002 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
<> 149:156823d33999 6003
<> 149:156823d33999 6004 /**
<> 149:156823d33999 6005 * @brief EXTI5 configuration
<> 149:156823d33999 6006 */
<> 149:156823d33999 6007 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
<> 149:156823d33999 6008 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
<> 149:156823d33999 6009 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
<> 149:156823d33999 6010 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
<> 149:156823d33999 6011 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
<> 149:156823d33999 6012 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
<> 149:156823d33999 6013 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
<> 149:156823d33999 6014
<> 149:156823d33999 6015 /**
<> 149:156823d33999 6016 * @brief EXTI6 configuration
<> 149:156823d33999 6017 */
<> 149:156823d33999 6018 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
<> 149:156823d33999 6019 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
<> 149:156823d33999 6020 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
<> 149:156823d33999 6021 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
<> 149:156823d33999 6022 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
<> 149:156823d33999 6023 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
<> 149:156823d33999 6024 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
<> 149:156823d33999 6025
<> 149:156823d33999 6026 /**
<> 149:156823d33999 6027 * @brief EXTI7 configuration
<> 149:156823d33999 6028 */
<> 149:156823d33999 6029 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
<> 149:156823d33999 6030 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
<> 149:156823d33999 6031 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
<> 149:156823d33999 6032 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
<> 149:156823d33999 6033 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
<> 149:156823d33999 6034 #define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
<> 149:156823d33999 6035 #define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
<> 149:156823d33999 6036
<> 149:156823d33999 6037 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
<> 149:156823d33999 6038 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
<> 149:156823d33999 6039 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
<> 149:156823d33999 6040 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
<> 149:156823d33999 6041 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
<> 149:156823d33999 6042 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 6043 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
<> 149:156823d33999 6044 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
<> 149:156823d33999 6045 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 6046 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
<> 149:156823d33999 6047 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
<> 149:156823d33999 6048 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
<> 149:156823d33999 6049 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
<> 149:156823d33999 6050
<> 149:156823d33999 6051 /**
<> 149:156823d33999 6052 * @brief EXTI8 configuration
<> 149:156823d33999 6053 */
<> 149:156823d33999 6054 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
<> 149:156823d33999 6055 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
<> 149:156823d33999 6056 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
<> 149:156823d33999 6057 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
<> 149:156823d33999 6058 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
<> 149:156823d33999 6059 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
<> 149:156823d33999 6060 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
<> 149:156823d33999 6061
<> 149:156823d33999 6062 /**
<> 149:156823d33999 6063 * @brief EXTI9 configuration
<> 149:156823d33999 6064 */
<> 149:156823d33999 6065 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
<> 149:156823d33999 6066 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
<> 149:156823d33999 6067 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
<> 149:156823d33999 6068 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
<> 149:156823d33999 6069 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
<> 149:156823d33999 6070 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
<> 149:156823d33999 6071 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
<> 149:156823d33999 6072
<> 149:156823d33999 6073 /**
<> 149:156823d33999 6074 * @brief EXTI10 configuration
<> 149:156823d33999 6075 */
<> 149:156823d33999 6076 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
<> 149:156823d33999 6077 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
<> 149:156823d33999 6078 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
<> 149:156823d33999 6079 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
<> 149:156823d33999 6080 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
<> 149:156823d33999 6081 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
<> 149:156823d33999 6082 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
<> 149:156823d33999 6083
<> 149:156823d33999 6084 /**
<> 149:156823d33999 6085 * @brief EXTI11 configuration
<> 149:156823d33999 6086 */
<> 149:156823d33999 6087 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
<> 149:156823d33999 6088 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
<> 149:156823d33999 6089 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
<> 149:156823d33999 6090 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
<> 149:156823d33999 6091 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
<> 149:156823d33999 6092 #define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
<> 149:156823d33999 6093 #define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
<> 149:156823d33999 6094
<> 149:156823d33999 6095 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
<> 149:156823d33999 6096 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
<> 149:156823d33999 6097 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
<> 149:156823d33999 6098 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
<> 149:156823d33999 6099 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
<> 149:156823d33999 6100 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 6101 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
<> 149:156823d33999 6102 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
<> 149:156823d33999 6103 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 6104 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
<> 149:156823d33999 6105 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
<> 149:156823d33999 6106 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
<> 149:156823d33999 6107 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
<> 149:156823d33999 6108
<> 149:156823d33999 6109 /**
<> 149:156823d33999 6110 * @brief EXTI12 configuration
<> 149:156823d33999 6111 */
<> 149:156823d33999 6112 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
<> 149:156823d33999 6113 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
<> 149:156823d33999 6114 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
<> 149:156823d33999 6115 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
<> 149:156823d33999 6116 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
<> 149:156823d33999 6117 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
<> 149:156823d33999 6118 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
<> 149:156823d33999 6119
<> 149:156823d33999 6120 /**
<> 149:156823d33999 6121 * @brief EXTI13 configuration
<> 149:156823d33999 6122 */
<> 149:156823d33999 6123 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
<> 149:156823d33999 6124 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
<> 149:156823d33999 6125 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
<> 149:156823d33999 6126 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
<> 149:156823d33999 6127 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
<> 149:156823d33999 6128 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
<> 149:156823d33999 6129 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
<> 149:156823d33999 6130
<> 149:156823d33999 6131 /**
<> 149:156823d33999 6132 * @brief EXTI14 configuration
<> 149:156823d33999 6133 */
<> 149:156823d33999 6134 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
<> 149:156823d33999 6135 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
<> 149:156823d33999 6136 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
<> 149:156823d33999 6137 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
<> 149:156823d33999 6138 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
<> 149:156823d33999 6139 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
<> 149:156823d33999 6140 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
<> 149:156823d33999 6141
<> 149:156823d33999 6142 /**
<> 149:156823d33999 6143 * @brief EXTI15 configuration
<> 149:156823d33999 6144 */
<> 149:156823d33999 6145 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
<> 149:156823d33999 6146 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
<> 149:156823d33999 6147 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
<> 149:156823d33999 6148 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
<> 149:156823d33999 6149 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
<> 149:156823d33999 6150 #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
<> 149:156823d33999 6151 #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
<> 149:156823d33999 6152
<> 149:156823d33999 6153 /******************************************************************************/
<> 149:156823d33999 6154 /* */
<> 149:156823d33999 6155 /* Routing Interface (RI) */
<> 149:156823d33999 6156 /* */
<> 149:156823d33999 6157 /******************************************************************************/
<> 149:156823d33999 6158
<> 149:156823d33999 6159 /******************** Bit definition for RI_ICR register ********************/
<> 149:156823d33999 6160 #define RI_ICR_IC1OS_Pos (0U)
<> 149:156823d33999 6161 #define RI_ICR_IC1OS_Msk (0xFU << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
<> 149:156823d33999 6162 #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
<> 149:156823d33999 6163 #define RI_ICR_IC1OS_0 (0x1U << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6164 #define RI_ICR_IC1OS_1 (0x2U << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6165 #define RI_ICR_IC1OS_2 (0x4U << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6166 #define RI_ICR_IC1OS_3 (0x8U << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6167
<> 149:156823d33999 6168 #define RI_ICR_IC2OS_Pos (4U)
<> 149:156823d33999 6169 #define RI_ICR_IC2OS_Msk (0xFU << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 6170 #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
<> 149:156823d33999 6171 #define RI_ICR_IC2OS_0 (0x1U << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6172 #define RI_ICR_IC2OS_1 (0x2U << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6173 #define RI_ICR_IC2OS_2 (0x4U << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6174 #define RI_ICR_IC2OS_3 (0x8U << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6175
<> 149:156823d33999 6176 #define RI_ICR_IC3OS_Pos (8U)
<> 149:156823d33999 6177 #define RI_ICR_IC3OS_Msk (0xFU << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 6178 #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
<> 149:156823d33999 6179 #define RI_ICR_IC3OS_0 (0x1U << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6180 #define RI_ICR_IC3OS_1 (0x2U << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6181 #define RI_ICR_IC3OS_2 (0x4U << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6182 #define RI_ICR_IC3OS_3 (0x8U << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6183
<> 149:156823d33999 6184 #define RI_ICR_IC4OS_Pos (12U)
<> 149:156823d33999 6185 #define RI_ICR_IC4OS_Msk (0xFU << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */
<> 149:156823d33999 6186 #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
<> 149:156823d33999 6187 #define RI_ICR_IC4OS_0 (0x1U << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6188 #define RI_ICR_IC4OS_1 (0x2U << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6189 #define RI_ICR_IC4OS_2 (0x4U << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6190 #define RI_ICR_IC4OS_3 (0x8U << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6191
<> 149:156823d33999 6192 #define RI_ICR_TIM_Pos (16U)
<> 149:156823d33999 6193 #define RI_ICR_TIM_Msk (0x3U << RI_ICR_TIM_Pos) /*!< 0x00030000 */
<> 149:156823d33999 6194 #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */
<> 149:156823d33999 6195 #define RI_ICR_TIM_0 (0x1U << RI_ICR_TIM_Pos) /*!< 0x00010000 */
<> 149:156823d33999 6196 #define RI_ICR_TIM_1 (0x2U << RI_ICR_TIM_Pos) /*!< 0x00020000 */
<> 149:156823d33999 6197
<> 149:156823d33999 6198 #define RI_ICR_IC1_Pos (18U)
<> 149:156823d33999 6199 #define RI_ICR_IC1_Msk (0x1U << RI_ICR_IC1_Pos) /*!< 0x00040000 */
<> 149:156823d33999 6200 #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */
<> 149:156823d33999 6201 #define RI_ICR_IC2_Pos (19U)
<> 149:156823d33999 6202 #define RI_ICR_IC2_Msk (0x1U << RI_ICR_IC2_Pos) /*!< 0x00080000 */
<> 149:156823d33999 6203 #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */
<> 149:156823d33999 6204 #define RI_ICR_IC3_Pos (20U)
<> 149:156823d33999 6205 #define RI_ICR_IC3_Msk (0x1U << RI_ICR_IC3_Pos) /*!< 0x00100000 */
<> 149:156823d33999 6206 #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */
<> 149:156823d33999 6207 #define RI_ICR_IC4_Pos (21U)
<> 149:156823d33999 6208 #define RI_ICR_IC4_Msk (0x1U << RI_ICR_IC4_Pos) /*!< 0x00200000 */
<> 149:156823d33999 6209 #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */
<> 149:156823d33999 6210
<> 149:156823d33999 6211 /******************** Bit definition for RI_ASCR1 register ********************/
<> 149:156823d33999 6212 #define RI_ASCR1_CH_Pos (0U)
<> 149:156823d33999 6213 #define RI_ASCR1_CH_Msk (0x7BFDFFFFU << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */
<> 149:156823d33999 6214 #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
<> 149:156823d33999 6215 #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */
<> 149:156823d33999 6216 #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */
<> 149:156823d33999 6217 #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */
<> 149:156823d33999 6218 #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */
<> 149:156823d33999 6219 #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */
<> 149:156823d33999 6220 #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */
<> 149:156823d33999 6221 #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */
<> 149:156823d33999 6222 #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */
<> 149:156823d33999 6223 #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */
<> 149:156823d33999 6224 #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */
<> 149:156823d33999 6225 #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */
<> 149:156823d33999 6226 #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */
<> 149:156823d33999 6227 #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */
<> 149:156823d33999 6228 #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */
<> 149:156823d33999 6229 #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */
<> 149:156823d33999 6230 #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */
<> 149:156823d33999 6231 #define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */
<> 149:156823d33999 6232 #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */
<> 149:156823d33999 6233 #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */
<> 149:156823d33999 6234 #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */
<> 149:156823d33999 6235 #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */
<> 149:156823d33999 6236 #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */
<> 149:156823d33999 6237 #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */
<> 149:156823d33999 6238 #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */
<> 149:156823d33999 6239 #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */
<> 149:156823d33999 6240 #define RI_ASCR1_VCOMP_Pos (26U)
<> 149:156823d33999 6241 #define RI_ASCR1_VCOMP_Msk (0x1U << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */
<> 149:156823d33999 6242 #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */
<> 149:156823d33999 6243 #define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */
<> 149:156823d33999 6244 #define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */
<> 149:156823d33999 6245 #define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */
<> 149:156823d33999 6246 #define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */
<> 149:156823d33999 6247 #define RI_ASCR1_SCM_Pos (31U)
<> 149:156823d33999 6248 #define RI_ASCR1_SCM_Msk (0x1U << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */
<> 149:156823d33999 6249 #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */
<> 149:156823d33999 6250
<> 149:156823d33999 6251 /******************** Bit definition for RI_ASCR2 register ********************/
<> 149:156823d33999 6252 #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */
<> 149:156823d33999 6253 #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */
<> 149:156823d33999 6254 #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */
<> 149:156823d33999 6255 #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */
<> 149:156823d33999 6256 #define RI_ASCR2_GR6_Pos (4U)
<> 149:156823d33999 6257 #define RI_ASCR2_GR6_Msk (0x1800003U << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */
<> 149:156823d33999 6258 #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */
<> 149:156823d33999 6259 #define RI_ASCR2_GR6_1 (0x0000001U << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6260 #define RI_ASCR2_GR6_2 (0x0000002U << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6261 #define RI_ASCR2_GR6_3 (0x0800000U << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */
<> 149:156823d33999 6262 #define RI_ASCR2_GR6_4 (0x1000000U << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */
<> 149:156823d33999 6263 #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */
<> 149:156823d33999 6264 #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */
<> 149:156823d33999 6265 #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */
<> 149:156823d33999 6266 #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */
<> 149:156823d33999 6267 #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */
<> 149:156823d33999 6268 #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */
<> 149:156823d33999 6269 #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */
<> 149:156823d33999 6270 #define RI_ASCR2_CH0b_Pos (16U)
<> 149:156823d33999 6271 #define RI_ASCR2_CH0b_Msk (0x1U << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */
<> 149:156823d33999 6272 #define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */
<> 149:156823d33999 6273 #define RI_ASCR2_CH1b_Pos (17U)
<> 149:156823d33999 6274 #define RI_ASCR2_CH1b_Msk (0x1U << RI_ASCR2_CH1b_Pos) /*!< 0x00020000 */
<> 149:156823d33999 6275 #define RI_ASCR2_CH1b RI_ASCR2_CH1b_Msk /*!< CH1b selection bit */
<> 149:156823d33999 6276 #define RI_ASCR2_CH2b_Pos (18U)
<> 149:156823d33999 6277 #define RI_ASCR2_CH2b_Msk (0x1U << RI_ASCR2_CH2b_Pos) /*!< 0x00040000 */
<> 149:156823d33999 6278 #define RI_ASCR2_CH2b RI_ASCR2_CH2b_Msk /*!< CH2b selection bit */
<> 149:156823d33999 6279 #define RI_ASCR2_CH3b_Pos (19U)
<> 149:156823d33999 6280 #define RI_ASCR2_CH3b_Msk (0x1U << RI_ASCR2_CH3b_Pos) /*!< 0x00080000 */
<> 149:156823d33999 6281 #define RI_ASCR2_CH3b RI_ASCR2_CH3b_Msk /*!< CH3b selection bit */
<> 149:156823d33999 6282 #define RI_ASCR2_CH6b_Pos (20U)
<> 149:156823d33999 6283 #define RI_ASCR2_CH6b_Msk (0x1U << RI_ASCR2_CH6b_Pos) /*!< 0x00100000 */
<> 149:156823d33999 6284 #define RI_ASCR2_CH6b RI_ASCR2_CH6b_Msk /*!< CH6b selection bit */
<> 149:156823d33999 6285 #define RI_ASCR2_CH7b_Pos (21U)
<> 149:156823d33999 6286 #define RI_ASCR2_CH7b_Msk (0x1U << RI_ASCR2_CH7b_Pos) /*!< 0x00200000 */
<> 149:156823d33999 6287 #define RI_ASCR2_CH7b RI_ASCR2_CH7b_Msk /*!< CH7b selection bit */
<> 149:156823d33999 6288 #define RI_ASCR2_CH8b_Pos (22U)
<> 149:156823d33999 6289 #define RI_ASCR2_CH8b_Msk (0x1U << RI_ASCR2_CH8b_Pos) /*!< 0x00400000 */
<> 149:156823d33999 6290 #define RI_ASCR2_CH8b RI_ASCR2_CH8b_Msk /*!< CH8b selection bit */
<> 149:156823d33999 6291 #define RI_ASCR2_CH9b_Pos (23U)
<> 149:156823d33999 6292 #define RI_ASCR2_CH9b_Msk (0x1U << RI_ASCR2_CH9b_Pos) /*!< 0x00800000 */
<> 149:156823d33999 6293 #define RI_ASCR2_CH9b RI_ASCR2_CH9b_Msk /*!< CH9b selection bit */
<> 149:156823d33999 6294 #define RI_ASCR2_CH10b_Pos (24U)
<> 149:156823d33999 6295 #define RI_ASCR2_CH10b_Msk (0x1U << RI_ASCR2_CH10b_Pos) /*!< 0x01000000 */
<> 149:156823d33999 6296 #define RI_ASCR2_CH10b RI_ASCR2_CH10b_Msk /*!< CH10b selection bit */
<> 149:156823d33999 6297 #define RI_ASCR2_CH11b_Pos (25U)
<> 149:156823d33999 6298 #define RI_ASCR2_CH11b_Msk (0x1U << RI_ASCR2_CH11b_Pos) /*!< 0x02000000 */
<> 149:156823d33999 6299 #define RI_ASCR2_CH11b RI_ASCR2_CH11b_Msk /*!< CH11b selection bit */
<> 149:156823d33999 6300 #define RI_ASCR2_CH12b_Pos (26U)
<> 149:156823d33999 6301 #define RI_ASCR2_CH12b_Msk (0x1U << RI_ASCR2_CH12b_Pos) /*!< 0x04000000 */
<> 149:156823d33999 6302 #define RI_ASCR2_CH12b RI_ASCR2_CH12b_Msk /*!< CH12b selection bit */
<> 149:156823d33999 6303
<> 149:156823d33999 6304 /******************** Bit definition for RI_HYSCR1 register ********************/
<> 149:156823d33999 6305 #define RI_HYSCR1_PA_Pos (0U)
<> 149:156823d33999 6306 #define RI_HYSCR1_PA_Msk (0xFFFFU << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6307 #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */
<> 149:156823d33999 6308 #define RI_HYSCR1_PA_0 (0x0001U << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6309 #define RI_HYSCR1_PA_1 (0x0002U << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6310 #define RI_HYSCR1_PA_2 (0x0004U << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6311 #define RI_HYSCR1_PA_3 (0x0008U << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6312 #define RI_HYSCR1_PA_4 (0x0010U << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6313 #define RI_HYSCR1_PA_5 (0x0020U << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6314 #define RI_HYSCR1_PA_6 (0x0040U << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6315 #define RI_HYSCR1_PA_7 (0x0080U << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6316 #define RI_HYSCR1_PA_8 (0x0100U << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6317 #define RI_HYSCR1_PA_9 (0x0200U << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6318 #define RI_HYSCR1_PA_10 (0x0400U << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6319 #define RI_HYSCR1_PA_11 (0x0800U << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6320 #define RI_HYSCR1_PA_12 (0x1000U << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6321 #define RI_HYSCR1_PA_13 (0x2000U << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6322 #define RI_HYSCR1_PA_14 (0x4000U << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6323 #define RI_HYSCR1_PA_15 (0x8000U << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6324
<> 149:156823d33999 6325 #define RI_HYSCR1_PB_Pos (16U)
<> 149:156823d33999 6326 #define RI_HYSCR1_PB_Msk (0xFFFFU << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */
<> 149:156823d33999 6327 #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */
<> 149:156823d33999 6328 #define RI_HYSCR1_PB_0 (0x0001U << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */
<> 149:156823d33999 6329 #define RI_HYSCR1_PB_1 (0x0002U << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */
<> 149:156823d33999 6330 #define RI_HYSCR1_PB_2 (0x0004U << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */
<> 149:156823d33999 6331 #define RI_HYSCR1_PB_3 (0x0008U << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */
<> 149:156823d33999 6332 #define RI_HYSCR1_PB_4 (0x0010U << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */
<> 149:156823d33999 6333 #define RI_HYSCR1_PB_5 (0x0020U << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */
<> 149:156823d33999 6334 #define RI_HYSCR1_PB_6 (0x0040U << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */
<> 149:156823d33999 6335 #define RI_HYSCR1_PB_7 (0x0080U << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */
<> 149:156823d33999 6336 #define RI_HYSCR1_PB_8 (0x0100U << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */
<> 149:156823d33999 6337 #define RI_HYSCR1_PB_9 (0x0200U << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */
<> 149:156823d33999 6338 #define RI_HYSCR1_PB_10 (0x0400U << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */
<> 149:156823d33999 6339 #define RI_HYSCR1_PB_11 (0x0800U << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */
<> 149:156823d33999 6340 #define RI_HYSCR1_PB_12 (0x1000U << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */
<> 149:156823d33999 6341 #define RI_HYSCR1_PB_13 (0x2000U << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */
<> 149:156823d33999 6342 #define RI_HYSCR1_PB_14 (0x4000U << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */
<> 149:156823d33999 6343 #define RI_HYSCR1_PB_15 (0x8000U << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */
<> 149:156823d33999 6344
<> 149:156823d33999 6345 /******************** Bit definition for RI_HYSCR2 register ********************/
<> 149:156823d33999 6346 #define RI_HYSCR2_PC_Pos (0U)
<> 149:156823d33999 6347 #define RI_HYSCR2_PC_Msk (0xFFFFU << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6348 #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */
<> 149:156823d33999 6349 #define RI_HYSCR2_PC_0 (0x0001U << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6350 #define RI_HYSCR2_PC_1 (0x0002U << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6351 #define RI_HYSCR2_PC_2 (0x0004U << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6352 #define RI_HYSCR2_PC_3 (0x0008U << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6353 #define RI_HYSCR2_PC_4 (0x0010U << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6354 #define RI_HYSCR2_PC_5 (0x0020U << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6355 #define RI_HYSCR2_PC_6 (0x0040U << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6356 #define RI_HYSCR2_PC_7 (0x0080U << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6357 #define RI_HYSCR2_PC_8 (0x0100U << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6358 #define RI_HYSCR2_PC_9 (0x0200U << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6359 #define RI_HYSCR2_PC_10 (0x0400U << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6360 #define RI_HYSCR2_PC_11 (0x0800U << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6361 #define RI_HYSCR2_PC_12 (0x1000U << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6362 #define RI_HYSCR2_PC_13 (0x2000U << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6363 #define RI_HYSCR2_PC_14 (0x4000U << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6364 #define RI_HYSCR2_PC_15 (0x8000U << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6365
<> 149:156823d33999 6366 #define RI_HYSCR2_PD_Pos (16U)
<> 149:156823d33999 6367 #define RI_HYSCR2_PD_Msk (0xFFFFU << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */
<> 149:156823d33999 6368 #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */
<> 149:156823d33999 6369 #define RI_HYSCR2_PD_0 (0x0001U << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */
<> 149:156823d33999 6370 #define RI_HYSCR2_PD_1 (0x0002U << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */
<> 149:156823d33999 6371 #define RI_HYSCR2_PD_2 (0x0004U << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */
<> 149:156823d33999 6372 #define RI_HYSCR2_PD_3 (0x0008U << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */
<> 149:156823d33999 6373 #define RI_HYSCR2_PD_4 (0x0010U << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */
<> 149:156823d33999 6374 #define RI_HYSCR2_PD_5 (0x0020U << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */
<> 149:156823d33999 6375 #define RI_HYSCR2_PD_6 (0x0040U << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */
<> 149:156823d33999 6376 #define RI_HYSCR2_PD_7 (0x0080U << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */
<> 149:156823d33999 6377 #define RI_HYSCR2_PD_8 (0x0100U << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */
<> 149:156823d33999 6378 #define RI_HYSCR2_PD_9 (0x0200U << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */
<> 149:156823d33999 6379 #define RI_HYSCR2_PD_10 (0x0400U << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */
<> 149:156823d33999 6380 #define RI_HYSCR2_PD_11 (0x0800U << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */
<> 149:156823d33999 6381 #define RI_HYSCR2_PD_12 (0x1000U << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */
<> 149:156823d33999 6382 #define RI_HYSCR2_PD_13 (0x2000U << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */
<> 149:156823d33999 6383 #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
<> 149:156823d33999 6384 #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */
<> 149:156823d33999 6385
<> 149:156823d33999 6386 /******************** Bit definition for RI_HYSCR3 register ********************/
<> 149:156823d33999 6387 #define RI_HYSCR3_PE_Pos (0U)
<> 149:156823d33999 6388 #define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6389 #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
<> 149:156823d33999 6390 #define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6391 #define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6392 #define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6393 #define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6394 #define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6395 #define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6396 #define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6397 #define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6398 #define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6399 #define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6400 #define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6401 #define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6402 #define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6403 #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6404 #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6405 #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6406 #define RI_HYSCR3_PF_Pos (16U)
<> 149:156823d33999 6407 #define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */
<> 149:156823d33999 6408 #define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */
<> 149:156823d33999 6409 #define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */
<> 149:156823d33999 6410 #define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */
<> 149:156823d33999 6411 #define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */
<> 149:156823d33999 6412 #define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */
<> 149:156823d33999 6413 #define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */
<> 149:156823d33999 6414 #define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */
<> 149:156823d33999 6415 #define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */
<> 149:156823d33999 6416 #define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */
<> 149:156823d33999 6417 #define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */
<> 149:156823d33999 6418 #define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */
<> 149:156823d33999 6419 #define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */
<> 149:156823d33999 6420 #define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */
<> 149:156823d33999 6421 #define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */
<> 149:156823d33999 6422 #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */
<> 149:156823d33999 6423 #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */
<> 149:156823d33999 6424 #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */
<> 149:156823d33999 6425 /******************** Bit definition for RI_HYSCR4 register ********************/
<> 149:156823d33999 6426 #define RI_HYSCR4_PG_Pos (0U)
<> 149:156823d33999 6427 #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6428 #define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */
<> 149:156823d33999 6429 #define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6430 #define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6431 #define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6432 #define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6433 #define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6434 #define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6435 #define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6436 #define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6437 #define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6438 #define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6439 #define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6440 #define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6441 #define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6442 #define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6443 #define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6444 #define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6445
<> 149:156823d33999 6446 /******************** Bit definition for RI_ASMR1 register ********************/
<> 149:156823d33999 6447 #define RI_ASMR1_PA_Pos (0U)
<> 149:156823d33999 6448 #define RI_ASMR1_PA_Msk (0xFFFFU << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6449 #define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/
<> 149:156823d33999 6450 #define RI_ASMR1_PA_0 (0x0001U << RI_ASMR1_PA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6451 #define RI_ASMR1_PA_1 (0x0002U << RI_ASMR1_PA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6452 #define RI_ASMR1_PA_2 (0x0004U << RI_ASMR1_PA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6453 #define RI_ASMR1_PA_3 (0x0008U << RI_ASMR1_PA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6454 #define RI_ASMR1_PA_4 (0x0010U << RI_ASMR1_PA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6455 #define RI_ASMR1_PA_5 (0x0020U << RI_ASMR1_PA_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6456 #define RI_ASMR1_PA_6 (0x0040U << RI_ASMR1_PA_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6457 #define RI_ASMR1_PA_7 (0x0080U << RI_ASMR1_PA_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6458 #define RI_ASMR1_PA_8 (0x0100U << RI_ASMR1_PA_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6459 #define RI_ASMR1_PA_9 (0x0200U << RI_ASMR1_PA_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6460 #define RI_ASMR1_PA_10 (0x0400U << RI_ASMR1_PA_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6461 #define RI_ASMR1_PA_11 (0x0800U << RI_ASMR1_PA_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6462 #define RI_ASMR1_PA_12 (0x1000U << RI_ASMR1_PA_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6463 #define RI_ASMR1_PA_13 (0x2000U << RI_ASMR1_PA_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6464 #define RI_ASMR1_PA_14 (0x4000U << RI_ASMR1_PA_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6465 #define RI_ASMR1_PA_15 (0x8000U << RI_ASMR1_PA_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6466
<> 149:156823d33999 6467 /******************** Bit definition for RI_CMR1 register ********************/
<> 149:156823d33999 6468 #define RI_CMR1_PA_Pos (0U)
<> 149:156823d33999 6469 #define RI_CMR1_PA_Msk (0xFFFFU << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6470 #define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/
<> 149:156823d33999 6471 #define RI_CMR1_PA_0 (0x0001U << RI_CMR1_PA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6472 #define RI_CMR1_PA_1 (0x0002U << RI_CMR1_PA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6473 #define RI_CMR1_PA_2 (0x0004U << RI_CMR1_PA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6474 #define RI_CMR1_PA_3 (0x0008U << RI_CMR1_PA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6475 #define RI_CMR1_PA_4 (0x0010U << RI_CMR1_PA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6476 #define RI_CMR1_PA_5 (0x0020U << RI_CMR1_PA_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6477 #define RI_CMR1_PA_6 (0x0040U << RI_CMR1_PA_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6478 #define RI_CMR1_PA_7 (0x0080U << RI_CMR1_PA_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6479 #define RI_CMR1_PA_8 (0x0100U << RI_CMR1_PA_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6480 #define RI_CMR1_PA_9 (0x0200U << RI_CMR1_PA_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6481 #define RI_CMR1_PA_10 (0x0400U << RI_CMR1_PA_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6482 #define RI_CMR1_PA_11 (0x0800U << RI_CMR1_PA_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6483 #define RI_CMR1_PA_12 (0x1000U << RI_CMR1_PA_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6484 #define RI_CMR1_PA_13 (0x2000U << RI_CMR1_PA_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6485 #define RI_CMR1_PA_14 (0x4000U << RI_CMR1_PA_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6486 #define RI_CMR1_PA_15 (0x8000U << RI_CMR1_PA_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6487
<> 149:156823d33999 6488 /******************** Bit definition for RI_CICR1 register ********************/
<> 149:156823d33999 6489 #define RI_CICR1_PA_Pos (0U)
<> 149:156823d33999 6490 #define RI_CICR1_PA_Msk (0xFFFFU << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6491 #define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/
<> 149:156823d33999 6492 #define RI_CICR1_PA_0 (0x0001U << RI_CICR1_PA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6493 #define RI_CICR1_PA_1 (0x0002U << RI_CICR1_PA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6494 #define RI_CICR1_PA_2 (0x0004U << RI_CICR1_PA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6495 #define RI_CICR1_PA_3 (0x0008U << RI_CICR1_PA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6496 #define RI_CICR1_PA_4 (0x0010U << RI_CICR1_PA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6497 #define RI_CICR1_PA_5 (0x0020U << RI_CICR1_PA_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6498 #define RI_CICR1_PA_6 (0x0040U << RI_CICR1_PA_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6499 #define RI_CICR1_PA_7 (0x0080U << RI_CICR1_PA_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6500 #define RI_CICR1_PA_8 (0x0100U << RI_CICR1_PA_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6501 #define RI_CICR1_PA_9 (0x0200U << RI_CICR1_PA_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6502 #define RI_CICR1_PA_10 (0x0400U << RI_CICR1_PA_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6503 #define RI_CICR1_PA_11 (0x0800U << RI_CICR1_PA_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6504 #define RI_CICR1_PA_12 (0x1000U << RI_CICR1_PA_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6505 #define RI_CICR1_PA_13 (0x2000U << RI_CICR1_PA_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6506 #define RI_CICR1_PA_14 (0x4000U << RI_CICR1_PA_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6507 #define RI_CICR1_PA_15 (0x8000U << RI_CICR1_PA_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6508
<> 149:156823d33999 6509 /******************** Bit definition for RI_ASMR2 register ********************/
<> 149:156823d33999 6510 #define RI_ASMR2_PB_Pos (0U)
<> 149:156823d33999 6511 #define RI_ASMR2_PB_Msk (0xFFFFU << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6512 #define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */
<> 149:156823d33999 6513 #define RI_ASMR2_PB_0 (0x0001U << RI_ASMR2_PB_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6514 #define RI_ASMR2_PB_1 (0x0002U << RI_ASMR2_PB_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6515 #define RI_ASMR2_PB_2 (0x0004U << RI_ASMR2_PB_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6516 #define RI_ASMR2_PB_3 (0x0008U << RI_ASMR2_PB_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6517 #define RI_ASMR2_PB_4 (0x0010U << RI_ASMR2_PB_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6518 #define RI_ASMR2_PB_5 (0x0020U << RI_ASMR2_PB_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6519 #define RI_ASMR2_PB_6 (0x0040U << RI_ASMR2_PB_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6520 #define RI_ASMR2_PB_7 (0x0080U << RI_ASMR2_PB_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6521 #define RI_ASMR2_PB_8 (0x0100U << RI_ASMR2_PB_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6522 #define RI_ASMR2_PB_9 (0x0200U << RI_ASMR2_PB_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6523 #define RI_ASMR2_PB_10 (0x0400U << RI_ASMR2_PB_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6524 #define RI_ASMR2_PB_11 (0x0800U << RI_ASMR2_PB_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6525 #define RI_ASMR2_PB_12 (0x1000U << RI_ASMR2_PB_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6526 #define RI_ASMR2_PB_13 (0x2000U << RI_ASMR2_PB_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6527 #define RI_ASMR2_PB_14 (0x4000U << RI_ASMR2_PB_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6528 #define RI_ASMR2_PB_15 (0x8000U << RI_ASMR2_PB_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6529
<> 149:156823d33999 6530 /******************** Bit definition for RI_CMR2 register ********************/
<> 149:156823d33999 6531 #define RI_CMR2_PB_Pos (0U)
<> 149:156823d33999 6532 #define RI_CMR2_PB_Msk (0xFFFFU << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6533 #define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */
<> 149:156823d33999 6534 #define RI_CMR2_PB_0 (0x0001U << RI_CMR2_PB_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6535 #define RI_CMR2_PB_1 (0x0002U << RI_CMR2_PB_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6536 #define RI_CMR2_PB_2 (0x0004U << RI_CMR2_PB_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6537 #define RI_CMR2_PB_3 (0x0008U << RI_CMR2_PB_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6538 #define RI_CMR2_PB_4 (0x0010U << RI_CMR2_PB_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6539 #define RI_CMR2_PB_5 (0x0020U << RI_CMR2_PB_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6540 #define RI_CMR2_PB_6 (0x0040U << RI_CMR2_PB_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6541 #define RI_CMR2_PB_7 (0x0080U << RI_CMR2_PB_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6542 #define RI_CMR2_PB_8 (0x0100U << RI_CMR2_PB_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6543 #define RI_CMR2_PB_9 (0x0200U << RI_CMR2_PB_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6544 #define RI_CMR2_PB_10 (0x0400U << RI_CMR2_PB_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6545 #define RI_CMR2_PB_11 (0x0800U << RI_CMR2_PB_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6546 #define RI_CMR2_PB_12 (0x1000U << RI_CMR2_PB_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6547 #define RI_CMR2_PB_13 (0x2000U << RI_CMR2_PB_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6548 #define RI_CMR2_PB_14 (0x4000U << RI_CMR2_PB_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6549 #define RI_CMR2_PB_15 (0x8000U << RI_CMR2_PB_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6550
<> 149:156823d33999 6551 /******************** Bit definition for RI_CICR2 register ********************/
<> 149:156823d33999 6552 #define RI_CICR2_PB_Pos (0U)
<> 149:156823d33999 6553 #define RI_CICR2_PB_Msk (0xFFFFU << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6554 #define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */
<> 149:156823d33999 6555 #define RI_CICR2_PB_0 (0x0001U << RI_CICR2_PB_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6556 #define RI_CICR2_PB_1 (0x0002U << RI_CICR2_PB_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6557 #define RI_CICR2_PB_2 (0x0004U << RI_CICR2_PB_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6558 #define RI_CICR2_PB_3 (0x0008U << RI_CICR2_PB_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6559 #define RI_CICR2_PB_4 (0x0010U << RI_CICR2_PB_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6560 #define RI_CICR2_PB_5 (0x0020U << RI_CICR2_PB_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6561 #define RI_CICR2_PB_6 (0x0040U << RI_CICR2_PB_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6562 #define RI_CICR2_PB_7 (0x0080U << RI_CICR2_PB_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6563 #define RI_CICR2_PB_8 (0x0100U << RI_CICR2_PB_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6564 #define RI_CICR2_PB_9 (0x0200U << RI_CICR2_PB_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6565 #define RI_CICR2_PB_10 (0x0400U << RI_CICR2_PB_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6566 #define RI_CICR2_PB_11 (0x0800U << RI_CICR2_PB_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6567 #define RI_CICR2_PB_12 (0x1000U << RI_CICR2_PB_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6568 #define RI_CICR2_PB_13 (0x2000U << RI_CICR2_PB_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6569 #define RI_CICR2_PB_14 (0x4000U << RI_CICR2_PB_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6570 #define RI_CICR2_PB_15 (0x8000U << RI_CICR2_PB_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6571
<> 149:156823d33999 6572 /******************** Bit definition for RI_ASMR3 register ********************/
<> 149:156823d33999 6573 #define RI_ASMR3_PC_Pos (0U)
<> 149:156823d33999 6574 #define RI_ASMR3_PC_Msk (0xFFFFU << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6575 #define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */
<> 149:156823d33999 6576 #define RI_ASMR3_PC_0 (0x0001U << RI_ASMR3_PC_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6577 #define RI_ASMR3_PC_1 (0x0002U << RI_ASMR3_PC_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6578 #define RI_ASMR3_PC_2 (0x0004U << RI_ASMR3_PC_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6579 #define RI_ASMR3_PC_3 (0x0008U << RI_ASMR3_PC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6580 #define RI_ASMR3_PC_4 (0x0010U << RI_ASMR3_PC_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6581 #define RI_ASMR3_PC_5 (0x0020U << RI_ASMR3_PC_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6582 #define RI_ASMR3_PC_6 (0x0040U << RI_ASMR3_PC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6583 #define RI_ASMR3_PC_7 (0x0080U << RI_ASMR3_PC_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6584 #define RI_ASMR3_PC_8 (0x0100U << RI_ASMR3_PC_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6585 #define RI_ASMR3_PC_9 (0x0200U << RI_ASMR3_PC_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6586 #define RI_ASMR3_PC_10 (0x0400U << RI_ASMR3_PC_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6587 #define RI_ASMR3_PC_11 (0x0800U << RI_ASMR3_PC_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6588 #define RI_ASMR3_PC_12 (0x1000U << RI_ASMR3_PC_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6589 #define RI_ASMR3_PC_13 (0x2000U << RI_ASMR3_PC_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6590 #define RI_ASMR3_PC_14 (0x4000U << RI_ASMR3_PC_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6591 #define RI_ASMR3_PC_15 (0x8000U << RI_ASMR3_PC_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6592
<> 149:156823d33999 6593 /******************** Bit definition for RI_CMR3 register ********************/
<> 149:156823d33999 6594 #define RI_CMR3_PC_Pos (0U)
<> 149:156823d33999 6595 #define RI_CMR3_PC_Msk (0xFFFFU << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6596 #define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */
<> 149:156823d33999 6597 #define RI_CMR3_PC_0 (0x0001U << RI_CMR3_PC_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6598 #define RI_CMR3_PC_1 (0x0002U << RI_CMR3_PC_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6599 #define RI_CMR3_PC_2 (0x0004U << RI_CMR3_PC_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6600 #define RI_CMR3_PC_3 (0x0008U << RI_CMR3_PC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6601 #define RI_CMR3_PC_4 (0x0010U << RI_CMR3_PC_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6602 #define RI_CMR3_PC_5 (0x0020U << RI_CMR3_PC_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6603 #define RI_CMR3_PC_6 (0x0040U << RI_CMR3_PC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6604 #define RI_CMR3_PC_7 (0x0080U << RI_CMR3_PC_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6605 #define RI_CMR3_PC_8 (0x0100U << RI_CMR3_PC_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6606 #define RI_CMR3_PC_9 (0x0200U << RI_CMR3_PC_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6607 #define RI_CMR3_PC_10 (0x0400U << RI_CMR3_PC_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6608 #define RI_CMR3_PC_11 (0x0800U << RI_CMR3_PC_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6609 #define RI_CMR3_PC_12 (0x1000U << RI_CMR3_PC_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6610 #define RI_CMR3_PC_13 (0x2000U << RI_CMR3_PC_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6611 #define RI_CMR3_PC_14 (0x4000U << RI_CMR3_PC_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6612 #define RI_CMR3_PC_15 (0x8000U << RI_CMR3_PC_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6613
<> 149:156823d33999 6614 /******************** Bit definition for RI_CICR3 register ********************/
<> 149:156823d33999 6615 #define RI_CICR3_PC_Pos (0U)
<> 149:156823d33999 6616 #define RI_CICR3_PC_Msk (0xFFFFU << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6617 #define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */
<> 149:156823d33999 6618 #define RI_CICR3_PC_0 (0x0001U << RI_CICR3_PC_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6619 #define RI_CICR3_PC_1 (0x0002U << RI_CICR3_PC_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6620 #define RI_CICR3_PC_2 (0x0004U << RI_CICR3_PC_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6621 #define RI_CICR3_PC_3 (0x0008U << RI_CICR3_PC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6622 #define RI_CICR3_PC_4 (0x0010U << RI_CICR3_PC_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6623 #define RI_CICR3_PC_5 (0x0020U << RI_CICR3_PC_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6624 #define RI_CICR3_PC_6 (0x0040U << RI_CICR3_PC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6625 #define RI_CICR3_PC_7 (0x0080U << RI_CICR3_PC_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6626 #define RI_CICR3_PC_8 (0x0100U << RI_CICR3_PC_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6627 #define RI_CICR3_PC_9 (0x0200U << RI_CICR3_PC_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6628 #define RI_CICR3_PC_10 (0x0400U << RI_CICR3_PC_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6629 #define RI_CICR3_PC_11 (0x0800U << RI_CICR3_PC_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6630 #define RI_CICR3_PC_12 (0x1000U << RI_CICR3_PC_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6631 #define RI_CICR3_PC_13 (0x2000U << RI_CICR3_PC_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6632 #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6633 #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6634
<> 149:156823d33999 6635 /******************** Bit definition for RI_ASMR4 register ********************/
<> 149:156823d33999 6636 #define RI_ASMR4_PF_Pos (0U)
<> 149:156823d33999 6637 #define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6638 #define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */
<> 149:156823d33999 6639 #define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6640 #define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6641 #define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6642 #define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6643 #define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6644 #define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6645 #define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6646 #define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6647 #define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6648 #define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6649 #define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6650 #define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6651 #define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6652 #define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6653 #define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6654 #define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6655
<> 149:156823d33999 6656 /******************** Bit definition for RI_CMR4 register ********************/
<> 149:156823d33999 6657 #define RI_CMR4_PF_Pos (0U)
<> 149:156823d33999 6658 #define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6659 #define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */
<> 149:156823d33999 6660 #define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6661 #define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6662 #define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6663 #define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6664 #define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6665 #define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6666 #define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6667 #define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6668 #define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6669 #define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6670 #define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6671 #define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6672 #define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6673 #define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6674 #define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6675 #define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6676
<> 149:156823d33999 6677 /******************** Bit definition for RI_CICR4 register ********************/
<> 149:156823d33999 6678 #define RI_CICR4_PF_Pos (0U)
<> 149:156823d33999 6679 #define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6680 #define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */
<> 149:156823d33999 6681 #define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6682 #define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6683 #define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6684 #define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6685 #define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6686 #define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6687 #define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6688 #define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6689 #define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6690 #define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6691 #define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6692 #define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6693 #define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6694 #define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6695 #define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6696 #define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6697
<> 149:156823d33999 6698 /******************** Bit definition for RI_ASMR5 register ********************/
<> 149:156823d33999 6699 #define RI_ASMR5_PG_Pos (0U)
<> 149:156823d33999 6700 #define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6701 #define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */
<> 149:156823d33999 6702 #define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6703 #define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6704 #define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6705 #define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6706 #define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6707 #define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6708 #define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6709 #define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6710 #define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6711 #define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6712 #define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6713 #define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6714 #define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6715 #define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6716 #define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6717 #define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6718
<> 149:156823d33999 6719 /******************** Bit definition for RI_CMR5 register ********************/
<> 149:156823d33999 6720 #define RI_CMR5_PG_Pos (0U)
<> 149:156823d33999 6721 #define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6722 #define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */
<> 149:156823d33999 6723 #define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6724 #define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6725 #define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6726 #define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6727 #define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6728 #define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6729 #define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6730 #define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6731 #define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6732 #define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6733 #define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6734 #define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6735 #define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6736 #define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6737 #define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6738 #define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6739
<> 149:156823d33999 6740 /******************** Bit definition for RI_CICR5 register ********************/
<> 149:156823d33999 6741 #define RI_CICR5_PG_Pos (0U)
<> 149:156823d33999 6742 #define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 6743 #define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */
<> 149:156823d33999 6744 #define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6745 #define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6746 #define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6747 #define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6748 #define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6749 #define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6750 #define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6751 #define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6752 #define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6753 #define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6754 #define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6755 #define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6756 #define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6757 #define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6758 #define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6759 #define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6760
<> 149:156823d33999 6761 /******************************************************************************/
<> 149:156823d33999 6762 /* */
<> 149:156823d33999 6763 /* Timers (TIM) */
<> 149:156823d33999 6764 /* */
<> 149:156823d33999 6765 /******************************************************************************/
<> 149:156823d33999 6766
<> 149:156823d33999 6767 /******************* Bit definition for TIM_CR1 register ********************/
<> 149:156823d33999 6768 #define TIM_CR1_CEN_Pos (0U)
<> 149:156823d33999 6769 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6770 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
<> 149:156823d33999 6771 #define TIM_CR1_UDIS_Pos (1U)
<> 149:156823d33999 6772 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6773 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
<> 149:156823d33999 6774 #define TIM_CR1_URS_Pos (2U)
<> 149:156823d33999 6775 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6776 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
<> 149:156823d33999 6777 #define TIM_CR1_OPM_Pos (3U)
<> 149:156823d33999 6778 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6779 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
<> 149:156823d33999 6780 #define TIM_CR1_DIR_Pos (4U)
<> 149:156823d33999 6781 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6782 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
<> 149:156823d33999 6783
<> 149:156823d33999 6784 #define TIM_CR1_CMS_Pos (5U)
<> 149:156823d33999 6785 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
<> 149:156823d33999 6786 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 149:156823d33999 6787 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6788 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6789
<> 149:156823d33999 6790 #define TIM_CR1_ARPE_Pos (7U)
<> 149:156823d33999 6791 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6792 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
<> 149:156823d33999 6793
<> 149:156823d33999 6794 #define TIM_CR1_CKD_Pos (8U)
<> 149:156823d33999 6795 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
<> 149:156823d33999 6796 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
<> 149:156823d33999 6797 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6798 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6799
<> 149:156823d33999 6800 /******************* Bit definition for TIM_CR2 register ********************/
<> 149:156823d33999 6801 #define TIM_CR2_CCDS_Pos (3U)
<> 149:156823d33999 6802 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6803 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
<> 149:156823d33999 6804
<> 149:156823d33999 6805 #define TIM_CR2_MMS_Pos (4U)
<> 149:156823d33999 6806 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
<> 149:156823d33999 6807 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 149:156823d33999 6808 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6809 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6810 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6811
<> 149:156823d33999 6812 #define TIM_CR2_TI1S_Pos (7U)
<> 149:156823d33999 6813 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6814 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
<> 149:156823d33999 6815
<> 149:156823d33999 6816 /******************* Bit definition for TIM_SMCR register *******************/
<> 149:156823d33999 6817 #define TIM_SMCR_SMS_Pos (0U)
<> 149:156823d33999 6818 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
<> 149:156823d33999 6819 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
<> 149:156823d33999 6820 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6821 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6822 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6823
<> 149:156823d33999 6824 #define TIM_SMCR_OCCS_Pos (3U)
<> 149:156823d33999 6825 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6826 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
<> 149:156823d33999 6827
<> 149:156823d33999 6828 #define TIM_SMCR_TS_Pos (4U)
<> 149:156823d33999 6829 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
<> 149:156823d33999 6830 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
<> 149:156823d33999 6831 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6832 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6833 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6834
<> 149:156823d33999 6835 #define TIM_SMCR_MSM_Pos (7U)
<> 149:156823d33999 6836 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6837 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
<> 149:156823d33999 6838
<> 149:156823d33999 6839 #define TIM_SMCR_ETF_Pos (8U)
<> 149:156823d33999 6840 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
<> 149:156823d33999 6841 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
<> 149:156823d33999 6842 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6843 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6844 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6845 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6846
<> 149:156823d33999 6847 #define TIM_SMCR_ETPS_Pos (12U)
<> 149:156823d33999 6848 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
<> 149:156823d33999 6849 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 149:156823d33999 6850 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6851 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6852
<> 149:156823d33999 6853 #define TIM_SMCR_ECE_Pos (14U)
<> 149:156823d33999 6854 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6855 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
<> 149:156823d33999 6856 #define TIM_SMCR_ETP_Pos (15U)
<> 149:156823d33999 6857 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6858 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 149:156823d33999 6859
<> 149:156823d33999 6860 /******************* Bit definition for TIM_DIER register *******************/
<> 149:156823d33999 6861 #define TIM_DIER_UIE_Pos (0U)
<> 149:156823d33999 6862 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6863 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
<> 149:156823d33999 6864 #define TIM_DIER_CC1IE_Pos (1U)
<> 149:156823d33999 6865 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6866 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
<> 149:156823d33999 6867 #define TIM_DIER_CC2IE_Pos (2U)
<> 149:156823d33999 6868 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6869 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
<> 149:156823d33999 6870 #define TIM_DIER_CC3IE_Pos (3U)
<> 149:156823d33999 6871 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6872 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
<> 149:156823d33999 6873 #define TIM_DIER_CC4IE_Pos (4U)
<> 149:156823d33999 6874 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6875 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
<> 149:156823d33999 6876 #define TIM_DIER_TIE_Pos (6U)
<> 149:156823d33999 6877 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6878 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
<> 149:156823d33999 6879 #define TIM_DIER_UDE_Pos (8U)
<> 149:156823d33999 6880 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6881 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
<> 149:156823d33999 6882 #define TIM_DIER_CC1DE_Pos (9U)
<> 149:156823d33999 6883 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6884 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
<> 149:156823d33999 6885 #define TIM_DIER_CC2DE_Pos (10U)
<> 149:156823d33999 6886 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6887 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
<> 149:156823d33999 6888 #define TIM_DIER_CC3DE_Pos (11U)
<> 149:156823d33999 6889 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6890 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
<> 149:156823d33999 6891 #define TIM_DIER_CC4DE_Pos (12U)
<> 149:156823d33999 6892 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6893 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
<> 149:156823d33999 6894 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */
<> 149:156823d33999 6895 #define TIM_DIER_TDE_Pos (14U)
<> 149:156823d33999 6896 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6897 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 149:156823d33999 6898
<> 149:156823d33999 6899 /******************** Bit definition for TIM_SR register ********************/
<> 149:156823d33999 6900 #define TIM_SR_UIF_Pos (0U)
<> 149:156823d33999 6901 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6902 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
<> 149:156823d33999 6903 #define TIM_SR_CC1IF_Pos (1U)
<> 149:156823d33999 6904 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6905 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
<> 149:156823d33999 6906 #define TIM_SR_CC2IF_Pos (2U)
<> 149:156823d33999 6907 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6908 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
<> 149:156823d33999 6909 #define TIM_SR_CC3IF_Pos (3U)
<> 149:156823d33999 6910 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6911 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
<> 149:156823d33999 6912 #define TIM_SR_CC4IF_Pos (4U)
<> 149:156823d33999 6913 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6914 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
<> 149:156823d33999 6915 #define TIM_SR_TIF_Pos (6U)
<> 149:156823d33999 6916 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6917 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
<> 149:156823d33999 6918 #define TIM_SR_CC1OF_Pos (9U)
<> 149:156823d33999 6919 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6920 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
<> 149:156823d33999 6921 #define TIM_SR_CC2OF_Pos (10U)
<> 149:156823d33999 6922 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6923 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
<> 149:156823d33999 6924 #define TIM_SR_CC3OF_Pos (11U)
<> 149:156823d33999 6925 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6926 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
<> 149:156823d33999 6927 #define TIM_SR_CC4OF_Pos (12U)
<> 149:156823d33999 6928 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6929 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 149:156823d33999 6930
<> 149:156823d33999 6931 /******************* Bit definition for TIM_EGR register ********************/
<> 149:156823d33999 6932 #define TIM_EGR_UG_Pos (0U)
<> 149:156823d33999 6933 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6934 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
<> 149:156823d33999 6935 #define TIM_EGR_CC1G_Pos (1U)
<> 149:156823d33999 6936 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6937 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
<> 149:156823d33999 6938 #define TIM_EGR_CC2G_Pos (2U)
<> 149:156823d33999 6939 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6940 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
<> 149:156823d33999 6941 #define TIM_EGR_CC3G_Pos (3U)
<> 149:156823d33999 6942 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6943 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
<> 149:156823d33999 6944 #define TIM_EGR_CC4G_Pos (4U)
<> 149:156823d33999 6945 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6946 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
<> 149:156823d33999 6947 #define TIM_EGR_TG_Pos (6U)
<> 149:156823d33999 6948 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6949 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
<> 149:156823d33999 6950
<> 149:156823d33999 6951 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 149:156823d33999 6952 #define TIM_CCMR1_CC1S_Pos (0U)
<> 149:156823d33999 6953 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
<> 149:156823d33999 6954 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 149:156823d33999 6955 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
<> 149:156823d33999 6956 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
<> 149:156823d33999 6957
<> 149:156823d33999 6958 #define TIM_CCMR1_OC1FE_Pos (2U)
<> 149:156823d33999 6959 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 6960 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
<> 149:156823d33999 6961 #define TIM_CCMR1_OC1PE_Pos (3U)
<> 149:156823d33999 6962 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 6963 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
<> 149:156823d33999 6964
<> 149:156823d33999 6965 #define TIM_CCMR1_OC1M_Pos (4U)
<> 149:156823d33999 6966 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
<> 149:156823d33999 6967 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 149:156823d33999 6968 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
<> 149:156823d33999 6969 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
<> 149:156823d33999 6970 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
<> 149:156823d33999 6971
<> 149:156823d33999 6972 #define TIM_CCMR1_OC1CE_Pos (7U)
<> 149:156823d33999 6973 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 6974 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
<> 149:156823d33999 6975
<> 149:156823d33999 6976 #define TIM_CCMR1_CC2S_Pos (8U)
<> 149:156823d33999 6977 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
<> 149:156823d33999 6978 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 149:156823d33999 6979 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
<> 149:156823d33999 6980 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
<> 149:156823d33999 6981
<> 149:156823d33999 6982 #define TIM_CCMR1_OC2FE_Pos (10U)
<> 149:156823d33999 6983 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 6984 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
<> 149:156823d33999 6985 #define TIM_CCMR1_OC2PE_Pos (11U)
<> 149:156823d33999 6986 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 6987 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
<> 149:156823d33999 6988
<> 149:156823d33999 6989 #define TIM_CCMR1_OC2M_Pos (12U)
<> 149:156823d33999 6990 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
<> 149:156823d33999 6991 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 149:156823d33999 6992 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
<> 149:156823d33999 6993 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
<> 149:156823d33999 6994 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
<> 149:156823d33999 6995
<> 149:156823d33999 6996 #define TIM_CCMR1_OC2CE_Pos (15U)
<> 149:156823d33999 6997 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 6998 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 149:156823d33999 6999
<> 149:156823d33999 7000 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 7001
<> 149:156823d33999 7002 #define TIM_CCMR1_IC1PSC_Pos (2U)
<> 149:156823d33999 7003 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
<> 149:156823d33999 7004 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 149:156823d33999 7005 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7006 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7007
<> 149:156823d33999 7008 #define TIM_CCMR1_IC1F_Pos (4U)
<> 149:156823d33999 7009 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 7010 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 149:156823d33999 7011 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7012 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7013 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7014 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7015
<> 149:156823d33999 7016 #define TIM_CCMR1_IC2PSC_Pos (10U)
<> 149:156823d33999 7017 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
<> 149:156823d33999 7018 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 149:156823d33999 7019 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7020 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7021
<> 149:156823d33999 7022 #define TIM_CCMR1_IC2F_Pos (12U)
<> 149:156823d33999 7023 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
<> 149:156823d33999 7024 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 149:156823d33999 7025 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7026 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7027 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7028 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7029
<> 149:156823d33999 7030 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 149:156823d33999 7031 #define TIM_CCMR2_CC3S_Pos (0U)
<> 149:156823d33999 7032 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
<> 149:156823d33999 7033 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 149:156823d33999 7034 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7035 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7036
<> 149:156823d33999 7037 #define TIM_CCMR2_OC3FE_Pos (2U)
<> 149:156823d33999 7038 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7039 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
<> 149:156823d33999 7040 #define TIM_CCMR2_OC3PE_Pos (3U)
<> 149:156823d33999 7041 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7042 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
<> 149:156823d33999 7043
<> 149:156823d33999 7044 #define TIM_CCMR2_OC3M_Pos (4U)
<> 149:156823d33999 7045 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
<> 149:156823d33999 7046 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 149:156823d33999 7047 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7048 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7049 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7050
<> 149:156823d33999 7051 #define TIM_CCMR2_OC3CE_Pos (7U)
<> 149:156823d33999 7052 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7053 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
<> 149:156823d33999 7054
<> 149:156823d33999 7055 #define TIM_CCMR2_CC4S_Pos (8U)
<> 149:156823d33999 7056 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
<> 149:156823d33999 7057 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 149:156823d33999 7058 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7059 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7060
<> 149:156823d33999 7061 #define TIM_CCMR2_OC4FE_Pos (10U)
<> 149:156823d33999 7062 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7063 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
<> 149:156823d33999 7064 #define TIM_CCMR2_OC4PE_Pos (11U)
<> 149:156823d33999 7065 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7066 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
<> 149:156823d33999 7067
<> 149:156823d33999 7068 #define TIM_CCMR2_OC4M_Pos (12U)
<> 149:156823d33999 7069 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
<> 149:156823d33999 7070 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 149:156823d33999 7071 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7072 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7073 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7074
<> 149:156823d33999 7075 #define TIM_CCMR2_OC4CE_Pos (15U)
<> 149:156823d33999 7076 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7077 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 149:156823d33999 7078
<> 149:156823d33999 7079 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 7080
<> 149:156823d33999 7081 #define TIM_CCMR2_IC3PSC_Pos (2U)
<> 149:156823d33999 7082 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
<> 149:156823d33999 7083 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 149:156823d33999 7084 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7085 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7086
<> 149:156823d33999 7087 #define TIM_CCMR2_IC3F_Pos (4U)
<> 149:156823d33999 7088 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
<> 149:156823d33999 7089 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 149:156823d33999 7090 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7091 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7092 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7093 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7094
<> 149:156823d33999 7095 #define TIM_CCMR2_IC4PSC_Pos (10U)
<> 149:156823d33999 7096 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
<> 149:156823d33999 7097 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 149:156823d33999 7098 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7099 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7100
<> 149:156823d33999 7101 #define TIM_CCMR2_IC4F_Pos (12U)
<> 149:156823d33999 7102 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
<> 149:156823d33999 7103 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 149:156823d33999 7104 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7105 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7106 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7107 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7108
<> 149:156823d33999 7109 /******************* Bit definition for TIM_CCER register *******************/
<> 149:156823d33999 7110 #define TIM_CCER_CC1E_Pos (0U)
<> 149:156823d33999 7111 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7112 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
<> 149:156823d33999 7113 #define TIM_CCER_CC1P_Pos (1U)
<> 149:156823d33999 7114 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7115 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
<> 149:156823d33999 7116 #define TIM_CCER_CC1NP_Pos (3U)
<> 149:156823d33999 7117 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7118 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
<> 149:156823d33999 7119 #define TIM_CCER_CC2E_Pos (4U)
<> 149:156823d33999 7120 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7121 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
<> 149:156823d33999 7122 #define TIM_CCER_CC2P_Pos (5U)
<> 149:156823d33999 7123 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7124 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
<> 149:156823d33999 7125 #define TIM_CCER_CC2NP_Pos (7U)
<> 149:156823d33999 7126 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7127 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
<> 149:156823d33999 7128 #define TIM_CCER_CC3E_Pos (8U)
<> 149:156823d33999 7129 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7130 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
<> 149:156823d33999 7131 #define TIM_CCER_CC3P_Pos (9U)
<> 149:156823d33999 7132 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7133 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
<> 149:156823d33999 7134 #define TIM_CCER_CC3NP_Pos (11U)
<> 149:156823d33999 7135 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7136 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
<> 149:156823d33999 7137 #define TIM_CCER_CC4E_Pos (12U)
<> 149:156823d33999 7138 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7139 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
<> 149:156823d33999 7140 #define TIM_CCER_CC4P_Pos (13U)
<> 149:156823d33999 7141 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7142 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
<> 149:156823d33999 7143 #define TIM_CCER_CC4NP_Pos (15U)
<> 149:156823d33999 7144 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7145 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 149:156823d33999 7146
<> 149:156823d33999 7147 /******************* Bit definition for TIM_CNT register ********************/
<> 149:156823d33999 7148 #define TIM_CNT_CNT_Pos (0U)
<> 149:156823d33999 7149 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 7150 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 149:156823d33999 7151
<> 149:156823d33999 7152 /******************* Bit definition for TIM_PSC register ********************/
<> 149:156823d33999 7153 #define TIM_PSC_PSC_Pos (0U)
<> 149:156823d33999 7154 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 7155 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 149:156823d33999 7156
<> 149:156823d33999 7157 /******************* Bit definition for TIM_ARR register ********************/
<> 149:156823d33999 7158 #define TIM_ARR_ARR_Pos (0U)
<> 149:156823d33999 7159 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 7160 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
<> 149:156823d33999 7161
<> 149:156823d33999 7162 /******************* Bit definition for TIM_CCR1 register *******************/
<> 149:156823d33999 7163 #define TIM_CCR1_CCR1_Pos (0U)
<> 149:156823d33999 7164 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 7165 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 149:156823d33999 7166
<> 149:156823d33999 7167 /******************* Bit definition for TIM_CCR2 register *******************/
<> 149:156823d33999 7168 #define TIM_CCR2_CCR2_Pos (0U)
<> 149:156823d33999 7169 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 7170 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 149:156823d33999 7171
<> 149:156823d33999 7172 /******************* Bit definition for TIM_CCR3 register *******************/
<> 149:156823d33999 7173 #define TIM_CCR3_CCR3_Pos (0U)
<> 149:156823d33999 7174 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 7175 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 149:156823d33999 7176
<> 149:156823d33999 7177 /******************* Bit definition for TIM_CCR4 register *******************/
<> 149:156823d33999 7178 #define TIM_CCR4_CCR4_Pos (0U)
<> 149:156823d33999 7179 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 7180 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 149:156823d33999 7181
<> 149:156823d33999 7182 /******************* Bit definition for TIM_DCR register ********************/
<> 149:156823d33999 7183 #define TIM_DCR_DBA_Pos (0U)
<> 149:156823d33999 7184 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
<> 149:156823d33999 7185 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
<> 149:156823d33999 7186 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7187 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7188 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7189 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7190 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7191
<> 149:156823d33999 7192 #define TIM_DCR_DBL_Pos (8U)
<> 149:156823d33999 7193 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
<> 149:156823d33999 7194 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
<> 149:156823d33999 7195 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7196 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7197 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7198 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7199 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7200
<> 149:156823d33999 7201 /******************* Bit definition for TIM_DMAR register *******************/
<> 149:156823d33999 7202 #define TIM_DMAR_DMAB_Pos (0U)
<> 149:156823d33999 7203 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
<> 149:156823d33999 7204 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 149:156823d33999 7205
<> 149:156823d33999 7206 /******************* Bit definition for TIM_OR register *********************/
<> 149:156823d33999 7207 #define TIM_OR_TI1RMP_Pos (0U)
<> 149:156823d33999 7208 #define TIM_OR_TI1RMP_Msk (0x3U << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */
<> 149:156823d33999 7209 #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
<> 149:156823d33999 7210 #define TIM_OR_TI1RMP_0 (0x1U << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7211 #define TIM_OR_TI1RMP_1 (0x2U << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7212
<> 149:156823d33999 7213 #define TIM_OR_ETR_RMP_Pos (2U)
<> 149:156823d33999 7214 #define TIM_OR_ETR_RMP_Msk (0x1U << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7215 #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
<> 149:156823d33999 7216 #define TIM_OR_TI1_RMP_RI_Pos (3U)
<> 149:156823d33999 7217 #define TIM_OR_TI1_RMP_RI_Msk (0x1U << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7218 #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
<> 149:156823d33999 7219
<> 149:156823d33999 7220 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 7221 #define TIM9_OR_ITR1_RMP_Pos (2U)
<> 149:156823d33999 7222 #define TIM9_OR_ITR1_RMP_Msk (0x1U << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7223 #define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
<> 149:156823d33999 7224
<> 149:156823d33999 7225 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 7226 #define TIM2_OR_ITR1_RMP_Pos (0U)
<> 149:156823d33999 7227 #define TIM2_OR_ITR1_RMP_Msk (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7228 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
<> 149:156823d33999 7229
<> 149:156823d33999 7230 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 7231 #define TIM3_OR_ITR2_RMP_Pos (0U)
<> 149:156823d33999 7232 #define TIM3_OR_ITR2_RMP_Msk (0x1U << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7233 #define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
<> 149:156823d33999 7234
<> 149:156823d33999 7235 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 7236
<> 149:156823d33999 7237 /******************************************************************************/
<> 149:156823d33999 7238 /* */
<> 149:156823d33999 7239 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<> 149:156823d33999 7240 /* */
<> 149:156823d33999 7241 /******************************************************************************/
<> 149:156823d33999 7242
<> 149:156823d33999 7243 /******************* Bit definition for USART_SR register *******************/
<> 149:156823d33999 7244 #define USART_SR_PE_Pos (0U)
<> 149:156823d33999 7245 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7246 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
<> 149:156823d33999 7247 #define USART_SR_FE_Pos (1U)
<> 149:156823d33999 7248 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7249 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
<> 149:156823d33999 7250 #define USART_SR_NE_Pos (2U)
<> 149:156823d33999 7251 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7252 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
<> 149:156823d33999 7253 #define USART_SR_ORE_Pos (3U)
<> 149:156823d33999 7254 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7255 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
<> 149:156823d33999 7256 #define USART_SR_IDLE_Pos (4U)
<> 149:156823d33999 7257 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7258 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
<> 149:156823d33999 7259 #define USART_SR_RXNE_Pos (5U)
<> 149:156823d33999 7260 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7261 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
<> 149:156823d33999 7262 #define USART_SR_TC_Pos (6U)
<> 149:156823d33999 7263 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7264 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
<> 149:156823d33999 7265 #define USART_SR_TXE_Pos (7U)
<> 149:156823d33999 7266 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7267 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
<> 149:156823d33999 7268 #define USART_SR_LBD_Pos (8U)
<> 149:156823d33999 7269 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7270 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
<> 149:156823d33999 7271 #define USART_SR_CTS_Pos (9U)
<> 149:156823d33999 7272 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7273 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
<> 149:156823d33999 7274
<> 149:156823d33999 7275 /******************* Bit definition for USART_DR register *******************/
<> 149:156823d33999 7276 #define USART_DR_DR_Pos (0U)
<> 149:156823d33999 7277 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
<> 149:156823d33999 7278 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
<> 149:156823d33999 7279
<> 149:156823d33999 7280 /****************** Bit definition for USART_BRR register *******************/
<> 149:156823d33999 7281 #define USART_BRR_DIV_FRACTION_Pos (0U)
<> 149:156823d33999 7282 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7283 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
<> 149:156823d33999 7284 #define USART_BRR_DIV_MANTISSA_Pos (4U)
<> 149:156823d33999 7285 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
<> 149:156823d33999 7286 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
<> 149:156823d33999 7287
<> 149:156823d33999 7288 /****************** Bit definition for USART_CR1 register *******************/
<> 149:156823d33999 7289 #define USART_CR1_SBK_Pos (0U)
<> 149:156823d33999 7290 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7291 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
<> 149:156823d33999 7292 #define USART_CR1_RWU_Pos (1U)
<> 149:156823d33999 7293 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7294 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
<> 149:156823d33999 7295 #define USART_CR1_RE_Pos (2U)
<> 149:156823d33999 7296 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7297 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
<> 149:156823d33999 7298 #define USART_CR1_TE_Pos (3U)
<> 149:156823d33999 7299 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7300 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
<> 149:156823d33999 7301 #define USART_CR1_IDLEIE_Pos (4U)
<> 149:156823d33999 7302 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7303 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
<> 149:156823d33999 7304 #define USART_CR1_RXNEIE_Pos (5U)
<> 149:156823d33999 7305 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7306 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
<> 149:156823d33999 7307 #define USART_CR1_TCIE_Pos (6U)
<> 149:156823d33999 7308 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7309 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
<> 149:156823d33999 7310 #define USART_CR1_TXEIE_Pos (7U)
<> 149:156823d33999 7311 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7312 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
<> 149:156823d33999 7313 #define USART_CR1_PEIE_Pos (8U)
<> 149:156823d33999 7314 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7315 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
<> 149:156823d33999 7316 #define USART_CR1_PS_Pos (9U)
<> 149:156823d33999 7317 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7318 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
<> 149:156823d33999 7319 #define USART_CR1_PCE_Pos (10U)
<> 149:156823d33999 7320 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7321 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
<> 149:156823d33999 7322 #define USART_CR1_WAKE_Pos (11U)
<> 149:156823d33999 7323 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7324 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
<> 149:156823d33999 7325 #define USART_CR1_M_Pos (12U)
<> 149:156823d33999 7326 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7327 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
<> 149:156823d33999 7328 #define USART_CR1_UE_Pos (13U)
<> 149:156823d33999 7329 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7330 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
<> 149:156823d33999 7331 #define USART_CR1_OVER8_Pos (15U)
<> 149:156823d33999 7332 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7333 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */
<> 149:156823d33999 7334
<> 149:156823d33999 7335 /****************** Bit definition for USART_CR2 register *******************/
<> 149:156823d33999 7336 #define USART_CR2_ADD_Pos (0U)
<> 149:156823d33999 7337 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7338 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
<> 149:156823d33999 7339 #define USART_CR2_LBDL_Pos (5U)
<> 149:156823d33999 7340 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7341 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
<> 149:156823d33999 7342 #define USART_CR2_LBDIE_Pos (6U)
<> 149:156823d33999 7343 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7344 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
<> 149:156823d33999 7345 #define USART_CR2_LBCL_Pos (8U)
<> 149:156823d33999 7346 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7347 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
<> 149:156823d33999 7348 #define USART_CR2_CPHA_Pos (9U)
<> 149:156823d33999 7349 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7350 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
<> 149:156823d33999 7351 #define USART_CR2_CPOL_Pos (10U)
<> 149:156823d33999 7352 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7353 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
<> 149:156823d33999 7354 #define USART_CR2_CLKEN_Pos (11U)
<> 149:156823d33999 7355 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7356 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
<> 149:156823d33999 7357
<> 149:156823d33999 7358 #define USART_CR2_STOP_Pos (12U)
<> 149:156823d33999 7359 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7360 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
<> 149:156823d33999 7361 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7362 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7363
<> 149:156823d33999 7364 #define USART_CR2_LINEN_Pos (14U)
<> 149:156823d33999 7365 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7366 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
<> 149:156823d33999 7367
<> 149:156823d33999 7368 /****************** Bit definition for USART_CR3 register *******************/
<> 149:156823d33999 7369 #define USART_CR3_EIE_Pos (0U)
<> 149:156823d33999 7370 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7371 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
<> 149:156823d33999 7372 #define USART_CR3_IREN_Pos (1U)
<> 149:156823d33999 7373 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7374 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
<> 149:156823d33999 7375 #define USART_CR3_IRLP_Pos (2U)
<> 149:156823d33999 7376 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7377 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
<> 149:156823d33999 7378 #define USART_CR3_HDSEL_Pos (3U)
<> 149:156823d33999 7379 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7380 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
<> 149:156823d33999 7381 #define USART_CR3_NACK_Pos (4U)
<> 149:156823d33999 7382 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7383 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
<> 149:156823d33999 7384 #define USART_CR3_SCEN_Pos (5U)
<> 149:156823d33999 7385 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7386 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
<> 149:156823d33999 7387 #define USART_CR3_DMAR_Pos (6U)
<> 149:156823d33999 7388 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7389 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
<> 149:156823d33999 7390 #define USART_CR3_DMAT_Pos (7U)
<> 149:156823d33999 7391 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7392 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
<> 149:156823d33999 7393 #define USART_CR3_RTSE_Pos (8U)
<> 149:156823d33999 7394 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7395 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
<> 149:156823d33999 7396 #define USART_CR3_CTSE_Pos (9U)
<> 149:156823d33999 7397 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7398 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
<> 149:156823d33999 7399 #define USART_CR3_CTSIE_Pos (10U)
<> 149:156823d33999 7400 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7401 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
<> 149:156823d33999 7402 #define USART_CR3_ONEBIT_Pos (11U)
<> 149:156823d33999 7403 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7404 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
<> 149:156823d33999 7405
<> 149:156823d33999 7406 /****************** Bit definition for USART_GTPR register ******************/
<> 149:156823d33999 7407 #define USART_GTPR_PSC_Pos (0U)
<> 149:156823d33999 7408 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
<> 149:156823d33999 7409 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
<> 149:156823d33999 7410 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7411 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7412 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7413 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7414 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7415 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7416 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7417 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7418
<> 149:156823d33999 7419 #define USART_GTPR_GT_Pos (8U)
<> 149:156823d33999 7420 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
<> 149:156823d33999 7421 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
<> 149:156823d33999 7422
<> 149:156823d33999 7423 /******************************************************************************/
<> 149:156823d33999 7424 /* */
<> 149:156823d33999 7425 /* Universal Serial Bus (USB) */
<> 149:156823d33999 7426 /* */
<> 149:156823d33999 7427 /******************************************************************************/
<> 149:156823d33999 7428
<> 149:156823d33999 7429 /*!<Endpoint-specific registers */
<> 149:156823d33999 7430
<> 149:156823d33999 7431 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
<> 149:156823d33999 7432 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */
<> 149:156823d33999 7433 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */
<> 149:156823d33999 7434 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */
<> 149:156823d33999 7435 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */
<> 149:156823d33999 7436 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */
<> 149:156823d33999 7437 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */
<> 149:156823d33999 7438 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */
<> 149:156823d33999 7439
<> 149:156823d33999 7440 /* bit positions */
<> 149:156823d33999 7441 #define USB_EP_CTR_RX_Pos (15U)
<> 149:156823d33999 7442 #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7443 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
<> 149:156823d33999 7444 #define USB_EP_DTOG_RX_Pos (14U)
<> 149:156823d33999 7445 #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7446 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
<> 149:156823d33999 7447 #define USB_EPRX_STAT_Pos (12U)
<> 149:156823d33999 7448 #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7449 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
<> 149:156823d33999 7450 #define USB_EP_SETUP_Pos (11U)
<> 149:156823d33999 7451 #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7452 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
<> 149:156823d33999 7453 #define USB_EP_T_FIELD_Pos (9U)
<> 149:156823d33999 7454 #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7455 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
<> 149:156823d33999 7456 #define USB_EP_KIND_Pos (8U)
<> 149:156823d33999 7457 #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7458 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
<> 149:156823d33999 7459 #define USB_EP_CTR_TX_Pos (7U)
<> 149:156823d33999 7460 #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7461 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
<> 149:156823d33999 7462 #define USB_EP_DTOG_TX_Pos (6U)
<> 149:156823d33999 7463 #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7464 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
<> 149:156823d33999 7465 #define USB_EPTX_STAT_Pos (4U)
<> 149:156823d33999 7466 #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7467 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
<> 149:156823d33999 7468 #define USB_EPADDR_FIELD_Pos (0U)
<> 149:156823d33999 7469 #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7470 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
<> 149:156823d33999 7471
<> 149:156823d33999 7472 /* EndPoint REGister MASK (no toggle fields) */
<> 149:156823d33999 7473 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
<> 149:156823d33999 7474 /*!< EP_TYPE[1:0] EndPoint TYPE */
<> 149:156823d33999 7475 #define USB_EP_TYPE_MASK_Pos (9U)
<> 149:156823d33999 7476 #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7477 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
<> 149:156823d33999 7478 #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */
<> 149:156823d33999 7479 #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */
<> 149:156823d33999 7480 #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */
<> 149:156823d33999 7481 #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */
<> 149:156823d33999 7482 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
<> 149:156823d33999 7483
<> 149:156823d33999 7484 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
<> 149:156823d33999 7485 /*!< STAT_TX[1:0] STATus for TX transfer */
<> 149:156823d33999 7486 #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */
<> 149:156823d33999 7487 #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */
<> 149:156823d33999 7488 #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */
<> 149:156823d33999 7489 #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */
<> 149:156823d33999 7490 #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */
<> 149:156823d33999 7491 #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */
<> 149:156823d33999 7492 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
<> 149:156823d33999 7493 /*!< STAT_RX[1:0] STATus for RX transfer */
<> 149:156823d33999 7494 #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */
<> 149:156823d33999 7495 #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */
<> 149:156823d33999 7496 #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */
<> 149:156823d33999 7497 #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */
<> 149:156823d33999 7498 #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 149:156823d33999 7499 #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 149:156823d33999 7500 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
<> 149:156823d33999 7501
<> 149:156823d33999 7502 /******************* Bit definition for USB_EP0R register *******************/
<> 149:156823d33999 7503 #define USB_EP0R_EA_Pos (0U)
<> 149:156823d33999 7504 #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7505 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7506
<> 149:156823d33999 7507 #define USB_EP0R_STAT_TX_Pos (4U)
<> 149:156823d33999 7508 #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7509 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7510 #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7511 #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7512
<> 149:156823d33999 7513 #define USB_EP0R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7514 #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7515 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7516 #define USB_EP0R_CTR_TX_Pos (7U)
<> 149:156823d33999 7517 #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7518 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7519 #define USB_EP0R_EP_KIND_Pos (8U)
<> 149:156823d33999 7520 #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7521 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7522
<> 149:156823d33999 7523 #define USB_EP0R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7524 #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7525 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7526 #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7527 #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7528
<> 149:156823d33999 7529 #define USB_EP0R_SETUP_Pos (11U)
<> 149:156823d33999 7530 #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7531 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7532
<> 149:156823d33999 7533 #define USB_EP0R_STAT_RX_Pos (12U)
<> 149:156823d33999 7534 #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7535 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7536 #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7537 #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7538
<> 149:156823d33999 7539 #define USB_EP0R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7540 #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7541 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7542 #define USB_EP0R_CTR_RX_Pos (15U)
<> 149:156823d33999 7543 #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7544 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7545
<> 149:156823d33999 7546 /******************* Bit definition for USB_EP1R register *******************/
<> 149:156823d33999 7547 #define USB_EP1R_EA_Pos (0U)
<> 149:156823d33999 7548 #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7549 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7550
<> 149:156823d33999 7551 #define USB_EP1R_STAT_TX_Pos (4U)
<> 149:156823d33999 7552 #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7553 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7554 #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7555 #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7556
<> 149:156823d33999 7557 #define USB_EP1R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7558 #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7559 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7560 #define USB_EP1R_CTR_TX_Pos (7U)
<> 149:156823d33999 7561 #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7562 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7563 #define USB_EP1R_EP_KIND_Pos (8U)
<> 149:156823d33999 7564 #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7565 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7566
<> 149:156823d33999 7567 #define USB_EP1R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7568 #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7569 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7570 #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7571 #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7572
<> 149:156823d33999 7573 #define USB_EP1R_SETUP_Pos (11U)
<> 149:156823d33999 7574 #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7575 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7576
<> 149:156823d33999 7577 #define USB_EP1R_STAT_RX_Pos (12U)
<> 149:156823d33999 7578 #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7579 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7580 #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7581 #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7582
<> 149:156823d33999 7583 #define USB_EP1R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7584 #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7585 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7586 #define USB_EP1R_CTR_RX_Pos (15U)
<> 149:156823d33999 7587 #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7588 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7589
<> 149:156823d33999 7590 /******************* Bit definition for USB_EP2R register *******************/
<> 149:156823d33999 7591 #define USB_EP2R_EA_Pos (0U)
<> 149:156823d33999 7592 #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7593 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7594
<> 149:156823d33999 7595 #define USB_EP2R_STAT_TX_Pos (4U)
<> 149:156823d33999 7596 #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7597 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7598 #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7599 #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7600
<> 149:156823d33999 7601 #define USB_EP2R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7602 #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7603 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7604 #define USB_EP2R_CTR_TX_Pos (7U)
<> 149:156823d33999 7605 #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7606 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7607 #define USB_EP2R_EP_KIND_Pos (8U)
<> 149:156823d33999 7608 #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7609 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7610
<> 149:156823d33999 7611 #define USB_EP2R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7612 #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7613 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7614 #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7615 #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7616
<> 149:156823d33999 7617 #define USB_EP2R_SETUP_Pos (11U)
<> 149:156823d33999 7618 #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7619 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7620
<> 149:156823d33999 7621 #define USB_EP2R_STAT_RX_Pos (12U)
<> 149:156823d33999 7622 #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7623 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7624 #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7625 #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7626
<> 149:156823d33999 7627 #define USB_EP2R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7628 #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7629 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7630 #define USB_EP2R_CTR_RX_Pos (15U)
<> 149:156823d33999 7631 #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7632 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7633
<> 149:156823d33999 7634 /******************* Bit definition for USB_EP3R register *******************/
<> 149:156823d33999 7635 #define USB_EP3R_EA_Pos (0U)
<> 149:156823d33999 7636 #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7637 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7638
<> 149:156823d33999 7639 #define USB_EP3R_STAT_TX_Pos (4U)
<> 149:156823d33999 7640 #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7641 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7642 #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7643 #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7644
<> 149:156823d33999 7645 #define USB_EP3R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7646 #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7647 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7648 #define USB_EP3R_CTR_TX_Pos (7U)
<> 149:156823d33999 7649 #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7650 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7651 #define USB_EP3R_EP_KIND_Pos (8U)
<> 149:156823d33999 7652 #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7653 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7654
<> 149:156823d33999 7655 #define USB_EP3R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7656 #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7657 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7658 #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7659 #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7660
<> 149:156823d33999 7661 #define USB_EP3R_SETUP_Pos (11U)
<> 149:156823d33999 7662 #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7663 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7664
<> 149:156823d33999 7665 #define USB_EP3R_STAT_RX_Pos (12U)
<> 149:156823d33999 7666 #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7667 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7668 #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7669 #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7670
<> 149:156823d33999 7671 #define USB_EP3R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7672 #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7673 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7674 #define USB_EP3R_CTR_RX_Pos (15U)
<> 149:156823d33999 7675 #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7676 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7677
<> 149:156823d33999 7678 /******************* Bit definition for USB_EP4R register *******************/
<> 149:156823d33999 7679 #define USB_EP4R_EA_Pos (0U)
<> 149:156823d33999 7680 #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7681 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7682
<> 149:156823d33999 7683 #define USB_EP4R_STAT_TX_Pos (4U)
<> 149:156823d33999 7684 #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7685 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7686 #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7687 #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7688
<> 149:156823d33999 7689 #define USB_EP4R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7690 #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7691 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7692 #define USB_EP4R_CTR_TX_Pos (7U)
<> 149:156823d33999 7693 #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7694 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7695 #define USB_EP4R_EP_KIND_Pos (8U)
<> 149:156823d33999 7696 #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7697 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7698
<> 149:156823d33999 7699 #define USB_EP4R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7700 #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7701 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7702 #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7703 #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7704
<> 149:156823d33999 7705 #define USB_EP4R_SETUP_Pos (11U)
<> 149:156823d33999 7706 #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7707 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7708
<> 149:156823d33999 7709 #define USB_EP4R_STAT_RX_Pos (12U)
<> 149:156823d33999 7710 #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7711 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7712 #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7713 #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7714
<> 149:156823d33999 7715 #define USB_EP4R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7716 #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7717 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7718 #define USB_EP4R_CTR_RX_Pos (15U)
<> 149:156823d33999 7719 #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7720 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7721
<> 149:156823d33999 7722 /******************* Bit definition for USB_EP5R register *******************/
<> 149:156823d33999 7723 #define USB_EP5R_EA_Pos (0U)
<> 149:156823d33999 7724 #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7725 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7726
<> 149:156823d33999 7727 #define USB_EP5R_STAT_TX_Pos (4U)
<> 149:156823d33999 7728 #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7729 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7730 #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7731 #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7732
<> 149:156823d33999 7733 #define USB_EP5R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7734 #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7735 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7736 #define USB_EP5R_CTR_TX_Pos (7U)
<> 149:156823d33999 7737 #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7738 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7739 #define USB_EP5R_EP_KIND_Pos (8U)
<> 149:156823d33999 7740 #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7741 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7742
<> 149:156823d33999 7743 #define USB_EP5R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7744 #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7745 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7746 #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7747 #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7748
<> 149:156823d33999 7749 #define USB_EP5R_SETUP_Pos (11U)
<> 149:156823d33999 7750 #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7751 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7752
<> 149:156823d33999 7753 #define USB_EP5R_STAT_RX_Pos (12U)
<> 149:156823d33999 7754 #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7755 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7756 #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7757 #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7758
<> 149:156823d33999 7759 #define USB_EP5R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7760 #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7761 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7762 #define USB_EP5R_CTR_RX_Pos (15U)
<> 149:156823d33999 7763 #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7764 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7765
<> 149:156823d33999 7766 /******************* Bit definition for USB_EP6R register *******************/
<> 149:156823d33999 7767 #define USB_EP6R_EA_Pos (0U)
<> 149:156823d33999 7768 #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7769 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7770
<> 149:156823d33999 7771 #define USB_EP6R_STAT_TX_Pos (4U)
<> 149:156823d33999 7772 #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7773 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7774 #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7775 #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7776
<> 149:156823d33999 7777 #define USB_EP6R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7778 #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7779 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7780 #define USB_EP6R_CTR_TX_Pos (7U)
<> 149:156823d33999 7781 #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7782 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7783 #define USB_EP6R_EP_KIND_Pos (8U)
<> 149:156823d33999 7784 #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7785 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7786
<> 149:156823d33999 7787 #define USB_EP6R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7788 #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7789 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7790 #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7791 #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7792
<> 149:156823d33999 7793 #define USB_EP6R_SETUP_Pos (11U)
<> 149:156823d33999 7794 #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7795 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7796
<> 149:156823d33999 7797 #define USB_EP6R_STAT_RX_Pos (12U)
<> 149:156823d33999 7798 #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7799 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7800 #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7801 #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7802
<> 149:156823d33999 7803 #define USB_EP6R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7804 #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7805 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7806 #define USB_EP6R_CTR_RX_Pos (15U)
<> 149:156823d33999 7807 #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7808 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7809
<> 149:156823d33999 7810 /******************* Bit definition for USB_EP7R register *******************/
<> 149:156823d33999 7811 #define USB_EP7R_EA_Pos (0U)
<> 149:156823d33999 7812 #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7813 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */
<> 149:156823d33999 7814
<> 149:156823d33999 7815 #define USB_EP7R_STAT_TX_Pos (4U)
<> 149:156823d33999 7816 #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
<> 149:156823d33999 7817 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 149:156823d33999 7818 #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7819 #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7820
<> 149:156823d33999 7821 #define USB_EP7R_DTOG_TX_Pos (6U)
<> 149:156823d33999 7822 #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7823 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 149:156823d33999 7824 #define USB_EP7R_CTR_TX_Pos (7U)
<> 149:156823d33999 7825 #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7826 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 149:156823d33999 7827 #define USB_EP7R_EP_KIND_Pos (8U)
<> 149:156823d33999 7828 #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7829 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */
<> 149:156823d33999 7830
<> 149:156823d33999 7831 #define USB_EP7R_EP_TYPE_Pos (9U)
<> 149:156823d33999 7832 #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 149:156823d33999 7833 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 149:156823d33999 7834 #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7835 #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7836
<> 149:156823d33999 7837 #define USB_EP7R_SETUP_Pos (11U)
<> 149:156823d33999 7838 #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7839 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */
<> 149:156823d33999 7840
<> 149:156823d33999 7841 #define USB_EP7R_STAT_RX_Pos (12U)
<> 149:156823d33999 7842 #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
<> 149:156823d33999 7843 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 149:156823d33999 7844 #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7845 #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7846
<> 149:156823d33999 7847 #define USB_EP7R_DTOG_RX_Pos (14U)
<> 149:156823d33999 7848 #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7849 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 149:156823d33999 7850 #define USB_EP7R_CTR_RX_Pos (15U)
<> 149:156823d33999 7851 #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7852 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 149:156823d33999 7853
<> 149:156823d33999 7854 /*!<Common registers */
<> 149:156823d33999 7855
<> 149:156823d33999 7856 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
<> 149:156823d33999 7857 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
<> 149:156823d33999 7858 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
<> 149:156823d33999 7859 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
<> 149:156823d33999 7860 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
<> 149:156823d33999 7861
<> 149:156823d33999 7862
<> 149:156823d33999 7863
<> 149:156823d33999 7864 /******************* Bit definition for USB_CNTR register *******************/
<> 149:156823d33999 7865 #define USB_CNTR_FRES_Pos (0U)
<> 149:156823d33999 7866 #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7867 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */
<> 149:156823d33999 7868 #define USB_CNTR_PDWN_Pos (1U)
<> 149:156823d33999 7869 #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7870 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */
<> 149:156823d33999 7871 #define USB_CNTR_LPMODE_Pos (2U)
<> 149:156823d33999 7872 #define USB_CNTR_LPMODE_Msk (0x1U << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7873 #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */
<> 149:156823d33999 7874 #define USB_CNTR_FSUSP_Pos (3U)
<> 149:156823d33999 7875 #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7876 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */
<> 149:156823d33999 7877 #define USB_CNTR_RESUME_Pos (4U)
<> 149:156823d33999 7878 #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7879 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */
<> 149:156823d33999 7880 #define USB_CNTR_ESOFM_Pos (8U)
<> 149:156823d33999 7881 #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7882 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */
<> 149:156823d33999 7883 #define USB_CNTR_SOFM_Pos (9U)
<> 149:156823d33999 7884 #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7885 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */
<> 149:156823d33999 7886 #define USB_CNTR_RESETM_Pos (10U)
<> 149:156823d33999 7887 #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7888 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */
<> 149:156823d33999 7889 #define USB_CNTR_SUSPM_Pos (11U)
<> 149:156823d33999 7890 #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7891 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */
<> 149:156823d33999 7892 #define USB_CNTR_WKUPM_Pos (12U)
<> 149:156823d33999 7893 #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7894 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */
<> 149:156823d33999 7895 #define USB_CNTR_ERRM_Pos (13U)
<> 149:156823d33999 7896 #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7897 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */
<> 149:156823d33999 7898 #define USB_CNTR_PMAOVRM_Pos (14U)
<> 149:156823d33999 7899 #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7900 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */
<> 149:156823d33999 7901 #define USB_CNTR_CTRM_Pos (15U)
<> 149:156823d33999 7902 #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7903 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */
<> 149:156823d33999 7904
<> 149:156823d33999 7905 /******************* Bit definition for USB_ISTR register *******************/
<> 149:156823d33999 7906 #define USB_ISTR_EP_ID_Pos (0U)
<> 149:156823d33999 7907 #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
<> 149:156823d33999 7908 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */
<> 149:156823d33999 7909 #define USB_ISTR_DIR_Pos (4U)
<> 149:156823d33999 7910 #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7911 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */
<> 149:156823d33999 7912 #define USB_ISTR_ESOF_Pos (8U)
<> 149:156823d33999 7913 #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
<> 149:156823d33999 7914 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */
<> 149:156823d33999 7915 #define USB_ISTR_SOF_Pos (9U)
<> 149:156823d33999 7916 #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
<> 149:156823d33999 7917 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */
<> 149:156823d33999 7918 #define USB_ISTR_RESET_Pos (10U)
<> 149:156823d33999 7919 #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
<> 149:156823d33999 7920 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */
<> 149:156823d33999 7921 #define USB_ISTR_SUSP_Pos (11U)
<> 149:156823d33999 7922 #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
<> 149:156823d33999 7923 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */
<> 149:156823d33999 7924 #define USB_ISTR_WKUP_Pos (12U)
<> 149:156823d33999 7925 #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
<> 149:156823d33999 7926 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */
<> 149:156823d33999 7927 #define USB_ISTR_ERR_Pos (13U)
<> 149:156823d33999 7928 #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7929 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */
<> 149:156823d33999 7930 #define USB_ISTR_PMAOVR_Pos (14U)
<> 149:156823d33999 7931 #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7932 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */
<> 149:156823d33999 7933 #define USB_ISTR_CTR_Pos (15U)
<> 149:156823d33999 7934 #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7935 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */
<> 149:156823d33999 7936
<> 149:156823d33999 7937 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
<> 149:156823d33999 7938 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
<> 149:156823d33999 7939 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
<> 149:156823d33999 7940 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
<> 149:156823d33999 7941 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
<> 149:156823d33999 7942 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
<> 149:156823d33999 7943 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
<> 149:156823d33999 7944 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
<> 149:156823d33999 7945
<> 149:156823d33999 7946
<> 149:156823d33999 7947 /******************* Bit definition for USB_FNR register ********************/
<> 149:156823d33999 7948 #define USB_FNR_FN_Pos (0U)
<> 149:156823d33999 7949 #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
<> 149:156823d33999 7950 #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */
<> 149:156823d33999 7951 #define USB_FNR_LSOF_Pos (11U)
<> 149:156823d33999 7952 #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
<> 149:156823d33999 7953 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */
<> 149:156823d33999 7954 #define USB_FNR_LCK_Pos (13U)
<> 149:156823d33999 7955 #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 7956 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */
<> 149:156823d33999 7957 #define USB_FNR_RXDM_Pos (14U)
<> 149:156823d33999 7958 #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
<> 149:156823d33999 7959 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */
<> 149:156823d33999 7960 #define USB_FNR_RXDP_Pos (15U)
<> 149:156823d33999 7961 #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
<> 149:156823d33999 7962 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */
<> 149:156823d33999 7963
<> 149:156823d33999 7964 /****************** Bit definition for USB_DADDR register *******************/
<> 149:156823d33999 7965 #define USB_DADDR_ADD_Pos (0U)
<> 149:156823d33999 7966 #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
<> 149:156823d33999 7967 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */
<> 149:156823d33999 7968 #define USB_DADDR_ADD0_Pos (0U)
<> 149:156823d33999 7969 #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
<> 149:156823d33999 7970 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */
<> 149:156823d33999 7971 #define USB_DADDR_ADD1_Pos (1U)
<> 149:156823d33999 7972 #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
<> 149:156823d33999 7973 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */
<> 149:156823d33999 7974 #define USB_DADDR_ADD2_Pos (2U)
<> 149:156823d33999 7975 #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
<> 149:156823d33999 7976 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */
<> 149:156823d33999 7977 #define USB_DADDR_ADD3_Pos (3U)
<> 149:156823d33999 7978 #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
<> 149:156823d33999 7979 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */
<> 149:156823d33999 7980 #define USB_DADDR_ADD4_Pos (4U)
<> 149:156823d33999 7981 #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
<> 149:156823d33999 7982 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */
<> 149:156823d33999 7983 #define USB_DADDR_ADD5_Pos (5U)
<> 149:156823d33999 7984 #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
<> 149:156823d33999 7985 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */
<> 149:156823d33999 7986 #define USB_DADDR_ADD6_Pos (6U)
<> 149:156823d33999 7987 #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
<> 149:156823d33999 7988 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */
<> 149:156823d33999 7989
<> 149:156823d33999 7990 #define USB_DADDR_EF_Pos (7U)
<> 149:156823d33999 7991 #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
<> 149:156823d33999 7992 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */
<> 149:156823d33999 7993
<> 149:156823d33999 7994 /****************** Bit definition for USB_BTABLE register ******************/
<> 149:156823d33999 7995 #define USB_BTABLE_BTABLE_Pos (3U)
<> 149:156823d33999 7996 #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
<> 149:156823d33999 7997 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */
<> 149:156823d33999 7998
<> 149:156823d33999 7999 /*!< Buffer descriptor table */
<> 149:156823d33999 8000 /***************** Bit definition for USB_ADDR0_TX register *****************/
<> 149:156823d33999 8001 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
<> 149:156823d33999 8002 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8003 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
<> 149:156823d33999 8004
<> 149:156823d33999 8005 /***************** Bit definition for USB_ADDR1_TX register *****************/
<> 149:156823d33999 8006 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
<> 149:156823d33999 8007 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8008 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
<> 149:156823d33999 8009
<> 149:156823d33999 8010 /***************** Bit definition for USB_ADDR2_TX register *****************/
<> 149:156823d33999 8011 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
<> 149:156823d33999 8012 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8013 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
<> 149:156823d33999 8014
<> 149:156823d33999 8015 /***************** Bit definition for USB_ADDR3_TX register *****************/
<> 149:156823d33999 8016 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
<> 149:156823d33999 8017 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8018 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
<> 149:156823d33999 8019
<> 149:156823d33999 8020 /***************** Bit definition for USB_ADDR4_TX register *****************/
<> 149:156823d33999 8021 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
<> 149:156823d33999 8022 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8023 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
<> 149:156823d33999 8024
<> 149:156823d33999 8025 /***************** Bit definition for USB_ADDR5_TX register *****************/
<> 149:156823d33999 8026 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
<> 149:156823d33999 8027 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8028 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
<> 149:156823d33999 8029
<> 149:156823d33999 8030 /***************** Bit definition for USB_ADDR6_TX register *****************/
<> 149:156823d33999 8031 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
<> 149:156823d33999 8032 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8033 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
<> 149:156823d33999 8034
<> 149:156823d33999 8035 /***************** Bit definition for USB_ADDR7_TX register *****************/
<> 149:156823d33999 8036 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
<> 149:156823d33999 8037 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8038 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
<> 149:156823d33999 8039
<> 149:156823d33999 8040 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 8041
<> 149:156823d33999 8042 /***************** Bit definition for USB_COUNT0_TX register ****************/
<> 149:156823d33999 8043 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
<> 149:156823d33999 8044 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8045 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
<> 149:156823d33999 8046
<> 149:156823d33999 8047 /***************** Bit definition for USB_COUNT1_TX register ****************/
<> 149:156823d33999 8048 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
<> 149:156823d33999 8049 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8050 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
<> 149:156823d33999 8051
<> 149:156823d33999 8052 /***************** Bit definition for USB_COUNT2_TX register ****************/
<> 149:156823d33999 8053 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
<> 149:156823d33999 8054 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8055 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
<> 149:156823d33999 8056
<> 149:156823d33999 8057 /***************** Bit definition for USB_COUNT3_TX register ****************/
<> 149:156823d33999 8058 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
<> 149:156823d33999 8059 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8060 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
<> 149:156823d33999 8061
<> 149:156823d33999 8062 /***************** Bit definition for USB_COUNT4_TX register ****************/
<> 149:156823d33999 8063 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
<> 149:156823d33999 8064 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8065 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
<> 149:156823d33999 8066
<> 149:156823d33999 8067 /***************** Bit definition for USB_COUNT5_TX register ****************/
<> 149:156823d33999 8068 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
<> 149:156823d33999 8069 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8070 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
<> 149:156823d33999 8071
<> 149:156823d33999 8072 /***************** Bit definition for USB_COUNT6_TX register ****************/
<> 149:156823d33999 8073 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
<> 149:156823d33999 8074 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8075 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
<> 149:156823d33999 8076
<> 149:156823d33999 8077 /***************** Bit definition for USB_COUNT7_TX register ****************/
<> 149:156823d33999 8078 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
<> 149:156823d33999 8079 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8080 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
<> 149:156823d33999 8081
<> 149:156823d33999 8082 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 8083
<> 149:156823d33999 8084 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
<> 149:156823d33999 8085 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
<> 149:156823d33999 8086
<> 149:156823d33999 8087 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
<> 149:156823d33999 8088 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
<> 149:156823d33999 8089
<> 149:156823d33999 8090 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
<> 149:156823d33999 8091 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
<> 149:156823d33999 8092
<> 149:156823d33999 8093 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
<> 149:156823d33999 8094 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
<> 149:156823d33999 8095
<> 149:156823d33999 8096 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
<> 149:156823d33999 8097 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
<> 149:156823d33999 8098
<> 149:156823d33999 8099 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
<> 149:156823d33999 8100 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
<> 149:156823d33999 8101
<> 149:156823d33999 8102 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
<> 149:156823d33999 8103 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /*!< Transmission Byte Count 3 (low) */
<> 149:156823d33999 8104
<> 149:156823d33999 8105 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
<> 149:156823d33999 8106 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /*!< Transmission Byte Count 3 (high) */
<> 149:156823d33999 8107
<> 149:156823d33999 8108 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
<> 149:156823d33999 8109 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
<> 149:156823d33999 8110
<> 149:156823d33999 8111 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
<> 149:156823d33999 8112 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
<> 149:156823d33999 8113
<> 149:156823d33999 8114 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
<> 149:156823d33999 8115 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
<> 149:156823d33999 8116
<> 149:156823d33999 8117 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
<> 149:156823d33999 8118 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
<> 149:156823d33999 8119
<> 149:156823d33999 8120 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
<> 149:156823d33999 8121 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
<> 149:156823d33999 8122
<> 149:156823d33999 8123 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
<> 149:156823d33999 8124 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
<> 149:156823d33999 8125
<> 149:156823d33999 8126 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
<> 149:156823d33999 8127 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
<> 149:156823d33999 8128
<> 149:156823d33999 8129 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
<> 149:156823d33999 8130 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
<> 149:156823d33999 8131
<> 149:156823d33999 8132 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 8133
<> 149:156823d33999 8134 /***************** Bit definition for USB_ADDR0_RX register *****************/
<> 149:156823d33999 8135 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
<> 149:156823d33999 8136 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8137 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
<> 149:156823d33999 8138
<> 149:156823d33999 8139 /***************** Bit definition for USB_ADDR1_RX register *****************/
<> 149:156823d33999 8140 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
<> 149:156823d33999 8141 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8142 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
<> 149:156823d33999 8143
<> 149:156823d33999 8144 /***************** Bit definition for USB_ADDR2_RX register *****************/
<> 149:156823d33999 8145 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
<> 149:156823d33999 8146 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8147 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
<> 149:156823d33999 8148
<> 149:156823d33999 8149 /***************** Bit definition for USB_ADDR3_RX register *****************/
<> 149:156823d33999 8150 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
<> 149:156823d33999 8151 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8152 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
<> 149:156823d33999 8153
<> 149:156823d33999 8154 /***************** Bit definition for USB_ADDR4_RX register *****************/
<> 149:156823d33999 8155 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
<> 149:156823d33999 8156 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8157 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
<> 149:156823d33999 8158
<> 149:156823d33999 8159 /***************** Bit definition for USB_ADDR5_RX register *****************/
<> 149:156823d33999 8160 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
<> 149:156823d33999 8161 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8162 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
<> 149:156823d33999 8163
<> 149:156823d33999 8164 /***************** Bit definition for USB_ADDR6_RX register *****************/
<> 149:156823d33999 8165 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
<> 149:156823d33999 8166 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8167 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
<> 149:156823d33999 8168
<> 149:156823d33999 8169 /***************** Bit definition for USB_ADDR7_RX register *****************/
<> 149:156823d33999 8170 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
<> 149:156823d33999 8171 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
<> 149:156823d33999 8172 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
<> 149:156823d33999 8173
<> 149:156823d33999 8174 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 8175
<> 149:156823d33999 8176 /***************** Bit definition for USB_COUNT0_RX register ****************/
<> 149:156823d33999 8177 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
<> 149:156823d33999 8178 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8179 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8180
<> 149:156823d33999 8181 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8182 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8183 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8184 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8185 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8186 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8187 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8188 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8189
<> 149:156823d33999 8190 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8191 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8192 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8193
<> 149:156823d33999 8194 /***************** Bit definition for USB_COUNT1_RX register ****************/
<> 149:156823d33999 8195 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
<> 149:156823d33999 8196 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8197 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8198
<> 149:156823d33999 8199 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8200 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8201 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8202 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8203 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8204 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8205 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8206 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8207
<> 149:156823d33999 8208 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8209 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8210 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8211
<> 149:156823d33999 8212 /***************** Bit definition for USB_COUNT2_RX register ****************/
<> 149:156823d33999 8213 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
<> 149:156823d33999 8214 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8215 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8216
<> 149:156823d33999 8217 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8218 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8219 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8220 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8221 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8222 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8223 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8224 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8225
<> 149:156823d33999 8226 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8227 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8228 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8229
<> 149:156823d33999 8230 /***************** Bit definition for USB_COUNT3_RX register ****************/
<> 149:156823d33999 8231 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
<> 149:156823d33999 8232 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8233 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8234
<> 149:156823d33999 8235 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8236 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8237 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8238 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8239 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8240 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8241 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8242 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8243
<> 149:156823d33999 8244 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8245 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8246 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8247
<> 149:156823d33999 8248 /***************** Bit definition for USB_COUNT4_RX register ****************/
<> 149:156823d33999 8249 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
<> 149:156823d33999 8250 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8251 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8252
<> 149:156823d33999 8253 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8254 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8255 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8256 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8257 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8258 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8259 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8260 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8261
<> 149:156823d33999 8262 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8263 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8264 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8265
<> 149:156823d33999 8266 /***************** Bit definition for USB_COUNT5_RX register ****************/
<> 149:156823d33999 8267 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
<> 149:156823d33999 8268 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8269 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8270
<> 149:156823d33999 8271 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8272 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8273 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8274 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8275 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8276 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8277 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8278 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8279
<> 149:156823d33999 8280 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8281 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8282 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8283
<> 149:156823d33999 8284 /***************** Bit definition for USB_COUNT6_RX register ****************/
<> 149:156823d33999 8285 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
<> 149:156823d33999 8286 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8287 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8288
<> 149:156823d33999 8289 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8290 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8291 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8292 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8293 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8294 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8295 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8296 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8297
<> 149:156823d33999 8298 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8299 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8300 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8301
<> 149:156823d33999 8302 /***************** Bit definition for USB_COUNT7_RX register ****************/
<> 149:156823d33999 8303 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
<> 149:156823d33999 8304 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
<> 149:156823d33999 8305 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
<> 149:156823d33999 8306
<> 149:156823d33999 8307 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
<> 149:156823d33999 8308 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 149:156823d33999 8309 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 149:156823d33999 8310 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8311 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8312 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8313 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8314 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8315
<> 149:156823d33999 8316 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
<> 149:156823d33999 8317 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8318 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 149:156823d33999 8319
<> 149:156823d33999 8320 /*----------------------------------------------------------------------------*/
<> 149:156823d33999 8321
<> 149:156823d33999 8322 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
<> 149:156823d33999 8323 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8324
<> 149:156823d33999 8325 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8326 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8327 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8328 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8329 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8330 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8331
<> 149:156823d33999 8332 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8333
<> 149:156823d33999 8334 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
<> 149:156823d33999 8335 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8336
<> 149:156823d33999 8337 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8338 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
<> 149:156823d33999 8339 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8340 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8341 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8342 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8343
<> 149:156823d33999 8344 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8345
<> 149:156823d33999 8346 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
<> 149:156823d33999 8347 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8348
<> 149:156823d33999 8349 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8350 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8351 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8352 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8353 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8354 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8355
<> 149:156823d33999 8356 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8357
<> 149:156823d33999 8358 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
<> 149:156823d33999 8359 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8360
<> 149:156823d33999 8361 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8362 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 149:156823d33999 8363 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8364 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8365 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8366 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8367
<> 149:156823d33999 8368 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8369
<> 149:156823d33999 8370 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
<> 149:156823d33999 8371 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8372
<> 149:156823d33999 8373 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8374 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8375 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8376 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8377 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8378 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8379
<> 149:156823d33999 8380 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8381
<> 149:156823d33999 8382 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
<> 149:156823d33999 8383 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8384
<> 149:156823d33999 8385 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8386 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 149:156823d33999 8387 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8388 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8389 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8390 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8391
<> 149:156823d33999 8392 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8393
<> 149:156823d33999 8394 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
<> 149:156823d33999 8395 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8396
<> 149:156823d33999 8397 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8398 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8399 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8400 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8401 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8402 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8403
<> 149:156823d33999 8404 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8405
<> 149:156823d33999 8406 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
<> 149:156823d33999 8407 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8408
<> 149:156823d33999 8409 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8410 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 149:156823d33999 8411 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8412 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8413 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8414 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8415
<> 149:156823d33999 8416 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8417
<> 149:156823d33999 8418 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
<> 149:156823d33999 8419 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8420
<> 149:156823d33999 8421 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8422 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8423 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8424 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8425 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8426 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8427
<> 149:156823d33999 8428 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8429
<> 149:156823d33999 8430 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
<> 149:156823d33999 8431 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8432
<> 149:156823d33999 8433 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8434 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 149:156823d33999 8435 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8436 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8437 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8438 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8439
<> 149:156823d33999 8440 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8441
<> 149:156823d33999 8442 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
<> 149:156823d33999 8443 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8444
<> 149:156823d33999 8445 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8446 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8447 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8448 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8449 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8450 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8451
<> 149:156823d33999 8452 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8453
<> 149:156823d33999 8454 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
<> 149:156823d33999 8455 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8456
<> 149:156823d33999 8457 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8458 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 149:156823d33999 8459 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8460 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8461 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8462 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8463
<> 149:156823d33999 8464 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8465
<> 149:156823d33999 8466 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
<> 149:156823d33999 8467 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8468
<> 149:156823d33999 8469 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8470 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8471 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8472 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8473 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8474 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8475
<> 149:156823d33999 8476 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8477
<> 149:156823d33999 8478 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
<> 149:156823d33999 8479 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8480
<> 149:156823d33999 8481 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8482 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 149:156823d33999 8483 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8484 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8485 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8486 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8487
<> 149:156823d33999 8488 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8489
<> 149:156823d33999 8490 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
<> 149:156823d33999 8491 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 149:156823d33999 8492
<> 149:156823d33999 8493 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 149:156823d33999 8494 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 149:156823d33999 8495 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 149:156823d33999 8496 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 149:156823d33999 8497 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 149:156823d33999 8498 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 149:156823d33999 8499
<> 149:156823d33999 8500 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 149:156823d33999 8501
<> 149:156823d33999 8502 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
<> 149:156823d33999 8503 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 149:156823d33999 8504
<> 149:156823d33999 8505 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 149:156823d33999 8506 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 149:156823d33999 8507 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 149:156823d33999 8508 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 149:156823d33999 8509 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 149:156823d33999 8510 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 149:156823d33999 8511
<> 149:156823d33999 8512 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 149:156823d33999 8513
<> 149:156823d33999 8514 /******************************************************************************/
<> 149:156823d33999 8515 /* */
<> 149:156823d33999 8516 /* Window WATCHDOG (WWDG) */
<> 149:156823d33999 8517 /* */
<> 149:156823d33999 8518 /******************************************************************************/
<> 149:156823d33999 8519
<> 149:156823d33999 8520 /******************* Bit definition for WWDG_CR register ********************/
<> 149:156823d33999 8521 #define WWDG_CR_T_Pos (0U)
<> 149:156823d33999 8522 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
<> 149:156823d33999 8523 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 149:156823d33999 8524 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8525 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
<> 149:156823d33999 8526 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
<> 149:156823d33999 8527 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
<> 149:156823d33999 8528 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
<> 149:156823d33999 8529 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
<> 149:156823d33999 8530 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
<> 149:156823d33999 8531
<> 149:156823d33999 8532 /* Legacy defines */
<> 149:156823d33999 8533 #define WWDG_CR_T0 WWDG_CR_T_0
<> 149:156823d33999 8534 #define WWDG_CR_T1 WWDG_CR_T_1
<> 149:156823d33999 8535 #define WWDG_CR_T2 WWDG_CR_T_2
<> 149:156823d33999 8536 #define WWDG_CR_T3 WWDG_CR_T_3
<> 149:156823d33999 8537 #define WWDG_CR_T4 WWDG_CR_T_4
<> 149:156823d33999 8538 #define WWDG_CR_T5 WWDG_CR_T_5
<> 149:156823d33999 8539 #define WWDG_CR_T6 WWDG_CR_T_6
<> 149:156823d33999 8540
<> 149:156823d33999 8541 #define WWDG_CR_WDGA_Pos (7U)
<> 149:156823d33999 8542 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
<> 149:156823d33999 8543 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
<> 149:156823d33999 8544
<> 149:156823d33999 8545 /******************* Bit definition for WWDG_CFR register *******************/
<> 149:156823d33999 8546 #define WWDG_CFR_W_Pos (0U)
<> 149:156823d33999 8547 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
<> 149:156823d33999 8548 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
<> 149:156823d33999 8549 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8550 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
<> 149:156823d33999 8551 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
<> 149:156823d33999 8552 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
<> 149:156823d33999 8553 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
<> 149:156823d33999 8554 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
<> 149:156823d33999 8555 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
<> 149:156823d33999 8556
<> 149:156823d33999 8557 /* Legacy defines */
<> 149:156823d33999 8558 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 149:156823d33999 8559 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 149:156823d33999 8560 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 149:156823d33999 8561 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 149:156823d33999 8562 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 149:156823d33999 8563 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 149:156823d33999 8564 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 149:156823d33999 8565
<> 149:156823d33999 8566 #define WWDG_CFR_WDGTB_Pos (7U)
<> 149:156823d33999 8567 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
<> 149:156823d33999 8568 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
<> 149:156823d33999 8569 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
<> 149:156823d33999 8570 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
<> 149:156823d33999 8571
<> 149:156823d33999 8572 /* Legacy defines */
<> 149:156823d33999 8573 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 149:156823d33999 8574 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 149:156823d33999 8575
<> 149:156823d33999 8576 #define WWDG_CFR_EWI_Pos (9U)
<> 149:156823d33999 8577 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
<> 149:156823d33999 8578 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
<> 149:156823d33999 8579
<> 149:156823d33999 8580 /******************* Bit definition for WWDG_SR register ********************/
<> 149:156823d33999 8581 #define WWDG_SR_EWIF_Pos (0U)
<> 149:156823d33999 8582 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8583 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
<> 149:156823d33999 8584
<> 149:156823d33999 8585 /******************************************************************************/
<> 149:156823d33999 8586 /* */
<> 149:156823d33999 8587 /* SystemTick (SysTick) */
<> 149:156823d33999 8588 /* */
<> 149:156823d33999 8589 /******************************************************************************/
<> 149:156823d33999 8590
<> 149:156823d33999 8591 /***************** Bit definition for SysTick_CTRL register *****************/
<> 149:156823d33999 8592 #define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */
<> 149:156823d33999 8593 #define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */
<> 149:156823d33999 8594 #define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */
<> 149:156823d33999 8595 #define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */
<> 149:156823d33999 8596
<> 149:156823d33999 8597 /***************** Bit definition for SysTick_LOAD register *****************/
<> 149:156823d33999 8598 #define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
<> 149:156823d33999 8599
<> 149:156823d33999 8600 /***************** Bit definition for SysTick_VAL register ******************/
<> 149:156823d33999 8601 #define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */
<> 149:156823d33999 8602
<> 149:156823d33999 8603 /***************** Bit definition for SysTick_CALIB register ****************/
<> 149:156823d33999 8604 #define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */
<> 149:156823d33999 8605 #define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */
<> 149:156823d33999 8606 #define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */
<> 149:156823d33999 8607
<> 149:156823d33999 8608 /******************************************************************************/
<> 149:156823d33999 8609 /* */
<> 149:156823d33999 8610 /* Nested Vectored Interrupt Controller (NVIC) */
<> 149:156823d33999 8611 /* */
<> 149:156823d33999 8612 /******************************************************************************/
<> 149:156823d33999 8613
<> 149:156823d33999 8614 /****************** Bit definition for NVIC_ISER register *******************/
<> 149:156823d33999 8615 #define NVIC_ISER_SETENA_Pos (0U)
<> 149:156823d33999 8616 #define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 8617 #define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
<> 149:156823d33999 8618 #define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8619 #define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 8620 #define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 8621 #define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 8622 #define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 8623 #define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
<> 149:156823d33999 8624 #define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
<> 149:156823d33999 8625 #define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
<> 149:156823d33999 8626 #define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
<> 149:156823d33999 8627 #define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
<> 149:156823d33999 8628 #define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8629 #define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8630 #define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8631 #define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8632 #define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8633 #define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8634 #define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
<> 149:156823d33999 8635 #define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
<> 149:156823d33999 8636 #define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
<> 149:156823d33999 8637 #define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
<> 149:156823d33999 8638 #define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
<> 149:156823d33999 8639 #define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
<> 149:156823d33999 8640 #define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
<> 149:156823d33999 8641 #define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
<> 149:156823d33999 8642 #define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
<> 149:156823d33999 8643 #define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
<> 149:156823d33999 8644 #define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
<> 149:156823d33999 8645 #define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
<> 149:156823d33999 8646 #define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
<> 149:156823d33999 8647 #define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
<> 149:156823d33999 8648 #define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
<> 149:156823d33999 8649 #define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
<> 149:156823d33999 8650
<> 149:156823d33999 8651 /****************** Bit definition for NVIC_ICER register *******************/
<> 149:156823d33999 8652 #define NVIC_ICER_CLRENA_Pos (0U)
<> 149:156823d33999 8653 #define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 8654 #define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
<> 149:156823d33999 8655 #define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8656 #define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
<> 149:156823d33999 8657 #define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
<> 149:156823d33999 8658 #define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
<> 149:156823d33999 8659 #define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
<> 149:156823d33999 8660 #define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
<> 149:156823d33999 8661 #define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
<> 149:156823d33999 8662 #define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
<> 149:156823d33999 8663 #define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
<> 149:156823d33999 8664 #define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
<> 149:156823d33999 8665 #define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8666 #define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8667 #define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8668 #define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8669 #define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8670 #define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8671 #define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
<> 149:156823d33999 8672 #define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
<> 149:156823d33999 8673 #define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
<> 149:156823d33999 8674 #define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
<> 149:156823d33999 8675 #define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
<> 149:156823d33999 8676 #define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
<> 149:156823d33999 8677 #define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
<> 149:156823d33999 8678 #define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
<> 149:156823d33999 8679 #define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
<> 149:156823d33999 8680 #define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
<> 149:156823d33999 8681 #define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
<> 149:156823d33999 8682 #define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
<> 149:156823d33999 8683 #define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
<> 149:156823d33999 8684 #define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
<> 149:156823d33999 8685 #define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
<> 149:156823d33999 8686 #define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
<> 149:156823d33999 8687
<> 149:156823d33999 8688 /****************** Bit definition for NVIC_ISPR register *******************/
<> 149:156823d33999 8689 #define NVIC_ISPR_SETPEND_Pos (0U)
<> 149:156823d33999 8690 #define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 8691 #define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
<> 149:156823d33999 8692 #define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8693 #define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
<> 149:156823d33999 8694 #define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
<> 149:156823d33999 8695 #define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
<> 149:156823d33999 8696 #define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
<> 149:156823d33999 8697 #define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
<> 149:156823d33999 8698 #define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
<> 149:156823d33999 8699 #define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
<> 149:156823d33999 8700 #define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 8701 #define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
<> 149:156823d33999 8702 #define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8703 #define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8704 #define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8705 #define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8706 #define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8707 #define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8708 #define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
<> 149:156823d33999 8709 #define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
<> 149:156823d33999 8710 #define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
<> 149:156823d33999 8711 #define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
<> 149:156823d33999 8712 #define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
<> 149:156823d33999 8713 #define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
<> 149:156823d33999 8714 #define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
<> 149:156823d33999 8715 #define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
<> 149:156823d33999 8716 #define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
<> 149:156823d33999 8717 #define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
<> 149:156823d33999 8718 #define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
<> 149:156823d33999 8719 #define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
<> 149:156823d33999 8720 #define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
<> 149:156823d33999 8721 #define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
<> 149:156823d33999 8722 #define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
<> 149:156823d33999 8723 #define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
<> 149:156823d33999 8724
<> 149:156823d33999 8725 /****************** Bit definition for NVIC_ICPR register *******************/
<> 149:156823d33999 8726 #define NVIC_ICPR_CLRPEND_Pos (0U)
<> 149:156823d33999 8727 #define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 8728 #define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
<> 149:156823d33999 8729 #define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8730 #define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
<> 149:156823d33999 8731 #define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
<> 149:156823d33999 8732 #define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
<> 149:156823d33999 8733 #define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
<> 149:156823d33999 8734 #define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
<> 149:156823d33999 8735 #define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
<> 149:156823d33999 8736 #define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
<> 149:156823d33999 8737 #define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
<> 149:156823d33999 8738 #define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
<> 149:156823d33999 8739 #define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8740 #define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8741 #define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8742 #define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8743 #define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8744 #define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8745 #define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
<> 149:156823d33999 8746 #define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
<> 149:156823d33999 8747 #define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
<> 149:156823d33999 8748 #define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
<> 149:156823d33999 8749 #define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
<> 149:156823d33999 8750 #define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
<> 149:156823d33999 8751 #define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
<> 149:156823d33999 8752 #define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
<> 149:156823d33999 8753 #define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
<> 149:156823d33999 8754 #define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
<> 149:156823d33999 8755 #define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
<> 149:156823d33999 8756 #define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
<> 149:156823d33999 8757 #define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
<> 149:156823d33999 8758 #define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
<> 149:156823d33999 8759 #define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
<> 149:156823d33999 8760 #define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
<> 149:156823d33999 8761
<> 149:156823d33999 8762 /****************** Bit definition for NVIC_IABR register *******************/
<> 149:156823d33999 8763 #define NVIC_IABR_ACTIVE_Pos (0U)
<> 149:156823d33999 8764 #define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 8765 #define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
<> 149:156823d33999 8766 #define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
<> 149:156823d33999 8767 #define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
<> 149:156823d33999 8768 #define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
<> 149:156823d33999 8769 #define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
<> 149:156823d33999 8770 #define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
<> 149:156823d33999 8771 #define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
<> 149:156823d33999 8772 #define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
<> 149:156823d33999 8773 #define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
<> 149:156823d33999 8774 #define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
<> 149:156823d33999 8775 #define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
<> 149:156823d33999 8776 #define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
<> 149:156823d33999 8777 #define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
<> 149:156823d33999 8778 #define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
<> 149:156823d33999 8779 #define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
<> 149:156823d33999 8780 #define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
<> 149:156823d33999 8781 #define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
<> 149:156823d33999 8782 #define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
<> 149:156823d33999 8783 #define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
<> 149:156823d33999 8784 #define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
<> 149:156823d33999 8785 #define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
<> 149:156823d33999 8786 #define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
<> 149:156823d33999 8787 #define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
<> 149:156823d33999 8788 #define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
<> 149:156823d33999 8789 #define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
<> 149:156823d33999 8790 #define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
<> 149:156823d33999 8791 #define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
<> 149:156823d33999 8792 #define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
<> 149:156823d33999 8793 #define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
<> 149:156823d33999 8794 #define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
<> 149:156823d33999 8795 #define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
<> 149:156823d33999 8796 #define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
<> 149:156823d33999 8797 #define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
<> 149:156823d33999 8798
<> 149:156823d33999 8799 /****************** Bit definition for NVIC_PRI0 register *******************/
<> 149:156823d33999 8800 #define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */
<> 149:156823d33999 8801 #define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */
<> 149:156823d33999 8802 #define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */
<> 149:156823d33999 8803 #define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */
<> 149:156823d33999 8804
<> 149:156823d33999 8805 /****************** Bit definition for NVIC_PRI1 register *******************/
<> 149:156823d33999 8806 #define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */
<> 149:156823d33999 8807 #define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */
<> 149:156823d33999 8808 #define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */
<> 149:156823d33999 8809 #define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */
<> 149:156823d33999 8810
<> 149:156823d33999 8811 /****************** Bit definition for NVIC_PRI2 register *******************/
<> 149:156823d33999 8812 #define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */
<> 149:156823d33999 8813 #define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */
<> 149:156823d33999 8814 #define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */
<> 149:156823d33999 8815 #define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */
<> 149:156823d33999 8816
<> 149:156823d33999 8817 /****************** Bit definition for NVIC_PRI3 register *******************/
<> 149:156823d33999 8818 #define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */
<> 149:156823d33999 8819 #define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */
<> 149:156823d33999 8820 #define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */
<> 149:156823d33999 8821 #define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */
<> 149:156823d33999 8822
<> 149:156823d33999 8823 /****************** Bit definition for NVIC_PRI4 register *******************/
<> 149:156823d33999 8824 #define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */
<> 149:156823d33999 8825 #define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */
<> 149:156823d33999 8826 #define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */
<> 149:156823d33999 8827 #define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */
<> 149:156823d33999 8828
<> 149:156823d33999 8829 /****************** Bit definition for NVIC_PRI5 register *******************/
<> 149:156823d33999 8830 #define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */
<> 149:156823d33999 8831 #define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */
<> 149:156823d33999 8832 #define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */
<> 149:156823d33999 8833 #define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */
<> 149:156823d33999 8834
<> 149:156823d33999 8835 /****************** Bit definition for NVIC_PRI6 register *******************/
<> 149:156823d33999 8836 #define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */
<> 149:156823d33999 8837 #define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */
<> 149:156823d33999 8838 #define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */
<> 149:156823d33999 8839 #define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */
<> 149:156823d33999 8840
<> 149:156823d33999 8841 /****************** Bit definition for NVIC_PRI7 register *******************/
<> 149:156823d33999 8842 #define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */
<> 149:156823d33999 8843 #define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */
<> 149:156823d33999 8844 #define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */
<> 149:156823d33999 8845 #define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */
<> 149:156823d33999 8846
<> 149:156823d33999 8847 /****************** Bit definition for SCB_CPUID register *******************/
<> 149:156823d33999 8848 #define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */
<> 149:156823d33999 8849 #define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */
<> 149:156823d33999 8850 #define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */
<> 149:156823d33999 8851 #define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */
<> 149:156823d33999 8852 #define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */
<> 149:156823d33999 8853
<> 149:156823d33999 8854 /******************* Bit definition for SCB_ICSR register *******************/
<> 149:156823d33999 8855 #define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */
<> 149:156823d33999 8856 #define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
<> 149:156823d33999 8857 #define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */
<> 149:156823d33999 8858 #define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */
<> 149:156823d33999 8859 #define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
<> 149:156823d33999 8860 #define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */
<> 149:156823d33999 8861 #define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */
<> 149:156823d33999 8862 #define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */
<> 149:156823d33999 8863 #define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */
<> 149:156823d33999 8864 #define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */
<> 149:156823d33999 8865
<> 149:156823d33999 8866 /******************* Bit definition for SCB_VTOR register *******************/
<> 149:156823d33999 8867 #define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */
<> 149:156823d33999 8868 #define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */
<> 149:156823d33999 8869
<> 149:156823d33999 8870 /*!<***************** Bit definition for SCB_AIRCR register *******************/
<> 149:156823d33999 8871 #define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */
<> 149:156823d33999 8872 #define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */
<> 149:156823d33999 8873 #define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */
<> 149:156823d33999 8874
<> 149:156823d33999 8875 #define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */
<> 149:156823d33999 8876 #define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */
<> 149:156823d33999 8877 #define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */
<> 149:156823d33999 8878 #define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */
<> 149:156823d33999 8879
<> 149:156823d33999 8880 /* prority group configuration */
<> 149:156823d33999 8881 #define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
<> 149:156823d33999 8882 #define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
<> 149:156823d33999 8883 #define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
<> 149:156823d33999 8884 #define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
<> 149:156823d33999 8885 #define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
<> 149:156823d33999 8886 #define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
<> 149:156823d33999 8887 #define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
<> 149:156823d33999 8888 #define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
<> 149:156823d33999 8889
<> 149:156823d33999 8890 #define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */
<> 149:156823d33999 8891 #define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
<> 149:156823d33999 8892
<> 149:156823d33999 8893 /******************* Bit definition for SCB_SCR register ********************/
<> 149:156823d33999 8894 #define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */
<> 149:156823d33999 8895 #define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */
<> 149:156823d33999 8896 #define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */
<> 149:156823d33999 8897
<> 149:156823d33999 8898 /******************** Bit definition for SCB_CCR register *******************/
<> 149:156823d33999 8899 #define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
<> 149:156823d33999 8900 #define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
<> 149:156823d33999 8901 #define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */
<> 149:156823d33999 8902 #define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */
<> 149:156823d33999 8903 #define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */
<> 149:156823d33999 8904 #define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
<> 149:156823d33999 8905
<> 149:156823d33999 8906 /******************* Bit definition for SCB_SHPR register ********************/
<> 149:156823d33999 8907 #define SCB_SHPR_PRI_N_Pos (0U)
<> 149:156823d33999 8908 #define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
<> 149:156823d33999 8909 #define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
<> 149:156823d33999 8910 #define SCB_SHPR_PRI_N1_Pos (8U)
<> 149:156823d33999 8911 #define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
<> 149:156823d33999 8912 #define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
<> 149:156823d33999 8913 #define SCB_SHPR_PRI_N2_Pos (16U)
<> 149:156823d33999 8914 #define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
<> 149:156823d33999 8915 #define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
<> 149:156823d33999 8916 #define SCB_SHPR_PRI_N3_Pos (24U)
<> 149:156823d33999 8917 #define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
<> 149:156823d33999 8918 #define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
<> 149:156823d33999 8919
<> 149:156823d33999 8920 /****************** Bit definition for SCB_SHCSR register *******************/
<> 149:156823d33999 8921 #define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */
<> 149:156823d33999 8922 #define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */
<> 149:156823d33999 8923 #define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */
<> 149:156823d33999 8924 #define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */
<> 149:156823d33999 8925 #define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */
<> 149:156823d33999 8926 #define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */
<> 149:156823d33999 8927 #define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */
<> 149:156823d33999 8928 #define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */
<> 149:156823d33999 8929 #define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */
<> 149:156823d33999 8930 #define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */
<> 149:156823d33999 8931 #define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */
<> 149:156823d33999 8932 #define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */
<> 149:156823d33999 8933 #define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */
<> 149:156823d33999 8934 #define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */
<> 149:156823d33999 8935
<> 149:156823d33999 8936 /******************* Bit definition for SCB_CFSR register *******************/
<> 149:156823d33999 8937 /*!< MFSR */
AnnaBridge 184:08ed48f1de7f 8938 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 184:08ed48f1de7f 8939 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
<> 149:156823d33999 8940 #define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
AnnaBridge 184:08ed48f1de7f 8941 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 184:08ed48f1de7f 8942 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
<> 149:156823d33999 8943 #define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
AnnaBridge 184:08ed48f1de7f 8944 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 184:08ed48f1de7f 8945 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
<> 149:156823d33999 8946 #define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
AnnaBridge 184:08ed48f1de7f 8947 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 184:08ed48f1de7f 8948 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
<> 149:156823d33999 8949 #define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
AnnaBridge 184:08ed48f1de7f 8950 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 184:08ed48f1de7f 8951 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
<> 149:156823d33999 8952 #define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
<> 149:156823d33999 8953 /*!< BFSR */
AnnaBridge 184:08ed48f1de7f 8954 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 184:08ed48f1de7f 8955 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
<> 149:156823d33999 8956 #define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
AnnaBridge 184:08ed48f1de7f 8957 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 184:08ed48f1de7f 8958 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
<> 149:156823d33999 8959 #define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
AnnaBridge 184:08ed48f1de7f 8960 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 184:08ed48f1de7f 8961 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
<> 149:156823d33999 8962 #define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
AnnaBridge 184:08ed48f1de7f 8963 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 184:08ed48f1de7f 8964 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
<> 149:156823d33999 8965 #define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
AnnaBridge 184:08ed48f1de7f 8966 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 184:08ed48f1de7f 8967 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
<> 149:156823d33999 8968 #define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
AnnaBridge 184:08ed48f1de7f 8969 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 184:08ed48f1de7f 8970 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
<> 149:156823d33999 8971 #define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
<> 149:156823d33999 8972 /*!< UFSR */
AnnaBridge 184:08ed48f1de7f 8973 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 184:08ed48f1de7f 8974 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
<> 149:156823d33999 8975 #define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
AnnaBridge 184:08ed48f1de7f 8976 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 184:08ed48f1de7f 8977 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
<> 149:156823d33999 8978 #define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
AnnaBridge 184:08ed48f1de7f 8979 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 184:08ed48f1de7f 8980 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
<> 149:156823d33999 8981 #define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
AnnaBridge 184:08ed48f1de7f 8982 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 184:08ed48f1de7f 8983 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
<> 149:156823d33999 8984 #define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
AnnaBridge 184:08ed48f1de7f 8985 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 184:08ed48f1de7f 8986 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
<> 149:156823d33999 8987 #define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
AnnaBridge 184:08ed48f1de7f 8988 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 184:08ed48f1de7f 8989 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
<> 149:156823d33999 8990 #define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
<> 149:156823d33999 8991
<> 149:156823d33999 8992 /******************* Bit definition for SCB_HFSR register *******************/
<> 149:156823d33999 8993 #define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */
<> 149:156823d33999 8994 #define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
<> 149:156823d33999 8995 #define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */
<> 149:156823d33999 8996
<> 149:156823d33999 8997 /******************* Bit definition for SCB_DFSR register *******************/
<> 149:156823d33999 8998 #define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */
<> 149:156823d33999 8999 #define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */
<> 149:156823d33999 9000 #define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */
<> 149:156823d33999 9001 #define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */
<> 149:156823d33999 9002 #define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */
<> 149:156823d33999 9003
<> 149:156823d33999 9004 /******************* Bit definition for SCB_MMFAR register ******************/
<> 149:156823d33999 9005 #define SCB_MMFAR_ADDRESS_Pos (0U)
<> 149:156823d33999 9006 #define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 9007 #define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
<> 149:156823d33999 9008
<> 149:156823d33999 9009 /******************* Bit definition for SCB_BFAR register *******************/
<> 149:156823d33999 9010 #define SCB_BFAR_ADDRESS_Pos (0U)
<> 149:156823d33999 9011 #define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 9012 #define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
<> 149:156823d33999 9013
<> 149:156823d33999 9014 /******************* Bit definition for SCB_afsr register *******************/
<> 149:156823d33999 9015 #define SCB_AFSR_IMPDEF_Pos (0U)
<> 149:156823d33999 9016 #define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
<> 149:156823d33999 9017 #define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
<> 149:156823d33999 9018 /**
<> 149:156823d33999 9019 * @}
<> 149:156823d33999 9020 */
<> 149:156823d33999 9021
<> 149:156823d33999 9022 /**
<> 149:156823d33999 9023 * @}
<> 149:156823d33999 9024 */
<> 149:156823d33999 9025 /** @addtogroup Exported_macro
<> 149:156823d33999 9026 * @{
<> 149:156823d33999 9027 */
<> 149:156823d33999 9028
<> 149:156823d33999 9029 /****************************** ADC Instances *********************************/
<> 149:156823d33999 9030 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 149:156823d33999 9031
<> 149:156823d33999 9032 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
<> 149:156823d33999 9033
<> 149:156823d33999 9034 /******************************** COMP Instances ******************************/
<> 149:156823d33999 9035 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
<> 149:156823d33999 9036 ((INSTANCE) == COMP2))
<> 149:156823d33999 9037
<> 149:156823d33999 9038 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
<> 149:156823d33999 9039
<> 149:156823d33999 9040 /****************************** CRC Instances *********************************/
<> 149:156823d33999 9041 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 149:156823d33999 9042
<> 149:156823d33999 9043 /****************************** DAC Instances *********************************/
<> 149:156823d33999 9044 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
<> 149:156823d33999 9045
<> 149:156823d33999 9046 /****************************** DMA Instances *********************************/
<> 149:156823d33999 9047 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 149:156823d33999 9048 ((INSTANCE) == DMA1_Channel2) || \
<> 149:156823d33999 9049 ((INSTANCE) == DMA1_Channel3) || \
<> 149:156823d33999 9050 ((INSTANCE) == DMA1_Channel4) || \
<> 149:156823d33999 9051 ((INSTANCE) == DMA1_Channel5) || \
<> 149:156823d33999 9052 ((INSTANCE) == DMA1_Channel6) || \
<> 149:156823d33999 9053 ((INSTANCE) == DMA1_Channel7) || \
<> 149:156823d33999 9054 ((INSTANCE) == DMA2_Channel1) || \
<> 149:156823d33999 9055 ((INSTANCE) == DMA2_Channel2) || \
<> 149:156823d33999 9056 ((INSTANCE) == DMA2_Channel3) || \
<> 149:156823d33999 9057 ((INSTANCE) == DMA2_Channel4) || \
<> 149:156823d33999 9058 ((INSTANCE) == DMA2_Channel5))
<> 149:156823d33999 9059
<> 149:156823d33999 9060 /******************************* GPIO Instances *******************************/
<> 149:156823d33999 9061 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 149:156823d33999 9062 ((INSTANCE) == GPIOB) || \
<> 149:156823d33999 9063 ((INSTANCE) == GPIOC) || \
<> 149:156823d33999 9064 ((INSTANCE) == GPIOD) || \
<> 149:156823d33999 9065 ((INSTANCE) == GPIOE) || \
<> 149:156823d33999 9066 ((INSTANCE) == GPIOF) || \
<> 149:156823d33999 9067 ((INSTANCE) == GPIOG) || \
<> 149:156823d33999 9068 ((INSTANCE) == GPIOH))
<> 149:156823d33999 9069
<> 149:156823d33999 9070 /**************************** GPIO Alternate Function Instances ***************/
<> 149:156823d33999 9071 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
<> 149:156823d33999 9072
<> 149:156823d33999 9073 /**************************** GPIO Lock Instances *****************************/
<> 149:156823d33999 9074 /* On L1, all GPIO Bank support the Lock mechanism */
<> 149:156823d33999 9075 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
<> 149:156823d33999 9076
<> 149:156823d33999 9077 /******************************** I2C Instances *******************************/
<> 149:156823d33999 9078 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 149:156823d33999 9079 ((INSTANCE) == I2C2))
<> 149:156823d33999 9080
<> 149:156823d33999 9081 /****************************** SMBUS Instances *******************************/
<> 149:156823d33999 9082 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
<> 149:156823d33999 9083
<> 149:156823d33999 9084 /******************************** I2S Instances *******************************/
<> 149:156823d33999 9085 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
<> 149:156823d33999 9086 ((INSTANCE) == SPI3))
<> 149:156823d33999 9087 /****************************** IWDG Instances ********************************/
<> 149:156823d33999 9088 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 149:156823d33999 9089
<> 149:156823d33999 9090 /****************************** OPAMP Instances *******************************/
<> 149:156823d33999 9091 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
<> 149:156823d33999 9092 ((INSTANCE) == OPAMP2))
<> 149:156823d33999 9093
<> 149:156823d33999 9094 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
<> 149:156823d33999 9095
<> 149:156823d33999 9096 /****************************** RTC Instances *********************************/
<> 149:156823d33999 9097 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 149:156823d33999 9098
<> 149:156823d33999 9099 /******************************** SPI Instances *******************************/
<> 149:156823d33999 9100 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 149:156823d33999 9101 ((INSTANCE) == SPI2) || \
<> 149:156823d33999 9102 ((INSTANCE) == SPI3))
<> 149:156823d33999 9103
<> 149:156823d33999 9104 /****************************** TIM Instances *********************************/
<> 149:156823d33999 9105 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9106 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9107 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9108 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9109 ((INSTANCE) == TIM6) || \
<> 149:156823d33999 9110 ((INSTANCE) == TIM7) || \
<> 149:156823d33999 9111 ((INSTANCE) == TIM9) || \
<> 149:156823d33999 9112 ((INSTANCE) == TIM10) || \
<> 149:156823d33999 9113 ((INSTANCE) == TIM11))
<> 149:156823d33999 9114
<> 149:156823d33999 9115 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9116 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9117 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9118 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9119 ((INSTANCE) == TIM9) || \
<> 149:156823d33999 9120 ((INSTANCE) == TIM10) || \
<> 149:156823d33999 9121 ((INSTANCE) == TIM11))
<> 149:156823d33999 9122
<> 149:156823d33999 9123 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9124 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9125 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9126 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9127 ((INSTANCE) == TIM9))
<> 149:156823d33999 9128
<> 149:156823d33999 9129 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9130 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9131 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9132 ((INSTANCE) == TIM5))
<> 149:156823d33999 9133
<> 149:156823d33999 9134 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9135 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9136 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9137 ((INSTANCE) == TIM5))
<> 149:156823d33999 9138
<> 149:156823d33999 9139 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9140 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9141 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9142 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9143 ((INSTANCE) == TIM9))
<> 149:156823d33999 9144
<> 149:156823d33999 9145 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9146 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9147 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9148 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9149 ((INSTANCE) == TIM9) || \
<> 149:156823d33999 9150 ((INSTANCE) == TIM10) || \
<> 149:156823d33999 9151 ((INSTANCE) == TIM11))
<> 149:156823d33999 9152
<> 149:156823d33999 9153 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9154 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9155 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9156 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9157 ((INSTANCE) == TIM9))
<> 149:156823d33999 9158
<> 149:156823d33999 9159 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9160 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9161 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9162 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9163 ((INSTANCE) == TIM9))
<> 149:156823d33999 9164
<> 149:156823d33999 9165 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9166 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9167 ((INSTANCE) == TIM4))
<> 149:156823d33999 9168
<> 149:156823d33999 9169 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9170 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9171 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9172 ((INSTANCE) == TIM5))
<> 149:156823d33999 9173
<> 149:156823d33999 9174 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9175 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9176 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9177 ((INSTANCE) == TIM5))
<> 149:156823d33999 9178
<> 149:156823d33999 9179
<> 149:156823d33999 9180 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9181 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9182 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9183 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9184 ((INSTANCE) == TIM6) || \
<> 149:156823d33999 9185 ((INSTANCE) == TIM7) || \
<> 149:156823d33999 9186 ((INSTANCE) == TIM9))
<> 149:156823d33999 9187
<> 149:156823d33999 9188 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9189 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9190 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9191 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9192 ((INSTANCE) == TIM9))
<> 149:156823d33999 9193
<> 149:156823d33999 9194 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
<> 149:156823d33999 9195
<> 149:156823d33999 9196 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9197 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9198 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9199 ((INSTANCE) == TIM5))
<> 149:156823d33999 9200
<> 149:156823d33999 9201 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 149:156823d33999 9202 ((((INSTANCE) == TIM2) && \
<> 149:156823d33999 9203 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 149:156823d33999 9204 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 149:156823d33999 9205 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 149:156823d33999 9206 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 149:156823d33999 9207 || \
<> 149:156823d33999 9208 (((INSTANCE) == TIM3) && \
<> 149:156823d33999 9209 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 149:156823d33999 9210 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 149:156823d33999 9211 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 149:156823d33999 9212 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 149:156823d33999 9213 || \
<> 149:156823d33999 9214 (((INSTANCE) == TIM4) && \
<> 149:156823d33999 9215 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 149:156823d33999 9216 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 149:156823d33999 9217 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 149:156823d33999 9218 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 149:156823d33999 9219 || \
<> 149:156823d33999 9220 (((INSTANCE) == TIM5) && \
<> 149:156823d33999 9221 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 149:156823d33999 9222 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 149:156823d33999 9223 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 149:156823d33999 9224 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 149:156823d33999 9225 || \
<> 149:156823d33999 9226 (((INSTANCE) == TIM9) && \
<> 149:156823d33999 9227 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 149:156823d33999 9228 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 149:156823d33999 9229 || \
<> 149:156823d33999 9230 (((INSTANCE) == TIM10) && \
<> 149:156823d33999 9231 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 149:156823d33999 9232 || \
<> 149:156823d33999 9233 (((INSTANCE) == TIM11) && \
<> 149:156823d33999 9234 (((CHANNEL) == TIM_CHANNEL_1))))
<> 149:156823d33999 9235
<> 149:156823d33999 9236 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9237 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9238 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9239 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9240 ((INSTANCE) == TIM9) || \
<> 149:156823d33999 9241 ((INSTANCE) == TIM10) || \
<> 149:156823d33999 9242 ((INSTANCE) == TIM11))
<> 149:156823d33999 9243
<> 149:156823d33999 9244 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9245 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9246 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9247 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9248 ((INSTANCE) == TIM6) || \
<> 149:156823d33999 9249 ((INSTANCE) == TIM7))
<> 149:156823d33999 9250
<> 149:156823d33999 9251 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9252 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9253 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9254 ((INSTANCE) == TIM5))
<> 149:156823d33999 9255
<> 149:156823d33999 9256 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9257 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9258 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9259 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9260 ((INSTANCE) == TIM9))
<> 149:156823d33999 9261
<> 149:156823d33999 9262 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9263 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9264 ((INSTANCE) == TIM4) || \
<> 149:156823d33999 9265 ((INSTANCE) == TIM5) || \
<> 149:156823d33999 9266 ((INSTANCE) == TIM9))
<> 149:156823d33999 9267
<> 149:156823d33999 9268 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 149:156823d33999 9269 ((INSTANCE) == TIM3) || \
<> 149:156823d33999 9270 ((INSTANCE) == TIM9) || \
<> 149:156823d33999 9271 ((INSTANCE) == TIM10) || \
<> 149:156823d33999 9272 ((INSTANCE) == TIM11))
<> 149:156823d33999 9273
<> 149:156823d33999 9274 /******************** USART Instances : Synchronous mode **********************/
<> 149:156823d33999 9275 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9276 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9277 ((INSTANCE) == USART3))
<> 149:156823d33999 9278
<> 149:156823d33999 9279 /******************** UART Instances : Asynchronous mode **********************/
<> 149:156823d33999 9280 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9281 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9282 ((INSTANCE) == USART3) || \
<> 149:156823d33999 9283 ((INSTANCE) == UART4) || \
<> 149:156823d33999 9284 ((INSTANCE) == UART5))
<> 149:156823d33999 9285
<> 149:156823d33999 9286 /******************** UART Instances : Half-Duplex mode **********************/
<> 149:156823d33999 9287 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9288 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9289 ((INSTANCE) == USART3) || \
<> 149:156823d33999 9290 ((INSTANCE) == UART4) || \
<> 149:156823d33999 9291 ((INSTANCE) == UART5))
<> 149:156823d33999 9292
<> 149:156823d33999 9293 /******************** UART Instances : LIN mode **********************/
<> 149:156823d33999 9294 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9295 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9296 ((INSTANCE) == USART3) || \
<> 149:156823d33999 9297 ((INSTANCE) == UART4) || \
<> 149:156823d33999 9298 ((INSTANCE) == UART5))
<> 149:156823d33999 9299
<> 149:156823d33999 9300 /****************** UART Instances : Hardware Flow control ********************/
<> 149:156823d33999 9301 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9302 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9303 ((INSTANCE) == USART3))
<> 149:156823d33999 9304
<> 149:156823d33999 9305 /********************* UART Instances : Smard card mode ***********************/
<> 149:156823d33999 9306 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9307 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9308 ((INSTANCE) == USART3))
<> 149:156823d33999 9309
<> 149:156823d33999 9310 /*********************** UART Instances : IRDA mode ***************************/
<> 149:156823d33999 9311 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9312 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9313 ((INSTANCE) == USART3) || \
<> 149:156823d33999 9314 ((INSTANCE) == UART4) || \
<> 149:156823d33999 9315 ((INSTANCE) == UART5))
<> 149:156823d33999 9316
<> 149:156823d33999 9317 /***************** UART Instances : Multi-Processor mode **********************/
<> 149:156823d33999 9318 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 149:156823d33999 9319 ((INSTANCE) == USART2) || \
<> 149:156823d33999 9320 ((INSTANCE) == USART3) || \
<> 149:156823d33999 9321 ((INSTANCE) == UART4) || \
<> 149:156823d33999 9322 ((INSTANCE) == UART5))
<> 149:156823d33999 9323
<> 149:156823d33999 9324 /****************************** WWDG Instances ********************************/
<> 149:156823d33999 9325 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 149:156823d33999 9326
<> 149:156823d33999 9327
<> 149:156823d33999 9328 /****************************** LCD Instances ********************************/
<> 149:156823d33999 9329 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
<> 149:156823d33999 9330
<> 149:156823d33999 9331 /****************************** USB Instances ********************************/
<> 149:156823d33999 9332 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
<> 149:156823d33999 9333
<> 149:156823d33999 9334 /**
<> 149:156823d33999 9335 * @}
<> 149:156823d33999 9336 */
<> 149:156823d33999 9337
<> 149:156823d33999 9338 /******************************************************************************/
<> 149:156823d33999 9339 /* For a painless codes migration between the STM32L1xx device product */
<> 149:156823d33999 9340 /* lines, the aliases defined below are put in place to overcome the */
<> 149:156823d33999 9341 /* differences in the interrupt handlers and IRQn definitions. */
<> 149:156823d33999 9342 /* No need to update developed interrupt code when moving across */
<> 149:156823d33999 9343 /* product lines within the same STM32L1 Family */
<> 149:156823d33999 9344 /******************************************************************************/
<> 149:156823d33999 9345
<> 149:156823d33999 9346 /* Aliases for __IRQn */
<> 149:156823d33999 9347
<> 149:156823d33999 9348 /* Aliases for __IRQHandler */
<> 149:156823d33999 9349
<> 149:156823d33999 9350 /**
<> 149:156823d33999 9351 * @}
<> 149:156823d33999 9352 */
<> 149:156823d33999 9353
<> 149:156823d33999 9354 /**
<> 149:156823d33999 9355 * @}
<> 149:156823d33999 9356 */
<> 149:156823d33999 9357
<> 149:156823d33999 9358 #ifdef __cplusplus
<> 149:156823d33999 9359 }
<> 149:156823d33999 9360 #endif /* __cplusplus */
<> 149:156823d33999 9361
<> 149:156823d33999 9362 #endif /* __STM32L152xE_H */
<> 149:156823d33999 9363
<> 149:156823d33999 9364
<> 149:156823d33999 9365
<> 149:156823d33999 9366 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/