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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 158:b23ee177fd68 1 /**
Kojto 158:b23ee177fd68 2 ******************************************************************************
Kojto 158:b23ee177fd68 3 * @file stm32l0xx_ll_cortex.h
Kojto 158:b23ee177fd68 4 * @author MCD Application Team
Kojto 158:b23ee177fd68 5 * @brief Header file of CORTEX LL module.
Kojto 158:b23ee177fd68 6 @verbatim
Kojto 158:b23ee177fd68 7 ==============================================================================
Kojto 158:b23ee177fd68 8 ##### How to use this driver #####
Kojto 158:b23ee177fd68 9 ==============================================================================
Kojto 158:b23ee177fd68 10 [..]
Kojto 158:b23ee177fd68 11 The LL CORTEX driver contains a set of generic APIs that can be
Kojto 158:b23ee177fd68 12 used by user:
Kojto 158:b23ee177fd68 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
Kojto 158:b23ee177fd68 14 functions
Kojto 158:b23ee177fd68 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
Kojto 158:b23ee177fd68 16 (+) MPU API to configure and enable regions
Kojto 158:b23ee177fd68 17 (+) API to access to MCU info (CPUID register)
Kojto 158:b23ee177fd68 18
Kojto 158:b23ee177fd68 19 @endverbatim
Kojto 158:b23ee177fd68 20 ******************************************************************************
Kojto 158:b23ee177fd68 21 * @attention
Kojto 158:b23ee177fd68 22 *
Kojto 158:b23ee177fd68 23 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 158:b23ee177fd68 24 *
Kojto 158:b23ee177fd68 25 * Redistribution and use in source and binary forms, with or without modification,
Kojto 158:b23ee177fd68 26 * are permitted provided that the following conditions are met:
Kojto 158:b23ee177fd68 27 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 158:b23ee177fd68 28 * this list of conditions and the following disclaimer.
Kojto 158:b23ee177fd68 29 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 158:b23ee177fd68 30 * this list of conditions and the following disclaimer in the documentation
Kojto 158:b23ee177fd68 31 * and/or other materials provided with the distribution.
Kojto 158:b23ee177fd68 32 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 158:b23ee177fd68 33 * may be used to endorse or promote products derived from this software
Kojto 158:b23ee177fd68 34 * without specific prior written permission.
Kojto 158:b23ee177fd68 35 *
Kojto 158:b23ee177fd68 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 158:b23ee177fd68 37 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 158:b23ee177fd68 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 158:b23ee177fd68 39 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 158:b23ee177fd68 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 158:b23ee177fd68 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 158:b23ee177fd68 42 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 158:b23ee177fd68 43 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 158:b23ee177fd68 44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 158:b23ee177fd68 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 158:b23ee177fd68 46 *
Kojto 158:b23ee177fd68 47 ******************************************************************************
Kojto 158:b23ee177fd68 48 */
Kojto 158:b23ee177fd68 49
Kojto 158:b23ee177fd68 50 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 158:b23ee177fd68 51 #ifndef __STM32L0xx_LL_CORTEX_H
Kojto 158:b23ee177fd68 52 #define __STM32L0xx_LL_CORTEX_H
Kojto 158:b23ee177fd68 53
Kojto 158:b23ee177fd68 54 #ifdef __cplusplus
Kojto 158:b23ee177fd68 55 extern "C" {
Kojto 158:b23ee177fd68 56 #endif
Kojto 158:b23ee177fd68 57
Kojto 158:b23ee177fd68 58 /* Includes ------------------------------------------------------------------*/
Kojto 158:b23ee177fd68 59 #include "stm32l0xx.h"
Kojto 158:b23ee177fd68 60
Kojto 158:b23ee177fd68 61 /** @addtogroup STM32L0xx_LL_Driver
Kojto 158:b23ee177fd68 62 * @{
Kojto 158:b23ee177fd68 63 */
Kojto 158:b23ee177fd68 64
Kojto 158:b23ee177fd68 65 /** @defgroup CORTEX_LL CORTEX
Kojto 158:b23ee177fd68 66 * @{
Kojto 158:b23ee177fd68 67 */
Kojto 158:b23ee177fd68 68
Kojto 158:b23ee177fd68 69 /* Private types -------------------------------------------------------------*/
Kojto 158:b23ee177fd68 70 /* Private variables ---------------------------------------------------------*/
Kojto 158:b23ee177fd68 71
Kojto 158:b23ee177fd68 72 /* Private constants ---------------------------------------------------------*/
Kojto 158:b23ee177fd68 73
Kojto 158:b23ee177fd68 74 /* Private macros ------------------------------------------------------------*/
Kojto 158:b23ee177fd68 75
Kojto 158:b23ee177fd68 76 /* Exported types ------------------------------------------------------------*/
Kojto 158:b23ee177fd68 77 /* Exported constants --------------------------------------------------------*/
Kojto 158:b23ee177fd68 78 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
Kojto 158:b23ee177fd68 79 * @{
Kojto 158:b23ee177fd68 80 */
Kojto 158:b23ee177fd68 81
Kojto 158:b23ee177fd68 82 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
Kojto 158:b23ee177fd68 83 * @{
Kojto 158:b23ee177fd68 84 */
Kojto 158:b23ee177fd68 85 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
Kojto 158:b23ee177fd68 86 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
Kojto 158:b23ee177fd68 87 /**
Kojto 158:b23ee177fd68 88 * @}
Kojto 158:b23ee177fd68 89 */
Kojto 158:b23ee177fd68 90
Kojto 158:b23ee177fd68 91 #if __MPU_PRESENT
Kojto 158:b23ee177fd68 92
Kojto 158:b23ee177fd68 93 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
Kojto 158:b23ee177fd68 94 * @{
Kojto 158:b23ee177fd68 95 */
Kojto 158:b23ee177fd68 96 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */
Kojto 158:b23ee177fd68 97 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
Kojto 158:b23ee177fd68 98 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
Kojto 158:b23ee177fd68 99 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
Kojto 158:b23ee177fd68 100 /**
Kojto 158:b23ee177fd68 101 * @}
Kojto 158:b23ee177fd68 102 */
Kojto 158:b23ee177fd68 103
Kojto 158:b23ee177fd68 104 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
Kojto 158:b23ee177fd68 105 * @{
Kojto 158:b23ee177fd68 106 */
Kojto 158:b23ee177fd68 107 #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */
Kojto 158:b23ee177fd68 108 #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */
Kojto 158:b23ee177fd68 109 #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */
Kojto 158:b23ee177fd68 110 #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */
Kojto 158:b23ee177fd68 111 #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */
Kojto 158:b23ee177fd68 112 #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */
Kojto 158:b23ee177fd68 113 #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */
Kojto 158:b23ee177fd68 114 #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */
Kojto 158:b23ee177fd68 115 /**
Kojto 158:b23ee177fd68 116 * @}
Kojto 158:b23ee177fd68 117 */
Kojto 158:b23ee177fd68 118
Kojto 158:b23ee177fd68 119 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
Kojto 158:b23ee177fd68 120 * @{
Kojto 158:b23ee177fd68 121 */
Kojto 158:b23ee177fd68 122 #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
Kojto 158:b23ee177fd68 123 #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
Kojto 158:b23ee177fd68 124 #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
Kojto 158:b23ee177fd68 125 #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
Kojto 158:b23ee177fd68 126 #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
Kojto 158:b23ee177fd68 127 #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 128 #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 129 #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 130 #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 131 #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 132 #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 133 #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 134 #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 135 #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 136 #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
Kojto 158:b23ee177fd68 137 #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 138 #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 139 #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 140 #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 141 #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 142 #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 143 #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 144 #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 145 #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 146 #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
Kojto 158:b23ee177fd68 147 #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
Kojto 158:b23ee177fd68 148 #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
Kojto 158:b23ee177fd68 149 #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
Kojto 158:b23ee177fd68 150 /**
Kojto 158:b23ee177fd68 151 * @}
Kojto 158:b23ee177fd68 152 */
Kojto 158:b23ee177fd68 153
Kojto 158:b23ee177fd68 154 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
Kojto 158:b23ee177fd68 155 * @{
Kojto 158:b23ee177fd68 156 */
Kojto 158:b23ee177fd68 157 #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
Kojto 158:b23ee177fd68 158 #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
Kojto 158:b23ee177fd68 159 #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
Kojto 158:b23ee177fd68 160 #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
Kojto 158:b23ee177fd68 161 #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
Kojto 158:b23ee177fd68 162 #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
Kojto 158:b23ee177fd68 163 /**
Kojto 158:b23ee177fd68 164 * @}
Kojto 158:b23ee177fd68 165 */
Kojto 158:b23ee177fd68 166
Kojto 158:b23ee177fd68 167 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
Kojto 158:b23ee177fd68 168 * @{
Kojto 158:b23ee177fd68 169 */
Kojto 158:b23ee177fd68 170 #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
Kojto 158:b23ee177fd68 171 #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
Kojto 158:b23ee177fd68 172 #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
Kojto 158:b23ee177fd68 173 #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
Kojto 158:b23ee177fd68 174 /**
Kojto 158:b23ee177fd68 175 * @}
Kojto 158:b23ee177fd68 176 */
Kojto 158:b23ee177fd68 177
Kojto 158:b23ee177fd68 178 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
Kojto 158:b23ee177fd68 179 * @{
Kojto 158:b23ee177fd68 180 */
Kojto 158:b23ee177fd68 181 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */
Kojto 158:b23ee177fd68 182 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
Kojto 158:b23ee177fd68 183 /**
Kojto 158:b23ee177fd68 184 * @}
Kojto 158:b23ee177fd68 185 */
Kojto 158:b23ee177fd68 186
Kojto 158:b23ee177fd68 187 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
Kojto 158:b23ee177fd68 188 * @{
Kojto 158:b23ee177fd68 189 */
Kojto 158:b23ee177fd68 190 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
Kojto 158:b23ee177fd68 191 #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
Kojto 158:b23ee177fd68 192 /**
Kojto 158:b23ee177fd68 193 * @}
Kojto 158:b23ee177fd68 194 */
Kojto 158:b23ee177fd68 195
Kojto 158:b23ee177fd68 196 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
Kojto 158:b23ee177fd68 197 * @{
Kojto 158:b23ee177fd68 198 */
Kojto 158:b23ee177fd68 199 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
Kojto 158:b23ee177fd68 200 #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
Kojto 158:b23ee177fd68 201 /**
Kojto 158:b23ee177fd68 202 * @}
Kojto 158:b23ee177fd68 203 */
Kojto 158:b23ee177fd68 204
Kojto 158:b23ee177fd68 205 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
Kojto 158:b23ee177fd68 206 * @{
Kojto 158:b23ee177fd68 207 */
Kojto 158:b23ee177fd68 208 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
Kojto 158:b23ee177fd68 209 #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
Kojto 158:b23ee177fd68 210 /**
Kojto 158:b23ee177fd68 211 * @}
Kojto 158:b23ee177fd68 212 */
Kojto 158:b23ee177fd68 213 #endif /* __MPU_PRESENT */
Kojto 158:b23ee177fd68 214 /**
Kojto 158:b23ee177fd68 215 * @}
Kojto 158:b23ee177fd68 216 */
Kojto 158:b23ee177fd68 217
Kojto 158:b23ee177fd68 218 /* Exported macro ------------------------------------------------------------*/
Kojto 158:b23ee177fd68 219
Kojto 158:b23ee177fd68 220 /* Exported functions --------------------------------------------------------*/
Kojto 158:b23ee177fd68 221 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
Kojto 158:b23ee177fd68 222 * @{
Kojto 158:b23ee177fd68 223 */
Kojto 158:b23ee177fd68 224
Kojto 158:b23ee177fd68 225 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
Kojto 158:b23ee177fd68 226 * @{
Kojto 158:b23ee177fd68 227 */
Kojto 158:b23ee177fd68 228
Kojto 158:b23ee177fd68 229 /**
Kojto 158:b23ee177fd68 230 * @brief This function checks if the Systick counter flag is active or not.
Kojto 158:b23ee177fd68 231 * @note It can be used in timeout function on application side.
Kojto 158:b23ee177fd68 232 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Kojto 158:b23ee177fd68 233 * @retval State of bit (1 or 0).
Kojto 158:b23ee177fd68 234 */
Kojto 158:b23ee177fd68 235 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
Kojto 158:b23ee177fd68 236 {
Kojto 158:b23ee177fd68 237 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
Kojto 158:b23ee177fd68 238 }
Kojto 158:b23ee177fd68 239
Kojto 158:b23ee177fd68 240 /**
Kojto 158:b23ee177fd68 241 * @brief Configures the SysTick clock source
Kojto 158:b23ee177fd68 242 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Kojto 158:b23ee177fd68 243 * @param Source This parameter can be one of the following values:
Kojto 158:b23ee177fd68 244 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
Kojto 158:b23ee177fd68 245 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
Kojto 158:b23ee177fd68 246 * @retval None
Kojto 158:b23ee177fd68 247 */
Kojto 158:b23ee177fd68 248 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
Kojto 158:b23ee177fd68 249 {
Kojto 158:b23ee177fd68 250 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
Kojto 158:b23ee177fd68 251 {
Kojto 158:b23ee177fd68 252 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 158:b23ee177fd68 253 }
Kojto 158:b23ee177fd68 254 else
Kojto 158:b23ee177fd68 255 {
Kojto 158:b23ee177fd68 256 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 158:b23ee177fd68 257 }
Kojto 158:b23ee177fd68 258 }
Kojto 158:b23ee177fd68 259
Kojto 158:b23ee177fd68 260 /**
Kojto 158:b23ee177fd68 261 * @brief Get the SysTick clock source
Kojto 158:b23ee177fd68 262 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Kojto 158:b23ee177fd68 263 * @retval Returned value can be one of the following values:
Kojto 158:b23ee177fd68 264 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
Kojto 158:b23ee177fd68 265 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
Kojto 158:b23ee177fd68 266 */
Kojto 158:b23ee177fd68 267 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
Kojto 158:b23ee177fd68 268 {
Kojto 158:b23ee177fd68 269 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 158:b23ee177fd68 270 }
Kojto 158:b23ee177fd68 271
Kojto 158:b23ee177fd68 272 /**
Kojto 158:b23ee177fd68 273 * @brief Enable SysTick exception request
Kojto 158:b23ee177fd68 274 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
Kojto 158:b23ee177fd68 275 * @retval None
Kojto 158:b23ee177fd68 276 */
Kojto 158:b23ee177fd68 277 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
Kojto 158:b23ee177fd68 278 {
Kojto 158:b23ee177fd68 279 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
Kojto 158:b23ee177fd68 280 }
Kojto 158:b23ee177fd68 281
Kojto 158:b23ee177fd68 282 /**
Kojto 158:b23ee177fd68 283 * @brief Disable SysTick exception request
Kojto 158:b23ee177fd68 284 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
Kojto 158:b23ee177fd68 285 * @retval None
Kojto 158:b23ee177fd68 286 */
Kojto 158:b23ee177fd68 287 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
Kojto 158:b23ee177fd68 288 {
Kojto 158:b23ee177fd68 289 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
Kojto 158:b23ee177fd68 290 }
Kojto 158:b23ee177fd68 291
Kojto 158:b23ee177fd68 292 /**
Kojto 158:b23ee177fd68 293 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
Kojto 158:b23ee177fd68 294 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Kojto 158:b23ee177fd68 295 * @retval State of bit (1 or 0).
Kojto 158:b23ee177fd68 296 */
Kojto 158:b23ee177fd68 297 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
Kojto 158:b23ee177fd68 298 {
Kojto 158:b23ee177fd68 299 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
Kojto 158:b23ee177fd68 300 }
Kojto 158:b23ee177fd68 301
Kojto 158:b23ee177fd68 302 /**
Kojto 158:b23ee177fd68 303 * @}
Kojto 158:b23ee177fd68 304 */
Kojto 158:b23ee177fd68 305
Kojto 158:b23ee177fd68 306 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
Kojto 158:b23ee177fd68 307 * @{
Kojto 158:b23ee177fd68 308 */
Kojto 158:b23ee177fd68 309
Kojto 158:b23ee177fd68 310 /**
Kojto 158:b23ee177fd68 311 * @brief Processor uses sleep as its low power mode
Kojto 158:b23ee177fd68 312 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Kojto 158:b23ee177fd68 313 * @retval None
Kojto 158:b23ee177fd68 314 */
Kojto 158:b23ee177fd68 315 __STATIC_INLINE void LL_LPM_EnableSleep(void)
Kojto 158:b23ee177fd68 316 {
Kojto 158:b23ee177fd68 317 /* Clear SLEEPDEEP bit of Cortex System Control Register */
Kojto 158:b23ee177fd68 318 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
Kojto 158:b23ee177fd68 319 }
Kojto 158:b23ee177fd68 320
Kojto 158:b23ee177fd68 321 /**
Kojto 158:b23ee177fd68 322 * @brief Processor uses deep sleep as its low power mode
Kojto 158:b23ee177fd68 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Kojto 158:b23ee177fd68 324 * @retval None
Kojto 158:b23ee177fd68 325 */
Kojto 158:b23ee177fd68 326 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
Kojto 158:b23ee177fd68 327 {
Kojto 158:b23ee177fd68 328 /* Set SLEEPDEEP bit of Cortex System Control Register */
Kojto 158:b23ee177fd68 329 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
Kojto 158:b23ee177fd68 330 }
Kojto 158:b23ee177fd68 331
Kojto 158:b23ee177fd68 332 /**
Kojto 158:b23ee177fd68 333 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
Kojto 158:b23ee177fd68 334 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
Kojto 158:b23ee177fd68 335 * empty main application.
Kojto 158:b23ee177fd68 336 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Kojto 158:b23ee177fd68 337 * @retval None
Kojto 158:b23ee177fd68 338 */
Kojto 158:b23ee177fd68 339 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
Kojto 158:b23ee177fd68 340 {
Kojto 158:b23ee177fd68 341 /* Set SLEEPONEXIT bit of Cortex System Control Register */
Kojto 158:b23ee177fd68 342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
Kojto 158:b23ee177fd68 343 }
Kojto 158:b23ee177fd68 344
Kojto 158:b23ee177fd68 345 /**
Kojto 158:b23ee177fd68 346 * @brief Do not sleep when returning to Thread mode.
Kojto 158:b23ee177fd68 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Kojto 158:b23ee177fd68 348 * @retval None
Kojto 158:b23ee177fd68 349 */
Kojto 158:b23ee177fd68 350 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
Kojto 158:b23ee177fd68 351 {
Kojto 158:b23ee177fd68 352 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
Kojto 158:b23ee177fd68 353 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
Kojto 158:b23ee177fd68 354 }
Kojto 158:b23ee177fd68 355
Kojto 158:b23ee177fd68 356 /**
Kojto 158:b23ee177fd68 357 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
Kojto 158:b23ee177fd68 358 * processor.
Kojto 158:b23ee177fd68 359 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Kojto 158:b23ee177fd68 360 * @retval None
Kojto 158:b23ee177fd68 361 */
Kojto 158:b23ee177fd68 362 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
Kojto 158:b23ee177fd68 363 {
Kojto 158:b23ee177fd68 364 /* Set SEVEONPEND bit of Cortex System Control Register */
Kojto 158:b23ee177fd68 365 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
Kojto 158:b23ee177fd68 366 }
Kojto 158:b23ee177fd68 367
Kojto 158:b23ee177fd68 368 /**
Kojto 158:b23ee177fd68 369 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
Kojto 158:b23ee177fd68 370 * excluded
Kojto 158:b23ee177fd68 371 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Kojto 158:b23ee177fd68 372 * @retval None
Kojto 158:b23ee177fd68 373 */
Kojto 158:b23ee177fd68 374 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
Kojto 158:b23ee177fd68 375 {
Kojto 158:b23ee177fd68 376 /* Clear SEVEONPEND bit of Cortex System Control Register */
Kojto 158:b23ee177fd68 377 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
Kojto 158:b23ee177fd68 378 }
Kojto 158:b23ee177fd68 379
Kojto 158:b23ee177fd68 380 /**
Kojto 158:b23ee177fd68 381 * @}
Kojto 158:b23ee177fd68 382 */
Kojto 158:b23ee177fd68 383
Kojto 158:b23ee177fd68 384 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
Kojto 158:b23ee177fd68 385 * @{
Kojto 158:b23ee177fd68 386 */
Kojto 158:b23ee177fd68 387
Kojto 158:b23ee177fd68 388 /**
Kojto 158:b23ee177fd68 389 * @brief Get Implementer code
Kojto 158:b23ee177fd68 390 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Kojto 158:b23ee177fd68 391 * @retval Value should be equal to 0x41 for ARM
Kojto 158:b23ee177fd68 392 */
Kojto 158:b23ee177fd68 393 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
Kojto 158:b23ee177fd68 394 {
Kojto 158:b23ee177fd68 395 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
Kojto 158:b23ee177fd68 396 }
Kojto 158:b23ee177fd68 397
Kojto 158:b23ee177fd68 398 /**
Kojto 158:b23ee177fd68 399 * @brief Get Variant number (The r value in the rnpn product revision identifier)
Kojto 158:b23ee177fd68 400 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
Kojto 158:b23ee177fd68 401 * @retval Value between 0 and 255 (0x0: revision 0)
Kojto 158:b23ee177fd68 402 */
Kojto 158:b23ee177fd68 403 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
Kojto 158:b23ee177fd68 404 {
Kojto 158:b23ee177fd68 405 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
Kojto 158:b23ee177fd68 406 }
Kojto 158:b23ee177fd68 407
Kojto 158:b23ee177fd68 408 /**
Kojto 158:b23ee177fd68 409 * @brief Get Architecture number
Kojto 158:b23ee177fd68 410 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
Kojto 158:b23ee177fd68 411 * @retval Value should be equal to 0xC for Cortex-M0+ devices
Kojto 158:b23ee177fd68 412 */
Kojto 158:b23ee177fd68 413 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
Kojto 158:b23ee177fd68 414 {
Kojto 158:b23ee177fd68 415 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
Kojto 158:b23ee177fd68 416 }
Kojto 158:b23ee177fd68 417
Kojto 158:b23ee177fd68 418 /**
Kojto 158:b23ee177fd68 419 * @brief Get Part number
Kojto 158:b23ee177fd68 420 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
Kojto 158:b23ee177fd68 421 * @retval Value should be equal to 0xC60 for Cortex-M0+
Kojto 158:b23ee177fd68 422 */
Kojto 158:b23ee177fd68 423 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
Kojto 158:b23ee177fd68 424 {
Kojto 158:b23ee177fd68 425 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
Kojto 158:b23ee177fd68 426 }
Kojto 158:b23ee177fd68 427
Kojto 158:b23ee177fd68 428 /**
Kojto 158:b23ee177fd68 429 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
Kojto 158:b23ee177fd68 430 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
Kojto 158:b23ee177fd68 431 * @retval Value between 0 and 255 (0x1: patch 1)
Kojto 158:b23ee177fd68 432 */
Kojto 158:b23ee177fd68 433 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
Kojto 158:b23ee177fd68 434 {
Kojto 158:b23ee177fd68 435 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
Kojto 158:b23ee177fd68 436 }
Kojto 158:b23ee177fd68 437
Kojto 158:b23ee177fd68 438 /**
Kojto 158:b23ee177fd68 439 * @}
Kojto 158:b23ee177fd68 440 */
Kojto 158:b23ee177fd68 441
Kojto 158:b23ee177fd68 442 #if __MPU_PRESENT
Kojto 158:b23ee177fd68 443 /** @defgroup CORTEX_LL_EF_MPU MPU
Kojto 158:b23ee177fd68 444 * @{
Kojto 158:b23ee177fd68 445 */
Kojto 158:b23ee177fd68 446
Kojto 158:b23ee177fd68 447 /**
Kojto 158:b23ee177fd68 448 * @brief Enable MPU with input options
Kojto 158:b23ee177fd68 449 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
Kojto 158:b23ee177fd68 450 * @param Options This parameter can be one of the following values:
Kojto 158:b23ee177fd68 451 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
Kojto 158:b23ee177fd68 452 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
Kojto 158:b23ee177fd68 453 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
Kojto 158:b23ee177fd68 454 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
Kojto 158:b23ee177fd68 455 * @retval None
Kojto 158:b23ee177fd68 456 */
Kojto 158:b23ee177fd68 457 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
Kojto 158:b23ee177fd68 458 {
Kojto 158:b23ee177fd68 459 /* Enable the MPU*/
Kojto 158:b23ee177fd68 460 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
Kojto 158:b23ee177fd68 461 /* Ensure MPU settings take effects */
Kojto 158:b23ee177fd68 462 __DSB();
Kojto 158:b23ee177fd68 463 /* Sequence instruction fetches using update settings */
Kojto 158:b23ee177fd68 464 __ISB();
Kojto 158:b23ee177fd68 465 }
Kojto 158:b23ee177fd68 466
Kojto 158:b23ee177fd68 467 /**
Kojto 158:b23ee177fd68 468 * @brief Disable MPU
Kojto 158:b23ee177fd68 469 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
Kojto 158:b23ee177fd68 470 * @retval None
Kojto 158:b23ee177fd68 471 */
Kojto 158:b23ee177fd68 472 __STATIC_INLINE void LL_MPU_Disable(void)
Kojto 158:b23ee177fd68 473 {
Kojto 158:b23ee177fd68 474 /* Make sure outstanding transfers are done */
Kojto 158:b23ee177fd68 475 __DMB();
Kojto 158:b23ee177fd68 476 /* Disable MPU*/
Kojto 158:b23ee177fd68 477 WRITE_REG(MPU->CTRL, 0U);
Kojto 158:b23ee177fd68 478 }
Kojto 158:b23ee177fd68 479
Kojto 158:b23ee177fd68 480 /**
Kojto 158:b23ee177fd68 481 * @brief Check if MPU is enabled or not
Kojto 158:b23ee177fd68 482 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
Kojto 158:b23ee177fd68 483 * @retval State of bit (1 or 0).
Kojto 158:b23ee177fd68 484 */
Kojto 158:b23ee177fd68 485 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
Kojto 158:b23ee177fd68 486 {
Kojto 158:b23ee177fd68 487 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
Kojto 158:b23ee177fd68 488 }
Kojto 158:b23ee177fd68 489
Kojto 158:b23ee177fd68 490 /**
Kojto 158:b23ee177fd68 491 * @brief Enable a MPU region
Kojto 158:b23ee177fd68 492 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
Kojto 158:b23ee177fd68 493 * @param Region This parameter can be one of the following values:
Kojto 158:b23ee177fd68 494 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 158:b23ee177fd68 495 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 158:b23ee177fd68 496 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 158:b23ee177fd68 497 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 158:b23ee177fd68 498 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 158:b23ee177fd68 499 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 158:b23ee177fd68 500 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 158:b23ee177fd68 501 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 158:b23ee177fd68 502 * @retval None
Kojto 158:b23ee177fd68 503 */
Kojto 158:b23ee177fd68 504 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
Kojto 158:b23ee177fd68 505 {
Kojto 158:b23ee177fd68 506 /* Set Region number */
Kojto 158:b23ee177fd68 507 WRITE_REG(MPU->RNR, Region);
Kojto 158:b23ee177fd68 508 /* Enable the MPU region */
Kojto 158:b23ee177fd68 509 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
Kojto 158:b23ee177fd68 510 }
Kojto 158:b23ee177fd68 511
Kojto 158:b23ee177fd68 512 /**
Kojto 158:b23ee177fd68 513 * @brief Configure and enable a region
Kojto 158:b23ee177fd68 514 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 515 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 516 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 517 * MPU_RASR XN LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 518 * MPU_RASR AP LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 519 * MPU_RASR S LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 520 * MPU_RASR C LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 521 * MPU_RASR B LL_MPU_ConfigRegion\n
Kojto 158:b23ee177fd68 522 * MPU_RASR SIZE LL_MPU_ConfigRegion
Kojto 158:b23ee177fd68 523 * @param Region This parameter can be one of the following values:
Kojto 158:b23ee177fd68 524 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 158:b23ee177fd68 525 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 158:b23ee177fd68 526 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 158:b23ee177fd68 527 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 158:b23ee177fd68 528 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 158:b23ee177fd68 529 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 158:b23ee177fd68 530 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 158:b23ee177fd68 531 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 158:b23ee177fd68 532 * @param Address Value of region base address
Kojto 158:b23ee177fd68 533 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Kojto 158:b23ee177fd68 534 * @param Attributes This parameter can be a combination of the following values:
Kojto 158:b23ee177fd68 535 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
Kojto 158:b23ee177fd68 536 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
Kojto 158:b23ee177fd68 537 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
Kojto 158:b23ee177fd68 538 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
Kojto 158:b23ee177fd68 539 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
Kojto 158:b23ee177fd68 540 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
Kojto 158:b23ee177fd68 541 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
Kojto 158:b23ee177fd68 542 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
Kojto 158:b23ee177fd68 543 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
Kojto 158:b23ee177fd68 544 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
Kojto 158:b23ee177fd68 545 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
Kojto 158:b23ee177fd68 546 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
Kojto 158:b23ee177fd68 547 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
Kojto 158:b23ee177fd68 548 * @retval None
Kojto 158:b23ee177fd68 549 */
Kojto 158:b23ee177fd68 550 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Kojto 158:b23ee177fd68 551 {
Kojto 158:b23ee177fd68 552 /* Set Region number */
Kojto 158:b23ee177fd68 553 WRITE_REG(MPU->RNR, Region);
Kojto 158:b23ee177fd68 554 /* Set base address */
Kojto 158:b23ee177fd68 555 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
Kojto 158:b23ee177fd68 556 /* Configure MPU */
Kojto 158:b23ee177fd68 557 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
Kojto 158:b23ee177fd68 558 }
Kojto 158:b23ee177fd68 559
Kojto 158:b23ee177fd68 560 /**
Kojto 158:b23ee177fd68 561 * @brief Disable a region
Kojto 158:b23ee177fd68 562 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
Kojto 158:b23ee177fd68 563 * MPU_RASR ENABLE LL_MPU_DisableRegion
Kojto 158:b23ee177fd68 564 * @param Region This parameter can be one of the following values:
Kojto 158:b23ee177fd68 565 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 158:b23ee177fd68 566 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 158:b23ee177fd68 567 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 158:b23ee177fd68 568 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 158:b23ee177fd68 569 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 158:b23ee177fd68 570 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 158:b23ee177fd68 571 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 158:b23ee177fd68 572 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 158:b23ee177fd68 573 * @retval None
Kojto 158:b23ee177fd68 574 */
Kojto 158:b23ee177fd68 575 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
Kojto 158:b23ee177fd68 576 {
Kojto 158:b23ee177fd68 577 /* Set Region number */
Kojto 158:b23ee177fd68 578 WRITE_REG(MPU->RNR, Region);
Kojto 158:b23ee177fd68 579 /* Disable the MPU region */
Kojto 158:b23ee177fd68 580 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
Kojto 158:b23ee177fd68 581 }
Kojto 158:b23ee177fd68 582
Kojto 158:b23ee177fd68 583 /**
Kojto 158:b23ee177fd68 584 * @}
Kojto 158:b23ee177fd68 585 */
Kojto 158:b23ee177fd68 586
Kojto 158:b23ee177fd68 587 #endif /* __MPU_PRESENT */
Kojto 158:b23ee177fd68 588 /**
Kojto 158:b23ee177fd68 589 * @}
Kojto 158:b23ee177fd68 590 */
Kojto 158:b23ee177fd68 591
Kojto 158:b23ee177fd68 592 /**
Kojto 158:b23ee177fd68 593 * @}
Kojto 158:b23ee177fd68 594 */
Kojto 158:b23ee177fd68 595
Kojto 158:b23ee177fd68 596 /**
Kojto 158:b23ee177fd68 597 * @}
Kojto 158:b23ee177fd68 598 */
Kojto 158:b23ee177fd68 599
Kojto 158:b23ee177fd68 600 #ifdef __cplusplus
Kojto 158:b23ee177fd68 601 }
Kojto 158:b23ee177fd68 602 #endif
Kojto 158:b23ee177fd68 603
Kojto 158:b23ee177fd68 604 #endif /* __STM32L0xx_LL_CORTEX_H */
Kojto 158:b23ee177fd68 605
Kojto 158:b23ee177fd68 606 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/