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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_bus.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 186:707f6e361f3e
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 158:b23ee177fd68 | 1 | /** |
| Kojto | 158:b23ee177fd68 | 2 | ****************************************************************************** |
| Kojto | 158:b23ee177fd68 | 3 | * @file stm32l0xx_ll_bus.h |
| Kojto | 158:b23ee177fd68 | 4 | * @author MCD Application Team |
| Kojto | 158:b23ee177fd68 | 5 | * @brief Header file of BUS LL module. |
| Kojto | 158:b23ee177fd68 | 6 | |
| Kojto | 158:b23ee177fd68 | 7 | @verbatim |
| Kojto | 158:b23ee177fd68 | 8 | ##### RCC Limitations ##### |
| Kojto | 158:b23ee177fd68 | 9 | ============================================================================== |
| Kojto | 158:b23ee177fd68 | 10 | [..] |
| Kojto | 158:b23ee177fd68 | 11 | A delay between an RCC peripheral clock enable and the effective peripheral |
| Kojto | 158:b23ee177fd68 | 12 | enabling should be taken into account in order to manage the peripheral read/write |
| Kojto | 158:b23ee177fd68 | 13 | from/to registers. |
| Kojto | 158:b23ee177fd68 | 14 | (+) This delay depends on the peripheral mapping. |
| Kojto | 158:b23ee177fd68 | 15 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| Kojto | 158:b23ee177fd68 | 16 | |
| Kojto | 158:b23ee177fd68 | 17 | [..] |
| Kojto | 158:b23ee177fd68 | 18 | Workarounds: |
| Kojto | 158:b23ee177fd68 | 19 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| Kojto | 158:b23ee177fd68 | 20 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| Kojto | 158:b23ee177fd68 | 21 | |
| Kojto | 158:b23ee177fd68 | 22 | @endverbatim |
| Kojto | 158:b23ee177fd68 | 23 | ****************************************************************************** |
| Kojto | 158:b23ee177fd68 | 24 | * @attention |
| Kojto | 158:b23ee177fd68 | 25 | * |
| Kojto | 158:b23ee177fd68 | 26 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| Kojto | 158:b23ee177fd68 | 27 | * |
| Kojto | 158:b23ee177fd68 | 28 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 158:b23ee177fd68 | 29 | * are permitted provided that the following conditions are met: |
| Kojto | 158:b23ee177fd68 | 30 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 158:b23ee177fd68 | 31 | * this list of conditions and the following disclaimer. |
| Kojto | 158:b23ee177fd68 | 32 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 158:b23ee177fd68 | 33 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 158:b23ee177fd68 | 34 | * and/or other materials provided with the distribution. |
| Kojto | 158:b23ee177fd68 | 35 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 158:b23ee177fd68 | 36 | * may be used to endorse or promote products derived from this software |
| Kojto | 158:b23ee177fd68 | 37 | * without specific prior written permission. |
| Kojto | 158:b23ee177fd68 | 38 | * |
| Kojto | 158:b23ee177fd68 | 39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 158:b23ee177fd68 | 40 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 158:b23ee177fd68 | 41 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 158:b23ee177fd68 | 42 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 158:b23ee177fd68 | 43 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 158:b23ee177fd68 | 44 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 158:b23ee177fd68 | 45 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 158:b23ee177fd68 | 46 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 158:b23ee177fd68 | 47 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 158:b23ee177fd68 | 48 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 158:b23ee177fd68 | 49 | * |
| Kojto | 158:b23ee177fd68 | 50 | ****************************************************************************** |
| Kojto | 158:b23ee177fd68 | 51 | */ |
| Kojto | 158:b23ee177fd68 | 52 | |
| Kojto | 158:b23ee177fd68 | 53 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 54 | #ifndef __STM32L0xx_LL_BUS_H |
| Kojto | 158:b23ee177fd68 | 55 | #define __STM32L0xx_LL_BUS_H |
| Kojto | 158:b23ee177fd68 | 56 | |
| Kojto | 158:b23ee177fd68 | 57 | #ifdef __cplusplus |
| Kojto | 158:b23ee177fd68 | 58 | extern "C" { |
| Kojto | 158:b23ee177fd68 | 59 | #endif |
| Kojto | 158:b23ee177fd68 | 60 | |
| Kojto | 158:b23ee177fd68 | 61 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 62 | #include "stm32l0xx.h" |
| Kojto | 158:b23ee177fd68 | 63 | |
| Kojto | 158:b23ee177fd68 | 64 | /** @addtogroup STM32L0xx_LL_Driver |
| Kojto | 158:b23ee177fd68 | 65 | * @{ |
| Kojto | 158:b23ee177fd68 | 66 | */ |
| Kojto | 158:b23ee177fd68 | 67 | |
| Kojto | 158:b23ee177fd68 | 68 | #if defined(RCC) |
| Kojto | 158:b23ee177fd68 | 69 | |
| Kojto | 158:b23ee177fd68 | 70 | /** @defgroup BUS_LL BUS |
| Kojto | 158:b23ee177fd68 | 71 | * @{ |
| Kojto | 158:b23ee177fd68 | 72 | */ |
| Kojto | 158:b23ee177fd68 | 73 | |
| Kojto | 158:b23ee177fd68 | 74 | /* Private types -------------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 75 | /* Private variables ---------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 76 | |
| Kojto | 158:b23ee177fd68 | 77 | /* Private constants ---------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 78 | |
| Kojto | 158:b23ee177fd68 | 79 | /* Private macros ------------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 80 | |
| Kojto | 158:b23ee177fd68 | 81 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 82 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 83 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| Kojto | 158:b23ee177fd68 | 84 | * @{ |
| Kojto | 158:b23ee177fd68 | 85 | */ |
| Kojto | 158:b23ee177fd68 | 86 | |
| Kojto | 158:b23ee177fd68 | 87 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| Kojto | 158:b23ee177fd68 | 88 | * @{ |
| Kojto | 158:b23ee177fd68 | 89 | */ |
| Kojto | 158:b23ee177fd68 | 90 | #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| Kojto | 158:b23ee177fd68 | 91 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ |
| Kojto | 158:b23ee177fd68 | 92 | #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ |
| Kojto | 158:b23ee177fd68 | 93 | #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable */ |
| Kojto | 158:b23ee177fd68 | 94 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ |
| Kojto | 158:b23ee177fd68 | 95 | #if defined(TSC) |
| Kojto | 158:b23ee177fd68 | 96 | #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ |
| Kojto | 158:b23ee177fd68 | 97 | #endif /*TSC*/ |
| Kojto | 158:b23ee177fd68 | 98 | #if defined(RNG) |
| Kojto | 158:b23ee177fd68 | 99 | #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ |
| Kojto | 158:b23ee177fd68 | 100 | #endif /*RNG*/ |
| Kojto | 158:b23ee177fd68 | 101 | #if defined(AES) |
| Kojto | 158:b23ee177fd68 | 102 | #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ |
| Kojto | 158:b23ee177fd68 | 103 | #endif /*AES*/ |
| Kojto | 158:b23ee177fd68 | 104 | /** |
| Kojto | 158:b23ee177fd68 | 105 | * @} |
| Kojto | 158:b23ee177fd68 | 106 | */ |
| Kojto | 158:b23ee177fd68 | 107 | |
| Kojto | 158:b23ee177fd68 | 108 | |
| Kojto | 158:b23ee177fd68 | 109 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| Kojto | 158:b23ee177fd68 | 110 | * @{ |
| Kojto | 158:b23ee177fd68 | 111 | */ |
| Kojto | 158:b23ee177fd68 | 112 | #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| Kojto | 158:b23ee177fd68 | 113 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ |
| Kojto | 158:b23ee177fd68 | 114 | #if defined(TIM3) |
| Kojto | 158:b23ee177fd68 | 115 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ |
| Kojto | 158:b23ee177fd68 | 116 | #endif |
| Kojto | 158:b23ee177fd68 | 117 | #if defined(TIM6) |
| Kojto | 158:b23ee177fd68 | 118 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ |
| Kojto | 158:b23ee177fd68 | 119 | #endif |
| Kojto | 158:b23ee177fd68 | 120 | #if defined(TIM7) |
| Kojto | 158:b23ee177fd68 | 121 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ |
| Kojto | 158:b23ee177fd68 | 122 | #endif |
| Kojto | 158:b23ee177fd68 | 123 | #if defined(LCD) |
| Kojto | 158:b23ee177fd68 | 124 | #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ |
| Kojto | 158:b23ee177fd68 | 125 | #endif /*LCD*/ |
| Kojto | 158:b23ee177fd68 | 126 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ |
| Kojto | 158:b23ee177fd68 | 127 | #if defined(SPI2) |
| Kojto | 158:b23ee177fd68 | 128 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ |
| Kojto | 158:b23ee177fd68 | 129 | #endif |
| Kojto | 158:b23ee177fd68 | 130 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ |
| Kojto | 158:b23ee177fd68 | 131 | #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ |
| Kojto | 158:b23ee177fd68 | 132 | #if defined(USART4) |
| Kojto | 158:b23ee177fd68 | 133 | #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ |
| Kojto | 158:b23ee177fd68 | 134 | #endif |
| Kojto | 158:b23ee177fd68 | 135 | #if defined(USART5) |
| Kojto | 158:b23ee177fd68 | 136 | #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ |
| Kojto | 158:b23ee177fd68 | 137 | #endif |
| Kojto | 158:b23ee177fd68 | 138 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ |
| Kojto | 158:b23ee177fd68 | 139 | #if defined(I2C2) |
| Kojto | 158:b23ee177fd68 | 140 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ |
| Kojto | 158:b23ee177fd68 | 141 | #endif |
| Kojto | 158:b23ee177fd68 | 142 | #if defined(USB) |
| Kojto | 158:b23ee177fd68 | 143 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ |
| Kojto | 158:b23ee177fd68 | 144 | #endif /*USB*/ |
| Kojto | 158:b23ee177fd68 | 145 | #if defined(CRS) |
| Kojto | 158:b23ee177fd68 | 146 | #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ |
| Kojto | 158:b23ee177fd68 | 147 | #endif /*CRS*/ |
| Kojto | 158:b23ee177fd68 | 148 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ |
| Kojto | 158:b23ee177fd68 | 149 | #if defined(DAC) |
| Kojto | 158:b23ee177fd68 | 150 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ |
| Kojto | 158:b23ee177fd68 | 151 | #endif |
| Kojto | 158:b23ee177fd68 | 152 | #if defined(I2C3) |
| Kojto | 158:b23ee177fd68 | 153 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ |
| Kojto | 158:b23ee177fd68 | 154 | #endif |
| Kojto | 158:b23ee177fd68 | 155 | #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ |
| Kojto | 158:b23ee177fd68 | 156 | /** |
| Kojto | 158:b23ee177fd68 | 157 | * @} |
| Kojto | 158:b23ee177fd68 | 158 | */ |
| Kojto | 158:b23ee177fd68 | 159 | |
| Kojto | 158:b23ee177fd68 | 160 | |
| Kojto | 158:b23ee177fd68 | 161 | |
| Kojto | 158:b23ee177fd68 | 162 | |
| Kojto | 158:b23ee177fd68 | 163 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| Kojto | 158:b23ee177fd68 | 164 | * @{ |
| Kojto | 158:b23ee177fd68 | 165 | */ |
| Kojto | 158:b23ee177fd68 | 166 | #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| Kojto | 158:b23ee177fd68 | 167 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ |
| Kojto | 158:b23ee177fd68 | 168 | #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ |
| Kojto | 158:b23ee177fd68 | 169 | #if defined(TIM22) |
| Kojto | 158:b23ee177fd68 | 170 | #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ |
| Kojto | 158:b23ee177fd68 | 171 | #endif |
| Kojto | 158:b23ee177fd68 | 172 | #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ |
| Kojto | 158:b23ee177fd68 | 173 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ |
| Kojto | 158:b23ee177fd68 | 174 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ |
| Kojto | 158:b23ee177fd68 | 175 | #if defined(USART1) |
| Kojto | 158:b23ee177fd68 | 176 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ |
| Kojto | 158:b23ee177fd68 | 177 | #endif |
| Kojto | 158:b23ee177fd68 | 178 | #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ |
| Kojto | 158:b23ee177fd68 | 179 | |
| Kojto | 158:b23ee177fd68 | 180 | /** |
| Kojto | 158:b23ee177fd68 | 181 | * @} |
| Kojto | 158:b23ee177fd68 | 182 | */ |
| Kojto | 158:b23ee177fd68 | 183 | |
| Kojto | 158:b23ee177fd68 | 184 | |
| Kojto | 158:b23ee177fd68 | 185 | |
| Kojto | 158:b23ee177fd68 | 186 | /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH |
| Kojto | 158:b23ee177fd68 | 187 | * @{ |
| Kojto | 158:b23ee177fd68 | 188 | */ |
| Kojto | 158:b23ee177fd68 | 189 | #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| Kojto | 158:b23ee177fd68 | 190 | #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ |
| Kojto | 158:b23ee177fd68 | 191 | #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ |
| Kojto | 158:b23ee177fd68 | 192 | #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ |
| Kojto | 158:b23ee177fd68 | 193 | #if defined(GPIOD) |
| Kojto | 158:b23ee177fd68 | 194 | #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ |
| Kojto | 158:b23ee177fd68 | 195 | #endif /*GPIOD*/ |
| Kojto | 158:b23ee177fd68 | 196 | #if defined(GPIOE) |
| Kojto | 158:b23ee177fd68 | 197 | #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ |
| Kojto | 158:b23ee177fd68 | 198 | #endif /*GPIOE*/ |
| Kojto | 158:b23ee177fd68 | 199 | #if defined(GPIOH) |
| Kojto | 158:b23ee177fd68 | 200 | #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ |
| Kojto | 158:b23ee177fd68 | 201 | #endif /*GPIOH*/ |
| Kojto | 158:b23ee177fd68 | 202 | /** |
| Kojto | 158:b23ee177fd68 | 203 | * @} |
| Kojto | 158:b23ee177fd68 | 204 | */ |
| Kojto | 158:b23ee177fd68 | 205 | |
| Kojto | 158:b23ee177fd68 | 206 | |
| Kojto | 158:b23ee177fd68 | 207 | /** |
| Kojto | 158:b23ee177fd68 | 208 | * @} |
| Kojto | 158:b23ee177fd68 | 209 | */ |
| Kojto | 158:b23ee177fd68 | 210 | |
| Kojto | 158:b23ee177fd68 | 211 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 212 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 158:b23ee177fd68 | 213 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| Kojto | 158:b23ee177fd68 | 214 | * @{ |
| Kojto | 158:b23ee177fd68 | 215 | */ |
| Kojto | 158:b23ee177fd68 | 216 | |
| Kojto | 158:b23ee177fd68 | 217 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| Kojto | 158:b23ee177fd68 | 218 | * @{ |
| Kojto | 158:b23ee177fd68 | 219 | */ |
| Kojto | 158:b23ee177fd68 | 220 | |
| Kojto | 158:b23ee177fd68 | 221 | /** |
| Kojto | 158:b23ee177fd68 | 222 | * @brief Enable AHB1 peripherals clock. |
| Kojto | 158:b23ee177fd68 | 223 | * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 224 | * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 225 | * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 226 | * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 227 | * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 228 | * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock |
| Kojto | 158:b23ee177fd68 | 229 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 230 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| Kojto | 158:b23ee177fd68 | 231 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| Kojto | 158:b23ee177fd68 | 232 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| Kojto | 158:b23ee177fd68 | 233 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| Kojto | 158:b23ee177fd68 | 234 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| Kojto | 158:b23ee177fd68 | 235 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| Kojto | 158:b23ee177fd68 | 236 | * |
| Kojto | 158:b23ee177fd68 | 237 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 238 | * @retval None |
| Kojto | 158:b23ee177fd68 | 239 | */ |
| Kojto | 158:b23ee177fd68 | 240 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 241 | { |
| Kojto | 158:b23ee177fd68 | 242 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 243 | SET_BIT(RCC->AHBENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 244 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 245 | tmpreg = READ_BIT(RCC->AHBENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 246 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 247 | } |
| Kojto | 158:b23ee177fd68 | 248 | |
| Kojto | 158:b23ee177fd68 | 249 | /** |
| Kojto | 158:b23ee177fd68 | 250 | * @brief Check if AHB1 peripheral clock is enabled or not |
| Kojto | 158:b23ee177fd68 | 251 | * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 252 | * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 253 | * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 254 | * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 255 | * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 256 | * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock |
| Kojto | 158:b23ee177fd68 | 257 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 258 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| Kojto | 158:b23ee177fd68 | 259 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| Kojto | 158:b23ee177fd68 | 260 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| Kojto | 158:b23ee177fd68 | 261 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| Kojto | 158:b23ee177fd68 | 262 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| Kojto | 158:b23ee177fd68 | 263 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| Kojto | 158:b23ee177fd68 | 264 | * |
| Kojto | 158:b23ee177fd68 | 265 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 266 | * @retval State of Periphs (1 or 0). |
| Kojto | 158:b23ee177fd68 | 267 | */ |
| Kojto | 158:b23ee177fd68 | 268 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 269 | { |
| Kojto | 158:b23ee177fd68 | 270 | return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); |
| Kojto | 158:b23ee177fd68 | 271 | } |
| Kojto | 158:b23ee177fd68 | 272 | |
| Kojto | 158:b23ee177fd68 | 273 | /** |
| Kojto | 158:b23ee177fd68 | 274 | * @brief Disable AHB1 peripherals clock. |
| Kojto | 158:b23ee177fd68 | 275 | * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 276 | * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 277 | * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 278 | * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 279 | * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 280 | * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock |
| Kojto | 158:b23ee177fd68 | 281 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 282 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| Kojto | 158:b23ee177fd68 | 283 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| Kojto | 158:b23ee177fd68 | 284 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| Kojto | 158:b23ee177fd68 | 285 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| Kojto | 158:b23ee177fd68 | 286 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| Kojto | 158:b23ee177fd68 | 287 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| Kojto | 158:b23ee177fd68 | 288 | * |
| Kojto | 158:b23ee177fd68 | 289 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 290 | * @retval None |
| Kojto | 158:b23ee177fd68 | 291 | */ |
| Kojto | 158:b23ee177fd68 | 292 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 293 | { |
| Kojto | 158:b23ee177fd68 | 294 | CLEAR_BIT(RCC->AHBENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 295 | } |
| Kojto | 158:b23ee177fd68 | 296 | |
| Kojto | 158:b23ee177fd68 | 297 | /** |
| Kojto | 158:b23ee177fd68 | 298 | * @brief Force AHB1 peripherals reset. |
| Kojto | 158:b23ee177fd68 | 299 | * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 300 | * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 301 | * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 302 | * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 303 | * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 304 | * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset |
| Kojto | 158:b23ee177fd68 | 305 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 306 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 307 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| Kojto | 158:b23ee177fd68 | 308 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| Kojto | 158:b23ee177fd68 | 309 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| Kojto | 158:b23ee177fd68 | 310 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| Kojto | 158:b23ee177fd68 | 311 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| Kojto | 158:b23ee177fd68 | 312 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| Kojto | 158:b23ee177fd68 | 313 | * |
| Kojto | 158:b23ee177fd68 | 314 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 315 | * @retval None |
| Kojto | 158:b23ee177fd68 | 316 | */ |
| Kojto | 158:b23ee177fd68 | 317 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 318 | { |
| Kojto | 158:b23ee177fd68 | 319 | SET_BIT(RCC->AHBRSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 320 | } |
| Kojto | 158:b23ee177fd68 | 321 | |
| Kojto | 158:b23ee177fd68 | 322 | /** |
| Kojto | 158:b23ee177fd68 | 323 | * @brief Release AHB1 peripherals reset. |
| Kojto | 158:b23ee177fd68 | 324 | * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 325 | * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 326 | * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 327 | * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 328 | * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 329 | * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset |
| Kojto | 158:b23ee177fd68 | 330 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 331 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 332 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| Kojto | 158:b23ee177fd68 | 333 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| Kojto | 158:b23ee177fd68 | 334 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| Kojto | 158:b23ee177fd68 | 335 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| Kojto | 158:b23ee177fd68 | 336 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| Kojto | 158:b23ee177fd68 | 337 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| Kojto | 158:b23ee177fd68 | 338 | * |
| Kojto | 158:b23ee177fd68 | 339 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 340 | * @retval None |
| Kojto | 158:b23ee177fd68 | 341 | */ |
| Kojto | 158:b23ee177fd68 | 342 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 343 | { |
| Kojto | 158:b23ee177fd68 | 344 | CLEAR_BIT(RCC->AHBRSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 345 | } |
| Kojto | 158:b23ee177fd68 | 346 | |
| Kojto | 158:b23ee177fd68 | 347 | /** |
| Kojto | 158:b23ee177fd68 | 348 | * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 349 | * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 350 | * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 351 | * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 352 | * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 353 | * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 354 | * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 355 | * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep |
| Kojto | 158:b23ee177fd68 | 356 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 357 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| Kojto | 158:b23ee177fd68 | 358 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| Kojto | 158:b23ee177fd68 | 359 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| Kojto | 158:b23ee177fd68 | 360 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| Kojto | 158:b23ee177fd68 | 361 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| Kojto | 158:b23ee177fd68 | 362 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| Kojto | 158:b23ee177fd68 | 363 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| Kojto | 158:b23ee177fd68 | 364 | * |
| Kojto | 158:b23ee177fd68 | 365 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 366 | * @retval None |
| Kojto | 158:b23ee177fd68 | 367 | */ |
| Kojto | 158:b23ee177fd68 | 368 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 369 | { |
| Kojto | 158:b23ee177fd68 | 370 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 371 | SET_BIT(RCC->AHBSMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 372 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 373 | tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 374 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 375 | } |
| Kojto | 158:b23ee177fd68 | 376 | |
| Kojto | 158:b23ee177fd68 | 377 | /** |
| Kojto | 158:b23ee177fd68 | 378 | * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 379 | * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 380 | * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 381 | * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 382 | * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 383 | * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 384 | * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 385 | * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep |
| Kojto | 158:b23ee177fd68 | 386 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 387 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| Kojto | 158:b23ee177fd68 | 388 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| Kojto | 158:b23ee177fd68 | 389 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| Kojto | 158:b23ee177fd68 | 390 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| Kojto | 158:b23ee177fd68 | 391 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| Kojto | 158:b23ee177fd68 | 392 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| Kojto | 158:b23ee177fd68 | 393 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| Kojto | 158:b23ee177fd68 | 394 | * |
| Kojto | 158:b23ee177fd68 | 395 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 396 | * @retval None |
| Kojto | 158:b23ee177fd68 | 397 | */ |
| Kojto | 158:b23ee177fd68 | 398 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 399 | { |
| Kojto | 158:b23ee177fd68 | 400 | CLEAR_BIT(RCC->AHBSMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 401 | } |
| Kojto | 158:b23ee177fd68 | 402 | |
| Kojto | 158:b23ee177fd68 | 403 | /** |
| Kojto | 158:b23ee177fd68 | 404 | * @} |
| Kojto | 158:b23ee177fd68 | 405 | */ |
| Kojto | 158:b23ee177fd68 | 406 | |
| Kojto | 158:b23ee177fd68 | 407 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| Kojto | 158:b23ee177fd68 | 408 | * @{ |
| Kojto | 158:b23ee177fd68 | 409 | */ |
| Kojto | 158:b23ee177fd68 | 410 | |
| Kojto | 158:b23ee177fd68 | 411 | /** |
| Kojto | 158:b23ee177fd68 | 412 | * @brief Enable APB1 peripherals clock. |
| Kojto | 158:b23ee177fd68 | 413 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 414 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 415 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 416 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 417 | * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 418 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 419 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 420 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 421 | * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 422 | * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 423 | * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 424 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 425 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 426 | * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 427 | * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 428 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 429 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 430 | * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 431 | * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock |
| Kojto | 158:b23ee177fd68 | 432 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 433 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| Kojto | 158:b23ee177fd68 | 434 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| Kojto | 158:b23ee177fd68 | 435 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| Kojto | 158:b23ee177fd68 | 436 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| Kojto | 158:b23ee177fd68 | 437 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| Kojto | 158:b23ee177fd68 | 438 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| Kojto | 158:b23ee177fd68 | 439 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| Kojto | 158:b23ee177fd68 | 440 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| Kojto | 158:b23ee177fd68 | 441 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| Kojto | 158:b23ee177fd68 | 442 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| Kojto | 158:b23ee177fd68 | 443 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| Kojto | 158:b23ee177fd68 | 444 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| Kojto | 158:b23ee177fd68 | 445 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| Kojto | 158:b23ee177fd68 | 446 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| Kojto | 158:b23ee177fd68 | 447 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| Kojto | 158:b23ee177fd68 | 448 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| Kojto | 158:b23ee177fd68 | 449 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| Kojto | 158:b23ee177fd68 | 450 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| Kojto | 158:b23ee177fd68 | 451 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| Kojto | 158:b23ee177fd68 | 452 | * |
| Kojto | 158:b23ee177fd68 | 453 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 454 | * @retval None |
| Kojto | 158:b23ee177fd68 | 455 | */ |
| Kojto | 158:b23ee177fd68 | 456 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 457 | { |
| Kojto | 158:b23ee177fd68 | 458 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 459 | SET_BIT(RCC->APB1ENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 460 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 461 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 462 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 463 | } |
| Kojto | 158:b23ee177fd68 | 464 | |
| Kojto | 158:b23ee177fd68 | 465 | /** |
| Kojto | 158:b23ee177fd68 | 466 | * @brief Check if APB1 peripheral clock is enabled or not |
| Kojto | 158:b23ee177fd68 | 467 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 468 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 469 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 470 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 471 | * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 472 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 473 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 474 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 475 | * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 476 | * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 477 | * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 478 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 479 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 480 | * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 481 | * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 482 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 483 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 484 | * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 485 | * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock |
| Kojto | 158:b23ee177fd68 | 486 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 487 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| Kojto | 158:b23ee177fd68 | 488 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| Kojto | 158:b23ee177fd68 | 489 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| Kojto | 158:b23ee177fd68 | 490 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| Kojto | 158:b23ee177fd68 | 491 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| Kojto | 158:b23ee177fd68 | 492 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| Kojto | 158:b23ee177fd68 | 493 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| Kojto | 158:b23ee177fd68 | 494 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| Kojto | 158:b23ee177fd68 | 495 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| Kojto | 158:b23ee177fd68 | 496 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| Kojto | 158:b23ee177fd68 | 497 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| Kojto | 158:b23ee177fd68 | 498 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| Kojto | 158:b23ee177fd68 | 499 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| Kojto | 158:b23ee177fd68 | 500 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| Kojto | 158:b23ee177fd68 | 501 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| Kojto | 158:b23ee177fd68 | 502 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| Kojto | 158:b23ee177fd68 | 503 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| Kojto | 158:b23ee177fd68 | 504 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| Kojto | 158:b23ee177fd68 | 505 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| Kojto | 158:b23ee177fd68 | 506 | * |
| Kojto | 158:b23ee177fd68 | 507 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 508 | * @retval State of Periphs (1 or 0). |
| Kojto | 158:b23ee177fd68 | 509 | */ |
| Kojto | 158:b23ee177fd68 | 510 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 511 | { |
| Kojto | 158:b23ee177fd68 | 512 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| Kojto | 158:b23ee177fd68 | 513 | } |
| Kojto | 158:b23ee177fd68 | 514 | |
| Kojto | 158:b23ee177fd68 | 515 | /** |
| Kojto | 158:b23ee177fd68 | 516 | * @brief Disable APB1 peripherals clock. |
| Kojto | 158:b23ee177fd68 | 517 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 518 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 519 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 520 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 521 | * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 522 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 523 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 524 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 525 | * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 526 | * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 527 | * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 528 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 529 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 530 | * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 531 | * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 532 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 533 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 534 | * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 535 | * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock |
| Kojto | 158:b23ee177fd68 | 536 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 537 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| Kojto | 158:b23ee177fd68 | 538 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| Kojto | 158:b23ee177fd68 | 539 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| Kojto | 158:b23ee177fd68 | 540 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| Kojto | 158:b23ee177fd68 | 541 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| Kojto | 158:b23ee177fd68 | 542 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| Kojto | 158:b23ee177fd68 | 543 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| Kojto | 158:b23ee177fd68 | 544 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| Kojto | 158:b23ee177fd68 | 545 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| Kojto | 158:b23ee177fd68 | 546 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| Kojto | 158:b23ee177fd68 | 547 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| Kojto | 158:b23ee177fd68 | 548 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| Kojto | 158:b23ee177fd68 | 549 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| Kojto | 158:b23ee177fd68 | 550 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| Kojto | 158:b23ee177fd68 | 551 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| Kojto | 158:b23ee177fd68 | 552 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| Kojto | 158:b23ee177fd68 | 553 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| Kojto | 158:b23ee177fd68 | 554 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| Kojto | 158:b23ee177fd68 | 555 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| Kojto | 158:b23ee177fd68 | 556 | * |
| Kojto | 158:b23ee177fd68 | 557 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 558 | * @retval None |
| Kojto | 158:b23ee177fd68 | 559 | */ |
| Kojto | 158:b23ee177fd68 | 560 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 561 | { |
| Kojto | 158:b23ee177fd68 | 562 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 563 | } |
| Kojto | 158:b23ee177fd68 | 564 | |
| Kojto | 158:b23ee177fd68 | 565 | /** |
| Kojto | 158:b23ee177fd68 | 566 | * @brief Force APB1 peripherals reset. |
| Kojto | 158:b23ee177fd68 | 567 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 568 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 569 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 570 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 571 | * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 572 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 573 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 574 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 575 | * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 576 | * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 577 | * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 578 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 579 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 580 | * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 581 | * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 582 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 583 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 584 | * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 585 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset |
| Kojto | 158:b23ee177fd68 | 586 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 587 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 588 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| Kojto | 158:b23ee177fd68 | 589 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| Kojto | 158:b23ee177fd68 | 590 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| Kojto | 158:b23ee177fd68 | 591 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| Kojto | 158:b23ee177fd68 | 592 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| Kojto | 158:b23ee177fd68 | 593 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| Kojto | 158:b23ee177fd68 | 594 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| Kojto | 158:b23ee177fd68 | 595 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| Kojto | 158:b23ee177fd68 | 596 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| Kojto | 158:b23ee177fd68 | 597 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| Kojto | 158:b23ee177fd68 | 598 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| Kojto | 158:b23ee177fd68 | 599 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| Kojto | 158:b23ee177fd68 | 600 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| Kojto | 158:b23ee177fd68 | 601 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| Kojto | 158:b23ee177fd68 | 602 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| Kojto | 158:b23ee177fd68 | 603 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| Kojto | 158:b23ee177fd68 | 604 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| Kojto | 158:b23ee177fd68 | 605 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| Kojto | 158:b23ee177fd68 | 606 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| Kojto | 158:b23ee177fd68 | 607 | * |
| Kojto | 158:b23ee177fd68 | 608 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 609 | * @retval None |
| Kojto | 158:b23ee177fd68 | 610 | */ |
| Kojto | 158:b23ee177fd68 | 611 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 612 | { |
| Kojto | 158:b23ee177fd68 | 613 | SET_BIT(RCC->APB1RSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 614 | } |
| Kojto | 158:b23ee177fd68 | 615 | |
| Kojto | 158:b23ee177fd68 | 616 | /** |
| Kojto | 158:b23ee177fd68 | 617 | * @brief Release APB1 peripherals reset. |
| Kojto | 158:b23ee177fd68 | 618 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 619 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 620 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 621 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 622 | * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 623 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 624 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 625 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 626 | * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 627 | * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 628 | * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 629 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 630 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 631 | * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 632 | * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 633 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 634 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 635 | * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 636 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset |
| Kojto | 158:b23ee177fd68 | 637 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 638 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 639 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| Kojto | 158:b23ee177fd68 | 640 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| Kojto | 158:b23ee177fd68 | 641 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| Kojto | 158:b23ee177fd68 | 642 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| Kojto | 158:b23ee177fd68 | 643 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| Kojto | 158:b23ee177fd68 | 644 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| Kojto | 158:b23ee177fd68 | 645 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| Kojto | 158:b23ee177fd68 | 646 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| Kojto | 158:b23ee177fd68 | 647 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| Kojto | 158:b23ee177fd68 | 648 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| Kojto | 158:b23ee177fd68 | 649 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| Kojto | 158:b23ee177fd68 | 650 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| Kojto | 158:b23ee177fd68 | 651 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| Kojto | 158:b23ee177fd68 | 652 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| Kojto | 158:b23ee177fd68 | 653 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| Kojto | 158:b23ee177fd68 | 654 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| Kojto | 158:b23ee177fd68 | 655 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| Kojto | 158:b23ee177fd68 | 656 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| Kojto | 158:b23ee177fd68 | 657 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| Kojto | 158:b23ee177fd68 | 658 | * |
| Kojto | 158:b23ee177fd68 | 659 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 660 | * @retval None |
| Kojto | 158:b23ee177fd68 | 661 | */ |
| Kojto | 158:b23ee177fd68 | 662 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 663 | { |
| Kojto | 158:b23ee177fd68 | 664 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 665 | } |
| Kojto | 158:b23ee177fd68 | 666 | |
| Kojto | 158:b23ee177fd68 | 667 | /** |
| Kojto | 158:b23ee177fd68 | 668 | * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 669 | * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 670 | * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 671 | * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 672 | * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 673 | * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 674 | * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 675 | * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 676 | * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 677 | * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 678 | * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 679 | * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 680 | * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 681 | * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 682 | * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 683 | * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 684 | * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 685 | * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 686 | * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 687 | * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep |
| Kojto | 158:b23ee177fd68 | 688 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 689 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| Kojto | 158:b23ee177fd68 | 690 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| Kojto | 158:b23ee177fd68 | 691 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| Kojto | 158:b23ee177fd68 | 692 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| Kojto | 158:b23ee177fd68 | 693 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| Kojto | 158:b23ee177fd68 | 694 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| Kojto | 158:b23ee177fd68 | 695 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| Kojto | 158:b23ee177fd68 | 696 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| Kojto | 158:b23ee177fd68 | 697 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| Kojto | 158:b23ee177fd68 | 698 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| Kojto | 158:b23ee177fd68 | 699 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| Kojto | 158:b23ee177fd68 | 700 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| Kojto | 158:b23ee177fd68 | 701 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| Kojto | 158:b23ee177fd68 | 702 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| Kojto | 158:b23ee177fd68 | 703 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| Kojto | 158:b23ee177fd68 | 704 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| Kojto | 158:b23ee177fd68 | 705 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| Kojto | 158:b23ee177fd68 | 706 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| Kojto | 158:b23ee177fd68 | 707 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| Kojto | 158:b23ee177fd68 | 708 | * |
| Kojto | 158:b23ee177fd68 | 709 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 710 | * @retval None |
| Kojto | 158:b23ee177fd68 | 711 | */ |
| Kojto | 158:b23ee177fd68 | 712 | __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 713 | { |
| Kojto | 158:b23ee177fd68 | 714 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 715 | SET_BIT(RCC->APB1SMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 716 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 717 | tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 718 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 719 | } |
| Kojto | 158:b23ee177fd68 | 720 | |
| Kojto | 158:b23ee177fd68 | 721 | /** |
| Kojto | 158:b23ee177fd68 | 722 | * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 723 | * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 724 | * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 725 | * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 726 | * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 727 | * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 728 | * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 729 | * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 730 | * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 731 | * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 732 | * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 733 | * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 734 | * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 735 | * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 736 | * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 737 | * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 738 | * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 739 | * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 740 | * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 741 | * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep |
| Kojto | 158:b23ee177fd68 | 742 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 743 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| Kojto | 158:b23ee177fd68 | 744 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| Kojto | 158:b23ee177fd68 | 745 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| Kojto | 158:b23ee177fd68 | 746 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| Kojto | 158:b23ee177fd68 | 747 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| Kojto | 158:b23ee177fd68 | 748 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| Kojto | 158:b23ee177fd68 | 749 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| Kojto | 158:b23ee177fd68 | 750 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| Kojto | 158:b23ee177fd68 | 751 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| Kojto | 158:b23ee177fd68 | 752 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| Kojto | 158:b23ee177fd68 | 753 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| Kojto | 158:b23ee177fd68 | 754 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| Kojto | 158:b23ee177fd68 | 755 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| Kojto | 158:b23ee177fd68 | 756 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| Kojto | 158:b23ee177fd68 | 757 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| Kojto | 158:b23ee177fd68 | 758 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| Kojto | 158:b23ee177fd68 | 759 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| Kojto | 158:b23ee177fd68 | 760 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| Kojto | 158:b23ee177fd68 | 761 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| Kojto | 158:b23ee177fd68 | 762 | * |
| Kojto | 158:b23ee177fd68 | 763 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 764 | * @retval None |
| Kojto | 158:b23ee177fd68 | 765 | */ |
| Kojto | 158:b23ee177fd68 | 766 | __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 767 | { |
| Kojto | 158:b23ee177fd68 | 768 | CLEAR_BIT(RCC->APB1SMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 769 | } |
| Kojto | 158:b23ee177fd68 | 770 | |
| Kojto | 158:b23ee177fd68 | 771 | /** |
| Kojto | 158:b23ee177fd68 | 772 | * @} |
| Kojto | 158:b23ee177fd68 | 773 | */ |
| Kojto | 158:b23ee177fd68 | 774 | |
| Kojto | 158:b23ee177fd68 | 775 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| Kojto | 158:b23ee177fd68 | 776 | * @{ |
| Kojto | 158:b23ee177fd68 | 777 | */ |
| Kojto | 158:b23ee177fd68 | 778 | |
| Kojto | 158:b23ee177fd68 | 779 | /** |
| Kojto | 158:b23ee177fd68 | 780 | * @brief Enable APB2 peripherals clock. |
| Kojto | 158:b23ee177fd68 | 781 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 782 | * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 783 | * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 784 | * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 785 | * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 786 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 787 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 788 | * APB2ENR DBGEN LL_APB2_GRP1_EnableClock |
| Kojto | 158:b23ee177fd68 | 789 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 790 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| Kojto | 158:b23ee177fd68 | 791 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| Kojto | 158:b23ee177fd68 | 792 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| Kojto | 158:b23ee177fd68 | 793 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| Kojto | 158:b23ee177fd68 | 794 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| Kojto | 158:b23ee177fd68 | 795 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| Kojto | 158:b23ee177fd68 | 796 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| Kojto | 158:b23ee177fd68 | 797 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| Kojto | 158:b23ee177fd68 | 798 | * |
| Kojto | 158:b23ee177fd68 | 799 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 800 | * @retval None |
| Kojto | 158:b23ee177fd68 | 801 | */ |
| Kojto | 158:b23ee177fd68 | 802 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 803 | { |
| Kojto | 158:b23ee177fd68 | 804 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 805 | SET_BIT(RCC->APB2ENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 806 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 807 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 808 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 809 | } |
| Kojto | 158:b23ee177fd68 | 810 | |
| Kojto | 158:b23ee177fd68 | 811 | /** |
| Kojto | 158:b23ee177fd68 | 812 | * @brief Check if APB2 peripheral clock is enabled or not |
| Kojto | 158:b23ee177fd68 | 813 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 814 | * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 815 | * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 816 | * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 817 | * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 818 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 819 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 820 | * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock |
| Kojto | 158:b23ee177fd68 | 821 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 822 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| Kojto | 158:b23ee177fd68 | 823 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| Kojto | 158:b23ee177fd68 | 824 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| Kojto | 158:b23ee177fd68 | 825 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| Kojto | 158:b23ee177fd68 | 826 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| Kojto | 158:b23ee177fd68 | 827 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| Kojto | 158:b23ee177fd68 | 828 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| Kojto | 158:b23ee177fd68 | 829 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| Kojto | 158:b23ee177fd68 | 830 | * |
| Kojto | 158:b23ee177fd68 | 831 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 832 | * @retval State of Periphs (1 or 0). |
| Kojto | 158:b23ee177fd68 | 833 | */ |
| Kojto | 158:b23ee177fd68 | 834 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 835 | { |
| Kojto | 158:b23ee177fd68 | 836 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| Kojto | 158:b23ee177fd68 | 837 | } |
| Kojto | 158:b23ee177fd68 | 838 | |
| Kojto | 158:b23ee177fd68 | 839 | /** |
| Kojto | 158:b23ee177fd68 | 840 | * @brief Disable APB2 peripherals clock. |
| Kojto | 158:b23ee177fd68 | 841 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 842 | * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 843 | * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 844 | * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 845 | * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 846 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 847 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 848 | * APB2ENR DBGEN LL_APB2_GRP1_DisableClock |
| Kojto | 158:b23ee177fd68 | 849 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 850 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| Kojto | 158:b23ee177fd68 | 851 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| Kojto | 158:b23ee177fd68 | 852 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| Kojto | 158:b23ee177fd68 | 853 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| Kojto | 158:b23ee177fd68 | 854 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| Kojto | 158:b23ee177fd68 | 855 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| Kojto | 158:b23ee177fd68 | 856 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| Kojto | 158:b23ee177fd68 | 857 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| Kojto | 158:b23ee177fd68 | 858 | * |
| Kojto | 158:b23ee177fd68 | 859 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 860 | * @retval None |
| Kojto | 158:b23ee177fd68 | 861 | */ |
| Kojto | 158:b23ee177fd68 | 862 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 863 | { |
| Kojto | 158:b23ee177fd68 | 864 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 865 | } |
| Kojto | 158:b23ee177fd68 | 866 | |
| Kojto | 158:b23ee177fd68 | 867 | /** |
| Kojto | 158:b23ee177fd68 | 868 | * @brief Force APB2 peripherals reset. |
| Kojto | 158:b23ee177fd68 | 869 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 870 | * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 871 | * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 872 | * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 873 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 874 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 875 | * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset |
| Kojto | 158:b23ee177fd68 | 876 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 877 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 878 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| Kojto | 158:b23ee177fd68 | 879 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| Kojto | 158:b23ee177fd68 | 880 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| Kojto | 158:b23ee177fd68 | 881 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| Kojto | 158:b23ee177fd68 | 882 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| Kojto | 158:b23ee177fd68 | 883 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| Kojto | 158:b23ee177fd68 | 884 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| Kojto | 158:b23ee177fd68 | 885 | * |
| Kojto | 158:b23ee177fd68 | 886 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 887 | * @retval None |
| Kojto | 158:b23ee177fd68 | 888 | */ |
| Kojto | 158:b23ee177fd68 | 889 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 890 | { |
| Kojto | 158:b23ee177fd68 | 891 | SET_BIT(RCC->APB2RSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 892 | } |
| Kojto | 158:b23ee177fd68 | 893 | |
| Kojto | 158:b23ee177fd68 | 894 | /** |
| Kojto | 158:b23ee177fd68 | 895 | * @brief Release APB2 peripherals reset. |
| Kojto | 158:b23ee177fd68 | 896 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 897 | * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 898 | * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 899 | * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 900 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 901 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 902 | * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset |
| Kojto | 158:b23ee177fd68 | 903 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 904 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 905 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| Kojto | 158:b23ee177fd68 | 906 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| Kojto | 158:b23ee177fd68 | 907 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| Kojto | 158:b23ee177fd68 | 908 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| Kojto | 158:b23ee177fd68 | 909 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| Kojto | 158:b23ee177fd68 | 910 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| Kojto | 158:b23ee177fd68 | 911 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| Kojto | 158:b23ee177fd68 | 912 | * |
| Kojto | 158:b23ee177fd68 | 913 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 914 | * @retval None |
| Kojto | 158:b23ee177fd68 | 915 | */ |
| Kojto | 158:b23ee177fd68 | 916 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 917 | { |
| Kojto | 158:b23ee177fd68 | 918 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 919 | } |
| Kojto | 158:b23ee177fd68 | 920 | |
| Kojto | 158:b23ee177fd68 | 921 | /** |
| Kojto | 158:b23ee177fd68 | 922 | * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 923 | * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 924 | * APB2SMENR TIM21SMEN LL_APB2_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 925 | * APB2SMENR TIM22SMEN LL_APB2_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 926 | * APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 927 | * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 928 | * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 929 | * APB2SMENR DBGSMEN LL_APB2_GRP1_EnableClockSleep |
| Kojto | 158:b23ee177fd68 | 930 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 931 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| Kojto | 158:b23ee177fd68 | 932 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| Kojto | 158:b23ee177fd68 | 933 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| Kojto | 158:b23ee177fd68 | 934 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| Kojto | 158:b23ee177fd68 | 935 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| Kojto | 158:b23ee177fd68 | 936 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| Kojto | 158:b23ee177fd68 | 937 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| Kojto | 158:b23ee177fd68 | 938 | * |
| Kojto | 158:b23ee177fd68 | 939 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 940 | * @retval None |
| Kojto | 158:b23ee177fd68 | 941 | */ |
| Kojto | 158:b23ee177fd68 | 942 | __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 943 | { |
| Kojto | 158:b23ee177fd68 | 944 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 945 | SET_BIT(RCC->APB2SMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 946 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 947 | tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 948 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 949 | } |
| Kojto | 158:b23ee177fd68 | 950 | |
| Kojto | 158:b23ee177fd68 | 951 | /** |
| Kojto | 158:b23ee177fd68 | 952 | * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 953 | * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 954 | * APB2SMENR TIM21SMEN LL_APB2_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 955 | * APB2SMENR TIM22SMEN LL_APB2_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 956 | * APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 957 | * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 958 | * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 959 | * APB2SMENR DBGSMEN LL_APB2_GRP1_DisableClockSleep |
| Kojto | 158:b23ee177fd68 | 960 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 961 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| Kojto | 158:b23ee177fd68 | 962 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| Kojto | 158:b23ee177fd68 | 963 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| Kojto | 158:b23ee177fd68 | 964 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| Kojto | 158:b23ee177fd68 | 965 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| Kojto | 158:b23ee177fd68 | 966 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| Kojto | 158:b23ee177fd68 | 967 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| Kojto | 158:b23ee177fd68 | 968 | * |
| Kojto | 158:b23ee177fd68 | 969 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 970 | * @retval None |
| Kojto | 158:b23ee177fd68 | 971 | */ |
| Kojto | 158:b23ee177fd68 | 972 | __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 973 | { |
| Kojto | 158:b23ee177fd68 | 974 | CLEAR_BIT(RCC->APB2SMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 975 | } |
| Kojto | 158:b23ee177fd68 | 976 | |
| Kojto | 158:b23ee177fd68 | 977 | /** |
| Kojto | 158:b23ee177fd68 | 978 | * @} |
| Kojto | 158:b23ee177fd68 | 979 | */ |
| Kojto | 158:b23ee177fd68 | 980 | /** @defgroup BUS_LL_EF_IOP IOP |
| Kojto | 158:b23ee177fd68 | 981 | * @{ |
| Kojto | 158:b23ee177fd68 | 982 | */ |
| Kojto | 158:b23ee177fd68 | 983 | |
| Kojto | 158:b23ee177fd68 | 984 | /** |
| Kojto | 158:b23ee177fd68 | 985 | * @brief Enable IOP peripherals clock. |
| Kojto | 158:b23ee177fd68 | 986 | * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 987 | * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 988 | * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 989 | * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 990 | * IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n |
| Kojto | 158:b23ee177fd68 | 991 | * IOPENR GPIOHEN LL_IOP_GRP1_EnableClock |
| Kojto | 158:b23ee177fd68 | 992 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 993 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| Kojto | 158:b23ee177fd68 | 994 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| Kojto | 158:b23ee177fd68 | 995 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| Kojto | 158:b23ee177fd68 | 996 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| Kojto | 158:b23ee177fd68 | 997 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| Kojto | 158:b23ee177fd68 | 998 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| Kojto | 158:b23ee177fd68 | 999 | * |
| Kojto | 158:b23ee177fd68 | 1000 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 1001 | * @retval None |
| Kojto | 158:b23ee177fd68 | 1002 | */ |
| Kojto | 158:b23ee177fd68 | 1003 | __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 1004 | { |
| Kojto | 158:b23ee177fd68 | 1005 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 1006 | SET_BIT(RCC->IOPENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1007 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 1008 | tmpreg = READ_BIT(RCC->IOPENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1009 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 1010 | } |
| Kojto | 158:b23ee177fd68 | 1011 | |
| Kojto | 158:b23ee177fd68 | 1012 | /** |
| Kojto | 158:b23ee177fd68 | 1013 | * @brief Check if IOP peripheral clock is enabled or not |
| Kojto | 158:b23ee177fd68 | 1014 | * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 1015 | * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 1016 | * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 1017 | * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 1018 | * IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n |
| Kojto | 158:b23ee177fd68 | 1019 | * IOPENR GPIOHEN LL_IOP_GRP1_IsEnabledClock |
| Kojto | 158:b23ee177fd68 | 1020 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 1021 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| Kojto | 158:b23ee177fd68 | 1022 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| Kojto | 158:b23ee177fd68 | 1023 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| Kojto | 158:b23ee177fd68 | 1024 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| Kojto | 158:b23ee177fd68 | 1025 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| Kojto | 158:b23ee177fd68 | 1026 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| Kojto | 158:b23ee177fd68 | 1027 | * |
| Kojto | 158:b23ee177fd68 | 1028 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 1029 | * @retval State of Periphs (1 or 0). |
| Kojto | 158:b23ee177fd68 | 1030 | */ |
| Kojto | 158:b23ee177fd68 | 1031 | __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 1032 | { |
| Kojto | 158:b23ee177fd68 | 1033 | return (READ_BIT(RCC->IOPENR, Periphs) == Periphs); |
| Kojto | 158:b23ee177fd68 | 1034 | } |
| Kojto | 158:b23ee177fd68 | 1035 | |
| Kojto | 158:b23ee177fd68 | 1036 | /** |
| Kojto | 158:b23ee177fd68 | 1037 | * @brief Disable IOP peripherals clock. |
| Kojto | 158:b23ee177fd68 | 1038 | * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 1039 | * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 1040 | * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 1041 | * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 1042 | * IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n |
| Kojto | 158:b23ee177fd68 | 1043 | * IOPENR GPIOHEN LL_IOP_GRP1_DisableClock |
| Kojto | 158:b23ee177fd68 | 1044 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 1045 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| Kojto | 158:b23ee177fd68 | 1046 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| Kojto | 158:b23ee177fd68 | 1047 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| Kojto | 158:b23ee177fd68 | 1048 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| Kojto | 158:b23ee177fd68 | 1049 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| Kojto | 158:b23ee177fd68 | 1050 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| Kojto | 158:b23ee177fd68 | 1051 | * |
| Kojto | 158:b23ee177fd68 | 1052 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 1053 | * @retval None |
| Kojto | 158:b23ee177fd68 | 1054 | */ |
| Kojto | 158:b23ee177fd68 | 1055 | __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 1056 | { |
| Kojto | 158:b23ee177fd68 | 1057 | CLEAR_BIT(RCC->IOPENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1058 | } |
| Kojto | 158:b23ee177fd68 | 1059 | |
| Kojto | 158:b23ee177fd68 | 1060 | /** |
| Kojto | 158:b23ee177fd68 | 1061 | * @brief Disable IOP peripherals clock. |
| Kojto | 158:b23ee177fd68 | 1062 | * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 1063 | * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 1064 | * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 1065 | * IOPRSTR GPIODSMEN LL_IOP_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 1066 | * IOPRSTR GPIOESMEN LL_IOP_GRP1_ForceReset\n |
| Kojto | 158:b23ee177fd68 | 1067 | * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ForceReset |
| Kojto | 158:b23ee177fd68 | 1068 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 1069 | * @arg @ref LL_IOP_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 1070 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| Kojto | 158:b23ee177fd68 | 1071 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| Kojto | 158:b23ee177fd68 | 1072 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| Kojto | 158:b23ee177fd68 | 1073 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| Kojto | 158:b23ee177fd68 | 1074 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| Kojto | 158:b23ee177fd68 | 1075 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| Kojto | 158:b23ee177fd68 | 1076 | * |
| Kojto | 158:b23ee177fd68 | 1077 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 1078 | * @retval None |
| Kojto | 158:b23ee177fd68 | 1079 | */ |
| Kojto | 158:b23ee177fd68 | 1080 | __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 1081 | { |
| Kojto | 158:b23ee177fd68 | 1082 | SET_BIT(RCC->IOPRSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1083 | } |
| Kojto | 158:b23ee177fd68 | 1084 | |
| Kojto | 158:b23ee177fd68 | 1085 | /** |
| Kojto | 158:b23ee177fd68 | 1086 | * @brief Release IOP peripherals reset. |
| Kojto | 158:b23ee177fd68 | 1087 | * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 1088 | * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 1089 | * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 1090 | * IOPRSTR GPIODSMEN LL_IOP_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 1091 | * IOPRSTR GPIOESMEN LL_IOP_GRP1_ReleaseReset\n |
| Kojto | 158:b23ee177fd68 | 1092 | * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ReleaseReset |
| Kojto | 158:b23ee177fd68 | 1093 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 1094 | * @arg @ref LL_IOP_GRP1_PERIPH_ALL |
| Kojto | 158:b23ee177fd68 | 1095 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| Kojto | 158:b23ee177fd68 | 1096 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| Kojto | 158:b23ee177fd68 | 1097 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| Kojto | 158:b23ee177fd68 | 1098 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| Kojto | 158:b23ee177fd68 | 1099 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| Kojto | 158:b23ee177fd68 | 1100 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| Kojto | 158:b23ee177fd68 | 1101 | * |
| Kojto | 158:b23ee177fd68 | 1102 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 1103 | * @retval None |
| Kojto | 158:b23ee177fd68 | 1104 | */ |
| Kojto | 158:b23ee177fd68 | 1105 | __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 1106 | { |
| Kojto | 158:b23ee177fd68 | 1107 | CLEAR_BIT(RCC->IOPRSTR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1108 | } |
| Kojto | 158:b23ee177fd68 | 1109 | |
| Kojto | 158:b23ee177fd68 | 1110 | /** |
| Kojto | 158:b23ee177fd68 | 1111 | * @brief Enable IOP peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 1112 | * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1113 | * IOPSMENR GPIOBRST LL_IOP_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1114 | * IOPSMENR GPIOCRST LL_IOP_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1115 | * IOPSMENR GPIODRST LL_IOP_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1116 | * IOPSMENR GPIOERST LL_IOP_GRP1_EnableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1117 | * IOPSMENR GPIOHRST LL_IOP_GRP1_EnableClockSleep |
| Kojto | 158:b23ee177fd68 | 1118 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 1119 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| Kojto | 158:b23ee177fd68 | 1120 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| Kojto | 158:b23ee177fd68 | 1121 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| Kojto | 158:b23ee177fd68 | 1122 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| Kojto | 158:b23ee177fd68 | 1123 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| Kojto | 158:b23ee177fd68 | 1124 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| Kojto | 158:b23ee177fd68 | 1125 | * |
| Kojto | 158:b23ee177fd68 | 1126 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 1127 | * @retval None |
| Kojto | 158:b23ee177fd68 | 1128 | */ |
| Kojto | 158:b23ee177fd68 | 1129 | __STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 1130 | { |
| Kojto | 158:b23ee177fd68 | 1131 | __IO uint32_t tmpreg; |
| Kojto | 158:b23ee177fd68 | 1132 | SET_BIT(RCC->IOPSMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1133 | /* Delay after an RCC peripheral clock enabling */ |
| Kojto | 158:b23ee177fd68 | 1134 | tmpreg = READ_BIT(RCC->IOPSMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1135 | (void)tmpreg; |
| Kojto | 158:b23ee177fd68 | 1136 | } |
| Kojto | 158:b23ee177fd68 | 1137 | |
| Kojto | 158:b23ee177fd68 | 1138 | /** |
| Kojto | 158:b23ee177fd68 | 1139 | * @brief Disable IOP peripherals clock during Low Power (Sleep) mode. |
| Kojto | 158:b23ee177fd68 | 1140 | * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1141 | * IOPSMENR GPIOBRST LL_IOP_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1142 | * IOPSMENR GPIOCRST LL_IOP_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1143 | * IOPSMENR GPIODRST LL_IOP_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1144 | * IOPSMENR GPIOERST LL_IOP_GRP1_DisableClockSleep\n |
| Kojto | 158:b23ee177fd68 | 1145 | * IOPSMENR GPIOHRST LL_IOP_GRP1_DisableClockSleep |
| Kojto | 158:b23ee177fd68 | 1146 | * @param Periphs This parameter can be a combination of the following values: |
| Kojto | 158:b23ee177fd68 | 1147 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| Kojto | 158:b23ee177fd68 | 1148 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| Kojto | 158:b23ee177fd68 | 1149 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| Kojto | 158:b23ee177fd68 | 1150 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| Kojto | 158:b23ee177fd68 | 1151 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| Kojto | 158:b23ee177fd68 | 1152 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| Kojto | 158:b23ee177fd68 | 1153 | * |
| Kojto | 158:b23ee177fd68 | 1154 | * (*) value not defined in all devices. |
| Kojto | 158:b23ee177fd68 | 1155 | * @retval None |
| Kojto | 158:b23ee177fd68 | 1156 | */ |
| Kojto | 158:b23ee177fd68 | 1157 | __STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs) |
| Kojto | 158:b23ee177fd68 | 1158 | { |
| Kojto | 158:b23ee177fd68 | 1159 | CLEAR_BIT(RCC->IOPSMENR, Periphs); |
| Kojto | 158:b23ee177fd68 | 1160 | } |
| Kojto | 158:b23ee177fd68 | 1161 | |
| Kojto | 158:b23ee177fd68 | 1162 | /** |
| Kojto | 158:b23ee177fd68 | 1163 | * @} |
| Kojto | 158:b23ee177fd68 | 1164 | */ |
| Kojto | 158:b23ee177fd68 | 1165 | |
| Kojto | 158:b23ee177fd68 | 1166 | |
| Kojto | 158:b23ee177fd68 | 1167 | /** |
| Kojto | 158:b23ee177fd68 | 1168 | * @} |
| Kojto | 158:b23ee177fd68 | 1169 | */ |
| Kojto | 158:b23ee177fd68 | 1170 | |
| Kojto | 158:b23ee177fd68 | 1171 | /** |
| Kojto | 158:b23ee177fd68 | 1172 | * @} |
| Kojto | 158:b23ee177fd68 | 1173 | */ |
| Kojto | 158:b23ee177fd68 | 1174 | |
| Kojto | 158:b23ee177fd68 | 1175 | #endif /* defined(RCC) */ |
| Kojto | 158:b23ee177fd68 | 1176 | |
| Kojto | 158:b23ee177fd68 | 1177 | /** |
| Kojto | 158:b23ee177fd68 | 1178 | * @} |
| Kojto | 158:b23ee177fd68 | 1179 | */ |
| Kojto | 158:b23ee177fd68 | 1180 | |
| Kojto | 158:b23ee177fd68 | 1181 | #ifdef __cplusplus |
| Kojto | 158:b23ee177fd68 | 1182 | } |
| Kojto | 158:b23ee177fd68 | 1183 | #endif |
| Kojto | 158:b23ee177fd68 | 1184 | |
| Kojto | 158:b23ee177fd68 | 1185 | #endif /* __STM32L0xx_LL_BUS_H */ |
| Kojto | 158:b23ee177fd68 | 1186 | |
| Kojto | 158:b23ee177fd68 | 1187 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
