mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 186:707f6e361f3e
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32l0xx_hal_tim_ex.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief Header file of TIM HAL module. |
<> | 144:ef7eb2e8f9f7 | 6 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 7 | * @attention |
<> | 144:ef7eb2e8f9f7 | 8 | * |
<> | 144:ef7eb2e8f9f7 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 12 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 14 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 17 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 19 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 20 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 32 | * |
<> | 144:ef7eb2e8f9f7 | 33 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 34 | */ |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 37 | #ifndef __STM32L0xx_HAL_TIM_EX_H |
<> | 144:ef7eb2e8f9f7 | 38 | #define __STM32L0xx_HAL_TIM_EX_H |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 41 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 42 | #endif |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 45 | #include "stm32l0xx_hal_def.h" |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | /** @addtogroup STM32L0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 48 | * @{ |
<> | 144:ef7eb2e8f9f7 | 49 | */ |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | /** @defgroup TIMEx TIMEx |
<> | 144:ef7eb2e8f9f7 | 52 | * @{ |
<> | 144:ef7eb2e8f9f7 | 53 | */ |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 56 | /** @defgroup TIM_Exported_Types TIM Exported Types |
<> | 144:ef7eb2e8f9f7 | 57 | * @{ |
<> | 144:ef7eb2e8f9f7 | 58 | */ |
<> | 144:ef7eb2e8f9f7 | 59 | /** |
<> | 144:ef7eb2e8f9f7 | 60 | * @brief TIM Master configuration Structure definition |
<> | 144:ef7eb2e8f9f7 | 61 | */ |
<> | 144:ef7eb2e8f9f7 | 62 | typedef struct { |
<> | 144:ef7eb2e8f9f7 | 63 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
<> | 144:ef7eb2e8f9f7 | 64 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
<> | 144:ef7eb2e8f9f7 | 65 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
<> | 144:ef7eb2e8f9f7 | 66 | This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
<> | 144:ef7eb2e8f9f7 | 67 | }TIM_MasterConfigTypeDef; |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | /** |
<> | 144:ef7eb2e8f9f7 | 70 | * @} |
<> | 144:ef7eb2e8f9f7 | 71 | */ |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 74 | /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants |
<> | 144:ef7eb2e8f9f7 | 75 | * @{ |
<> | 144:ef7eb2e8f9f7 | 76 | */ |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | /** @defgroup TIMEx_Trigger_Selection Trigger selection |
<> | 144:ef7eb2e8f9f7 | 79 | * @{ |
<> | 144:ef7eb2e8f9f7 | 80 | */ |
<> | 151:5eaa88a5bcc7 | 81 | #define TIM_TRGO_RESET ((uint32_t)0x0000U) |
<> | 144:ef7eb2e8f9f7 | 82 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
<> | 144:ef7eb2e8f9f7 | 83 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
<> | 144:ef7eb2e8f9f7 | 84 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
<> | 144:ef7eb2e8f9f7 | 85 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
<> | 144:ef7eb2e8f9f7 | 86 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
<> | 144:ef7eb2e8f9f7 | 87 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
<> | 144:ef7eb2e8f9f7 | 88 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
<> | 144:ef7eb2e8f9f7 | 91 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 92 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
<> | 144:ef7eb2e8f9f7 | 93 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
<> | 144:ef7eb2e8f9f7 | 94 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
<> | 144:ef7eb2e8f9f7 | 95 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
<> | 144:ef7eb2e8f9f7 | 96 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
<> | 144:ef7eb2e8f9f7 | 97 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | /** |
<> | 144:ef7eb2e8f9f7 | 100 | * @} |
<> | 144:ef7eb2e8f9f7 | 101 | */ |
<> | 144:ef7eb2e8f9f7 | 102 | |
<> | 144:ef7eb2e8f9f7 | 103 | /** @defgroup TIMEx_Remap Remaping |
<> | 144:ef7eb2e8f9f7 | 104 | * @{ |
<> | 144:ef7eb2e8f9f7 | 105 | */ |
<> | 144:ef7eb2e8f9f7 | 106 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
<> | 144:ef7eb2e8f9f7 | 107 | || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 151:5eaa88a5bcc7 | 109 | #define TIM2_ETR_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 110 | #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 |
<> | 144:ef7eb2e8f9f7 | 111 | #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) |
<> | 144:ef7eb2e8f9f7 | 112 | #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) |
<> | 144:ef7eb2e8f9f7 | 113 | #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) |
<> | 144:ef7eb2e8f9f7 | 114 | #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | #elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) |
<> | 144:ef7eb2e8f9f7 | 117 | |
<> | 151:5eaa88a5bcc7 | 118 | #define TIM2_ETR_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 119 | #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) |
<> | 144:ef7eb2e8f9f7 | 120 | #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) |
<> | 144:ef7eb2e8f9f7 | 121 | #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) |
<> | 144:ef7eb2e8f9f7 | 122 | #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | #else |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 151:5eaa88a5bcc7 | 126 | #define TIM2_ETR_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 127 | #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 |
<> | 144:ef7eb2e8f9f7 | 128 | #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) |
<> | 144:ef7eb2e8f9f7 | 129 | #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) |
<> | 144:ef7eb2e8f9f7 | 130 | #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | #endif |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 151:5eaa88a5bcc7 | 136 | #define TIM2_TI4_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 137 | #define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0 |
<> | 144:ef7eb2e8f9f7 | 138 | #define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1 |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 151:5eaa88a5bcc7 | 140 | #define TIM21_ETR_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 141 | #define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0 |
<> | 144:ef7eb2e8f9f7 | 142 | #define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1 |
<> | 144:ef7eb2e8f9f7 | 143 | #define TIM21_ETR_LSE TIM21_OR_ETR_RMP |
<> | 151:5eaa88a5bcc7 | 144 | #define TIM21_TI1_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 145 | #define TIM21_TI1_MCO TIM21_OR_TI1_RMP |
<> | 144:ef7eb2e8f9f7 | 146 | #define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0 |
<> | 144:ef7eb2e8f9f7 | 147 | #define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1 |
<> | 144:ef7eb2e8f9f7 | 148 | #define TIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1) |
<> | 144:ef7eb2e8f9f7 | 149 | #define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2 |
<> | 144:ef7eb2e8f9f7 | 150 | #define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0) |
<> | 144:ef7eb2e8f9f7 | 151 | #define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1) |
<> | 151:5eaa88a5bcc7 | 152 | #define TIM21_TI2_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 153 | #define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | #if !defined(STM32L011xx) && !defined(STM32L021xx) |
Anna Bridge |
186:707f6e361f3e | 156 | #define TIM22_ETR_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 157 | #define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0 |
<> | 144:ef7eb2e8f9f7 | 158 | #define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1 |
Anna Bridge |
186:707f6e361f3e | 159 | #define TIM22_ETR_LSE TIM22_OR_ETR_RMP |
<> | 151:5eaa88a5bcc7 | 160 | #define TIM22_TI1_GPIO1 ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 161 | #define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0 |
<> | 144:ef7eb2e8f9f7 | 162 | #define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1 |
<> | 144:ef7eb2e8f9f7 | 163 | #define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP |
<> | 144:ef7eb2e8f9f7 | 164 | #endif |
<> | 144:ef7eb2e8f9f7 | 165 | |
<> | 144:ef7eb2e8f9f7 | 166 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
<> | 144:ef7eb2e8f9f7 | 167 | || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 151:5eaa88a5bcc7 | 169 | #define TIM3_TI4_GPIO_DEF ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 170 | #define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP |
<> | 151:5eaa88a5bcc7 | 171 | #define TIM3_TI2_GPIO_DEF ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 172 | #define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP |
<> | 151:5eaa88a5bcc7 | 173 | #define TIM3_TI1_USB_SOF ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 174 | #define TIM3_TI1_GPIO TIM3_OR_TI1_RMP |
<> | 151:5eaa88a5bcc7 | 175 | #define TIM3_ETR_GPIO ((uint32_t)0x0U) |
<> | 144:ef7eb2e8f9f7 | 176 | #define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1 |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
<> | 144:ef7eb2e8f9f7 | 182 | || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ |
Anna Bridge |
186:707f6e361f3e | 186 | ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ |
Anna Bridge |
186:707f6e361f3e | 187 | (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \ |
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186:707f6e361f3e | 188 | (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || \ |
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186:707f6e361f3e | 189 | (((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP)))) |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ |
Anna Bridge |
186:707f6e361f3e | 192 | ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 193 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
<> | 144:ef7eb2e8f9f7 | 194 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
<> | 144:ef7eb2e8f9f7 | 195 | ((__CHANNEL__) == TIM_CHANNEL_4))) || \ |
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186:707f6e361f3e | 196 | (((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 197 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
<> | 144:ef7eb2e8f9f7 | 198 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
<> | 144:ef7eb2e8f9f7 | 199 | ((__CHANNEL__) == TIM_CHANNEL_4))) || \ |
Anna Bridge |
186:707f6e361f3e | 200 | (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 201 | ((__CHANNEL__) == TIM_CHANNEL_2))) || \ |
Anna Bridge |
186:707f6e361f3e | 202 | (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 203 | ((__CHANNEL__) == TIM_CHANNEL_2)))) |
<> | 144:ef7eb2e8f9f7 | 204 | |
<> | 144:ef7eb2e8f9f7 | 205 | #elif defined (STM32L011xx) || defined (STM32L021xx) |
<> | 144:ef7eb2e8f9f7 | 206 | |
<> | 144:ef7eb2e8f9f7 | 207 | #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ |
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186:707f6e361f3e | 208 | ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ |
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186:707f6e361f3e | 209 | (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP)))) |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ |
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186:707f6e361f3e | 212 | ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 213 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
<> | 144:ef7eb2e8f9f7 | 214 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
<> | 144:ef7eb2e8f9f7 | 215 | ((__CHANNEL__) == TIM_CHANNEL_4))) || \ |
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186:707f6e361f3e | 216 | (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 217 | ((__CHANNEL__) == TIM_CHANNEL_2)))) |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | #else |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ |
Anna Bridge |
186:707f6e361f3e | 222 | ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ |
Anna Bridge |
186:707f6e361f3e | 223 | (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \ |
Anna Bridge |
186:707f6e361f3e | 224 | (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP)))) |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ |
Anna Bridge |
186:707f6e361f3e | 227 | ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 228 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
<> | 144:ef7eb2e8f9f7 | 229 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
<> | 144:ef7eb2e8f9f7 | 230 | ((__CHANNEL__) == TIM_CHANNEL_4))) || \ |
Anna Bridge |
186:707f6e361f3e | 231 | (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 232 | ((__CHANNEL__) == TIM_CHANNEL_2))) || \ |
Anna Bridge |
186:707f6e361f3e | 233 | (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
<> | 144:ef7eb2e8f9f7 | 234 | ((__CHANNEL__) == TIM_CHANNEL_2)))) |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | /** |
<> | 144:ef7eb2e8f9f7 | 240 | * @} |
<> | 144:ef7eb2e8f9f7 | 241 | */ |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 144:ef7eb2e8f9f7 | 243 | /** |
<> | 144:ef7eb2e8f9f7 | 244 | * @} |
<> | 144:ef7eb2e8f9f7 | 245 | */ |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | /* Exported macro ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 249 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 250 | /* Control functions ***********************************************************/ |
<> | 144:ef7eb2e8f9f7 | 251 | |
<> | 144:ef7eb2e8f9f7 | 252 | /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions |
<> | 144:ef7eb2e8f9f7 | 253 | * @{ |
<> | 144:ef7eb2e8f9f7 | 254 | */ |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | /** @defgroup TIMEx_Exported_Functions_Group1 TIMEx Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 257 | * @{ |
<> | 144:ef7eb2e8f9f7 | 258 | */ |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
<> | 144:ef7eb2e8f9f7 | 261 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | /** |
<> | 144:ef7eb2e8f9f7 | 264 | * @} |
<> | 144:ef7eb2e8f9f7 | 265 | */ |
<> | 144:ef7eb2e8f9f7 | 266 | |
<> | 144:ef7eb2e8f9f7 | 267 | /** |
<> | 144:ef7eb2e8f9f7 | 268 | * @} |
<> | 144:ef7eb2e8f9f7 | 269 | */ |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | /** |
<> | 144:ef7eb2e8f9f7 | 272 | * @} |
<> | 144:ef7eb2e8f9f7 | 273 | */ |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | /** |
<> | 144:ef7eb2e8f9f7 | 276 | * @} |
<> | 144:ef7eb2e8f9f7 | 277 | */ |
<> | 144:ef7eb2e8f9f7 | 278 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 279 | } |
<> | 144:ef7eb2e8f9f7 | 280 | #endif |
<> | 144:ef7eb2e8f9f7 | 281 | |
<> | 144:ef7eb2e8f9f7 | 282 | #endif /* __STM32L0xx_HAL_TIM_EX_H */ |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
<> | 144:ef7eb2e8f9f7 | 285 |