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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 6 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Timer (TIM) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 9 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 10 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ================================================================================
<> 144:ef7eb2e8f9f7 13 ##### TIM specific features integration #####
<> 144:ef7eb2e8f9f7 14 ================================================================================
<> 144:ef7eb2e8f9f7 15
<> 144:ef7eb2e8f9f7 16 [..] The Timer features include:
<> 144:ef7eb2e8f9f7 17 (#) 16-bit up, down, up/down auto-reload counter.
<> 144:ef7eb2e8f9f7 18 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
<> 144:ef7eb2e8f9f7 19 frequency either by any factor between 1 and 65536.
<> 144:ef7eb2e8f9f7 20 (#) Up to 4 independent channels for:
<> 144:ef7eb2e8f9f7 21 Input Capture
<> 144:ef7eb2e8f9f7 22 Output Compare
<> 144:ef7eb2e8f9f7 23 PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 24 One-pulse mode output
<> 144:ef7eb2e8f9f7 25 (#) Synchronization circuit to control the timer with external signals and to interconnect
<> 144:ef7eb2e8f9f7 26 several timers together.
<> 144:ef7eb2e8f9f7 27 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
<> 144:ef7eb2e8f9f7 28 purposes
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 31 ================================================================================
<> 144:ef7eb2e8f9f7 32 [..]
<> 144:ef7eb2e8f9f7 33 (#) Enable the TIM interface clock using
<> 144:ef7eb2e8f9f7 34 __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 (#) TIM pins configuration
<> 144:ef7eb2e8f9f7 37 (++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 38 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 39 (++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
<> 144:ef7eb2e8f9f7 42 using the following function:
<> 144:ef7eb2e8f9f7 43 HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 (#) Configure the TIM in the desired operating mode using one of the
<> 144:ef7eb2e8f9f7 46 configuration function of this driver:
<> 144:ef7eb2e8f9f7 47 (++) HAL_TIMEx_MasterConfigSynchronization() to configure the peripheral in master mode.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 (#) Remap the Timer I/O using HAL_TIMEx_RemapConfig() API.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 @endverbatim
<> 144:ef7eb2e8f9f7 53 ******************************************************************************
<> 144:ef7eb2e8f9f7 54 * @attention
<> 144:ef7eb2e8f9f7 55 *
<> 144:ef7eb2e8f9f7 56 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 59 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 60 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 61 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 62 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 64 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 65 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 66 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 67 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 70 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 72 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 73 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 74 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 75 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 76 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 77 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 78 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 ******************************************************************************
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 84 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 87 * @{
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @addtogroup TIMEx
<> 144:ef7eb2e8f9f7 91 * @brief TIMEx HAL module driver
<> 144:ef7eb2e8f9f7 92 * @{
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @addtogroup TIMEx_Exported_Functions
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @addtogroup TIMEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 104 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 @verbatim
<> 144:ef7eb2e8f9f7 107 ===============================================================================
<> 144:ef7eb2e8f9f7 108 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 109 ===============================================================================
<> 144:ef7eb2e8f9f7 110 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 111 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 @endverbatim
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /**
<> 144:ef7eb2e8f9f7 118 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 119 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 120 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 121 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 122 * mode.
<> 144:ef7eb2e8f9f7 123 * @retval HAL status
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 /* Check the parameters */
<> 144:ef7eb2e8f9f7 128 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 129 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 130 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Change the handler state */
<> 144:ef7eb2e8f9f7 135 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 138 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 139 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 140 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 143 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 144 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 145 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 return HAL_OK;
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
<> 144:ef7eb2e8f9f7 156 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @brief Configures the remapping of the TIM2, TIM3, TIM21 and TIM22 inputs.
<> 144:ef7eb2e8f9f7 160 * The channel inputs (T1..T4) and the Trigger input (ETR) of the
<> 144:ef7eb2e8f9f7 161 * timers can be remaped thanks to this function. When an input is
<> 144:ef7eb2e8f9f7 162 * mapped, on a GPIO, refer yourself to the GPIO alternate functions
<> 144:ef7eb2e8f9f7 163 * for more details.
<> 144:ef7eb2e8f9f7 164 * @note It is not possible to connect TIM2 and TIM21 on
<> 144:ef7eb2e8f9f7 165 * GPIOB5_AF4 at the same time.
<> 144:ef7eb2e8f9f7 166 * When selecting TIM3_TI2_GPIOB5_AF4, Channel2 of TIM3 will be
<> 144:ef7eb2e8f9f7 167 * connected to GPIOB5_AF4 and Channel2 of TIM22 will be connected to
<> 144:ef7eb2e8f9f7 168 * some other GPIOs. (refer to alternate functions for more details)
<> 144:ef7eb2e8f9f7 169 * When selecting TIM3_TI2_GPIO_DEF, Channel2 of Timer 3 will be
<> 144:ef7eb2e8f9f7 170 * connected an GPIO (other than GPIOB5_AF4) and Channel2 of TIM22
<> 144:ef7eb2e8f9f7 171 * will be connected to GPIOB5_AF4.
<> 144:ef7eb2e8f9f7 172 *
<> 144:ef7eb2e8f9f7 173 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 174 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 175 * @param Remap: specifies the TIM input remapping source.
<> 144:ef7eb2e8f9f7 176 * This parameter is a combination of the following values
<> 144:ef7eb2e8f9f7 177 * depending on TIM instance:
<> 144:ef7eb2e8f9f7 178 *
<> 144:ef7eb2e8f9f7 179 * For TIM2, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 180 * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
<> 144:ef7eb2e8f9f7 181 * GPIOA(0)_AF5 or GPIOA(5)_AF2 or
<> 144:ef7eb2e8f9f7 182 * GPIOA(15)_AF2 or GPIOE(9)_AF2
<> 144:ef7eb2e8f9f7 183 * @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48
<> 144:ef7eb2e8f9f7 184 * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HSI16
<> 144:ef7eb2e8f9f7 185 * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
<> 144:ef7eb2e8f9f7 186 * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 187 * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 188 * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO1(default):
<> 144:ef7eb2e8f9f7 189 * GPIOA(3)_AF2 or GPIOB(11)_AF2 or
<> 144:ef7eb2e8f9f7 190 * GPIOE(12)_AF0
<> 144:ef7eb2e8f9f7 191 * @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1
<> 144:ef7eb2e8f9f7 192 * @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2
<> 144:ef7eb2e8f9f7 193 *
<> 144:ef7eb2e8f9f7 194 * For TIM3, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 195 * @arg TIM3_ETR_GPIO: TIM3 ETR connected to GPIO (default):
<> 144:ef7eb2e8f9f7 196 * GPIOE(2)_AF2 or GPIOD(2)_AF2 or
<> 144:ef7eb2e8f9f7 197 * GPIOE(2)AF2
<> 144:ef7eb2e8f9f7 198 * @arg TIM3_ETR_HSI: TIM3 ETR connected to HSI
<> 144:ef7eb2e8f9f7 199 * @arg TIM3_TI1_USB_SOF: TIM3 TI1 connected to USB_SOF (default)
<> 144:ef7eb2e8f9f7 200 * @arg TIM3_TI1_GPIO: TIM3 TI1 connected to GPIO :
<> 144:ef7eb2e8f9f7 201 * GPIOE(3)_AF2 or GPIOA(6)_AF2 or
<> 144:ef7eb2e8f9f7 202 * GPIOC(6)_AF2 or GPIOB(4)_AF2
<> 144:ef7eb2e8f9f7 203 * @arg TIM3_TI2_GPIOB5_AF4:TIM3 TI3 connected to GPIOB(5)_AF4
<> 144:ef7eb2e8f9f7 204 * (refer to note)
<> 144:ef7eb2e8f9f7 205 * @arg TIM3_TI2_GPIO_DEF: TIM3 TI3 connected to GPIO (default):
<> 144:ef7eb2e8f9f7 206 * GPIO_A(7)_AF2 or GPIO_B(5)_AF4 or
<> 144:ef7eb2e8f9f7 207 * GPIOC(7)_AF2 or GPIOE(7)_AF2
<> 144:ef7eb2e8f9f7 208 * @arg TIM3_TI4_GPIO_DEF: TIM3 TI4 connected to GPIO:
<> 144:ef7eb2e8f9f7 209 * GPIO_B(1)_AF2 or GPIO_E(6)_AF2
<> 144:ef7eb2e8f9f7 210 * @arg TIM3_TI4_GPIOC9_AF2:TIM3 TI4 connected to GPIOC(9)_AF2
<> 144:ef7eb2e8f9f7 211 *
<> 144:ef7eb2e8f9f7 212 * For TIM21, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 213 * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
<> 144:ef7eb2e8f9f7 214 * APB2_PC(9)_AF0 or APB2_PA(1)_AF5
<> 144:ef7eb2e8f9f7 215 * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 216 * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 217 * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
<> 144:ef7eb2e8f9f7 218 * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
<> 144:ef7eb2e8f9f7 219 * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
<> 144:ef7eb2e8f9f7 220 * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
<> 144:ef7eb2e8f9f7 221 * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
<> 144:ef7eb2e8f9f7 222 * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
<> 144:ef7eb2e8f9f7 223 * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
<> 144:ef7eb2e8f9f7 224 * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
<> 144:ef7eb2e8f9f7 225 * @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 226 * GPIOA(2)_AF0 or GPIOB(13)_AF6 or
<> 144:ef7eb2e8f9f7 227 * GPIOE(5)_AF0 or GPIOD(0)_AF0
<> 144:ef7eb2e8f9f7 228 * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 229 * GPIOA(3)_AF0 or GPIOB(14)_AF6 or
<> 144:ef7eb2e8f9f7 230 * GPIOE(6)_AF0 or GPIOD(7)_AF1
<> 144:ef7eb2e8f9f7 231 * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
<> 144:ef7eb2e8f9f7 232 *
<> 144:ef7eb2e8f9f7 233 * For TIM22, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 234 * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE
<> 144:ef7eb2e8f9f7 235 * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 236 * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 237 * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default):
<> 144:ef7eb2e8f9f7 238 * GPIOC(8)_AF0 or GPIOA(4)_AF5
<> 144:ef7eb2e8f9f7 239 * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 240 * GPIOC(6)_AF0 or GPIOA(6)_AF5 or
<> 144:ef7eb2e8f9f7 241 * GPIOB(4)_AF4 or GPIOE(0)_AF3
<> 144:ef7eb2e8f9f7 242 * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
<> 144:ef7eb2e8f9f7 243 * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
<> 144:ef7eb2e8f9f7 244 * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO:
<> 144:ef7eb2e8f9f7 245 * GPIOC(6)_AF0 or GPIOA(6)_AF5 or
<> 144:ef7eb2e8f9f7 246 * GPIOB(4)_AF4 or GPIOE(3)_AF0
<> 144:ef7eb2e8f9f7 247 *
<> 144:ef7eb2e8f9f7 248 * @retval HAL status
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #elif defined (STM32L031xx) || defined (STM32L041xx)
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs.
<> 144:ef7eb2e8f9f7 253 * The channel inputs (T1..T4) and the Trigger input (ETR) of the
<> 144:ef7eb2e8f9f7 254 * timers can be remaped thanks to this function. When an input is
<> 144:ef7eb2e8f9f7 255 * mapped, on a GPIO, refer yourself to the GPIO alternate functions
<> 144:ef7eb2e8f9f7 256 * for more details.
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 259 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 260 * @param Remap: specifies the TIM input remapping source.
<> 144:ef7eb2e8f9f7 261 * This parameter is a combination of the following values
<> 144:ef7eb2e8f9f7 262 * depending on TIM instance:
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * For TIM2, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 265 * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
<> 144:ef7eb2e8f9f7 266 * GPIOA(0)_AF5 or GPIOA(5)_AF2 or
<> 144:ef7eb2e8f9f7 267 * GPIOA(15)_AF2
<> 144:ef7eb2e8f9f7 268 * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT)
<> 144:ef7eb2e8f9f7 269 * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
<> 144:ef7eb2e8f9f7 270 * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 271 * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 272 * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default):
<> 144:ef7eb2e8f9f7 273 * GPIOA(3)_AF2 or GPIOB(11)_AF2 or
<> 144:ef7eb2e8f9f7 274 * GPIOB(1)_AF5
<> 144:ef7eb2e8f9f7 275 * @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output
<> 144:ef7eb2e8f9f7 276 * @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output
<> 144:ef7eb2e8f9f7 277 *
<> 144:ef7eb2e8f9f7 278 * For TIM21, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 279 * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
<> 144:ef7eb2e8f9f7 280 * APB2_PA(1)_AF5
<> 144:ef7eb2e8f9f7 281 * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 282 * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 283 * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
<> 144:ef7eb2e8f9f7 284 * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
<> 144:ef7eb2e8f9f7 285 * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
<> 144:ef7eb2e8f9f7 286 * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
<> 144:ef7eb2e8f9f7 287 * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
<> 144:ef7eb2e8f9f7 288 * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
<> 144:ef7eb2e8f9f7 289 * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
<> 144:ef7eb2e8f9f7 290 * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
<> 144:ef7eb2e8f9f7 291 * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 292 * GPIOA(3)_AF0 or GPIOB(14)_AF6
<> 144:ef7eb2e8f9f7 293 * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
<> 144:ef7eb2e8f9f7 294 *
<> 144:ef7eb2e8f9f7 295 * For TIM22, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 296 * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE
<> 144:ef7eb2e8f9f7 297 * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 298 * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 299 * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default):
<> 144:ef7eb2e8f9f7 300 * GPIOA(4)_AF5
<> 144:ef7eb2e8f9f7 301 * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 302 * GPIOC(0)_AF6 or GPIOA(5)_AF6 or
<> 144:ef7eb2e8f9f7 303 * GPIOB(4)_AF4
<> 144:ef7eb2e8f9f7 304 * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
<> 144:ef7eb2e8f9f7 305 * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
<> 144:ef7eb2e8f9f7 306 * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO:
<> 144:ef7eb2e8f9f7 307 * GPIOA(6)_AF5 or GPIOB(4)_AF4
<> 144:ef7eb2e8f9f7 308 *
<> 144:ef7eb2e8f9f7 309 * @retval HAL status
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 #elif defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 312 /**
<> 144:ef7eb2e8f9f7 313 * @brief Configures the remapping of the TIM2 and TIM21 inputs.
<> 144:ef7eb2e8f9f7 314 * The channel inputs (T1..T4) and the Trigger input (ETR) of the
<> 144:ef7eb2e8f9f7 315 * timers can be remaped thanks to this function. When an input is
<> 144:ef7eb2e8f9f7 316 * mapped, on a GPIO, refer yourself to the GPIO alternate functions
<> 144:ef7eb2e8f9f7 317 * for more details.
<> 144:ef7eb2e8f9f7 318 *
<> 144:ef7eb2e8f9f7 319 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 320 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 321 * @param Remap: specifies the TIM input remapping source.
<> 144:ef7eb2e8f9f7 322 * This parameter is a combination of the following values
<> 144:ef7eb2e8f9f7 323 * depending on TIM instance:
<> 144:ef7eb2e8f9f7 324 *
<> 144:ef7eb2e8f9f7 325 * For TIM2, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 326 * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
<> 144:ef7eb2e8f9f7 327 * GPIOA(0)_AF5 or GPIOA(5)_AF2 or
<> 144:ef7eb2e8f9f7 328 * GPIOA(15)_AF2
<> 144:ef7eb2e8f9f7 329 * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT)
<> 144:ef7eb2e8f9f7 330 * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
<> 144:ef7eb2e8f9f7 331 * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 332 * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 333 * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default):
<> 144:ef7eb2e8f9f7 334 * GPIOA(3)_AF2 or GPIOB(11)_AF2 or
<> 144:ef7eb2e8f9f7 335 * GPIOB(1)_AF5
<> 144:ef7eb2e8f9f7 336 * @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output
<> 144:ef7eb2e8f9f7 337 * @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output
<> 144:ef7eb2e8f9f7 338 *
<> 144:ef7eb2e8f9f7 339 * For TIM21, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 340 * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
<> 144:ef7eb2e8f9f7 341 * APB2_PA(1)_AF5
<> 144:ef7eb2e8f9f7 342 * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 343 * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 344 * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
<> 144:ef7eb2e8f9f7 345 * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
<> 144:ef7eb2e8f9f7 346 * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
<> 144:ef7eb2e8f9f7 347 * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
<> 144:ef7eb2e8f9f7 348 * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
<> 144:ef7eb2e8f9f7 349 * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
<> 144:ef7eb2e8f9f7 350 * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
<> 144:ef7eb2e8f9f7 351 * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
<> 144:ef7eb2e8f9f7 352 * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 353 * GPIOA(3)_AF0 or GPIOB(14)_AF6
<> 144:ef7eb2e8f9f7 354 * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
<> 144:ef7eb2e8f9f7 355 *
<> 144:ef7eb2e8f9f7 356 * @retval HAL status
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #else
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs.
<> 144:ef7eb2e8f9f7 361 * The channel inputs (T1..T4) and the Trigger input (ETR) of the
<> 144:ef7eb2e8f9f7 362 * timers can be remaped thanks to this function. When an input is
<> 144:ef7eb2e8f9f7 363 * mapped, on a GPIO, refer yourself to the GPIO alternate functions
<> 144:ef7eb2e8f9f7 364 * for more details.
<> 144:ef7eb2e8f9f7 365 *
<> 144:ef7eb2e8f9f7 366 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 367 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 368 * @param Remap: specifies the TIM input remapping source.
<> 144:ef7eb2e8f9f7 369 * This parameter is a combination of the following values
<> 144:ef7eb2e8f9f7 370 * depending on TIM instance:
<> 144:ef7eb2e8f9f7 371 *
<> 144:ef7eb2e8f9f7 372 * For TIM2, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 373 * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default):
<> 144:ef7eb2e8f9f7 374 * GPIOA(0)_AF5 or GPIOA(5)_AF2 or
<> 144:ef7eb2e8f9f7 375 * GPIOA(15)_AF2 or GPIOE(9)_AF2
<> 144:ef7eb2e8f9f7 376 * @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48
<> 144:ef7eb2e8f9f7 377 * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE
<> 144:ef7eb2e8f9f7 378 * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 379 * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 380 * @arg TIM2_TI4_GPIO: TIM2 TI4 connected to GPIO1(default):
<> 144:ef7eb2e8f9f7 381 * GPIOA(3)_AF2 or GPIOB(11)_AF2 or
<> 144:ef7eb2e8f9f7 382 * GPIOE(12)_AF0
<> 144:ef7eb2e8f9f7 383 * @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1
<> 144:ef7eb2e8f9f7 384 * @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2
<> 144:ef7eb2e8f9f7 385 * @arg TIM2_TI4_GPIO2: TIM2 TI4 connected to GPIO2 :
<> 144:ef7eb2e8f9f7 386 * GPIOA(3)_AF2 or GPIOB(11)_AF2 or
<> 144:ef7eb2e8f9f7 387 * GPIOE(12)_AF0
<> 144:ef7eb2e8f9f7 388 *
<> 144:ef7eb2e8f9f7 389 * For TIM21, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 390 * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) :
<> 144:ef7eb2e8f9f7 391 * APB2_PC(9)_AF0 or APB2_PA(1)_AF5
<> 144:ef7eb2e8f9f7 392 * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 393 * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 394 * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE
<> 144:ef7eb2e8f9f7 395 * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO
<> 144:ef7eb2e8f9f7 396 * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt
<> 144:ef7eb2e8f9f7 397 * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC
<> 144:ef7eb2e8f9f7 398 * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock
<> 144:ef7eb2e8f9f7 399 * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE
<> 144:ef7eb2e8f9f7 400 * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI
<> 144:ef7eb2e8f9f7 401 * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT
<> 144:ef7eb2e8f9f7 402 * @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 403 * GPIOA(2)_AF0 or GPIOB(13)_AF6 or
<> 144:ef7eb2e8f9f7 404 * GPIOE(5)_AF0 or GPIOD(0)_AF0
<> 144:ef7eb2e8f9f7 405 * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 406 * GPIOA(3)_AF0 or GPIOB(14)_AF6 or
<> 144:ef7eb2e8f9f7 407 * GPIOE(6)_AF0 or GPIOD(7)_AF1
<> 144:ef7eb2e8f9f7 408 * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output
<> 144:ef7eb2e8f9f7 409 *
<> 144:ef7eb2e8f9f7 410 * For TIM22, the parameter can have the following values:
<> 144:ef7eb2e8f9f7 411 * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE
<> 144:ef7eb2e8f9f7 412 * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output
<> 144:ef7eb2e8f9f7 413 * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output
<> 144:ef7eb2e8f9f7 414 * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default):
<> 144:ef7eb2e8f9f7 415 * GPIOC(8)_AF0 or GPIOA(4)_AF5
<> 144:ef7eb2e8f9f7 416 * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default):
<> 144:ef7eb2e8f9f7 417 * GPIOC(6)_AF0 or GPIOA(6)_AF5 or
<> 144:ef7eb2e8f9f7 418 * GPIOB(4)_AF4 or GPIOE(0)_AF3
<> 144:ef7eb2e8f9f7 419 * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output
<> 144:ef7eb2e8f9f7 420 * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output
<> 144:ef7eb2e8f9f7 421 * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO:
<> 144:ef7eb2e8f9f7 422 * GPIOC(6)_AF0 or GPIOA(6)_AF5 or
<> 144:ef7eb2e8f9f7 423 * GPIOB(4)_AF4 or GPIOE(3)_AF0
<> 144:ef7eb2e8f9f7 424 *
<> 144:ef7eb2e8f9f7 425 * @retval HAL status
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 #endif /* STM32L07xxx or STM32L08xxx */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Check parameters */
<> 144:ef7eb2e8f9f7 436 assert_param(IS_TIM_REMAP(htim->Instance,Remap));
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Set the Timer remapping configuration */
<> 144:ef7eb2e8f9f7 439 htim->Instance->OR = Remap;
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 return HAL_OK;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /**
<> 144:ef7eb2e8f9f7 449 * @}
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @}
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 457 /**
<> 144:ef7eb2e8f9f7 458 * @}
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /**
<> 144:ef7eb2e8f9f7 462 * @}
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/