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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 186:707f6e361f3e

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_rcc_ex.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief Header file of RCC HAL Extension module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
Anna Bridge	186:707f6e361f3e	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	37	#ifndef __STM32L0xx_HAL_RCC_EX_H
<>	144:ef7eb2e8f9f7	38	#define __STM32L0xx_HAL_RCC_EX_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	45	#include "stm32l0xx_hal_def.h"
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	48	* @{
<>	144:ef7eb2e8f9f7	49	*/
<>	144:ef7eb2e8f9f7	50
Anna Bridge	186:707f6e361f3e	51	/** @addtogroup RCCEx
<>	144:ef7eb2e8f9f7	52	* @{
<>	144:ef7eb2e8f9f7	53	*/
<>	144:ef7eb2e8f9f7	54
Anna Bridge	186:707f6e361f3e	55	/** @addtogroup RCCEx_Private_Constants
Anna Bridge	186:707f6e361f3e	56	* @{
Anna Bridge	186:707f6e361f3e	57	*/
Anna Bridge	186:707f6e361f3e	58
Anna Bridge	186:707f6e361f3e	59
Anna Bridge	186:707f6e361f3e	60	#if defined(CRS)
Anna Bridge	186:707f6e361f3e	61	/* CRS IT Error Mask */
Anna Bridge	186:707f6e361f3e	62	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
Anna Bridge	186:707f6e361f3e	63
Anna Bridge	186:707f6e361f3e	64	/* CRS Flag Error Mask */
Anna Bridge	186:707f6e361f3e	65	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
Anna Bridge	186:707f6e361f3e	66
Anna Bridge	186:707f6e361f3e	67	#endif /* CRS */
Anna Bridge	186:707f6e361f3e	68	/**
Anna Bridge	186:707f6e361f3e	69	* @}
Anna Bridge	186:707f6e361f3e	70	*/
Anna Bridge	186:707f6e361f3e	71
Anna Bridge	186:707f6e361f3e	72	/** @addtogroup RCCEx_Private_Macros
Anna Bridge	186:707f6e361f3e	73	* @{
Anna Bridge	186:707f6e361f3e	74	*/
Anna Bridge	186:707f6e361f3e	75	#if defined (STM32L052xx) \|\| defined(STM32L062xx)
Anna Bridge	186:707f6e361f3e	76	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Anna Bridge	186:707f6e361f3e	77	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Anna Bridge	186:707f6e361f3e	78	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1))
Anna Bridge	186:707f6e361f3e	79	#elif defined (STM32L053xx) \|\| defined(STM32L063xx)
Anna Bridge	186:707f6e361f3e	80	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Anna Bridge	186:707f6e361f3e	81	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Anna Bridge	186:707f6e361f3e	82	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_LCD))
Anna Bridge	186:707f6e361f3e	83	#elif defined (STM32L072xx) \|\| defined(STM32L082xx)
Anna Bridge	186:707f6e361f3e	84	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Anna Bridge	186:707f6e361f3e	85	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Anna Bridge	186:707f6e361f3e	86	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 ))
Anna Bridge	186:707f6e361f3e	87	#elif defined (STM32L073xx) \|\| defined(STM32L083xx)
Anna Bridge	186:707f6e361f3e	88	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Anna Bridge	186:707f6e361f3e	89	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Anna Bridge	186:707f6e361f3e	90	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 \| \
Anna Bridge	186:707f6e361f3e	91	RCC_PERIPHCLK_LCD))
Anna Bridge	186:707f6e361f3e	92	#endif
Anna Bridge	186:707f6e361f3e	93
Anna Bridge	186:707f6e361f3e	94	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	95	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Anna Bridge	186:707f6e361f3e	96	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_RTC \| \
Anna Bridge	186:707f6e361f3e	97	RCC_PERIPHCLK_LPTIM1))
Anna Bridge	186:707f6e361f3e	98	#elif defined(STM32L051xx) \|\| defined(STM32L061xx)
Anna Bridge	186:707f6e361f3e	99	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Anna Bridge	186:707f6e361f3e	100	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Anna Bridge	186:707f6e361f3e	101	RCC_PERIPHCLK_LPTIM1))
Anna Bridge	186:707f6e361f3e	102	#elif defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	103	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Anna Bridge	186:707f6e361f3e	104	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Anna Bridge	186:707f6e361f3e	105	RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3))
Anna Bridge	186:707f6e361f3e	106	#endif
Anna Bridge	186:707f6e361f3e	107
Anna Bridge	186:707f6e361f3e	108	#if defined (RCC_CCIPR_USART1SEL)
Anna Bridge	186:707f6e361f3e	109	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Anna Bridge	186:707f6e361f3e	110	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Anna Bridge	186:707f6e361f3e	111	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	112	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Anna Bridge	186:707f6e361f3e	113	#endif /* RCC_CCIPR_USART1SEL */
Anna Bridge	186:707f6e361f3e	114
Anna Bridge	186:707f6e361f3e	115	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Anna Bridge	186:707f6e361f3e	116	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Anna Bridge	186:707f6e361f3e	117	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	118	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
Anna Bridge	186:707f6e361f3e	119
Anna Bridge	186:707f6e361f3e	120	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
Anna Bridge	186:707f6e361f3e	121	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
Anna Bridge	186:707f6e361f3e	122	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	123	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
Anna Bridge	186:707f6e361f3e	124
Anna Bridge	186:707f6e361f3e	125	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
Anna Bridge	186:707f6e361f3e	126	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
Anna Bridge	186:707f6e361f3e	127	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
Anna Bridge	186:707f6e361f3e	128
Anna Bridge	186:707f6e361f3e	129	#if defined(RCC_CCIPR_I2C3SEL)
Anna Bridge	186:707f6e361f3e	130	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
Anna Bridge	186:707f6e361f3e	131	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
Anna Bridge	186:707f6e361f3e	132	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
Anna Bridge	186:707f6e361f3e	133	#endif /* RCC_CCIPR_I2C3SEL */
Anna Bridge	186:707f6e361f3e	134
Anna Bridge	186:707f6e361f3e	135	#if defined(USB)
Anna Bridge	186:707f6e361f3e	136	#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) \|\| \
Anna Bridge	186:707f6e361f3e	137	((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
Anna Bridge	186:707f6e361f3e	138	#endif /* USB */
Anna Bridge	186:707f6e361f3e	139
Anna Bridge	186:707f6e361f3e	140	#if defined(RNG)
Anna Bridge	186:707f6e361f3e	141	#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) \|\| \
Anna Bridge	186:707f6e361f3e	142	((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
Anna Bridge	186:707f6e361f3e	143	#endif /* RNG */
Anna Bridge	186:707f6e361f3e	144
Anna Bridge	186:707f6e361f3e	145	#if defined(RCC_CCIPR_HSI48SEL)
Anna Bridge	186:707f6e361f3e	146	#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) \|\| ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
Anna Bridge	186:707f6e361f3e	147	#endif /* RCC_CCIPR_HSI48SEL */
Anna Bridge	186:707f6e361f3e	148
Anna Bridge	186:707f6e361f3e	149	#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
Anna Bridge	186:707f6e361f3e	150	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
Anna Bridge	186:707f6e361f3e	151	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
Anna Bridge	186:707f6e361f3e	152	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
Anna Bridge	186:707f6e361f3e	153
Anna Bridge	186:707f6e361f3e	154	#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
Anna Bridge	186:707f6e361f3e	155	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
Anna Bridge	186:707f6e361f3e	156
Anna Bridge	186:707f6e361f3e	157	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
Anna Bridge	186:707f6e361f3e	158	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
Anna Bridge	186:707f6e361f3e	159
Anna Bridge	186:707f6e361f3e	160	#if defined(CRS)
Anna Bridge	186:707f6e361f3e	161
Anna Bridge	186:707f6e361f3e	162	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
Anna Bridge	186:707f6e361f3e	163	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	164	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
Anna Bridge	186:707f6e361f3e	165	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
Anna Bridge	186:707f6e361f3e	166	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
Anna Bridge	186:707f6e361f3e	167	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
Anna Bridge	186:707f6e361f3e	168	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
Anna Bridge	186:707f6e361f3e	169	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
Anna Bridge	186:707f6e361f3e	170	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
Anna Bridge	186:707f6e361f3e	171	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
Anna Bridge	186:707f6e361f3e	172	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
Anna Bridge	186:707f6e361f3e	173	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
Anna Bridge	186:707f6e361f3e	174	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
Anna Bridge	186:707f6e361f3e	175	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
Anna Bridge	186:707f6e361f3e	176	#endif /* CRS */
Anna Bridge	186:707f6e361f3e	177	/**
Anna Bridge	186:707f6e361f3e	178	* @}
Anna Bridge	186:707f6e361f3e	179	*/
Anna Bridge	186:707f6e361f3e	180
<>	144:ef7eb2e8f9f7	181	/* Exported types ------------------------------------------------------------*/
Anna Bridge	186:707f6e361f3e	182
Anna Bridge	186:707f6e361f3e	183	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
<>	144:ef7eb2e8f9f7	184	* @{
<>	144:ef7eb2e8f9f7	185	*/
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	/**
<>	144:ef7eb2e8f9f7	188	* @brief RCC extended clocks structure definition
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190	typedef struct
<>	144:ef7eb2e8f9f7	191	{
Anna Bridge	186:707f6e361f3e	192	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Anna Bridge	186:707f6e361f3e	193	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Anna Bridge	186:707f6e361f3e	194
Anna Bridge	186:707f6e361f3e	195	uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
Anna Bridge	186:707f6e361f3e	196	This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
Anna Bridge	186:707f6e361f3e	197
Anna Bridge	186:707f6e361f3e	198	#if defined(LCD)
Anna Bridge	186:707f6e361f3e	199
Anna Bridge	186:707f6e361f3e	200	uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
Anna Bridge	186:707f6e361f3e	201	This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
Anna Bridge	186:707f6e361f3e	202
Anna Bridge	186:707f6e361f3e	203	#endif /* LCD */
Anna Bridge	186:707f6e361f3e	204	#if defined(RCC_CCIPR_USART1SEL)
<>	144:ef7eb2e8f9f7	205	uint32_t Usart1ClockSelection; /*!< USART1 clock source
<>	144:ef7eb2e8f9f7	206	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Anna Bridge	186:707f6e361f3e	207	#endif /* RCC_CCIPR_USART1SEL */
<>	144:ef7eb2e8f9f7	208	uint32_t Usart2ClockSelection; /*!< USART2 clock source
<>	144:ef7eb2e8f9f7	209	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
<>	144:ef7eb2e8f9f7	212	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<>	144:ef7eb2e8f9f7	215	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
<>	144:ef7eb2e8f9f7	216
Anna Bridge	186:707f6e361f3e	217	#if defined(RCC_CCIPR_I2C3SEL)
<>	144:ef7eb2e8f9f7	218	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
<>	144:ef7eb2e8f9f7	219	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Anna Bridge	186:707f6e361f3e	220	#endif /* RCC_CCIPR_I2C3SEL */
<>	144:ef7eb2e8f9f7	221	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
<>	144:ef7eb2e8f9f7	222	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Anna Bridge	186:707f6e361f3e	223	#if defined(USB)
Anna Bridge	186:707f6e361f3e	224	uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
Anna Bridge	186:707f6e361f3e	225	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Anna Bridge	186:707f6e361f3e	226	#endif /* USB */
Anna Bridge	186:707f6e361f3e	227	} RCC_PeriphCLKInitTypeDef;
<>	144:ef7eb2e8f9f7	228
Anna Bridge	186:707f6e361f3e	229	#if defined (CRS)
<>	144:ef7eb2e8f9f7	230	/**
<>	144:ef7eb2e8f9f7	231	* @brief RCC_CRS Init structure definition
<>	144:ef7eb2e8f9f7	232	*/
<>	144:ef7eb2e8f9f7	233	typedef struct
<>	144:ef7eb2e8f9f7	234	{
<>	144:ef7eb2e8f9f7	235	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
<>	144:ef7eb2e8f9f7	236	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	uint32_t Source; /*!< Specifies the SYNC signal source.
<>	144:ef7eb2e8f9f7	239	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
<>	144:ef7eb2e8f9f7	242	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
<>	144:ef7eb2e8f9f7	243
<>	144:ef7eb2e8f9f7	244	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Anna Bridge	186:707f6e361f3e	245	It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
<>	144:ef7eb2e8f9f7	246	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
<>	144:ef7eb2e8f9f7	249	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
<>	144:ef7eb2e8f9f7	252	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Anna Bridge	186:707f6e361f3e	253
<>	144:ef7eb2e8f9f7	254	}RCC_CRSInitTypeDef;
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/**
<>	144:ef7eb2e8f9f7	257	* @brief RCC_CRS Synchronization structure definition
<>	144:ef7eb2e8f9f7	258	*/
<>	144:ef7eb2e8f9f7	259	typedef struct
<>	144:ef7eb2e8f9f7	260	{
<>	144:ef7eb2e8f9f7	261	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Anna Bridge	186:707f6e361f3e	262	This parameter must be a number between 0 and 0xFFFF */
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
<>	144:ef7eb2e8f9f7	265	This parameter must be a number between 0 and 0x3F */
Anna Bridge	186:707f6e361f3e	266
<>	144:ef7eb2e8f9f7	267	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Anna Bridge	186:707f6e361f3e	268	value latched in the time of the last SYNC event.
<>	144:ef7eb2e8f9f7	269	This parameter must be a number between 0 and 0xFFFF */
Anna Bridge	186:707f6e361f3e	270
<>	144:ef7eb2e8f9f7	271	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
<>	144:ef7eb2e8f9f7	272	frequency error counter latched in the time of the last SYNC event.
<>	144:ef7eb2e8f9f7	273	It shows whether the actual frequency is below or above the target.
<>	144:ef7eb2e8f9f7	274	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
<>	144:ef7eb2e8f9f7	275
<>	144:ef7eb2e8f9f7	276	}RCC_CRSSynchroInfoTypeDef;
<>	144:ef7eb2e8f9f7	277
Anna Bridge	186:707f6e361f3e	278	#endif /* CRS */
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/**
<>	144:ef7eb2e8f9f7	281	* @}
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283
Anna Bridge	186:707f6e361f3e	284	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	285
Anna Bridge	186:707f6e361f3e	286	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
<>	144:ef7eb2e8f9f7	287	* @{
<>	144:ef7eb2e8f9f7	288	*/
<>	144:ef7eb2e8f9f7	289
<>	144:ef7eb2e8f9f7	290
<>	144:ef7eb2e8f9f7	291	/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
<>	144:ef7eb2e8f9f7	292	* @{
<>	144:ef7eb2e8f9f7	293	*/
<>	144:ef7eb2e8f9f7	294	#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /!< External interrupt line 19 connected to the LSE CSS EXTI Line /
<>	144:ef7eb2e8f9f7	295	/**
<>	144:ef7eb2e8f9f7	296	* @}
<>	144:ef7eb2e8f9f7	297	*/
<>	144:ef7eb2e8f9f7	298
Anna Bridge	186:707f6e361f3e	299	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
Anna Bridge	186:707f6e361f3e	300	* @{
Anna Bridge	186:707f6e361f3e	301	*/
Anna Bridge	186:707f6e361f3e	302	#if defined(RCC_CCIPR_USART1SEL)
Anna Bridge	186:707f6e361f3e	303	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Anna Bridge	186:707f6e361f3e	304	#endif /* RCC_CCIPR_USART1SEL */
Anna Bridge	186:707f6e361f3e	305	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Anna Bridge	186:707f6e361f3e	306	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
Anna Bridge	186:707f6e361f3e	307	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
Anna Bridge	186:707f6e361f3e	308	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
Anna Bridge	186:707f6e361f3e	309	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Anna Bridge	186:707f6e361f3e	310	#if defined(USB)
Anna Bridge	186:707f6e361f3e	311	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
Anna Bridge	186:707f6e361f3e	312	#endif /* USB */
Anna Bridge	186:707f6e361f3e	313	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
Anna Bridge	186:707f6e361f3e	314	#if defined(LCD)
Anna Bridge	186:707f6e361f3e	315	#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
Anna Bridge	186:707f6e361f3e	316	#endif /* LCD */
Anna Bridge	186:707f6e361f3e	317	#if defined(RCC_CCIPR_I2C3SEL)
Anna Bridge	186:707f6e361f3e	318	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
Anna Bridge	186:707f6e361f3e	319	#endif /* RCC_CCIPR_I2C3SEL */
Anna Bridge	186:707f6e361f3e	320
Anna Bridge	186:707f6e361f3e	321	/**
Anna Bridge	186:707f6e361f3e	322	* @}
Anna Bridge	186:707f6e361f3e	323	*/
Anna Bridge	186:707f6e361f3e	324
Anna Bridge	186:707f6e361f3e	325	#if defined (RCC_CCIPR_USART1SEL)
Anna Bridge	186:707f6e361f3e	326	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
Anna Bridge	186:707f6e361f3e	327	* @{
Anna Bridge	186:707f6e361f3e	328	*/
Anna Bridge	186:707f6e361f3e	329	#define RCC_USART1CLKSOURCE_PCLK2 (0x00000000U)
Anna Bridge	186:707f6e361f3e	330	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
Anna Bridge	186:707f6e361f3e	331	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
Anna Bridge	186:707f6e361f3e	332	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
Anna Bridge	186:707f6e361f3e	333	/**
Anna Bridge	186:707f6e361f3e	334	* @}
Anna Bridge	186:707f6e361f3e	335	*/
Anna Bridge	186:707f6e361f3e	336	#endif /* RCC_CCIPR_USART1SEL */
Anna Bridge	186:707f6e361f3e	337
Anna Bridge	186:707f6e361f3e	338	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
<>	144:ef7eb2e8f9f7	339	* @{
<>	144:ef7eb2e8f9f7	340	*/
Anna Bridge	186:707f6e361f3e	341	#define RCC_USART2CLKSOURCE_PCLK1 (0x00000000U)
Anna Bridge	186:707f6e361f3e	342	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
Anna Bridge	186:707f6e361f3e	343	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
Anna Bridge	186:707f6e361f3e	344	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
Anna Bridge	186:707f6e361f3e	345	/**
Anna Bridge	186:707f6e361f3e	346	* @}
Anna Bridge	186:707f6e361f3e	347	*/
Anna Bridge	186:707f6e361f3e	348
Anna Bridge	186:707f6e361f3e	349	/** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source
Anna Bridge	186:707f6e361f3e	350	* @{
Anna Bridge	186:707f6e361f3e	351	*/
Anna Bridge	186:707f6e361f3e	352	#define RCC_LPUART1CLKSOURCE_PCLK1 (0x00000000U)
Anna Bridge	186:707f6e361f3e	353	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
Anna Bridge	186:707f6e361f3e	354	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
Anna Bridge	186:707f6e361f3e	355	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
Anna Bridge	186:707f6e361f3e	356	/**
Anna Bridge	186:707f6e361f3e	357	* @}
Anna Bridge	186:707f6e361f3e	358	*/
Anna Bridge	186:707f6e361f3e	359
Anna Bridge	186:707f6e361f3e	360	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
Anna Bridge	186:707f6e361f3e	361	* @{
Anna Bridge	186:707f6e361f3e	362	*/
Anna Bridge	186:707f6e361f3e	363	#define RCC_I2C1CLKSOURCE_PCLK1 (0x00000000U)
Anna Bridge	186:707f6e361f3e	364	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
Anna Bridge	186:707f6e361f3e	365	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
Anna Bridge	186:707f6e361f3e	366	/**
Anna Bridge	186:707f6e361f3e	367	* @}
Anna Bridge	186:707f6e361f3e	368	*/
Anna Bridge	186:707f6e361f3e	369
Anna Bridge	186:707f6e361f3e	370	#if defined(RCC_CCIPR_I2C3SEL)
Anna Bridge	186:707f6e361f3e	371
Anna Bridge	186:707f6e361f3e	372	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
Anna Bridge	186:707f6e361f3e	373	* @{
Anna Bridge	186:707f6e361f3e	374	*/
Anna Bridge	186:707f6e361f3e	375	#define RCC_I2C3CLKSOURCE_PCLK1 (0x00000000U)
Anna Bridge	186:707f6e361f3e	376	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
Anna Bridge	186:707f6e361f3e	377	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
Anna Bridge	186:707f6e361f3e	378	/**
Anna Bridge	186:707f6e361f3e	379	* @}
Anna Bridge	186:707f6e361f3e	380	*/
Anna Bridge	186:707f6e361f3e	381	#endif /* RCC_CCIPR_I2C3SEL */
Anna Bridge	186:707f6e361f3e	382
Anna Bridge	186:707f6e361f3e	383	/** @defgroup RCCEx_TIM_PRescaler_Selection RCCEx TIM Prescaler Selection
Anna Bridge	186:707f6e361f3e	384	* @{
Anna Bridge	186:707f6e361f3e	385	*/
Anna Bridge	186:707f6e361f3e	386	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Anna Bridge	186:707f6e361f3e	387	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
<>	144:ef7eb2e8f9f7	388	/**
<>	144:ef7eb2e8f9f7	389	* @}
<>	144:ef7eb2e8f9f7	390	*/
<>	144:ef7eb2e8f9f7	391
Anna Bridge	186:707f6e361f3e	392	#if defined(USB)
Anna Bridge	186:707f6e361f3e	393	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Anna Bridge	186:707f6e361f3e	394	* @{
Anna Bridge	186:707f6e361f3e	395	*/
Anna Bridge	186:707f6e361f3e	396	#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
Anna Bridge	186:707f6e361f3e	397	#define RCC_USBCLKSOURCE_PLL (0x00000000U)
Anna Bridge	186:707f6e361f3e	398	/**
Anna Bridge	186:707f6e361f3e	399	* @}
Anna Bridge	186:707f6e361f3e	400	*/
Anna Bridge	186:707f6e361f3e	401	#endif /* USB */
Anna Bridge	186:707f6e361f3e	402
Anna Bridge	186:707f6e361f3e	403	#if defined(RNG)
Anna Bridge	186:707f6e361f3e	404	/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source
Anna Bridge	186:707f6e361f3e	405	* @{
Anna Bridge	186:707f6e361f3e	406	*/
Anna Bridge	186:707f6e361f3e	407	#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
Anna Bridge	186:707f6e361f3e	408	#define RCC_RNGCLKSOURCE_PLLCLK (0x00000000U)
Anna Bridge	186:707f6e361f3e	409	/**
Anna Bridge	186:707f6e361f3e	410	* @}
Anna Bridge	186:707f6e361f3e	411	*/
Anna Bridge	186:707f6e361f3e	412	#endif /* RNG */
Anna Bridge	186:707f6e361f3e	413
Anna Bridge	186:707f6e361f3e	414	#if defined(RCC_CCIPR_HSI48SEL)
Anna Bridge	186:707f6e361f3e	415	/** @defgroup RCCEx_HSI48M_Clock_Source RCCEx HSI48M Clock Source
Anna Bridge	186:707f6e361f3e	416	* @{
Anna Bridge	186:707f6e361f3e	417	*/
Anna Bridge	186:707f6e361f3e	418	#define RCC_FLAG_HSI48 SYSCFG_CFGR3_VREFINT_RDYF
Anna Bridge	186:707f6e361f3e	419
Anna Bridge	186:707f6e361f3e	420	#define RCC_HSI48M_PLL (0x00000000U)
Anna Bridge	186:707f6e361f3e	421	#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
Anna Bridge	186:707f6e361f3e	422
Anna Bridge	186:707f6e361f3e	423	/**
Anna Bridge	186:707f6e361f3e	424	* @}
Anna Bridge	186:707f6e361f3e	425	*/
Anna Bridge	186:707f6e361f3e	426	#endif /* RCC_CCIPR_HSI48SEL */
Anna Bridge	186:707f6e361f3e	427
Anna Bridge	186:707f6e361f3e	428	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
Anna Bridge	186:707f6e361f3e	429	* @{
Anna Bridge	186:707f6e361f3e	430	*/
Anna Bridge	186:707f6e361f3e	431	#define RCC_LPTIM1CLKSOURCE_PCLK (0x00000000U)
Anna Bridge	186:707f6e361f3e	432	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
Anna Bridge	186:707f6e361f3e	433	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
Anna Bridge	186:707f6e361f3e	434	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
Anna Bridge	186:707f6e361f3e	435	/**
Anna Bridge	186:707f6e361f3e	436	* @}
Anna Bridge	186:707f6e361f3e	437	*/
Anna Bridge	186:707f6e361f3e	438
Anna Bridge	186:707f6e361f3e	439	/** @defgroup RCCEx_StopWakeUp_Clock RCCEx StopWakeUp Clock
<>	144:ef7eb2e8f9f7	440	* @{
<>	144:ef7eb2e8f9f7	441	*/
Anna Bridge	186:707f6e361f3e	442
Anna Bridge	186:707f6e361f3e	443	#define RCC_STOP_WAKEUPCLOCK_MSI (0x00000000U)
Anna Bridge	186:707f6e361f3e	444	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
Anna Bridge	186:707f6e361f3e	445	/**
Anna Bridge	186:707f6e361f3e	446	* @}
Anna Bridge	186:707f6e361f3e	447	*/
Anna Bridge	186:707f6e361f3e	448
Anna Bridge	186:707f6e361f3e	449	/** @defgroup RCCEx_LSEDrive_Configuration RCCEx LSE Drive Configuration
Anna Bridge	186:707f6e361f3e	450	* @{
Anna Bridge	186:707f6e361f3e	451	*/
Anna Bridge	186:707f6e361f3e	452
Anna Bridge	186:707f6e361f3e	453	#define RCC_LSEDRIVE_LOW (0x00000000U)
Anna Bridge	186:707f6e361f3e	454	#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
Anna Bridge	186:707f6e361f3e	455	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
Anna Bridge	186:707f6e361f3e	456	#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
Anna Bridge	186:707f6e361f3e	457	/**
Anna Bridge	186:707f6e361f3e	458	* @}
Anna Bridge	186:707f6e361f3e	459	*/
Anna Bridge	186:707f6e361f3e	460
Anna Bridge	186:707f6e361f3e	461	#if defined(CRS)
Anna Bridge	186:707f6e361f3e	462
Anna Bridge	186:707f6e361f3e	463	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Anna Bridge	186:707f6e361f3e	464	* @{
Anna Bridge	186:707f6e361f3e	465	*/
Anna Bridge	186:707f6e361f3e	466	#define RCC_CRS_NONE (0x00000000U)
Anna Bridge	186:707f6e361f3e	467	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
Anna Bridge	186:707f6e361f3e	468	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
Anna Bridge	186:707f6e361f3e	469	#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004)
Anna Bridge	186:707f6e361f3e	470	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
Anna Bridge	186:707f6e361f3e	471	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
Anna Bridge	186:707f6e361f3e	472	#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020)
Anna Bridge	186:707f6e361f3e	473
Anna Bridge	186:707f6e361f3e	474	/**
Anna Bridge	186:707f6e361f3e	475	* @}
Anna Bridge	186:707f6e361f3e	476	*/
Anna Bridge	186:707f6e361f3e	477
Anna Bridge	186:707f6e361f3e	478	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
Anna Bridge	186:707f6e361f3e	479	* @{
Anna Bridge	186:707f6e361f3e	480	*/
Anna Bridge	186:707f6e361f3e	481	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /!< Synchro Signal source GPIO /
Anna Bridge	186:707f6e361f3e	482	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
Anna Bridge	186:707f6e361f3e	483	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
Anna Bridge	186:707f6e361f3e	484	/**
Anna Bridge	186:707f6e361f3e	485	* @}
Anna Bridge	186:707f6e361f3e	486	*/
Anna Bridge	186:707f6e361f3e	487
Anna Bridge	186:707f6e361f3e	488	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
Anna Bridge	186:707f6e361f3e	489	* @{
Anna Bridge	186:707f6e361f3e	490	*/
Anna Bridge	186:707f6e361f3e	491	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /!< Synchro Signal not divided (default) /
<>	144:ef7eb2e8f9f7	492	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
<>	144:ef7eb2e8f9f7	493	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
<>	144:ef7eb2e8f9f7	494	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
<>	144:ef7eb2e8f9f7	495	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
<>	144:ef7eb2e8f9f7	496	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
<>	144:ef7eb2e8f9f7	497	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
<>	144:ef7eb2e8f9f7	498	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
<>	144:ef7eb2e8f9f7	499	/**
<>	144:ef7eb2e8f9f7	500	* @}
<>	144:ef7eb2e8f9f7	501	*/
<>	144:ef7eb2e8f9f7	502
Anna Bridge	186:707f6e361f3e	503	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
<>	144:ef7eb2e8f9f7	504	* @{
<>	144:ef7eb2e8f9f7	505	*/
Anna Bridge	186:707f6e361f3e	506	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /!< Synchro Active on rising edge (default) /
Anna Bridge	186:707f6e361f3e	507	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
<>	144:ef7eb2e8f9f7	508	/**
<>	144:ef7eb2e8f9f7	509	* @}
<>	144:ef7eb2e8f9f7	510	*/
Anna Bridge	186:707f6e361f3e	511
Anna Bridge	186:707f6e361f3e	512	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
<>	144:ef7eb2e8f9f7	513	* @{
<>	144:ef7eb2e8f9f7	514	*/
Anna Bridge	186:707f6e361f3e	515	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
Anna Bridge	186:707f6e361f3e	516	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
<>	144:ef7eb2e8f9f7	517	/**
<>	144:ef7eb2e8f9f7	518	* @}
<>	144:ef7eb2e8f9f7	519	*/
<>	144:ef7eb2e8f9f7	520
Anna Bridge	186:707f6e361f3e	521	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
<>	144:ef7eb2e8f9f7	522	* @{
<>	144:ef7eb2e8f9f7	523	*/
Anna Bridge	186:707f6e361f3e	524	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /!< Default Frequency error limit /
<>	144:ef7eb2e8f9f7	525	/**
<>	144:ef7eb2e8f9f7	526	* @}
<>	144:ef7eb2e8f9f7	527	*/
<>	144:ef7eb2e8f9f7	528
Anna Bridge	186:707f6e361f3e	529	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
<>	144:ef7eb2e8f9f7	530	* @{
<>	144:ef7eb2e8f9f7	531	*/
Anna Bridge	186:707f6e361f3e	532	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Anna Bridge	186:707f6e361f3e	533	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Anna Bridge	186:707f6e361f3e	534	corresponds to a higher output frequency */
<>	144:ef7eb2e8f9f7	535	/**
<>	144:ef7eb2e8f9f7	536	* @}
<>	144:ef7eb2e8f9f7	537	*/
<>	144:ef7eb2e8f9f7	538
Anna Bridge	186:707f6e361f3e	539	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
<>	144:ef7eb2e8f9f7	540	* @{
<>	144:ef7eb2e8f9f7	541	*/
Anna Bridge	186:707f6e361f3e	542	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /!< Upcounting direction, the actual frequency is above the target /
Anna Bridge	186:707f6e361f3e	543	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
<>	144:ef7eb2e8f9f7	544	/**
<>	144:ef7eb2e8f9f7	545	* @}
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547
Anna Bridge	186:707f6e361f3e	548	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
<>	144:ef7eb2e8f9f7	549	* @{
<>	144:ef7eb2e8f9f7	550	*/
Anna Bridge	186:707f6e361f3e	551	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
Anna Bridge	186:707f6e361f3e	552	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
Anna Bridge	186:707f6e361f3e	553	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
Anna Bridge	186:707f6e361f3e	554	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
Anna Bridge	186:707f6e361f3e	555	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
Anna Bridge	186:707f6e361f3e	556	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
Anna Bridge	186:707f6e361f3e	557	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
<>	144:ef7eb2e8f9f7	558
<>	144:ef7eb2e8f9f7	559	/**
<>	144:ef7eb2e8f9f7	560	* @}
<>	144:ef7eb2e8f9f7	561	*/
<>	144:ef7eb2e8f9f7	562
Anna Bridge	186:707f6e361f3e	563	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
<>	144:ef7eb2e8f9f7	564	* @{
<>	144:ef7eb2e8f9f7	565	*/
Anna Bridge	186:707f6e361f3e	566	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
Anna Bridge	186:707f6e361f3e	567	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
Anna Bridge	186:707f6e361f3e	568	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
Anna Bridge	186:707f6e361f3e	569	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
Anna Bridge	186:707f6e361f3e	570	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
Anna Bridge	186:707f6e361f3e	571	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
Anna Bridge	186:707f6e361f3e	572	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/**
<>	144:ef7eb2e8f9f7	575	* @}
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577
Anna Bridge	186:707f6e361f3e	578	#endif /* CRS */
Anna Bridge	186:707f6e361f3e	579
<>	144:ef7eb2e8f9f7	580	/**
<>	144:ef7eb2e8f9f7	581	* @}
Anna Bridge	186:707f6e361f3e	582	*/
<>	144:ef7eb2e8f9f7	583
<>	144:ef7eb2e8f9f7	584	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	585	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Anna Bridge	186:707f6e361f3e	586	* @{
Anna Bridge	186:707f6e361f3e	587	*/
Anna Bridge	186:707f6e361f3e	588
<>	144:ef7eb2e8f9f7	589	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	590	* @brief Enable or disable the AHB peripheral clock.
<>	144:ef7eb2e8f9f7	591	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	592	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	593	* using it.
<>	144:ef7eb2e8f9f7	594	* @{
<>	144:ef7eb2e8f9f7	595	*/
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx) \|\| defined(STM32L021xx)
Anna Bridge	186:707f6e361f3e	598	#define __HAL_RCC_AES_CLK_ENABLE() do { \
Anna Bridge	186:707f6e361f3e	599	__IO uint32_t tmpreg; \
Anna Bridge	186:707f6e361f3e	600	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
Anna Bridge	186:707f6e361f3e	601	/* Delay after an RCC peripheral clock enabling */ \
Anna Bridge	186:707f6e361f3e	602	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
Anna Bridge	186:707f6e361f3e	603	UNUSED(tmpreg); \
Anna Bridge	186:707f6e361f3e	604	} while(0)
<>	144:ef7eb2e8f9f7	605	#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
Anna Bridge	186:707f6e361f3e	606
Anna Bridge	186:707f6e361f3e	607	#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != RESET)
Anna Bridge	186:707f6e361f3e	608	#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == RESET)
Anna Bridge	186:707f6e361f3e	609
<>	144:ef7eb2e8f9f7	610	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx \|\| STM32L021xx */
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	613	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
Anna Bridge	186:707f6e361f3e	614	__IO uint32_t tmpreg; \
Anna Bridge	186:707f6e361f3e	615	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Anna Bridge	186:707f6e361f3e	616	/* Delay after an RCC peripheral clock enabling */ \
Anna Bridge	186:707f6e361f3e	617	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Anna Bridge	186:707f6e361f3e	618	UNUSED(tmpreg); \
Anna Bridge	186:707f6e361f3e	619	} while(0)
<>	144:ef7eb2e8f9f7	620	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
<>	144:ef7eb2e8f9f7	621
Anna Bridge	186:707f6e361f3e	622	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != RESET)
Anna Bridge	186:707f6e361f3e	623	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == RESET)
Anna Bridge	186:707f6e361f3e	624
Anna Bridge	186:707f6e361f3e	625	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Anna Bridge	186:707f6e361f3e	626	__IO uint32_t tmpreg; \
Anna Bridge	186:707f6e361f3e	627	SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\
Anna Bridge	186:707f6e361f3e	628	/* Delay after an RCC peripheral clock enabling */ \
Anna Bridge	186:707f6e361f3e	629	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\
Anna Bridge	186:707f6e361f3e	630	UNUSED(tmpreg); \
Anna Bridge	186:707f6e361f3e	631	} while(0)
<>	144:ef7eb2e8f9f7	632	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
Anna Bridge	186:707f6e361f3e	633
Anna Bridge	186:707f6e361f3e	634	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET)
Anna Bridge	186:707f6e361f3e	635	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET)
Anna Bridge	186:707f6e361f3e	636	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Anna Bridge	186:707f6e361f3e	637
Anna Bridge	186:707f6e361f3e	638	/**
Anna Bridge	186:707f6e361f3e	639	* @}
Anna Bridge	186:707f6e361f3e	640	*/
Anna Bridge	186:707f6e361f3e	641
Anna Bridge	186:707f6e361f3e	642	/** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
Anna Bridge	186:707f6e361f3e	643	* @brief Enable or disable the IOPORT peripheral clock.
Anna Bridge	186:707f6e361f3e	644	* @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge	186:707f6e361f3e	645	* is disabled and the application software has to enable this clock before
Anna Bridge	186:707f6e361f3e	646	* using it.
Anna Bridge	186:707f6e361f3e	647	* @{
Anna Bridge	186:707f6e361f3e	648	*/
Anna Bridge	186:707f6e361f3e	649	#if defined(GPIOE)
Anna Bridge	186:707f6e361f3e	650	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Anna Bridge	186:707f6e361f3e	651	__IO uint32_t tmpreg; \
Anna Bridge	186:707f6e361f3e	652	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
Anna Bridge	186:707f6e361f3e	653	/* Delay after an RCC peripheral clock enabling */ \
Anna Bridge	186:707f6e361f3e	654	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
Anna Bridge	186:707f6e361f3e	655	UNUSED(tmpreg); \
Anna Bridge	186:707f6e361f3e	656	} while(0)
Anna Bridge	186:707f6e361f3e	657
Anna Bridge	186:707f6e361f3e	658	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
Anna Bridge	186:707f6e361f3e	659
Anna Bridge	186:707f6e361f3e	660	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET)
Anna Bridge	186:707f6e361f3e	661	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET)
Anna Bridge	186:707f6e361f3e	662
Anna Bridge	186:707f6e361f3e	663	#endif /* GPIOE */
Anna Bridge	186:707f6e361f3e	664	#if defined(GPIOD)
Anna Bridge	186:707f6e361f3e	665	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Anna Bridge	186:707f6e361f3e	666	__IO uint32_t tmpreg; \
Anna Bridge	186:707f6e361f3e	667	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
Anna Bridge	186:707f6e361f3e	668	/* Delay after an RCC peripheral clock enabling */ \
Anna Bridge	186:707f6e361f3e	669	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
Anna Bridge	186:707f6e361f3e	670	UNUSED(tmpreg); \
Anna Bridge	186:707f6e361f3e	671	} while(0)
Anna Bridge	186:707f6e361f3e	672	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
Anna Bridge	186:707f6e361f3e	673
Anna Bridge	186:707f6e361f3e	674	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET)
Anna Bridge	186:707f6e361f3e	675	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET)
Anna Bridge	186:707f6e361f3e	676
Anna Bridge	186:707f6e361f3e	677	#endif /* GPIOD */
Anna Bridge	186:707f6e361f3e	678	/**
Anna Bridge	186:707f6e361f3e	679	* @}
Anna Bridge	186:707f6e361f3e	680	*/
Anna Bridge	186:707f6e361f3e	681
Anna Bridge	186:707f6e361f3e	682	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Anna Bridge	186:707f6e361f3e	683	* @brief Enable or disable the APB1 peripheral clock.
Anna Bridge	186:707f6e361f3e	684	* @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge	186:707f6e361f3e	685	* is disabled and the application software has to enable this clock before
Anna Bridge	186:707f6e361f3e	686	* using it.
Anna Bridge	186:707f6e361f3e	687	* @{
Anna Bridge	186:707f6e361f3e	688	*/
Anna Bridge	186:707f6e361f3e	689
Anna Bridge	186:707f6e361f3e	690	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	691	#define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
Anna Bridge	186:707f6e361f3e	692	#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
Anna Bridge	186:707f6e361f3e	693
Anna Bridge	186:707f6e361f3e	694	#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) != RESET)
Anna Bridge	186:707f6e361f3e	695	#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) == RESET)
Anna Bridge	186:707f6e361f3e	696
Anna Bridge	186:707f6e361f3e	697	#define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
Anna Bridge	186:707f6e361f3e	698	#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
Anna Bridge	186:707f6e361f3e	699
Anna Bridge	186:707f6e361f3e	700	#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) != RESET)
Anna Bridge	186:707f6e361f3e	701	#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) == RESET)
Anna Bridge	186:707f6e361f3e	702
Anna Bridge	186:707f6e361f3e	703	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Anna Bridge	186:707f6e361f3e	704
Anna Bridge	186:707f6e361f3e	705
Anna Bridge	186:707f6e361f3e	706	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Anna Bridge	186:707f6e361f3e	707	#define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
Anna Bridge	186:707f6e361f3e	708	#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
Anna Bridge	186:707f6e361f3e	709
Anna Bridge	186:707f6e361f3e	710	#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) != RESET)
Anna Bridge	186:707f6e361f3e	711	#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) == RESET)
Anna Bridge	186:707f6e361f3e	712
Anna Bridge	186:707f6e361f3e	713	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
Anna Bridge	186:707f6e361f3e	714
Anna Bridge	186:707f6e361f3e	715	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \
Anna Bridge	186:707f6e361f3e	716	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \
Anna Bridge	186:707f6e361f3e	717	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx)
Anna Bridge	186:707f6e361f3e	718	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
Anna Bridge	186:707f6e361f3e	719	#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
Anna Bridge	186:707f6e361f3e	720	#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
Anna Bridge	186:707f6e361f3e	721	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
Anna Bridge	186:707f6e361f3e	722	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
Anna Bridge	186:707f6e361f3e	723	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
Anna Bridge	186:707f6e361f3e	724	#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
Anna Bridge	186:707f6e361f3e	725	#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
Anna Bridge	186:707f6e361f3e	726	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
Anna Bridge	186:707f6e361f3e	727
Anna Bridge	186:707f6e361f3e	728	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
Anna Bridge	186:707f6e361f3e	729	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
Anna Bridge	186:707f6e361f3e	730	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
Anna Bridge	186:707f6e361f3e	731	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
Anna Bridge	186:707f6e361f3e	732	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
Anna Bridge	186:707f6e361f3e	733	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
Anna Bridge	186:707f6e361f3e	734	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
Anna Bridge	186:707f6e361f3e	735	#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
Anna Bridge	186:707f6e361f3e	736	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
Anna Bridge	186:707f6e361f3e	737
Anna Bridge	186:707f6e361f3e	738	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != RESET)
Anna Bridge	186:707f6e361f3e	739	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != RESET)
Anna Bridge	186:707f6e361f3e	740	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != RESET)
Anna Bridge	186:707f6e361f3e	741	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != RESET)
Anna Bridge	186:707f6e361f3e	742	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != RESET)
Anna Bridge	186:707f6e361f3e	743	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != RESET)
Anna Bridge	186:707f6e361f3e	744	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != RESET)
Anna Bridge	186:707f6e361f3e	745	#define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != RESET)
Anna Bridge	186:707f6e361f3e	746	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET)
Anna Bridge	186:707f6e361f3e	747	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == RESET)
Anna Bridge	186:707f6e361f3e	748	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == RESET)
Anna Bridge	186:707f6e361f3e	749	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == RESET)
Anna Bridge	186:707f6e361f3e	750	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == RESET)
Anna Bridge	186:707f6e361f3e	751	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == RESET)
Anna Bridge	186:707f6e361f3e	752	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == RESET)
Anna Bridge	186:707f6e361f3e	753	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == RESET)
Anna Bridge	186:707f6e361f3e	754	#define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == RESET)
Anna Bridge	186:707f6e361f3e	755	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == RESET)
Anna Bridge	186:707f6e361f3e	756
Anna Bridge	186:707f6e361f3e	757	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
Anna Bridge	186:707f6e361f3e	758	/* STM32L052xx \|\| STM32L062xx \|\| */
Anna Bridge	186:707f6e361f3e	759	/* STM32L053xx \|\| STM32L063xx \|\| */
Anna Bridge	186:707f6e361f3e	760
Anna Bridge	186:707f6e361f3e	761	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	762	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
Anna Bridge	186:707f6e361f3e	763	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
Anna Bridge	186:707f6e361f3e	764	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
Anna Bridge	186:707f6e361f3e	765	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
Anna Bridge	186:707f6e361f3e	766	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
Anna Bridge	186:707f6e361f3e	767
Anna Bridge	186:707f6e361f3e	768	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
Anna Bridge	186:707f6e361f3e	769	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
Anna Bridge	186:707f6e361f3e	770	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
Anna Bridge	186:707f6e361f3e	771	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
Anna Bridge	186:707f6e361f3e	772	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
Anna Bridge	186:707f6e361f3e	773
Anna Bridge	186:707f6e361f3e	774	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != RESET)
Anna Bridge	186:707f6e361f3e	775	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != RESET)
Anna Bridge	186:707f6e361f3e	776	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != RESET)
Anna Bridge	186:707f6e361f3e	777	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != RESET)
Anna Bridge	186:707f6e361f3e	778	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET)
Anna Bridge	186:707f6e361f3e	779	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == RESET)
Anna Bridge	186:707f6e361f3e	780	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == RESET)
Anna Bridge	186:707f6e361f3e	781	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == RESET)
Anna Bridge	186:707f6e361f3e	782	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == RESET)
Anna Bridge	186:707f6e361f3e	783	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == RESET)
Anna Bridge	186:707f6e361f3e	784
Anna Bridge	186:707f6e361f3e	785	#endif /* STM32L011xx \|\| STM32L021xx \|\| STM32L031xx \|\| STM32L041xx */
Anna Bridge	186:707f6e361f3e	786
Anna Bridge	186:707f6e361f3e	787
Anna Bridge	186:707f6e361f3e	788	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	789	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	790	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	791	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
Anna Bridge	186:707f6e361f3e	792	#define __HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
Anna Bridge	186:707f6e361f3e	793	#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
Anna Bridge	186:707f6e361f3e	794	#define __HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
Anna Bridge	186:707f6e361f3e	795	#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
Anna Bridge	186:707f6e361f3e	796	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
Anna Bridge	186:707f6e361f3e	797	#define __HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
Anna Bridge	186:707f6e361f3e	798	#define __HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
Anna Bridge	186:707f6e361f3e	799	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
Anna Bridge	186:707f6e361f3e	800	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
Anna Bridge	186:707f6e361f3e	801	#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
Anna Bridge	186:707f6e361f3e	802	#define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
Anna Bridge	186:707f6e361f3e	803	#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
Anna Bridge	186:707f6e361f3e	804	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
Anna Bridge	186:707f6e361f3e	805
Anna Bridge	186:707f6e361f3e	806	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
Anna Bridge	186:707f6e361f3e	807	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
Anna Bridge	186:707f6e361f3e	808	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
Anna Bridge	186:707f6e361f3e	809	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
Anna Bridge	186:707f6e361f3e	810	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
Anna Bridge	186:707f6e361f3e	811	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
Anna Bridge	186:707f6e361f3e	812	#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
Anna Bridge	186:707f6e361f3e	813	#define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
Anna Bridge	186:707f6e361f3e	814	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
Anna Bridge	186:707f6e361f3e	815	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
Anna Bridge	186:707f6e361f3e	816	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
Anna Bridge	186:707f6e361f3e	817	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
Anna Bridge	186:707f6e361f3e	818	#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
Anna Bridge	186:707f6e361f3e	819	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
Anna Bridge	186:707f6e361f3e	820
Anna Bridge	186:707f6e361f3e	821	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != RESET)
Anna Bridge	186:707f6e361f3e	822	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) != RESET)
Anna Bridge	186:707f6e361f3e	823	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != RESET)
Anna Bridge	186:707f6e361f3e	824	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) != RESET)
Anna Bridge	186:707f6e361f3e	825	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != RESET)
Anna Bridge	186:707f6e361f3e	826	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != RESET)
Anna Bridge	186:707f6e361f3e	827	#define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) != RESET)
Anna Bridge	186:707f6e361f3e	828	#define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) != RESET)
Anna Bridge	186:707f6e361f3e	829	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != RESET)
Anna Bridge	186:707f6e361f3e	830	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != RESET)
Anna Bridge	186:707f6e361f3e	831	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != RESET)
Anna Bridge	186:707f6e361f3e	832	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != RESET)
Anna Bridge	186:707f6e361f3e	833	#define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != RESET)
Anna Bridge	186:707f6e361f3e	834	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET)
Anna Bridge	186:707f6e361f3e	835	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == RESET)
Anna Bridge	186:707f6e361f3e	836	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) == RESET)
Anna Bridge	186:707f6e361f3e	837	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == RESET)
Anna Bridge	186:707f6e361f3e	838	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) == RESET)
Anna Bridge	186:707f6e361f3e	839	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == RESET)
Anna Bridge	186:707f6e361f3e	840	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == RESET)
Anna Bridge	186:707f6e361f3e	841	#define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) == RESET)
Anna Bridge	186:707f6e361f3e	842	#define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) == RESET)
Anna Bridge	186:707f6e361f3e	843	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == RESET)
Anna Bridge	186:707f6e361f3e	844	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == RESET)
Anna Bridge	186:707f6e361f3e	845	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == RESET)
Anna Bridge	186:707f6e361f3e	846	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == RESET)
Anna Bridge	186:707f6e361f3e	847	#define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == RESET)
Anna Bridge	186:707f6e361f3e	848	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == RESET)
Anna Bridge	186:707f6e361f3e	849
Anna Bridge	186:707f6e361f3e	850	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	851	/* STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	852	/* STM32L073xx \|\| STM32L083xx */
Anna Bridge	186:707f6e361f3e	853
Anna Bridge	186:707f6e361f3e	854	/**
Anna Bridge	186:707f6e361f3e	855	* @}
Anna Bridge	186:707f6e361f3e	856	*/
Anna Bridge	186:707f6e361f3e	857
Anna Bridge	186:707f6e361f3e	858	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	859	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	860	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \
Anna Bridge	186:707f6e361f3e	861	\|\| defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L011xx) \|\| defined(STM32L021xx)
Anna Bridge	186:707f6e361f3e	862	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Anna Bridge	186:707f6e361f3e	863	* @brief Enable or disable the APB2 peripheral clock.
Anna Bridge	186:707f6e361f3e	864	* @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge	186:707f6e361f3e	865	* is disabled and the application software has to enable this clock before
Anna Bridge	186:707f6e361f3e	866	* using it.
Anna Bridge	186:707f6e361f3e	867	* @{
Anna Bridge	186:707f6e361f3e	868	*/
Anna Bridge	186:707f6e361f3e	869	#define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
Anna Bridge	186:707f6e361f3e	870	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	871	#define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
Anna Bridge	186:707f6e361f3e	872	#endif
Anna Bridge	186:707f6e361f3e	873	#define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
Anna Bridge	186:707f6e361f3e	874	#define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
Anna Bridge	186:707f6e361f3e	875	#define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
Anna Bridge	186:707f6e361f3e	876
Anna Bridge	186:707f6e361f3e	877	#define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
Anna Bridge	186:707f6e361f3e	878	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	879	#define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
Anna Bridge	186:707f6e361f3e	880	#endif
Anna Bridge	186:707f6e361f3e	881	#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
Anna Bridge	186:707f6e361f3e	882	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
Anna Bridge	186:707f6e361f3e	883	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
Anna Bridge	186:707f6e361f3e	884	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	885	#define __HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
Anna Bridge	186:707f6e361f3e	886	#define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
Anna Bridge	186:707f6e361f3e	887	#endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
Anna Bridge	186:707f6e361f3e	888
Anna Bridge	186:707f6e361f3e	889	#define __HAL_RCC_TIM21_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM21EN) != RESET)
Anna Bridge	186:707f6e361f3e	890	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	891	#define __HAL_RCC_TIM22_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM22EN) != RESET)
Anna Bridge	186:707f6e361f3e	892	#endif
Anna Bridge	186:707f6e361f3e	893	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != RESET)
Anna Bridge	186:707f6e361f3e	894	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
Anna Bridge	186:707f6e361f3e	895	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
Anna Bridge	186:707f6e361f3e	896
Anna Bridge	186:707f6e361f3e	897	#define __HAL_RCC_TIM21_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN) == RESET)
Anna Bridge	186:707f6e361f3e	898	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	899	#define __HAL_RCC_TIM22_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN) == RESET)
Anna Bridge	186:707f6e361f3e	900	#endif
Anna Bridge	186:707f6e361f3e	901	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN) == RESET)
Anna Bridge	186:707f6e361f3e	902	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN) == RESET)
Anna Bridge	186:707f6e361f3e	903	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN) == RESET)
Anna Bridge	186:707f6e361f3e	904	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	905	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MIFIEN) != RESET)
Anna Bridge	186:707f6e361f3e	906	#define __HAL_RCC_FIREWALL_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN) == RESET)
Anna Bridge	186:707f6e361f3e	907	#endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
Anna Bridge	186:707f6e361f3e	908
Anna Bridge	186:707f6e361f3e	909	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	910	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	911	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
Anna Bridge	186:707f6e361f3e	912	/* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
Anna Bridge	186:707f6e361f3e	913
Anna Bridge	186:707f6e361f3e	914	/**
Anna Bridge	186:707f6e361f3e	915	* @}
Anna Bridge	186:707f6e361f3e	916	*/
Anna Bridge	186:707f6e361f3e	917
Anna Bridge	186:707f6e361f3e	918	/** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
Anna Bridge	186:707f6e361f3e	919	* @brief Force or release AHB peripheral reset.
Anna Bridge	186:707f6e361f3e	920	* @{
Anna Bridge	186:707f6e361f3e	921	*/
Anna Bridge	186:707f6e361f3e	922	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx) \|\| defined(STM32L021xx)
Anna Bridge	186:707f6e361f3e	923	#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
Anna Bridge	186:707f6e361f3e	924	#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
Anna Bridge	186:707f6e361f3e	925	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx \|\| STM32L021xx*/
Anna Bridge	186:707f6e361f3e	926
Anna Bridge	186:707f6e361f3e	927	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	928	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
Anna Bridge	186:707f6e361f3e	929	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
Anna Bridge	186:707f6e361f3e	930	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
Anna Bridge	186:707f6e361f3e	931	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
<>	144:ef7eb2e8f9f7	932	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
<>	144:ef7eb2e8f9f7	933
Anna Bridge	186:707f6e361f3e	934	/**
Anna Bridge	186:707f6e361f3e	935	* @}
Anna Bridge	186:707f6e361f3e	936	*/
Anna Bridge	186:707f6e361f3e	937
Anna Bridge	186:707f6e361f3e	938	/** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
Anna Bridge	186:707f6e361f3e	939	* @brief Force or release IOPORT peripheral reset.
Anna Bridge	186:707f6e361f3e	940	* @{
Anna Bridge	186:707f6e361f3e	941	*/
Anna Bridge	186:707f6e361f3e	942	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	943	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	944	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	945	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
Anna Bridge	186:707f6e361f3e	946
Anna Bridge	186:707f6e361f3e	947	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
Anna Bridge	186:707f6e361f3e	948
Anna Bridge	186:707f6e361f3e	949	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	950	/* STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	951	/* STM32L073xx \|\| STM32L083xx */
Anna Bridge	186:707f6e361f3e	952	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	953	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
Anna Bridge	186:707f6e361f3e	954	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
Anna Bridge	186:707f6e361f3e	955	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
Anna Bridge	186:707f6e361f3e	956	/**
Anna Bridge	186:707f6e361f3e	957	* @}
Anna Bridge	186:707f6e361f3e	958	*/
Anna Bridge	186:707f6e361f3e	959
Anna Bridge	186:707f6e361f3e	960	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
Anna Bridge	186:707f6e361f3e	961	* @brief Force or release APB1 peripheral reset.
Anna Bridge	186:707f6e361f3e	962	* @{
Anna Bridge	186:707f6e361f3e	963	*/
Anna Bridge	186:707f6e361f3e	964
Anna Bridge	186:707f6e361f3e	965	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \
Anna Bridge	186:707f6e361f3e	966	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \
Anna Bridge	186:707f6e361f3e	967	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx)
Anna Bridge	186:707f6e361f3e	968	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
Anna Bridge	186:707f6e361f3e	969	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
Anna Bridge	186:707f6e361f3e	970	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
Anna Bridge	186:707f6e361f3e	971	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
Anna Bridge	186:707f6e361f3e	972	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
Anna Bridge	186:707f6e361f3e	973	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
Anna Bridge	186:707f6e361f3e	974	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
Anna Bridge	186:707f6e361f3e	975	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
Anna Bridge	186:707f6e361f3e	976	#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
Anna Bridge	186:707f6e361f3e	977
Anna Bridge	186:707f6e361f3e	978	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
Anna Bridge	186:707f6e361f3e	979	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
Anna Bridge	186:707f6e361f3e	980	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
Anna Bridge	186:707f6e361f3e	981	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
Anna Bridge	186:707f6e361f3e	982	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
Anna Bridge	186:707f6e361f3e	983	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
Anna Bridge	186:707f6e361f3e	984	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
Anna Bridge	186:707f6e361f3e	985	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
Anna Bridge	186:707f6e361f3e	986	#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
Anna Bridge	186:707f6e361f3e	987	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
Anna Bridge	186:707f6e361f3e	988	/* STM32L052xx \|\| STM32L062xx \|\| */
Anna Bridge	186:707f6e361f3e	989	/* STM32L053xx \|\| STM32L063xx */
Anna Bridge	186:707f6e361f3e	990	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	991	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
Anna Bridge	186:707f6e361f3e	992	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
Anna Bridge	186:707f6e361f3e	993	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
Anna Bridge	186:707f6e361f3e	994	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
Anna Bridge	186:707f6e361f3e	995	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
Anna Bridge	186:707f6e361f3e	996
Anna Bridge	186:707f6e361f3e	997	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
Anna Bridge	186:707f6e361f3e	998	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
Anna Bridge	186:707f6e361f3e	999	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
Anna Bridge	186:707f6e361f3e	1000	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
Anna Bridge	186:707f6e361f3e	1001	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
Anna Bridge	186:707f6e361f3e	1002	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
Anna Bridge	186:707f6e361f3e	1003
Anna Bridge	186:707f6e361f3e	1004	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	1005	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	1006	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	1007	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
Anna Bridge	186:707f6e361f3e	1008	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
Anna Bridge	186:707f6e361f3e	1009	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
Anna Bridge	186:707f6e361f3e	1010	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
Anna Bridge	186:707f6e361f3e	1011	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
Anna Bridge	186:707f6e361f3e	1012	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
Anna Bridge	186:707f6e361f3e	1013	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
Anna Bridge	186:707f6e361f3e	1014	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
Anna Bridge	186:707f6e361f3e	1015	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
Anna Bridge	186:707f6e361f3e	1016	#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
Anna Bridge	186:707f6e361f3e	1017	#define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
Anna Bridge	186:707f6e361f3e	1018	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
Anna Bridge	186:707f6e361f3e	1019	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
Anna Bridge	186:707f6e361f3e	1020	#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
Anna Bridge	186:707f6e361f3e	1021
Anna Bridge	186:707f6e361f3e	1022	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
Anna Bridge	186:707f6e361f3e	1023	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
Anna Bridge	186:707f6e361f3e	1024	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
Anna Bridge	186:707f6e361f3e	1025	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
Anna Bridge	186:707f6e361f3e	1026	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
Anna Bridge	186:707f6e361f3e	1027	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
Anna Bridge	186:707f6e361f3e	1028	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
Anna Bridge	186:707f6e361f3e	1029	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
Anna Bridge	186:707f6e361f3e	1030	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
Anna Bridge	186:707f6e361f3e	1031	#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
Anna Bridge	186:707f6e361f3e	1032	#define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
Anna Bridge	186:707f6e361f3e	1033	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
Anna Bridge	186:707f6e361f3e	1034	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
Anna Bridge	186:707f6e361f3e	1035	#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
Anna Bridge	186:707f6e361f3e	1036	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	1037	/* STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	1038	/* STM32L073xx \|\| STM32L083xx \|\| */
Anna Bridge	186:707f6e361f3e	1039
Anna Bridge	186:707f6e361f3e	1040	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	1041	#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
Anna Bridge	186:707f6e361f3e	1042	#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
Anna Bridge	186:707f6e361f3e	1043	#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST))
Anna Bridge	186:707f6e361f3e	1044	#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST))
Anna Bridge	186:707f6e361f3e	1045	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Anna Bridge	186:707f6e361f3e	1046
Anna Bridge	186:707f6e361f3e	1047	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Anna Bridge	186:707f6e361f3e	1048	#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
Anna Bridge	186:707f6e361f3e	1049	#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
Anna Bridge	186:707f6e361f3e	1050	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
Anna Bridge	186:707f6e361f3e	1051
Anna Bridge	186:707f6e361f3e	1052	/**
Anna Bridge	186:707f6e361f3e	1053	* @}
Anna Bridge	186:707f6e361f3e	1054	*/
Anna Bridge	186:707f6e361f3e	1055
Anna Bridge	186:707f6e361f3e	1056	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	1057	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	1058	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	1059
Anna Bridge	186:707f6e361f3e	1060	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
Anna Bridge	186:707f6e361f3e	1061	* @brief Force or release APB2 peripheral reset.
Anna Bridge	186:707f6e361f3e	1062	* @{
Anna Bridge	186:707f6e361f3e	1063	*/
Anna Bridge	186:707f6e361f3e	1064	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
Anna Bridge	186:707f6e361f3e	1065	#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
Anna Bridge	186:707f6e361f3e	1066	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
Anna Bridge	186:707f6e361f3e	1067	#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
Anna Bridge	186:707f6e361f3e	1068	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1069	#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
Anna Bridge	186:707f6e361f3e	1070	#endif
Anna Bridge	186:707f6e361f3e	1071
Anna Bridge	186:707f6e361f3e	1072	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
Anna Bridge	186:707f6e361f3e	1073	#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
Anna Bridge	186:707f6e361f3e	1074	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
Anna Bridge	186:707f6e361f3e	1075	#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
Anna Bridge	186:707f6e361f3e	1076	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1077	#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
Anna Bridge	186:707f6e361f3e	1078	#endif
Anna Bridge	186:707f6e361f3e	1079	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	1080	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	1081	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
Anna Bridge	186:707f6e361f3e	1082	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	1083	#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
Anna Bridge	186:707f6e361f3e	1084	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
Anna Bridge	186:707f6e361f3e	1085	#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
Anna Bridge	186:707f6e361f3e	1086	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1087	#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
Anna Bridge	186:707f6e361f3e	1088	#endif
Anna Bridge	186:707f6e361f3e	1089	#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
Anna Bridge	186:707f6e361f3e	1090	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
Anna Bridge	186:707f6e361f3e	1091	#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
Anna Bridge	186:707f6e361f3e	1092	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1093	#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
Anna Bridge	186:707f6e361f3e	1094	#endif
Anna Bridge	186:707f6e361f3e	1095	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx*/
Anna Bridge	186:707f6e361f3e	1096
Anna Bridge	186:707f6e361f3e	1097	/**
Anna Bridge	186:707f6e361f3e	1098	* @}
Anna Bridge	186:707f6e361f3e	1099	*/
Anna Bridge	186:707f6e361f3e	1100
Anna Bridge	186:707f6e361f3e	1101	/** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
Anna Bridge	186:707f6e361f3e	1102	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
Anna Bridge	186:707f6e361f3e	1103	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Anna Bridge	186:707f6e361f3e	1104	* power consumption.
Anna Bridge	186:707f6e361f3e	1105	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Anna Bridge	186:707f6e361f3e	1106	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Anna Bridge	186:707f6e361f3e	1107	* @{
Anna Bridge	186:707f6e361f3e	1108	*/
Anna Bridge	186:707f6e361f3e	1109
Anna Bridge	186:707f6e361f3e	1110	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	1111	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
Anna Bridge	186:707f6e361f3e	1112	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
Anna Bridge	186:707f6e361f3e	1113	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
Anna Bridge	186:707f6e361f3e	1114	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
Anna Bridge	186:707f6e361f3e	1115
Anna Bridge	186:707f6e361f3e	1116	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1117	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1118	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1119	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1120	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Anna Bridge	186:707f6e361f3e	1121
Anna Bridge	186:707f6e361f3e	1122	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	1123	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
Anna Bridge	186:707f6e361f3e	1124	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
Anna Bridge	186:707f6e361f3e	1125
Anna Bridge	186:707f6e361f3e	1126	#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1127	#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1128	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx */
Anna Bridge	186:707f6e361f3e	1129
Anna Bridge	186:707f6e361f3e	1130	/**
Anna Bridge	186:707f6e361f3e	1131	* @}
Anna Bridge	186:707f6e361f3e	1132	*/
Anna Bridge	186:707f6e361f3e	1133
Anna Bridge	186:707f6e361f3e	1134	/** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
Anna Bridge	186:707f6e361f3e	1135	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
Anna Bridge	186:707f6e361f3e	1136	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Anna Bridge	186:707f6e361f3e	1137	* power consumption.
Anna Bridge	186:707f6e361f3e	1138	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Anna Bridge	186:707f6e361f3e	1139	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Anna Bridge	186:707f6e361f3e	1140	* @{
Anna Bridge	186:707f6e361f3e	1141	*/
Anna Bridge	186:707f6e361f3e	1142	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	1143	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	1144	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	1145	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
Anna Bridge	186:707f6e361f3e	1146	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
Anna Bridge	186:707f6e361f3e	1147
Anna Bridge	186:707f6e361f3e	1148	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1149	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1150	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	1151	/* STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	1152	/* STM32L073xx \|\| STM32L083xx \|\| */
Anna Bridge	186:707f6e361f3e	1153	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	1154	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
Anna Bridge	186:707f6e361f3e	1155	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
Anna Bridge	186:707f6e361f3e	1156
Anna Bridge	186:707f6e361f3e	1157	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1158	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1159	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
Anna Bridge	186:707f6e361f3e	1160	/**
Anna Bridge	186:707f6e361f3e	1161	* @}
Anna Bridge	186:707f6e361f3e	1162	*/
Anna Bridge	186:707f6e361f3e	1163
Anna Bridge	186:707f6e361f3e	1164
Anna Bridge	186:707f6e361f3e	1165	/** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
Anna Bridge	186:707f6e361f3e	1166	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Anna Bridge	186:707f6e361f3e	1167	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Anna Bridge	186:707f6e361f3e	1168	* power consumption.
Anna Bridge	186:707f6e361f3e	1169	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Anna Bridge	186:707f6e361f3e	1170	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Anna Bridge	186:707f6e361f3e	1171	* @{
Anna Bridge	186:707f6e361f3e	1172	*/
Anna Bridge	186:707f6e361f3e	1173
Anna Bridge	186:707f6e361f3e	1174	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \
Anna Bridge	186:707f6e361f3e	1175	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \
Anna Bridge	186:707f6e361f3e	1176	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx)
Anna Bridge	186:707f6e361f3e	1177	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Anna Bridge	186:707f6e361f3e	1178	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
Anna Bridge	186:707f6e361f3e	1179	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
Anna Bridge	186:707f6e361f3e	1180	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Anna Bridge	186:707f6e361f3e	1181	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Anna Bridge	186:707f6e361f3e	1182	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
Anna Bridge	186:707f6e361f3e	1183	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
Anna Bridge	186:707f6e361f3e	1184	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
Anna Bridge	186:707f6e361f3e	1185	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
Anna Bridge	186:707f6e361f3e	1186
Anna Bridge	186:707f6e361f3e	1187	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Anna Bridge	186:707f6e361f3e	1188	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
Anna Bridge	186:707f6e361f3e	1189	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
Anna Bridge	186:707f6e361f3e	1190	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Anna Bridge	186:707f6e361f3e	1191	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Anna Bridge	186:707f6e361f3e	1192	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
Anna Bridge	186:707f6e361f3e	1193	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
Anna Bridge	186:707f6e361f3e	1194	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
Anna Bridge	186:707f6e361f3e	1195	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
Anna Bridge	186:707f6e361f3e	1196
Anna Bridge	186:707f6e361f3e	1197	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1198	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1199	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1200	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1201	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1202	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1203	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1204	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1205	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1206	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1207	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1208	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1209	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1210	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1211	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1212	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1213	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1214	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1215	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
Anna Bridge	186:707f6e361f3e	1216	/* STM32L052xx \|\| STM32L062xx \|\| */
Anna Bridge	186:707f6e361f3e	1217	/* STM32L053xx \|\| STM32L063xx */
Anna Bridge	186:707f6e361f3e	1218
Anna Bridge	186:707f6e361f3e	1219	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	1220	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	1221	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	1222	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Anna Bridge	186:707f6e361f3e	1223	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
Anna Bridge	186:707f6e361f3e	1224	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
Anna Bridge	186:707f6e361f3e	1225	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
Anna Bridge	186:707f6e361f3e	1226	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
Anna Bridge	186:707f6e361f3e	1227	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Anna Bridge	186:707f6e361f3e	1228	#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
Anna Bridge	186:707f6e361f3e	1229	#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
Anna Bridge	186:707f6e361f3e	1230	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Anna Bridge	186:707f6e361f3e	1231	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
Anna Bridge	186:707f6e361f3e	1232	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
Anna Bridge	186:707f6e361f3e	1233	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
Anna Bridge	186:707f6e361f3e	1234	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
Anna Bridge	186:707f6e361f3e	1235	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
Anna Bridge	186:707f6e361f3e	1236
Anna Bridge	186:707f6e361f3e	1237	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Anna Bridge	186:707f6e361f3e	1238	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
Anna Bridge	186:707f6e361f3e	1239	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
Anna Bridge	186:707f6e361f3e	1240	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
Anna Bridge	186:707f6e361f3e	1241	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
Anna Bridge	186:707f6e361f3e	1242	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Anna Bridge	186:707f6e361f3e	1243	#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
Anna Bridge	186:707f6e361f3e	1244	#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
Anna Bridge	186:707f6e361f3e	1245	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Anna Bridge	186:707f6e361f3e	1246	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
Anna Bridge	186:707f6e361f3e	1247	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
Anna Bridge	186:707f6e361f3e	1248	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
Anna Bridge	186:707f6e361f3e	1249	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
Anna Bridge	186:707f6e361f3e	1250	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
Anna Bridge	186:707f6e361f3e	1251
Anna Bridge	186:707f6e361f3e	1252	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1253	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1254	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1255	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1256	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1257	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1258	#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1259	#define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1260	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1261	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1262	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1263	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1264	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1265	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1266	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1267	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1268	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1269	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1270	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1271	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1272	#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1273	#define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1274	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1275	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1276	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1277	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1278	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1279	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1280	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	1281	/* STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	1282	/* STM32L073xx \|\| STM32L083xx \|\| */
Anna Bridge	186:707f6e361f3e	1283
Anna Bridge	186:707f6e361f3e	1284	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
Anna Bridge	186:707f6e361f3e	1285	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Anna Bridge	186:707f6e361f3e	1286	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Anna Bridge	186:707f6e361f3e	1287	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Anna Bridge	186:707f6e361f3e	1288	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
Anna Bridge	186:707f6e361f3e	1289	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
Anna Bridge	186:707f6e361f3e	1290
Anna Bridge	186:707f6e361f3e	1291	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Anna Bridge	186:707f6e361f3e	1292	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Anna Bridge	186:707f6e361f3e	1293	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Anna Bridge	186:707f6e361f3e	1294	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
Anna Bridge	186:707f6e361f3e	1295	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
Anna Bridge	186:707f6e361f3e	1296
Anna Bridge	186:707f6e361f3e	1297	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1298	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1299	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1300	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1301	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1302	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1303	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1304	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1305	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1306	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1307
Anna Bridge	186:707f6e361f3e	1308	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
Anna Bridge	186:707f6e361f3e	1309
Anna Bridge	186:707f6e361f3e	1310	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	1311	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
Anna Bridge	186:707f6e361f3e	1312	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
Anna Bridge	186:707f6e361f3e	1313	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
Anna Bridge	186:707f6e361f3e	1314	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
Anna Bridge	186:707f6e361f3e	1315
Anna Bridge	186:707f6e361f3e	1316	#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1317	#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1318	#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1319	#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1320	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Anna Bridge	186:707f6e361f3e	1321
Anna Bridge	186:707f6e361f3e	1322	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Anna Bridge	186:707f6e361f3e	1323	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
Anna Bridge	186:707f6e361f3e	1324	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
Anna Bridge	186:707f6e361f3e	1325
Anna Bridge	186:707f6e361f3e	1326	#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1327	#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1328	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
Anna Bridge	186:707f6e361f3e	1329
Anna Bridge	186:707f6e361f3e	1330	/**
Anna Bridge	186:707f6e361f3e	1331	* @}
Anna Bridge	186:707f6e361f3e	1332	*/
Anna Bridge	186:707f6e361f3e	1333
Anna Bridge	186:707f6e361f3e	1334	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	1335	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
Anna Bridge	186:707f6e361f3e	1336	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \
Anna Bridge	186:707f6e361f3e	1337	\|\| defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L011xx) \|\| defined(STM32L021xx)
Anna Bridge	186:707f6e361f3e	1338
Anna Bridge	186:707f6e361f3e	1339	/** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
Anna Bridge	186:707f6e361f3e	1340	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Anna Bridge	186:707f6e361f3e	1341	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Anna Bridge	186:707f6e361f3e	1342	* power consumption.
Anna Bridge	186:707f6e361f3e	1343	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Anna Bridge	186:707f6e361f3e	1344	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Anna Bridge	186:707f6e361f3e	1345	* @{
Anna Bridge	186:707f6e361f3e	1346	*/
Anna Bridge	186:707f6e361f3e	1347	#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
Anna Bridge	186:707f6e361f3e	1348	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1349	#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
Anna Bridge	186:707f6e361f3e	1350	#endif
Anna Bridge	186:707f6e361f3e	1351	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
Anna Bridge	186:707f6e361f3e	1352	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
Anna Bridge	186:707f6e361f3e	1353	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
Anna Bridge	186:707f6e361f3e	1354
Anna Bridge	186:707f6e361f3e	1355	#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
Anna Bridge	186:707f6e361f3e	1356	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1357	#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
Anna Bridge	186:707f6e361f3e	1358	#endif
Anna Bridge	186:707f6e361f3e	1359	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
Anna Bridge	186:707f6e361f3e	1360	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
Anna Bridge	186:707f6e361f3e	1361	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
Anna Bridge	186:707f6e361f3e	1362
Anna Bridge	186:707f6e361f3e	1363	#define __HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM21SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1364	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1365	#define __HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM22SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1366	#endif
Anna Bridge	186:707f6e361f3e	1367	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADC1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1368	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1369	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1370
Anna Bridge	186:707f6e361f3e	1371	#define __HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1372	#if !defined (STM32L011xx) && !defined (STM32L021xx)
Anna Bridge	186:707f6e361f3e	1373	#define __HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1374	#endif
Anna Bridge	186:707f6e361f3e	1375	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1376	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1377	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1378
Anna Bridge	186:707f6e361f3e	1379	/**
Anna Bridge	186:707f6e361f3e	1380	* @}
Anna Bridge	186:707f6e361f3e	1381	*/
Anna Bridge	186:707f6e361f3e	1382
Anna Bridge	186:707f6e361f3e	1383	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
Anna Bridge	186:707f6e361f3e	1384	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
Anna Bridge	186:707f6e361f3e	1385	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
Anna Bridge	186:707f6e361f3e	1386	/* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
Anna Bridge	186:707f6e361f3e	1387
<>	144:ef7eb2e8f9f7	1388
<>	144:ef7eb2e8f9f7	1389	/**
<>	144:ef7eb2e8f9f7	1390	* @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
<>	144:ef7eb2e8f9f7	1391	* @retval None
<>	144:ef7eb2e8f9f7	1392	*/
<>	144:ef7eb2e8f9f7	1393	#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1394
<>	144:ef7eb2e8f9f7	1395	/**
<>	144:ef7eb2e8f9f7	1396	* @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
<>	144:ef7eb2e8f9f7	1397	* @retval None
<>	144:ef7eb2e8f9f7	1398	*/
<>	144:ef7eb2e8f9f7	1399	#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	/**
<>	144:ef7eb2e8f9f7	1402	* @brief Enable event on RCC LSE CSS EXTI Line 19.
<>	144:ef7eb2e8f9f7	1403	* @retval None.
<>	144:ef7eb2e8f9f7	1404	*/
<>	144:ef7eb2e8f9f7	1405	#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	/**
<>	144:ef7eb2e8f9f7	1408	* @brief Disable event on RCC LSE CSS EXTI Line 19.
<>	144:ef7eb2e8f9f7	1409	* @retval None.
<>	144:ef7eb2e8f9f7	1410	*/
<>	144:ef7eb2e8f9f7	1411	#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	/**
<>	144:ef7eb2e8f9f7	1415	* @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.
<>	144:ef7eb2e8f9f7	1416	* @retval None.
<>	144:ef7eb2e8f9f7	1417	*/
<>	144:ef7eb2e8f9f7	1418	#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1419
<>	144:ef7eb2e8f9f7	1420
<>	144:ef7eb2e8f9f7	1421	/**
<>	144:ef7eb2e8f9f7	1422	* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
<>	144:ef7eb2e8f9f7	1423	* @retval None.
<>	144:ef7eb2e8f9f7	1424	*/
<>	144:ef7eb2e8f9f7	1425	#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1426
<>	144:ef7eb2e8f9f7	1427
<>	144:ef7eb2e8f9f7	1428	/**
<>	144:ef7eb2e8f9f7	1429	* @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.
<>	144:ef7eb2e8f9f7	1430	* @retval None.
<>	144:ef7eb2e8f9f7	1431	*/
<>	144:ef7eb2e8f9f7	1432	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1433
<>	144:ef7eb2e8f9f7	1434	/**
<>	144:ef7eb2e8f9f7	1435	* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
<>	144:ef7eb2e8f9f7	1436	* @retval None.
<>	144:ef7eb2e8f9f7	1437	*/
<>	144:ef7eb2e8f9f7	1438	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1439
<>	144:ef7eb2e8f9f7	1440	/**
<>	144:ef7eb2e8f9f7	1441	* @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
<>	144:ef7eb2e8f9f7	1442	* @retval None.
<>	144:ef7eb2e8f9f7	1443	*/
<>	144:ef7eb2e8f9f7	1444	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
<>	144:ef7eb2e8f9f7	1445	do { \
<>	144:ef7eb2e8f9f7	1446	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
<>	144:ef7eb2e8f9f7	1447	__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
<>	144:ef7eb2e8f9f7	1448	} while(0)
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/**
<>	144:ef7eb2e8f9f7	1451	* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
<>	144:ef7eb2e8f9f7	1452	* @retval None.
<>	144:ef7eb2e8f9f7	1453	*/
<>	144:ef7eb2e8f9f7	1454	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
<>	144:ef7eb2e8f9f7	1455	do { \
<>	144:ef7eb2e8f9f7	1456	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
<>	144:ef7eb2e8f9f7	1457	__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
<>	144:ef7eb2e8f9f7	1458	} while(0)
<>	144:ef7eb2e8f9f7	1459
<>	144:ef7eb2e8f9f7	1460	/**
<>	144:ef7eb2e8f9f7	1461	* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
<>	144:ef7eb2e8f9f7	1462	* @retval EXTI RCC LSE CSS Line Status.
<>	144:ef7eb2e8f9f7	1463	*/
<>	144:ef7eb2e8f9f7	1464	#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	/**
<>	144:ef7eb2e8f9f7	1467	* @brief Clear the RCC LSE CSS EXTI flag.
<>	144:ef7eb2e8f9f7	1468	* @retval None.
<>	144:ef7eb2e8f9f7	1469	*/
<>	144:ef7eb2e8f9f7	1470	#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
<>	144:ef7eb2e8f9f7	1471
<>	144:ef7eb2e8f9f7	1472	/**
<>	144:ef7eb2e8f9f7	1473	* @brief Generate a Software interrupt on selected EXTI line.
<>	144:ef7eb2e8f9f7	1474	* @retval None.
<>	144:ef7eb2e8f9f7	1475	*/
<>	144:ef7eb2e8f9f7	1476	#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478
Anna Bridge	186:707f6e361f3e	1479	#if defined(LCD)
Anna Bridge	186:707f6e361f3e	1480
Anna Bridge	186:707f6e361f3e	1481	/** @defgroup RCCEx_LCD_Configuration LCD Configuration
Anna Bridge	186:707f6e361f3e	1482	* @brief Macros to configure clock source of LCD peripherals.
<>	144:ef7eb2e8f9f7	1483	* @{
Anna Bridge	186:707f6e361f3e	1484	*/
<>	144:ef7eb2e8f9f7	1485
<>	144:ef7eb2e8f9f7	1486	/** @brief Macro to configures LCD clock (LCDCLK).
<>	144:ef7eb2e8f9f7	1487	* @note LCD and RTC use the same configuration
<>	144:ef7eb2e8f9f7	1488	* @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
Anna Bridge	186:707f6e361f3e	1489	* LCD clock source.
<>	144:ef7eb2e8f9f7	1490	*
<>	144:ef7eb2e8f9f7	1491	* @param __LCD_CLKSOURCE__ specifies the LCD clock source.
<>	144:ef7eb2e8f9f7	1492	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1493	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
<>	144:ef7eb2e8f9f7	1494	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
<>	144:ef7eb2e8f9f7	1495	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
<>	144:ef7eb2e8f9f7	1496	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
<>	144:ef7eb2e8f9f7	1497	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
<>	144:ef7eb2e8f9f7	1498	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
<>	144:ef7eb2e8f9f7	1499	*/
<>	144:ef7eb2e8f9f7	1500	#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
<>	144:ef7eb2e8f9f7	1501
Anna Bridge	186:707f6e361f3e	1502	/** @brief Macro to get the LCD clock source.
<>	144:ef7eb2e8f9f7	1503	*/
<>	144:ef7eb2e8f9f7	1504	#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
<>	144:ef7eb2e8f9f7	1505
Anna Bridge	186:707f6e361f3e	1506	/** @brief Macro to get the LCD clock pre-scaler.
<>	144:ef7eb2e8f9f7	1507	*/
<>	144:ef7eb2e8f9f7	1508	#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()
Anna Bridge	186:707f6e361f3e	1509
<>	144:ef7eb2e8f9f7	1510	/**
<>	144:ef7eb2e8f9f7	1511	* @}
<>	144:ef7eb2e8f9f7	1512	*/
Anna Bridge	186:707f6e361f3e	1513
Anna Bridge	186:707f6e361f3e	1514	#endif /* LCD */
Anna Bridge	186:707f6e361f3e	1515
Anna Bridge	186:707f6e361f3e	1516	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
<>	144:ef7eb2e8f9f7	1517	*
Anna Bridge	186:707f6e361f3e	1518	* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
<>	144:ef7eb2e8f9f7	1519	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1520	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
Anna Bridge	186:707f6e361f3e	1521	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Anna Bridge	186:707f6e361f3e	1522	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
<>	144:ef7eb2e8f9f7	1523	*/
<>	144:ef7eb2e8f9f7	1524	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1525	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/** @brief Macro to get the I2C1 clock source.
<>	144:ef7eb2e8f9f7	1528	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1529	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
Anna Bridge	186:707f6e361f3e	1530	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Anna Bridge	186:707f6e361f3e	1531	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
<>	144:ef7eb2e8f9f7	1532	*/
<>	144:ef7eb2e8f9f7	1533	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
<>	144:ef7eb2e8f9f7	1534
Anna Bridge	186:707f6e361f3e	1535	#if defined(RCC_CCIPR_I2C3SEL)
Anna Bridge	186:707f6e361f3e	1536	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
<>	144:ef7eb2e8f9f7	1537	*
Anna Bridge	186:707f6e361f3e	1538	* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
<>	144:ef7eb2e8f9f7	1539	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1540	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
Anna Bridge	186:707f6e361f3e	1541	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Anna Bridge	186:707f6e361f3e	1542	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
<>	144:ef7eb2e8f9f7	1543	*/
<>	144:ef7eb2e8f9f7	1544	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1545	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1546
<>	144:ef7eb2e8f9f7	1547	/** @brief Macro to get the I2C3 clock source.
<>	144:ef7eb2e8f9f7	1548	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1549	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
Anna Bridge	186:707f6e361f3e	1550	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Anna Bridge	186:707f6e361f3e	1551	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
<>	144:ef7eb2e8f9f7	1552	*/
<>	144:ef7eb2e8f9f7	1553	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
<>	144:ef7eb2e8f9f7	1554
Anna Bridge	186:707f6e361f3e	1555	#endif /* RCC_CCIPR_I2C3SEL */
<>	144:ef7eb2e8f9f7	1556
Anna Bridge	186:707f6e361f3e	1557	#if defined (RCC_CCIPR_USART1SEL)
Anna Bridge	186:707f6e361f3e	1558	/** @brief Macro to configure the USART1 clock (USART1CLK).
<>	144:ef7eb2e8f9f7	1559	*
Anna Bridge	186:707f6e361f3e	1560	* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
<>	144:ef7eb2e8f9f7	1561	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1562	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Anna Bridge	186:707f6e361f3e	1563	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Anna Bridge	186:707f6e361f3e	1564	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Anna Bridge	186:707f6e361f3e	1565	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
<>	144:ef7eb2e8f9f7	1566	*/
<>	144:ef7eb2e8f9f7	1567	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1568	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1569
<>	144:ef7eb2e8f9f7	1570	/** @brief Macro to get the USART1 clock source.
<>	144:ef7eb2e8f9f7	1571	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1572	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Anna Bridge	186:707f6e361f3e	1573	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Anna Bridge	186:707f6e361f3e	1574	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Anna Bridge	186:707f6e361f3e	1575	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
<>	144:ef7eb2e8f9f7	1576	*/
<>	144:ef7eb2e8f9f7	1577	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Anna Bridge	186:707f6e361f3e	1578	#endif /* RCC_CCIPR_USART1SEL */
<>	144:ef7eb2e8f9f7	1579
Anna Bridge	186:707f6e361f3e	1580	/** @brief Macro to configure the USART2 clock (USART2CLK).
<>	144:ef7eb2e8f9f7	1581	*
Anna Bridge	186:707f6e361f3e	1582	* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
<>	144:ef7eb2e8f9f7	1583	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1584	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Anna Bridge	186:707f6e361f3e	1585	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Anna Bridge	186:707f6e361f3e	1586	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Anna Bridge	186:707f6e361f3e	1587	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
<>	144:ef7eb2e8f9f7	1588	*/
<>	144:ef7eb2e8f9f7	1589	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1590	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1591
<>	144:ef7eb2e8f9f7	1592	/** @brief Macro to get the USART2 clock source.
<>	144:ef7eb2e8f9f7	1593	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1594	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Anna Bridge	186:707f6e361f3e	1595	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Anna Bridge	186:707f6e361f3e	1596	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Anna Bridge	186:707f6e361f3e	1597	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
<>	144:ef7eb2e8f9f7	1598	*/
<>	144:ef7eb2e8f9f7	1599	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
<>	144:ef7eb2e8f9f7	1600
Anna Bridge	186:707f6e361f3e	1601	/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
<>	144:ef7eb2e8f9f7	1602	*
Anna Bridge	186:707f6e361f3e	1603	* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
<>	144:ef7eb2e8f9f7	1604	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1605	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1606	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1607	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1608	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
<>	144:ef7eb2e8f9f7	1609	*/
<>	144:ef7eb2e8f9f7	1610	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1611	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1612
<>	144:ef7eb2e8f9f7	1613	/** @brief Macro to get the LPUART1 clock source.
<>	144:ef7eb2e8f9f7	1614	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1615	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1616	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1617	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1618	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
<>	144:ef7eb2e8f9f7	1619	*/
<>	144:ef7eb2e8f9f7	1620	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
<>	144:ef7eb2e8f9f7	1621
Anna Bridge	186:707f6e361f3e	1622	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
<>	144:ef7eb2e8f9f7	1623	*
Anna Bridge	186:707f6e361f3e	1624	* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
<>	144:ef7eb2e8f9f7	1625	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1626	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPTIM1 clock
Anna Bridge	186:707f6e361f3e	1627	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
Anna Bridge	186:707f6e361f3e	1628	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
Anna Bridge	186:707f6e361f3e	1629	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	1630	*/
<>	144:ef7eb2e8f9f7	1631	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1632	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1633
<>	144:ef7eb2e8f9f7	1634	/** @brief Macro to get the LPTIM1 clock source.
<>	144:ef7eb2e8f9f7	1635	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1636	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1637	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1638	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
Anna Bridge	186:707f6e361f3e	1639	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
<>	144:ef7eb2e8f9f7	1640	*/
<>	144:ef7eb2e8f9f7	1641	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
<>	144:ef7eb2e8f9f7	1642
Anna Bridge	186:707f6e361f3e	1643	#if defined(USB)
<>	144:ef7eb2e8f9f7	1644	/** @brief Macro to configure the USB clock (USBCLK).
Anna Bridge	186:707f6e361f3e	1645	* @param __USB_CLKSOURCE__ specifies the USB clock source.
<>	144:ef7eb2e8f9f7	1646	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1647	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
Anna Bridge	186:707f6e361f3e	1648	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
<>	144:ef7eb2e8f9f7	1649	*/
Anna Bridge	186:707f6e361f3e	1650	#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
Anna Bridge	186:707f6e361f3e	1651	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USB_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1652
<>	144:ef7eb2e8f9f7	1653	/** @brief Macro to get the USB clock source.
<>	144:ef7eb2e8f9f7	1654	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1655	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
Anna Bridge	186:707f6e361f3e	1656	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
<>	144:ef7eb2e8f9f7	1657	*/
<>	144:ef7eb2e8f9f7	1658	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
Anna Bridge	186:707f6e361f3e	1659	#endif /* USB */
<>	144:ef7eb2e8f9f7	1660
Anna Bridge	186:707f6e361f3e	1661	#if defined(RNG)
<>	144:ef7eb2e8f9f7	1662	/** @brief Macro to configure the RNG clock (RNGCLK).
Anna Bridge	186:707f6e361f3e	1663	* @param __RNG_CLKSOURCE__ specifies the USB clock source.
<>	144:ef7eb2e8f9f7	1664	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1665	* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock
Anna Bridge	186:707f6e361f3e	1666	* @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock
<>	144:ef7eb2e8f9f7	1667	*/
Anna Bridge	186:707f6e361f3e	1668	#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
Anna Bridge	186:707f6e361f3e	1669	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNG_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1670
<>	144:ef7eb2e8f9f7	1671	/** @brief Macro to get the RNG clock source.
<>	144:ef7eb2e8f9f7	1672	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1673	* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock
Anna Bridge	186:707f6e361f3e	1674	* @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock
<>	144:ef7eb2e8f9f7	1675	*/
<>	144:ef7eb2e8f9f7	1676	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
Anna Bridge	186:707f6e361f3e	1677	#endif /* RNG */
<>	144:ef7eb2e8f9f7	1678
Anna Bridge	186:707f6e361f3e	1679	#if defined(RCC_CCIPR_HSI48SEL)
Anna Bridge	186:707f6e361f3e	1680	/** @brief Macro to select the HSI48M clock source
<>	144:ef7eb2e8f9f7	1681	* @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
<>	144:ef7eb2e8f9f7	1682	* __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
<>	144:ef7eb2e8f9f7	1683	*
Anna Bridge	186:707f6e361f3e	1684	* @param __HSI48M_CLKSOURCE__ specifies the HSI48M clock source dedicated for
<>	144:ef7eb2e8f9f7	1685	* USB an RNG peripherals.
<>	144:ef7eb2e8f9f7	1686	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1687	* @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output.
Anna Bridge	186:707f6e361f3e	1688	* @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator.
<>	144:ef7eb2e8f9f7	1689	*/
Anna Bridge	186:707f6e361f3e	1690	#define __HAL_RCC_HSI48M_CONFIG(__HSI48M_CLKSOURCE__) \
Anna Bridge	186:707f6e361f3e	1691	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48M_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1692
Anna Bridge	186:707f6e361f3e	1693	/** @brief Macro to get the HSI48M clock source.
<>	144:ef7eb2e8f9f7	1694	* @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
<>	144:ef7eb2e8f9f7	1695	* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
<>	144:ef7eb2e8f9f7	1696	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1697	* @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output.
Anna Bridge	186:707f6e361f3e	1698	* @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator.
<>	144:ef7eb2e8f9f7	1699	*/
<>	144:ef7eb2e8f9f7	1700	#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
Anna Bridge	186:707f6e361f3e	1701	#endif /* RCC_CCIPR_HSI48SEL */
<>	144:ef7eb2e8f9f7	1702
<>	144:ef7eb2e8f9f7	1703	/**
Anna Bridge	186:707f6e361f3e	1704	* @brief Macro to enable the force of the Internal High Speed oscillator (HSI)
<>	144:ef7eb2e8f9f7	1705	* in STOP mode to be quickly available as kernel clock for USART and I2C.
<>	144:ef7eb2e8f9f7	1706	* @note The Enable of this function has not effect on the HSION bit.
Anna Bridge	186:707f6e361f3e	1707	*/
Anna Bridge	186:707f6e361f3e	1708	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Anna Bridge	186:707f6e361f3e	1709
Anna Bridge	186:707f6e361f3e	1710	/**
Anna Bridge	186:707f6e361f3e	1711	* @brief Macro to disable the force of the Internal High Speed oscillator (HSI)
Anna Bridge	186:707f6e361f3e	1712	* in STOP mode to be quickly available as kernel clock for USART and I2C.
<>	144:ef7eb2e8f9f7	1713	* @retval None
<>	144:ef7eb2e8f9f7	1714	*/
<>	144:ef7eb2e8f9f7	1715	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	/**
<>	144:ef7eb2e8f9f7	1718	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
Anna Bridge	186:707f6e361f3e	1719	* @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
<>	144:ef7eb2e8f9f7	1720	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1721	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
Anna Bridge	186:707f6e361f3e	1722	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
Anna Bridge	186:707f6e361f3e	1723	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
Anna Bridge	186:707f6e361f3e	1724	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
<>	144:ef7eb2e8f9f7	1725	* @retval None
<>	144:ef7eb2e8f9f7	1726	*/
Anna Bridge	186:707f6e361f3e	1727	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->CSR,\
Anna Bridge	186:707f6e361f3e	1728	RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
<>	144:ef7eb2e8f9f7	1729
<>	144:ef7eb2e8f9f7	1730	/**
<>	144:ef7eb2e8f9f7	1731	* @brief Macro to configures the wake up from stop clock.
Anna Bridge	186:707f6e361f3e	1732	* @param __RCC_STOPWUCLK__ specifies the clock source used after wake up from stop
<>	144:ef7eb2e8f9f7	1733	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1734	* @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
Anna Bridge	186:707f6e361f3e	1735	* @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
<>	144:ef7eb2e8f9f7	1736	* @retval None
<>	144:ef7eb2e8f9f7	1737	*/
<>	144:ef7eb2e8f9f7	1738	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
<>	144:ef7eb2e8f9f7	1739	RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
Anna Bridge	186:707f6e361f3e	1740
Anna Bridge	186:707f6e361f3e	1741	#if defined(CRS)
<>	144:ef7eb2e8f9f7	1742	/**
<>	144:ef7eb2e8f9f7	1743	* @brief Enables the specified CRS interrupts.
Anna Bridge	186:707f6e361f3e	1744	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	1745	* This parameter can be any combination of the following values:
Anna Bridge	186:707f6e361f3e	1746	* @arg @ref RCC_CRS_IT_SYNCOK
Anna Bridge	186:707f6e361f3e	1747	* @arg @ref RCC_CRS_IT_SYNCWARN
Anna Bridge	186:707f6e361f3e	1748	* @arg @ref RCC_CRS_IT_ERR
Anna Bridge	186:707f6e361f3e	1749	* @arg @ref RCC_CRS_IT_ESYNC
<>	144:ef7eb2e8f9f7	1750	* @retval None
<>	144:ef7eb2e8f9f7	1751	*/
<>	144:ef7eb2e8f9f7	1752	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1753
<>	144:ef7eb2e8f9f7	1754	/**
<>	144:ef7eb2e8f9f7	1755	* @brief Disables the specified CRS interrupts.
Anna Bridge	186:707f6e361f3e	1756	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	1757	* This parameter can be any combination of the following values:
Anna Bridge	186:707f6e361f3e	1758	* @arg @ref RCC_CRS_IT_SYNCOK
Anna Bridge	186:707f6e361f3e	1759	* @arg @ref RCC_CRS_IT_SYNCWARN
Anna Bridge	186:707f6e361f3e	1760	* @arg @ref RCC_CRS_IT_ERR
Anna Bridge	186:707f6e361f3e	1761	* @arg @ref RCC_CRS_IT_ESYNC
<>	144:ef7eb2e8f9f7	1762	* @retval None
<>	144:ef7eb2e8f9f7	1763	*/
<>	144:ef7eb2e8f9f7	1764	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR,(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1765
<>	144:ef7eb2e8f9f7	1766	/** @brief Check the CRS interrupt has occurred or not.
Anna Bridge	186:707f6e361f3e	1767	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
<>	144:ef7eb2e8f9f7	1768	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1769	* @arg @ref RCC_CRS_IT_SYNCOK
Anna Bridge	186:707f6e361f3e	1770	* @arg @ref RCC_CRS_IT_SYNCWARN
Anna Bridge	186:707f6e361f3e	1771	* @arg @ref RCC_CRS_IT_ERR
Anna Bridge	186:707f6e361f3e	1772	* @arg @ref RCC_CRS_IT_ESYNC
<>	144:ef7eb2e8f9f7	1773	* @retval The new state of __INTERRUPT__ (SET or RESET).
<>	144:ef7eb2e8f9f7	1774	*/
<>	144:ef7eb2e8f9f7	1775	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/** @brief Clear the CRS interrupt pending bits
<>	144:ef7eb2e8f9f7	1778	* bits to clear the selected interrupt pending bits.
Anna Bridge	186:707f6e361f3e	1779	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	1780	* This parameter can be any combination of the following values:
Anna Bridge	186:707f6e361f3e	1781	* @arg @ref RCC_CRS_IT_SYNCOK
Anna Bridge	186:707f6e361f3e	1782	* @arg @ref RCC_CRS_IT_SYNCWARN
Anna Bridge	186:707f6e361f3e	1783	* @arg @ref RCC_CRS_IT_ERR
Anna Bridge	186:707f6e361f3e	1784	* @arg @ref RCC_CRS_IT_ESYNC
Anna Bridge	186:707f6e361f3e	1785	* @arg @ref RCC_CRS_IT_TRIMOVF
Anna Bridge	186:707f6e361f3e	1786	* @arg @ref RCC_CRS_IT_SYNCERR
Anna Bridge	186:707f6e361f3e	1787	* @arg @ref RCC_CRS_IT_SYNCMISS
<>	144:ef7eb2e8f9f7	1788	*/
Anna Bridge	186:707f6e361f3e	1789	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
Anna Bridge	186:707f6e361f3e	1790	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
Anna Bridge	186:707f6e361f3e	1791	{ \
Anna Bridge	186:707f6e361f3e	1792	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
Anna Bridge	186:707f6e361f3e	1793	} \
Anna Bridge	186:707f6e361f3e	1794	else \
Anna Bridge	186:707f6e361f3e	1795	{ \
Anna Bridge	186:707f6e361f3e	1796	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
Anna Bridge	186:707f6e361f3e	1797	} \
Anna Bridge	186:707f6e361f3e	1798	} while(0)
<>	144:ef7eb2e8f9f7	1799
<>	144:ef7eb2e8f9f7	1800	/**
<>	144:ef7eb2e8f9f7	1801	* @brief Checks whether the specified CRS flag is set or not.
Anna Bridge	186:707f6e361f3e	1802	* @param __FLAG__ specifies the flag to check.
<>	144:ef7eb2e8f9f7	1803	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1804	* @arg @ref RCC_CRS_FLAG_SYNCOK
Anna Bridge	186:707f6e361f3e	1805	* @arg @ref RCC_CRS_FLAG_SYNCWARN
Anna Bridge	186:707f6e361f3e	1806	* @arg @ref RCC_CRS_FLAG_ERR
Anna Bridge	186:707f6e361f3e	1807	* @arg @ref RCC_CRS_FLAG_ESYNC
Anna Bridge	186:707f6e361f3e	1808	* @arg @ref RCC_CRS_FLAG_TRIMOVF
Anna Bridge	186:707f6e361f3e	1809	* @arg @ref RCC_CRS_FLAG_SYNCERR
Anna Bridge	186:707f6e361f3e	1810	* @arg @ref RCC_CRS_FLAG_SYNCMISS
Anna Bridge	186:707f6e361f3e	1811	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1812	*/
<>	144:ef7eb2e8f9f7	1813	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	1814
<>	144:ef7eb2e8f9f7	1815	/**
<>	144:ef7eb2e8f9f7	1816	* @brief Clears the CRS specified FLAG.
Anna Bridge	186:707f6e361f3e	1817	* @param __FLAG__ specifies the flag to clear.
<>	144:ef7eb2e8f9f7	1818	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1819	* @arg @ref RCC_CRS_FLAG_SYNCOK
Anna Bridge	186:707f6e361f3e	1820	* @arg @ref RCC_CRS_FLAG_SYNCWARN
Anna Bridge	186:707f6e361f3e	1821	* @arg @ref RCC_CRS_FLAG_ERR
Anna Bridge	186:707f6e361f3e	1822	* @arg @ref RCC_CRS_FLAG_ESYNC
Anna Bridge	186:707f6e361f3e	1823	* @arg @ref RCC_CRS_FLAG_TRIMOVF
Anna Bridge	186:707f6e361f3e	1824	* @arg @ref RCC_CRS_FLAG_SYNCERR
Anna Bridge	186:707f6e361f3e	1825	* @arg @ref RCC_CRS_FLAG_SYNCMISS
<>	144:ef7eb2e8f9f7	1826	* @retval None
<>	144:ef7eb2e8f9f7	1827	*/
Anna Bridge	186:707f6e361f3e	1828	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
Anna Bridge	186:707f6e361f3e	1829	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
Anna Bridge	186:707f6e361f3e	1830	{ \
Anna Bridge	186:707f6e361f3e	1831	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
Anna Bridge	186:707f6e361f3e	1832	} \
Anna Bridge	186:707f6e361f3e	1833	else \
Anna Bridge	186:707f6e361f3e	1834	{ \
Anna Bridge	186:707f6e361f3e	1835	WRITE_REG(CRS->ICR, (__FLAG__)); \
Anna Bridge	186:707f6e361f3e	1836	} \
Anna Bridge	186:707f6e361f3e	1837	} while(0)
<>	144:ef7eb2e8f9f7	1838
<>	144:ef7eb2e8f9f7	1839	/**
<>	144:ef7eb2e8f9f7	1840	* @brief Enables the oscillator clock for frequency error counter.
<>	144:ef7eb2e8f9f7	1841	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
<>	144:ef7eb2e8f9f7	1842	* @retval None
<>	144:ef7eb2e8f9f7	1843	*/
<>	144:ef7eb2e8f9f7	1844	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
<>	144:ef7eb2e8f9f7	1845
<>	144:ef7eb2e8f9f7	1846	/**
<>	144:ef7eb2e8f9f7	1847	* @brief Disables the oscillator clock for frequency error counter.
<>	144:ef7eb2e8f9f7	1848	* @retval None
<>	144:ef7eb2e8f9f7	1849	*/
Anna Bridge	186:707f6e361f3e	1850	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
<>	144:ef7eb2e8f9f7	1851
<>	144:ef7eb2e8f9f7	1852	/**
<>	144:ef7eb2e8f9f7	1853	* @brief Enables the automatic hardware adjustment of TRIM bits.
<>	144:ef7eb2e8f9f7	1854	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
<>	144:ef7eb2e8f9f7	1855	* @retval None
<>	144:ef7eb2e8f9f7	1856	*/
<>	144:ef7eb2e8f9f7	1857	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
<>	144:ef7eb2e8f9f7	1858
<>	144:ef7eb2e8f9f7	1859	/**
<>	144:ef7eb2e8f9f7	1860	* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
<>	144:ef7eb2e8f9f7	1861	* @retval None
<>	144:ef7eb2e8f9f7	1862	*/
Anna Bridge	186:707f6e361f3e	1863	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
<>	144:ef7eb2e8f9f7	1864
<>	144:ef7eb2e8f9f7	1865	/**
<>	144:ef7eb2e8f9f7	1866	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
<>	144:ef7eb2e8f9f7	1867	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
<>	144:ef7eb2e8f9f7	1868	* of the synchronization source after prescaling. It is then decreased by one in order to
<>	144:ef7eb2e8f9f7	1869	* reach the expected synchronization on the zero value. The formula is the following:
<>	144:ef7eb2e8f9f7	1870	* RELOAD = (fTARGET / fSYNC) -1
<>	144:ef7eb2e8f9f7	1871	* @param __FTARGET__ Target frequency (value in Hz)
Anna Bridge	186:707f6e361f3e	1872	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
<>	144:ef7eb2e8f9f7	1873	* @retval None
<>	144:ef7eb2e8f9f7	1874	*/
<>	144:ef7eb2e8f9f7	1875	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
<>	144:ef7eb2e8f9f7	1876
Anna Bridge	186:707f6e361f3e	1877	#endif /* CRS */
Anna Bridge	186:707f6e361f3e	1878
<>	144:ef7eb2e8f9f7	1879
Anna Bridge	186:707f6e361f3e	1880	#if defined(RCC_CR_HSIOUTEN)
Anna Bridge	186:707f6e361f3e	1881	/** @brief Enable he HSI OUT .
<>	144:ef7eb2e8f9f7	1882	* @note After reset, the HSI output is not available
<>	144:ef7eb2e8f9f7	1883	*/
<>	144:ef7eb2e8f9f7	1884
<>	144:ef7eb2e8f9f7	1885	#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
Anna Bridge	186:707f6e361f3e	1886
Anna Bridge	186:707f6e361f3e	1887	/** @brief Disable the HSI OUT .
Anna Bridge	186:707f6e361f3e	1888	* @note After reset, the HSI output is not available
Anna Bridge	186:707f6e361f3e	1889	*/
Anna Bridge	186:707f6e361f3e	1890
<>	144:ef7eb2e8f9f7	1891	#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
<>	144:ef7eb2e8f9f7	1892
Anna Bridge	186:707f6e361f3e	1893	#endif /* RCC_CR_HSIOUTEN */
<>	144:ef7eb2e8f9f7	1894
Anna Bridge	186:707f6e361f3e	1895	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)\
Anna Bridge	186:707f6e361f3e	1896	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx)
<>	144:ef7eb2e8f9f7	1897
<>	144:ef7eb2e8f9f7	1898	/**
Anna Bridge	186:707f6e361f3e	1899	* @brief Enable the Internal High Speed oscillator for USB (HSI48).
<>	144:ef7eb2e8f9f7	1900	* @note After enabling the HSI48, the application software should wait on
<>	144:ef7eb2e8f9f7	1901	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
<>	144:ef7eb2e8f9f7	1902	* be used to clock the USB.
<>	144:ef7eb2e8f9f7	1903	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1904	*/
Anna Bridge	186:707f6e361f3e	1905	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
Anna Bridge	186:707f6e361f3e	1906	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
Anna Bridge	186:707f6e361f3e	1907	SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \
Anna Bridge	186:707f6e361f3e	1908	} while (0)
Anna Bridge	186:707f6e361f3e	1909	/**
Anna Bridge	186:707f6e361f3e	1910	* @brief Disable the Internal High Speed oscillator for USB (HSI48).
Anna Bridge	186:707f6e361f3e	1911	*/
<>	144:ef7eb2e8f9f7	1912	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
Anna Bridge	186:707f6e361f3e	1913	CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \
Anna Bridge	186:707f6e361f3e	1914	} while (0)
Anna Bridge	186:707f6e361f3e	1915
Anna Bridge	186:707f6e361f3e	1916	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Anna Bridge	186:707f6e361f3e	1917	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1918	* @arg @ref RCC_HSI48_ON HSI48 enabled
Anna Bridge	186:707f6e361f3e	1919	* @arg @ref RCC_HSI48_OFF HSI48 disabled
Anna Bridge	186:707f6e361f3e	1920	*/
Anna Bridge	186:707f6e361f3e	1921	#define __HAL_RCC_GET_HSI48_STATE() \
Anna Bridge	186:707f6e361f3e	1922	(((uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
Anna Bridge	186:707f6e361f3e	1923
<>	144:ef7eb2e8f9f7	1924	/** @brief Enable or disable the HSI48M DIV6 OUT .
<>	144:ef7eb2e8f9f7	1925	* @note After reset, the HSI48Mhz (divided by 6) output is not available
<>	144:ef7eb2e8f9f7	1926	*/
<>	144:ef7eb2e8f9f7	1927
<>	144:ef7eb2e8f9f7	1928	#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
<>	144:ef7eb2e8f9f7	1929	#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
<>	144:ef7eb2e8f9f7	1930
<>	144:ef7eb2e8f9f7	1931	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
<>	144:ef7eb2e8f9f7	1932	/* STM32L072xx \|\| STM32L082xx \|\| */
<>	144:ef7eb2e8f9f7	1933	/* STM32L073xx \|\| STM32L083xx */
<>	144:ef7eb2e8f9f7	1934
Anna Bridge	186:707f6e361f3e	1935
<>	144:ef7eb2e8f9f7	1936	/**
<>	144:ef7eb2e8f9f7	1937	* @}
<>	144:ef7eb2e8f9f7	1938	*/
<>	144:ef7eb2e8f9f7	1939
Anna Bridge	186:707f6e361f3e	1940	/* Exported functions --------------------------------------------------------*/
Anna Bridge	186:707f6e361f3e	1941	/** @addtogroup RCCEx_Exported_Functions
<>	144:ef7eb2e8f9f7	1942	* @{
<>	144:ef7eb2e8f9f7	1943	*/
<>	144:ef7eb2e8f9f7	1944
Anna Bridge	186:707f6e361f3e	1945	/** @addtogroup RCCEx_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1946	* @{
<>	144:ef7eb2e8f9f7	1947	*/
<>	144:ef7eb2e8f9f7	1948
Anna Bridge	186:707f6e361f3e	1949	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Anna Bridge	186:707f6e361f3e	1950	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Anna Bridge	186:707f6e361f3e	1951	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
<>	144:ef7eb2e8f9f7	1952
<>	144:ef7eb2e8f9f7	1953
Anna Bridge	186:707f6e361f3e	1954	void HAL_RCCEx_EnableLSECSS(void);
Anna Bridge	186:707f6e361f3e	1955	void HAL_RCCEx_DisableLSECSS(void);
Anna Bridge	186:707f6e361f3e	1956	void HAL_RCCEx_EnableLSECSS_IT(void);
Anna Bridge	186:707f6e361f3e	1957	void HAL_RCCEx_LSECSS_IRQHandler(void);
Anna Bridge	186:707f6e361f3e	1958	void HAL_RCCEx_LSECSS_Callback(void);
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960
Anna Bridge	186:707f6e361f3e	1961	#if defined(SYSCFG_CFGR3_ENREF_HSI48)
Anna Bridge	186:707f6e361f3e	1962	void HAL_RCCEx_EnableHSI48_VREFINT(void);
Anna Bridge	186:707f6e361f3e	1963	void HAL_RCCEx_DisableHSI48_VREFINT(void);
Anna Bridge	186:707f6e361f3e	1964	#endif /* SYSCFG_CFGR3_ENREF_HSI48 */
<>	144:ef7eb2e8f9f7	1965
<>	144:ef7eb2e8f9f7	1966	/**
<>	144:ef7eb2e8f9f7	1967	* @}
<>	144:ef7eb2e8f9f7	1968	*/
Anna Bridge	186:707f6e361f3e	1969
Anna Bridge	186:707f6e361f3e	1970	#if defined(CRS)
Anna Bridge	186:707f6e361f3e	1971
Anna Bridge	186:707f6e361f3e	1972	/** @addtogroup RCCEx_Exported_Functions_Group3
Anna Bridge	186:707f6e361f3e	1973	* @{
Anna Bridge	186:707f6e361f3e	1974	*/
Anna Bridge	186:707f6e361f3e	1975
Anna Bridge	186:707f6e361f3e	1976	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Anna Bridge	186:707f6e361f3e	1977	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Anna Bridge	186:707f6e361f3e	1978	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Anna Bridge	186:707f6e361f3e	1979	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Anna Bridge	186:707f6e361f3e	1980	void HAL_RCCEx_CRS_IRQHandler(void);
Anna Bridge	186:707f6e361f3e	1981	void HAL_RCCEx_CRS_SyncOkCallback(void);
Anna Bridge	186:707f6e361f3e	1982	void HAL_RCCEx_CRS_SyncWarnCallback(void);
Anna Bridge	186:707f6e361f3e	1983	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
Anna Bridge	186:707f6e361f3e	1984	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
Anna Bridge	186:707f6e361f3e	1985
Anna Bridge	186:707f6e361f3e	1986	/**
Anna Bridge	186:707f6e361f3e	1987	* @}
Anna Bridge	186:707f6e361f3e	1988	*/
Anna Bridge	186:707f6e361f3e	1989
Anna Bridge	186:707f6e361f3e	1990	#endif /* CRS */
Anna Bridge	186:707f6e361f3e	1991
<>	144:ef7eb2e8f9f7	1992	/**
<>	144:ef7eb2e8f9f7	1993	* @}
<>	144:ef7eb2e8f9f7	1994	*/
<>	144:ef7eb2e8f9f7	1995
<>	144:ef7eb2e8f9f7	1996	/**
<>	144:ef7eb2e8f9f7	1997	* @}
Anna Bridge	186:707f6e361f3e	1998	*/
Anna Bridge	186:707f6e361f3e	1999
<>	144:ef7eb2e8f9f7	2000	/**
<>	144:ef7eb2e8f9f7	2001	* @}
<>	144:ef7eb2e8f9f7	2002	*/
<>	144:ef7eb2e8f9f7	2003
<>	144:ef7eb2e8f9f7	2004	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	2005	}
<>	144:ef7eb2e8f9f7	2006	#endif
<>	144:ef7eb2e8f9f7	2007
<>	144:ef7eb2e8f9f7	2008	#endif /* __STM32L0xx_HAL_RCC_EX_H */
<>	144:ef7eb2e8f9f7	2009
<>	144:ef7eb2e8f9f7	2010	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	2011