mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_rcc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Extended RCC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities RCC extension peripheral:
<> 144:ef7eb2e8f9f7 8 * + Extended Peripheral Control functions
Anna Bridge 186:707f6e361f3e 9 * + Extended Clock Recovery System Control functions
Anna Bridge 186:707f6e361f3e 10 *
<> 144:ef7eb2e8f9f7 11 ******************************************************************************
<> 144:ef7eb2e8f9f7 12 * @attention
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 17 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 18 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 20 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 22 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 24 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 25 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 *
<> 144:ef7eb2e8f9f7 38 ******************************************************************************
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 42 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 45 * @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 49
Anna Bridge 186:707f6e361f3e 50 /** @defgroup RCCEx RCCEx
<> 144:ef7eb2e8f9f7 51 * @brief RCC Extension HAL module driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
Anna Bridge 186:707f6e361f3e 55 /* Private typedef -----------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 56 /* Private define ------------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 57 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
Anna Bridge 186:707f6e361f3e 60 #if defined (CRS)
<> 144:ef7eb2e8f9f7 61 /* Bit position in register */
Anna Bridge 186:707f6e361f3e 62 #define CRS_CFGR_FELIM_BITNUMBER CRS_CFGR_FELIM_Pos
Anna Bridge 186:707f6e361f3e 63 #define CRS_CR_TRIM_BITNUMBER CRS_CR_TRIM_Pos
Anna Bridge 186:707f6e361f3e 64 #define CRS_ISR_FECAP_BITNUMBER CRS_ISR_FECAP_Pos
Anna Bridge 186:707f6e361f3e 65 #endif /* CRS */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 #if defined(USB)
<> 144:ef7eb2e8f9f7 68 extern const uint8_t PLLMulTable[];
Anna Bridge 186:707f6e361f3e 69 #endif /* USB */
Anna Bridge 186:707f6e361f3e 70 /**
Anna Bridge 186:707f6e361f3e 71 * @}
Anna Bridge 186:707f6e361f3e 72 */
Anna Bridge 186:707f6e361f3e 73
Anna Bridge 186:707f6e361f3e 74 /* Private macro -------------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 75 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
Anna Bridge 186:707f6e361f3e 76 * @{
Anna Bridge 186:707f6e361f3e 77 */
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
Anna Bridge 186:707f6e361f3e 82 /* Private variables ---------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 83 /* Private function prototypes -----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 84 /* Private functions ---------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 85
Anna Bridge 186:707f6e361f3e 86 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<> 144:ef7eb2e8f9f7 87 * @{
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
Anna Bridge 186:707f6e361f3e 90 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
Anna Bridge 186:707f6e361f3e 91 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 92 *
<> 144:ef7eb2e8f9f7 93 @verbatim
<> 144:ef7eb2e8f9f7 94 ===============================================================================
Anna Bridge 186:707f6e361f3e 95 ##### Extended Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 96 ===============================================================================
<> 144:ef7eb2e8f9f7 97 [..]
<> 144:ef7eb2e8f9f7 98 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 99 frequencies.
Anna Bridge 186:707f6e361f3e 100 [..]
Anna Bridge 186:707f6e361f3e 101 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
Anna Bridge 186:707f6e361f3e 102 select the RTC clock source; in this case the Backup domain will be reset in
Anna Bridge 186:707f6e361f3e 103 order to modify the RTC Clock source, as consequence RTC registers (including
Anna Bridge 186:707f6e361f3e 104 the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 @endverbatim
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
Anna Bridge 186:707f6e361f3e 111 * @brief Initializes the RCC extended peripherals clocks according to the specified
Anna Bridge 186:707f6e361f3e 112 * parameters in the RCC_PeriphCLKInitTypeDef.
Anna Bridge 186:707f6e361f3e 113 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 114 * contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
<> 144:ef7eb2e8f9f7 115 * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
<> 144:ef7eb2e8f9f7 116 * @retval HAL status
Anna Bridge 186:707f6e361f3e 117 * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
Anna Bridge 186:707f6e361f3e 118 * to possibly update HSE divider.
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 121 {
<> 151:5eaa88a5bcc7 122 uint32_t tickstart = 0U;
Anna Bridge 186:707f6e361f3e 123 uint32_t temp_reg = 0U;
Anna Bridge 186:707f6e361f3e 124
<> 144:ef7eb2e8f9f7 125 /* Check the parameters */
<> 144:ef7eb2e8f9f7 126 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
Anna Bridge 186:707f6e361f3e 127
Anna Bridge 186:707f6e361f3e 128 /*------------------------------- RTC/LCD Configuration ------------------------*/
Anna Bridge 186:707f6e361f3e 129 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
Anna Bridge 186:707f6e361f3e 130 #if defined(LCD)
Anna Bridge 186:707f6e361f3e 131 || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
Anna Bridge 186:707f6e361f3e 132 #endif /* LCD */
Anna Bridge 186:707f6e361f3e 133 )
Anna Bridge 186:707f6e361f3e 134 {
Anna Bridge 186:707f6e361f3e 135 /* check for RTC Parameters used to output RTCCLK */
Anna Bridge 186:707f6e361f3e 136 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
Anna Bridge 186:707f6e361f3e 137 {
Anna Bridge 186:707f6e361f3e 138 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
Anna Bridge 186:707f6e361f3e 139 }
<> 144:ef7eb2e8f9f7 140
Anna Bridge 186:707f6e361f3e 141 #if defined(LCD)
Anna Bridge 186:707f6e361f3e 142 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
Anna Bridge 186:707f6e361f3e 143 {
Anna Bridge 186:707f6e361f3e 144 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
Anna Bridge 186:707f6e361f3e 145 }
Anna Bridge 186:707f6e361f3e 146 #endif /* LCD */
Anna Bridge 186:707f6e361f3e 147
Anna Bridge 186:707f6e361f3e 148 FlagStatus pwrclkchanged = RESET;
Anna Bridge 186:707f6e361f3e 149
Anna Bridge 186:707f6e361f3e 150 /* As soon as function is called to change RTC clock source, activation of the
Anna Bridge 186:707f6e361f3e 151 power domain is done. */
Anna Bridge 186:707f6e361f3e 152 /* Requires to enable write access to Backup Domain of necessary */
Anna Bridge 186:707f6e361f3e 153 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
Anna Bridge 186:707f6e361f3e 154 {
Anna Bridge 186:707f6e361f3e 155 __HAL_RCC_PWR_CLK_ENABLE();
Anna Bridge 186:707f6e361f3e 156 pwrclkchanged = SET;
Anna Bridge 186:707f6e361f3e 157 }
Anna Bridge 186:707f6e361f3e 158
Anna Bridge 186:707f6e361f3e 159 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
Anna Bridge 186:707f6e361f3e 160 {
Anna Bridge 186:707f6e361f3e 161 /* Enable write access to Backup domain */
Anna Bridge 186:707f6e361f3e 162 SET_BIT(PWR->CR, PWR_CR_DBP);
Anna Bridge 186:707f6e361f3e 163
Anna Bridge 186:707f6e361f3e 164 /* Wait for Backup domain Write protection disable */
Anna Bridge 186:707f6e361f3e 165 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 166
Anna Bridge 186:707f6e361f3e 167 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
Anna Bridge 186:707f6e361f3e 168 {
Anna Bridge 186:707f6e361f3e 169 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
Anna Bridge 186:707f6e361f3e 170 {
Anna Bridge 186:707f6e361f3e 171 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 172 }
Anna Bridge 186:707f6e361f3e 173 }
Anna Bridge 186:707f6e361f3e 174 }
Anna Bridge 186:707f6e361f3e 175
Anna Bridge 186:707f6e361f3e 176 /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
Anna Bridge 186:707f6e361f3e 177 temp_reg = (RCC->CR & RCC_CR_RTCPRE);
Anna Bridge 186:707f6e361f3e 178 if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
Anna Bridge 186:707f6e361f3e 179 #if defined (LCD)
Anna Bridge 186:707f6e361f3e 180 || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
Anna Bridge 186:707f6e361f3e 181 #endif /* LCD */
Anna Bridge 186:707f6e361f3e 182 )
<> 144:ef7eb2e8f9f7 183 { /* Check HSE State */
<> 144:ef7eb2e8f9f7 184 if (((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) && HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
<> 144:ef7eb2e8f9f7 185 {
Anna Bridge 186:707f6e361f3e 186 /* To update HSE divider, first switch-OFF HSE clock oscillator*/
Anna Bridge 186:707f6e361f3e 187 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190
Anna Bridge 186:707f6e361f3e 191 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
Anna Bridge 186:707f6e361f3e 192 temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
Anna Bridge 186:707f6e361f3e 193
Anna Bridge 186:707f6e361f3e 194 if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
Anna Bridge 186:707f6e361f3e 195 && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Anna Bridge 186:707f6e361f3e 196 #if defined(LCD)
Anna Bridge 186:707f6e361f3e 197 || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
Anna Bridge 186:707f6e361f3e 198 && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
Anna Bridge 186:707f6e361f3e 199 #endif /* LCD */
Anna Bridge 186:707f6e361f3e 200 ))
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 /* Store the content of CSR register before the reset of Backup Domain */
Anna Bridge 186:707f6e361f3e 203 temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
Anna Bridge 186:707f6e361f3e 204
<> 144:ef7eb2e8f9f7 205 /* RTC Clock selection can be changed only if the Backup Domain is reset */
<> 144:ef7eb2e8f9f7 206 __HAL_RCC_BACKUPRESET_FORCE();
<> 144:ef7eb2e8f9f7 207 __HAL_RCC_BACKUPRESET_RELEASE();
Anna Bridge 186:707f6e361f3e 208
<> 144:ef7eb2e8f9f7 209 /* Restore the Content of CSR register */
Anna Bridge 186:707f6e361f3e 210 RCC->CSR = temp_reg;
Anna Bridge 186:707f6e361f3e 211
Anna Bridge 186:707f6e361f3e 212 /* Wait for LSERDY if LSE was enabled */
Anna Bridge 186:707f6e361f3e 213 if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
<> 144:ef7eb2e8f9f7 214 {
Anna Bridge 186:707f6e361f3e 215 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 216 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 217
Anna Bridge 186:707f6e361f3e 218 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 219 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226 }
Anna Bridge 186:707f6e361f3e 227 }
Anna Bridge 186:707f6e361f3e 228 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<> 144:ef7eb2e8f9f7 229
Anna Bridge 186:707f6e361f3e 230 /* Require to disable power clock if necessary */
Anna Bridge 186:707f6e361f3e 231 if(pwrclkchanged == SET)
Anna Bridge 186:707f6e361f3e 232 {
Anna Bridge 186:707f6e361f3e 233 __HAL_RCC_PWR_CLK_DISABLE();
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
Anna Bridge 186:707f6e361f3e 237 #if defined (RCC_CCIPR_USART1SEL)
<> 144:ef7eb2e8f9f7 238 /*------------------------------- USART1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 239 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 /* Check the parameters */
<> 144:ef7eb2e8f9f7 242 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Configure the USART1 clock source */
<> 144:ef7eb2e8f9f7 245 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
<> 144:ef7eb2e8f9f7 246 }
Anna Bridge 186:707f6e361f3e 247 #endif /* RCC_CCIPR_USART1SEL */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /*----------------------------- USART2 Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 250 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 /* Check the parameters */
<> 144:ef7eb2e8f9f7 253 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Configure the USART2 clock source */
<> 144:ef7eb2e8f9f7 256 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /*------------------------------ LPUART1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 260 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 /* Check the parameters */
<> 144:ef7eb2e8f9f7 263 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Configure the LPUAR1 clock source */
<> 144:ef7eb2e8f9f7 266 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /*------------------------------ I2C1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 270 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 /* Check the parameters */
<> 144:ef7eb2e8f9f7 273 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Configure the I2C1 clock source */
<> 144:ef7eb2e8f9f7 276 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278
Anna Bridge 186:707f6e361f3e 279 #if defined (RCC_CCIPR_I2C3SEL)
<> 144:ef7eb2e8f9f7 280 /*------------------------------ I2C3 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 281 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 /* Check the parameters */
<> 144:ef7eb2e8f9f7 284 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Configure the I2C3 clock source */
<> 144:ef7eb2e8f9f7 287 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
<> 144:ef7eb2e8f9f7 288 }
Anna Bridge 186:707f6e361f3e 289 #endif /* RCC_CCIPR_I2C3SEL */
<> 144:ef7eb2e8f9f7 290
Anna Bridge 186:707f6e361f3e 291 #if defined(USB)
<> 144:ef7eb2e8f9f7 292 /*---------------------------- USB and RNG configuration --------------------*/
<> 144:ef7eb2e8f9f7 293 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
<> 144:ef7eb2e8f9f7 296 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
<> 144:ef7eb2e8f9f7 297 }
Anna Bridge 186:707f6e361f3e 298 #endif /* USB */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /*---------------------------- LPTIM1 configuration ------------------------*/
<> 144:ef7eb2e8f9f7 301 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
<> 144:ef7eb2e8f9f7 304 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
<> 144:ef7eb2e8f9f7 305 }
Anna Bridge 186:707f6e361f3e 306
<> 144:ef7eb2e8f9f7 307 return HAL_OK;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /**
Anna Bridge 186:707f6e361f3e 311 * @brief Get the PeriphClkInit according to the internal RCC configuration registers.
Anna Bridge 186:707f6e361f3e 312 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 313 * returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
<> 144:ef7eb2e8f9f7 314 * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
<> 144:ef7eb2e8f9f7 315 * @retval None
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 318 {
Anna Bridge 186:707f6e361f3e 319 uint32_t srcclk = 0;
Anna Bridge 186:707f6e361f3e 320
<> 144:ef7eb2e8f9f7 321 /* Set all possible values for the extended clock type parameter -----------*/
<> 144:ef7eb2e8f9f7 322 /* Common part first */
Anna Bridge 186:707f6e361f3e 323 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Anna Bridge 186:707f6e361f3e 324 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | \
<> 144:ef7eb2e8f9f7 325 RCC_PERIPHCLK_LPTIM1;
Anna Bridge 186:707f6e361f3e 326 #if defined(RCC_CCIPR_USART1SEL)
Anna Bridge 186:707f6e361f3e 327 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART1;
Anna Bridge 186:707f6e361f3e 328 #endif /* RCC_CCIPR_USART1SEL */
Anna Bridge 186:707f6e361f3e 329 #if defined(RCC_CCIPR_I2C3SEL)
Anna Bridge 186:707f6e361f3e 330 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
Anna Bridge 186:707f6e361f3e 331 #endif /* RCC_CCIPR_I2C3SEL */
Anna Bridge 186:707f6e361f3e 332 #if defined(USB)
Anna Bridge 186:707f6e361f3e 333 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
Anna Bridge 186:707f6e361f3e 334 #endif /* USB */
Anna Bridge 186:707f6e361f3e 335 #if defined(LCD)
Anna Bridge 186:707f6e361f3e 336 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
Anna Bridge 186:707f6e361f3e 337 #endif /* LCD */
<> 144:ef7eb2e8f9f7 338
Anna Bridge 186:707f6e361f3e 339 /* Get the RTC/LCD configuration -----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 340 srcclk = __HAL_RCC_GET_RTC_SOURCE();
Anna Bridge 186:707f6e361f3e 341 if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
Anna Bridge 186:707f6e361f3e 342 {
Anna Bridge 186:707f6e361f3e 343 /* Source clock is LSE or LSI*/
Anna Bridge 186:707f6e361f3e 344 PeriphClkInit->RTCClockSelection = srcclk;
Anna Bridge 186:707f6e361f3e 345 }
Anna Bridge 186:707f6e361f3e 346 else
Anna Bridge 186:707f6e361f3e 347 {
Anna Bridge 186:707f6e361f3e 348 /* Source clock is HSE. Need to get the prescaler value*/
Anna Bridge 186:707f6e361f3e 349 PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
Anna Bridge 186:707f6e361f3e 350 }
Anna Bridge 186:707f6e361f3e 351 #if defined(LCD)
Anna Bridge 186:707f6e361f3e 352 PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
Anna Bridge 186:707f6e361f3e 353 #endif /* LCD */
Anna Bridge 186:707f6e361f3e 354 #if defined(RCC_CCIPR_USART1SEL)
<> 144:ef7eb2e8f9f7 355 /* Get the USART1 configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 356 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
Anna Bridge 186:707f6e361f3e 357 #endif /* RCC_CCIPR_USART1SEL */
<> 144:ef7eb2e8f9f7 358 /* Get the USART2 clock source ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 359 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 360 /* Get the LPUART1 clock source ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 361 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
<> 144:ef7eb2e8f9f7 362 /* Get the I2C1 clock source -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 363 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
Anna Bridge 186:707f6e361f3e 364 #if defined(RCC_CCIPR_I2C3SEL)
<> 144:ef7eb2e8f9f7 365 /* Get the I2C3 clock source -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 366 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
Anna Bridge 186:707f6e361f3e 367 #endif /* RCC_CCIPR_I2C3SEL */
<> 144:ef7eb2e8f9f7 368 /* Get the LPTIM1 clock source -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 369 PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
<> 144:ef7eb2e8f9f7 370 /* Get the RTC clock source -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 371 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
Anna Bridge 186:707f6e361f3e 372 #if defined(USB)
<> 144:ef7eb2e8f9f7 373 /* Get the USB/RNG clock source -----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 374 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
Anna Bridge 186:707f6e361f3e 375 #endif /* USB */
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
Anna Bridge 186:707f6e361f3e 379 * @brief Return the peripheral clock frequency
Anna Bridge 186:707f6e361f3e 380 * @note Return 0 if peripheral clock is unknown
Anna Bridge 186:707f6e361f3e 381 * @param PeriphClk Peripheral clock identifier
<> 144:ef7eb2e8f9f7 382 * This parameter can be one of the following values:
Anna Bridge 186:707f6e361f3e 383 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
Anna Bridge 186:707f6e361f3e 384 * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*)
Anna Bridge 186:707f6e361f3e 385 * @arg @ref RCC_PERIPHCLK_USB USB or RNG peripheral clock (*)
Anna Bridge 186:707f6e361f3e 386 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock (*)
Anna Bridge 186:707f6e361f3e 387 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
Anna Bridge 186:707f6e361f3e 388 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
Anna Bridge 186:707f6e361f3e 389 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
Anna Bridge 186:707f6e361f3e 390 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (*)
Anna Bridge 186:707f6e361f3e 391 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
Anna Bridge 186:707f6e361f3e 392 * @note (*) means that this peripheral is not present on all the devices
<> 144:ef7eb2e8f9f7 393 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
Anna Bridge 186:707f6e361f3e 396 {
Anna Bridge 186:707f6e361f3e 397 uint32_t temp_reg = 0U, clkprediv = 0U, frequency = 0U;
Anna Bridge 186:707f6e361f3e 398 uint32_t srcclk = 0U;
Anna Bridge 186:707f6e361f3e 399 #if defined(USB)
<> 151:5eaa88a5bcc7 400 uint32_t pllmul = 0U, plldiv = 0U, pllvco = 0U;
<> 144:ef7eb2e8f9f7 401 #endif /* USB */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Check the parameters */
<> 144:ef7eb2e8f9f7 404 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
Anna Bridge 186:707f6e361f3e 405
Anna Bridge 186:707f6e361f3e 406 switch (PeriphClk)
<> 144:ef7eb2e8f9f7 407 {
Anna Bridge 186:707f6e361f3e 408 case RCC_PERIPHCLK_RTC:
Anna Bridge 186:707f6e361f3e 409 #if defined(LCD)
Anna Bridge 186:707f6e361f3e 410 case RCC_PERIPHCLK_LCD:
Anna Bridge 186:707f6e361f3e 411 #endif /* LCD */
Anna Bridge 186:707f6e361f3e 412 {
Anna Bridge 186:707f6e361f3e 413 /* Get RCC CSR configuration ------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 414 temp_reg = RCC->CSR;
Anna Bridge 186:707f6e361f3e 415
<> 144:ef7eb2e8f9f7 416 /* Get the current RTC source */
<> 144:ef7eb2e8f9f7 417 srcclk = __HAL_RCC_GET_RTC_SOURCE();
Anna Bridge 186:707f6e361f3e 418
Anna Bridge 186:707f6e361f3e 419 /* Check if LSE is ready if RTC clock selection is LSE */
Anna Bridge 186:707f6e361f3e 420 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSERDY)))
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 423 }
Anna Bridge 186:707f6e361f3e 424 /* Check if LSI is ready if RTC clock selection is LSI */
Anna Bridge 186:707f6e361f3e 425 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSIRDY)))
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 428 }
Anna Bridge 186:707f6e361f3e 429 /* Check if HSE is ready and if RTC clock selection is HSE */
<> 144:ef7eb2e8f9f7 430 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
<> 144:ef7eb2e8f9f7 431 {
Anna Bridge 186:707f6e361f3e 432 /* Get the current HSE clock divider */
Anna Bridge 186:707f6e361f3e 433 clkprediv = __HAL_RCC_GET_RTC_HSE_PRESCALER();
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 switch (clkprediv)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
<> 144:ef7eb2e8f9f7 438 {
<> 151:5eaa88a5bcc7 439 frequency = HSE_VALUE / 16U;
<> 144:ef7eb2e8f9f7 440 break;
<> 144:ef7eb2e8f9f7 441 }
Anna Bridge 186:707f6e361f3e 442 case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
<> 144:ef7eb2e8f9f7 443 {
<> 151:5eaa88a5bcc7 444 frequency = HSE_VALUE / 8U;
<> 144:ef7eb2e8f9f7 445 break;
<> 144:ef7eb2e8f9f7 446 }
Anna Bridge 186:707f6e361f3e 447 case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
<> 144:ef7eb2e8f9f7 448 {
<> 151:5eaa88a5bcc7 449 frequency = HSE_VALUE / 4U;
<> 144:ef7eb2e8f9f7 450 break;
<> 144:ef7eb2e8f9f7 451 }
Anna Bridge 186:707f6e361f3e 452 default: /* HSE DIV2 has been selected */
<> 144:ef7eb2e8f9f7 453 {
<> 151:5eaa88a5bcc7 454 frequency = HSE_VALUE / 2U;
<> 144:ef7eb2e8f9f7 455 break;
<> 144:ef7eb2e8f9f7 456 }
Anna Bridge 186:707f6e361f3e 457 }
<> 144:ef7eb2e8f9f7 458 }
Anna Bridge 186:707f6e361f3e 459 /* Clock not enabled for RTC */
<> 144:ef7eb2e8f9f7 460 else
<> 144:ef7eb2e8f9f7 461 {
<> 151:5eaa88a5bcc7 462 frequency = 0U;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 break;
Anna Bridge 186:707f6e361f3e 465 }
<> 144:ef7eb2e8f9f7 466 #if defined(USB)
<> 144:ef7eb2e8f9f7 467 case RCC_PERIPHCLK_USB:
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 /* Get the current USB source */
<> 144:ef7eb2e8f9f7 470 srcclk = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 if((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 /* Get PLL clock source and multiplication factor ----------------------*/
<> 144:ef7eb2e8f9f7 475 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
<> 144:ef7eb2e8f9f7 476 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
Anna Bridge 186:707f6e361f3e 477 pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
Anna Bridge 186:707f6e361f3e 478 plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Compute PLL clock input */
<> 144:ef7eb2e8f9f7 481 if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
<> 144:ef7eb2e8f9f7 482 {
<> 151:5eaa88a5bcc7 483 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
<> 144:ef7eb2e8f9f7 484 {
<> 151:5eaa88a5bcc7 485 pllvco = (HSI_VALUE >> 2U);
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 else
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 pllvco = HSI_VALUE;
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 else /* HSE source */
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 pllvco = HSE_VALUE;
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496 /* pllvco * pllmul / plldiv */
<> 144:ef7eb2e8f9f7 497 pllvco = (pllvco * pllmul);
<> 144:ef7eb2e8f9f7 498 frequency = (pllvco/ plldiv);
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 else if((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)))
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 frequency = HSI48_VALUE;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 else /* RCC_USBCLKSOURCE_NONE */
<> 144:ef7eb2e8f9f7 506 {
<> 151:5eaa88a5bcc7 507 frequency = 0U;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509 break;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 #endif /* USB */
Anna Bridge 186:707f6e361f3e 512 #if defined(RCC_CCIPR_USART1SEL)
<> 144:ef7eb2e8f9f7 513 case RCC_PERIPHCLK_USART1:
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 /* Get the current USART1 source */
<> 144:ef7eb2e8f9f7 516 srcclk = __HAL_RCC_GET_USART1_SOURCE();
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Check if USART1 clock selection is PCLK2 */
<> 144:ef7eb2e8f9f7 519 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 frequency = HAL_RCC_GetPCLK2Freq();
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 /* Check if HSI is ready and if USART1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 524 else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528 /* Check if USART1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 529 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 /* Check if LSE is ready and if USART1 clock selection is LSE */
<> 144:ef7eb2e8f9f7 534 else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 /* Clock not enabled for USART1*/
<> 144:ef7eb2e8f9f7 539 else
<> 144:ef7eb2e8f9f7 540 {
<> 151:5eaa88a5bcc7 541 frequency = 0U;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543 break;
<> 144:ef7eb2e8f9f7 544 }
Anna Bridge 186:707f6e361f3e 545 #endif /* RCC_CCIPR_USART1SEL */
<> 144:ef7eb2e8f9f7 546 case RCC_PERIPHCLK_USART2:
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 /* Get the current USART2 source */
<> 144:ef7eb2e8f9f7 549 srcclk = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Check if USART2 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 552 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556 /* Check if HSI is ready and if USART2 clock selection is HSI */
<> 144:ef7eb2e8f9f7 557 else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 /* Check if USART2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 562 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566 /* Check if LSE is ready and if USART2 clock selection is LSE */
<> 144:ef7eb2e8f9f7 567 else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571 /* Clock not enabled for USART2*/
<> 144:ef7eb2e8f9f7 572 else
<> 144:ef7eb2e8f9f7 573 {
<> 151:5eaa88a5bcc7 574 frequency = 0U;
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 break;
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 case RCC_PERIPHCLK_LPUART1:
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 /* Get the current LPUART1 source */
<> 144:ef7eb2e8f9f7 581 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Check if LPUART1 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 584 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588 /* Check if HSI is ready and if LPUART1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 589 else if ((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593 /* Check if LPUART1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 594 else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598 /* Check if LSE is ready and if LPUART1 clock selection is LSE */
<> 144:ef7eb2e8f9f7 599 else if ((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603 /* Clock not enabled for LPUART1*/
<> 144:ef7eb2e8f9f7 604 else
<> 144:ef7eb2e8f9f7 605 {
<> 151:5eaa88a5bcc7 606 frequency = 0U;
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608 break;
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610 case RCC_PERIPHCLK_I2C1:
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 /* Get the current I2C1 source */
<> 144:ef7eb2e8f9f7 613 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Check if I2C1 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 616 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620 /* Check if HSI is ready and if I2C1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 621 else if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 624 }
<> 144:ef7eb2e8f9f7 625 /* Check if I2C1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 626 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 629 }
<> 144:ef7eb2e8f9f7 630 /* Clock not enabled for I2C1*/
<> 144:ef7eb2e8f9f7 631 else
<> 144:ef7eb2e8f9f7 632 {
<> 151:5eaa88a5bcc7 633 frequency = 0U;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 break;
<> 144:ef7eb2e8f9f7 636 }
Anna Bridge 186:707f6e361f3e 637 #if defined(I2C2)
<> 144:ef7eb2e8f9f7 638 case RCC_PERIPHCLK_I2C2:
<> 144:ef7eb2e8f9f7 639 {
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Check if I2C2 on APB1 clock enabled*/
<> 144:ef7eb2e8f9f7 642 if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN)
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646 else
<> 144:ef7eb2e8f9f7 647 {
<> 151:5eaa88a5bcc7 648 frequency = 0U;
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650 break;
<> 144:ef7eb2e8f9f7 651 }
Anna Bridge 186:707f6e361f3e 652 #endif /* I2C2 */
<> 144:ef7eb2e8f9f7 653
Anna Bridge 186:707f6e361f3e 654 #if defined(RCC_CCIPR_I2C3SEL)
<> 144:ef7eb2e8f9f7 655 case RCC_PERIPHCLK_I2C3:
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 /* Get the current I2C1 source */
<> 144:ef7eb2e8f9f7 658 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Check if I2C3 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 661 if (srcclk == RCC_I2C3CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665 /* Check if HSI is ready and if I2C3 clock selection is HSI */
<> 144:ef7eb2e8f9f7 666 else if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670 /* Check if I2C3 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 671 else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 /* Clock not enabled for I2C3*/
<> 144:ef7eb2e8f9f7 676 else
<> 144:ef7eb2e8f9f7 677 {
<> 151:5eaa88a5bcc7 678 frequency = 0U;
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680 break;
<> 144:ef7eb2e8f9f7 681 }
Anna Bridge 186:707f6e361f3e 682 #endif /* RCC_CCIPR_I2C3SEL */
Anna Bridge 186:707f6e361f3e 683 default:
Anna Bridge 186:707f6e361f3e 684 {
Anna Bridge 186:707f6e361f3e 685 break;
<> 144:ef7eb2e8f9f7 686 }
Anna Bridge 186:707f6e361f3e 687 }
Anna Bridge 186:707f6e361f3e 688 return(frequency);
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @brief Enables the LSE Clock Security System.
<> 144:ef7eb2e8f9f7 693 * @retval None
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 void HAL_RCCEx_EnableLSECSS(void)
<> 144:ef7eb2e8f9f7 696 {
Anna Bridge 186:707f6e361f3e 697 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @brief Disables the LSE Clock Security System.
Anna Bridge 186:707f6e361f3e 702 * @note Once enabled this bit cannot be disabled, except after an LSE failure detection
Anna Bridge 186:707f6e361f3e 703 * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
Anna Bridge 186:707f6e361f3e 704 * Reset by power on reset and RTC software reset (RTCRST bit).
<> 144:ef7eb2e8f9f7 705 * @retval None
<> 144:ef7eb2e8f9f7 706 */
<> 144:ef7eb2e8f9f7 707 void HAL_RCCEx_DisableLSECSS(void)
<> 144:ef7eb2e8f9f7 708 {
<> 144:ef7eb2e8f9f7 709 /* Disable LSE CSS */
<> 144:ef7eb2e8f9f7 710 CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Disable LSE CSS IT */
Anna Bridge 186:707f6e361f3e 713 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /**
<> 144:ef7eb2e8f9f7 717 * @brief Enable the LSE Clock Security System IT & corresponding EXTI line.
<> 144:ef7eb2e8f9f7 718 * @note LSE Clock Security System IT is mapped on RTC EXTI line 19
<> 144:ef7eb2e8f9f7 719 * @retval None
<> 144:ef7eb2e8f9f7 720 */
<> 144:ef7eb2e8f9f7 721 void HAL_RCCEx_EnableLSECSS_IT(void)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 /* Enable LSE CSS */
<> 144:ef7eb2e8f9f7 724 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Enable LSE CSS IT */
Anna Bridge 186:707f6e361f3e 727 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* Enable IT on EXTI Line 19 */
<> 144:ef7eb2e8f9f7 730 __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 731 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /**
<> 144:ef7eb2e8f9f7 735 * @brief Handle the RCC LSE Clock Security System interrupt request.
<> 144:ef7eb2e8f9f7 736 * @retval None
<> 144:ef7eb2e8f9f7 737 */
<> 144:ef7eb2e8f9f7 738 void HAL_RCCEx_LSECSS_IRQHandler(void)
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 /* Check RCC LSE CSSF flag */
Anna Bridge 186:707f6e361f3e 741 if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 /* RCC LSE Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 744 HAL_RCCEx_LSECSS_Callback();
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Clear RCC LSE CSS pending bit */
Anna Bridge 186:707f6e361f3e 747 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749 }
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /**
<> 144:ef7eb2e8f9f7 752 * @brief RCCEx LSE Clock Security System interrupt callback.
<> 144:ef7eb2e8f9f7 753 * @retval none
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755 __weak void HAL_RCCEx_LSECSS_Callback(void)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 758 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760 }
Anna Bridge 186:707f6e361f3e 761
Anna Bridge 186:707f6e361f3e 762 #if defined(SYSCFG_CFGR3_ENREF_HSI48)
Anna Bridge 186:707f6e361f3e 763 /**
Anna Bridge 186:707f6e361f3e 764 * @brief Enables Vrefint for the HSI48.
Anna Bridge 186:707f6e361f3e 765 * @note This is functional only if the LOCK is not set
Anna Bridge 186:707f6e361f3e 766 * @retval None
Anna Bridge 186:707f6e361f3e 767 */
Anna Bridge 186:707f6e361f3e 768 void HAL_RCCEx_EnableHSI48_VREFINT(void)
Anna Bridge 186:707f6e361f3e 769 {
Anna Bridge 186:707f6e361f3e 770 /* Enable the Buffer for the ADC by setting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */
Anna Bridge 186:707f6e361f3e 771 SET_BIT (SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
Anna Bridge 186:707f6e361f3e 772 }
<> 144:ef7eb2e8f9f7 773
Anna Bridge 186:707f6e361f3e 774 /**
Anna Bridge 186:707f6e361f3e 775 * @brief Disables the Vrefint for the HSI48.
Anna Bridge 186:707f6e361f3e 776 * @note This is functional only if the LOCK is not set
Anna Bridge 186:707f6e361f3e 777 * @retval None
Anna Bridge 186:707f6e361f3e 778 */
Anna Bridge 186:707f6e361f3e 779 void HAL_RCCEx_DisableHSI48_VREFINT(void)
Anna Bridge 186:707f6e361f3e 780 {
Anna Bridge 186:707f6e361f3e 781 /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */
Anna Bridge 186:707f6e361f3e 782 CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
Anna Bridge 186:707f6e361f3e 783 }
Anna Bridge 186:707f6e361f3e 784
Anna Bridge 186:707f6e361f3e 785 #endif /* SYSCFG_CFGR3_ENREF_HSI48 */
Anna Bridge 186:707f6e361f3e 786
<> 144:ef7eb2e8f9f7 787 /**
Anna Bridge 186:707f6e361f3e 788 * @}
Anna Bridge 186:707f6e361f3e 789 */
Anna Bridge 186:707f6e361f3e 790
Anna Bridge 186:707f6e361f3e 791 #if defined (CRS)
Anna Bridge 186:707f6e361f3e 792
Anna Bridge 186:707f6e361f3e 793 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
Anna Bridge 186:707f6e361f3e 794 * @brief Extended Clock Recovery System Control functions
Anna Bridge 186:707f6e361f3e 795 *
Anna Bridge 186:707f6e361f3e 796 @verbatim
Anna Bridge 186:707f6e361f3e 797 ===============================================================================
Anna Bridge 186:707f6e361f3e 798 ##### Extended Clock Recovery System Control functions #####
Anna Bridge 186:707f6e361f3e 799 ===============================================================================
Anna Bridge 186:707f6e361f3e 800 [..]
Anna Bridge 186:707f6e361f3e 801 For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
Anna Bridge 186:707f6e361f3e 802
Anna Bridge 186:707f6e361f3e 803 (#) In System clock config, HSI48 needs to be enabled
Anna Bridge 186:707f6e361f3e 804
Anna Bridge 186:707f6e361f3e 805 (#) Enable CRS clock in IP MSP init which will use CRS functions
Anna Bridge 186:707f6e361f3e 806
Anna Bridge 186:707f6e361f3e 807 (#) Call CRS functions as follows:
Anna Bridge 186:707f6e361f3e 808 (##) Prepare synchronization configuration necessary for HSI48 calibration
Anna Bridge 186:707f6e361f3e 809 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
Anna Bridge 186:707f6e361f3e 810 and also HSI48 oscillator smooth trimming.
Anna Bridge 186:707f6e361f3e 811 (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
Anna Bridge 186:707f6e361f3e 812 directly reload value with target and synchronization frequencies values
Anna Bridge 186:707f6e361f3e 813 (##) Call function @ref HAL_RCCEx_CRSConfig which
Anna Bridge 186:707f6e361f3e 814 (+++) Reset CRS registers to their default values.
Anna Bridge 186:707f6e361f3e 815 (+++) Configure CRS registers with synchronization configuration
Anna Bridge 186:707f6e361f3e 816 (+++) Enable automatic calibration and frequency error counter feature
Anna Bridge 186:707f6e361f3e 817 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
Anna Bridge 186:707f6e361f3e 818 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
Anna Bridge 186:707f6e361f3e 819 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
Anna Bridge 186:707f6e361f3e 820 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
Anna Bridge 186:707f6e361f3e 821 should be used as SYNC signal.
Anna Bridge 186:707f6e361f3e 822
Anna Bridge 186:707f6e361f3e 823 (##) A polling function is provided to wait for complete synchronization
Anna Bridge 186:707f6e361f3e 824 (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization()
Anna Bridge 186:707f6e361f3e 825 (+++) According to CRS status, user can decide to adjust again the calibration or continue
Anna Bridge 186:707f6e361f3e 826 application if synchronization is OK
Anna Bridge 186:707f6e361f3e 827
Anna Bridge 186:707f6e361f3e 828 (#) User can retrieve information related to synchronization in calling function
Anna Bridge 186:707f6e361f3e 829 @ref HAL_RCCEx_CRSGetSynchronizationInfo()
Anna Bridge 186:707f6e361f3e 830
Anna Bridge 186:707f6e361f3e 831 (#) Regarding synchronization status and synchronization information, user can try a new calibration
Anna Bridge 186:707f6e361f3e 832 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
Anna Bridge 186:707f6e361f3e 833 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
Anna Bridge 186:707f6e361f3e 834 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
Anna Bridge 186:707f6e361f3e 835 incremented), while when it is detected during the upcounting phase it means that the actual frequency
Anna Bridge 186:707f6e361f3e 836 is higher (and that the TRIM value should be decremented).
Anna Bridge 186:707f6e361f3e 837
Anna Bridge 186:707f6e361f3e 838 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
Anna Bridge 186:707f6e361f3e 839 through CRS Handler (RCC_IRQn/RCC_IRQHandler)
Anna Bridge 186:707f6e361f3e 840 (++) Call function @ref HAL_RCCEx_CRSConfig()
Anna Bridge 186:707f6e361f3e 841 (++) Enable RCC_IRQn (thanks to NVIC functions)
Anna Bridge 186:707f6e361f3e 842 (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT)
Anna Bridge 186:707f6e361f3e 843 (++) Implement CRS status management in the following user callbacks called from
Anna Bridge 186:707f6e361f3e 844 HAL_RCCEx_CRS_IRQHandler():
Anna Bridge 186:707f6e361f3e 845 (+++) @ref HAL_RCCEx_CRS_SyncOkCallback()
Anna Bridge 186:707f6e361f3e 846 (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback()
Anna Bridge 186:707f6e361f3e 847 (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback()
Anna Bridge 186:707f6e361f3e 848 (+++) @ref HAL_RCCEx_CRS_ErrorCallback()
Anna Bridge 186:707f6e361f3e 849
Anna Bridge 186:707f6e361f3e 850 (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
Anna Bridge 186:707f6e361f3e 851 This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler)
Anna Bridge 186:707f6e361f3e 852
Anna Bridge 186:707f6e361f3e 853 @endverbatim
Anna Bridge 186:707f6e361f3e 854 * @{
Anna Bridge 186:707f6e361f3e 855 */
Anna Bridge 186:707f6e361f3e 856
Anna Bridge 186:707f6e361f3e 857 /**
Anna Bridge 186:707f6e361f3e 858 * @brief Start automatic synchronization for polling mode
<> 144:ef7eb2e8f9f7 859 * @param pInit Pointer on RCC_CRSInitTypeDef structure
<> 144:ef7eb2e8f9f7 860 * @retval None
<> 144:ef7eb2e8f9f7 861 */
<> 144:ef7eb2e8f9f7 862 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
<> 144:ef7eb2e8f9f7 863 {
Anna Bridge 186:707f6e361f3e 864 uint32_t value = 0;
Anna Bridge 186:707f6e361f3e 865
<> 144:ef7eb2e8f9f7 866 /* Check the parameters */
<> 144:ef7eb2e8f9f7 867 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
<> 144:ef7eb2e8f9f7 868 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
<> 144:ef7eb2e8f9f7 869 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
<> 144:ef7eb2e8f9f7 870 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
<> 144:ef7eb2e8f9f7 871 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
<> 144:ef7eb2e8f9f7 872 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* CONFIGURATION */
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Before configuration, reset CRS registers to their default values*/
<> 144:ef7eb2e8f9f7 877 __HAL_RCC_CRS_FORCE_RESET();
<> 144:ef7eb2e8f9f7 878 __HAL_RCC_CRS_RELEASE_RESET();
<> 144:ef7eb2e8f9f7 879
Anna Bridge 186:707f6e361f3e 880 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
<> 144:ef7eb2e8f9f7 881 /* Set the SYNCSRC[1:0] bits according to Source value */
Anna Bridge 186:707f6e361f3e 882 /* Set the SYNCSPOL bit according to Polarity value */
Anna Bridge 186:707f6e361f3e 883 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
<> 144:ef7eb2e8f9f7 884 /* Set the RELOAD[15:0] bits according to ReloadValue value */
Anna Bridge 186:707f6e361f3e 885 value |= pInit->ReloadValue;
<> 144:ef7eb2e8f9f7 886 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
Anna Bridge 186:707f6e361f3e 887 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
Anna Bridge 186:707f6e361f3e 888 WRITE_REG(CRS->CFGR, value);
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Adjust HSI48 oscillator smooth trimming */
<> 144:ef7eb2e8f9f7 891 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
Anna Bridge 186:707f6e361f3e 892 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER));
Anna Bridge 186:707f6e361f3e 893
<> 144:ef7eb2e8f9f7 894 /* START AUTOMATIC SYNCHRONIZATION*/
<> 144:ef7eb2e8f9f7 895
Anna Bridge 186:707f6e361f3e 896 /* Enable Automatic trimming & Frequency error counter */
Anna Bridge 186:707f6e361f3e 897 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
<> 144:ef7eb2e8f9f7 898 }
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /**
<> 144:ef7eb2e8f9f7 901 * @brief Generate the software synchronization event
<> 144:ef7eb2e8f9f7 902 * @retval None
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
<> 144:ef7eb2e8f9f7 905 {
Anna Bridge 186:707f6e361f3e 906 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /**
Anna Bridge 186:707f6e361f3e 910 * @brief Return synchronization info
<> 144:ef7eb2e8f9f7 911 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
<> 144:ef7eb2e8f9f7 912 * @retval None
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 /* Check the parameter */
<> 144:ef7eb2e8f9f7 917 assert_param(pSynchroInfo != NULL);
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Get the reload value */
Anna Bridge 186:707f6e361f3e 920 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Get HSI48 oscillator smooth trimming */
Anna Bridge 186:707f6e361f3e 923 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Get Frequency error capture */
Anna Bridge 186:707f6e361f3e 926 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* Get Frequency error direction */
Anna Bridge 186:707f6e361f3e 929 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
<> 144:ef7eb2e8f9f7 930 }
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /**
Anna Bridge 186:707f6e361f3e 933 * @brief Wait for CRS Synchronization status.
Anna Bridge 186:707f6e361f3e 934 * @param Timeout Duration of the timeout
<> 144:ef7eb2e8f9f7 935 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
<> 144:ef7eb2e8f9f7 936 * frequency.
<> 144:ef7eb2e8f9f7 937 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
<> 144:ef7eb2e8f9f7 938 * @retval Combination of Synchronization status
<> 144:ef7eb2e8f9f7 939 * This parameter can be a combination of the following values:
Anna Bridge 186:707f6e361f3e 940 * @arg @ref RCC_CRS_TIMEOUT
Anna Bridge 186:707f6e361f3e 941 * @arg @ref RCC_CRS_SYNCOK
Anna Bridge 186:707f6e361f3e 942 * @arg @ref RCC_CRS_SYNCWARN
Anna Bridge 186:707f6e361f3e 943 * @arg @ref RCC_CRS_SYNCERR
Anna Bridge 186:707f6e361f3e 944 * @arg @ref RCC_CRS_SYNCMISS
Anna Bridge 186:707f6e361f3e 945 * @arg @ref RCC_CRS_TRIMOVF
<> 144:ef7eb2e8f9f7 946 */
<> 144:ef7eb2e8f9f7 947 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
<> 144:ef7eb2e8f9f7 948 {
<> 144:ef7eb2e8f9f7 949 uint32_t crsstatus = RCC_CRS_NONE;
<> 151:5eaa88a5bcc7 950 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Get timeout */
<> 144:ef7eb2e8f9f7 953 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 954
Anna Bridge 186:707f6e361f3e 955 /* Wait for CRS flag or timeout detection */
Anna Bridge 186:707f6e361f3e 956 do
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 959 {
Anna Bridge 186:707f6e361f3e 960 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 crsstatus = RCC_CRS_TIMEOUT;
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964 }
<> 144:ef7eb2e8f9f7 965 /* Check CRS SYNCOK flag */
<> 144:ef7eb2e8f9f7 966 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
<> 144:ef7eb2e8f9f7 967 {
<> 144:ef7eb2e8f9f7 968 /* CRS SYNC event OK */
<> 144:ef7eb2e8f9f7 969 crsstatus |= RCC_CRS_SYNCOK;
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Clear CRS SYNC event OK bit */
<> 144:ef7eb2e8f9f7 972 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /* Check CRS SYNCWARN flag */
<> 144:ef7eb2e8f9f7 976 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 /* CRS SYNC warning */
<> 151:5eaa88a5bcc7 979 crsstatus |= RCC_CRS_SYNCWARN;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Clear CRS SYNCWARN bit */
<> 144:ef7eb2e8f9f7 982 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Check CRS TRIM overflow flag */
<> 144:ef7eb2e8f9f7 986 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
<> 144:ef7eb2e8f9f7 987 {
<> 144:ef7eb2e8f9f7 988 /* CRS SYNC Error */
<> 151:5eaa88a5bcc7 989 crsstatus |= RCC_CRS_TRIMOVF;
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Clear CRS Error bit */
<> 144:ef7eb2e8f9f7 992 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /* Check CRS Error flag */
<> 144:ef7eb2e8f9f7 996 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
<> 144:ef7eb2e8f9f7 997 {
<> 144:ef7eb2e8f9f7 998 /* CRS SYNC Error */
<> 144:ef7eb2e8f9f7 999 crsstatus |= RCC_CRS_SYNCERR;
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Clear CRS Error bit */
<> 144:ef7eb2e8f9f7 1002 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /* Check CRS SYNC Missed flag */
<> 144:ef7eb2e8f9f7 1006 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
<> 144:ef7eb2e8f9f7 1007 {
<> 144:ef7eb2e8f9f7 1008 /* CRS SYNC Missed */
<> 144:ef7eb2e8f9f7 1009 crsstatus |= RCC_CRS_SYNCMISS;
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /* Clear CRS SYNC Missed bit */
<> 144:ef7eb2e8f9f7 1012 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Check CRS Expected SYNC flag */
<> 144:ef7eb2e8f9f7 1016 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
<> 144:ef7eb2e8f9f7 1017 {
<> 144:ef7eb2e8f9f7 1018 /* frequency error counter reached a zero value */
<> 144:ef7eb2e8f9f7 1019 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
<> 144:ef7eb2e8f9f7 1020 }
Anna Bridge 186:707f6e361f3e 1021 } while(RCC_CRS_NONE == crsstatus);
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 return crsstatus;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
Anna Bridge 186:707f6e361f3e 1027 * @brief Handle the Clock Recovery System interrupt request.
<> 144:ef7eb2e8f9f7 1028 * @retval None
<> 144:ef7eb2e8f9f7 1029 */
Anna Bridge 186:707f6e361f3e 1030 void HAL_RCCEx_CRS_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1031 {
Anna Bridge 186:707f6e361f3e 1032 uint32_t crserror = RCC_CRS_NONE;
Anna Bridge 186:707f6e361f3e 1033 /* Get current IT flags and IT sources values */
Anna Bridge 186:707f6e361f3e 1034 uint32_t itflags = READ_REG(CRS->ISR);
Anna Bridge 186:707f6e361f3e 1035 uint32_t itsources = READ_REG(CRS->CR);
Anna Bridge 186:707f6e361f3e 1036
Anna Bridge 186:707f6e361f3e 1037 /* Check CRS SYNCOK flag */
Anna Bridge 186:707f6e361f3e 1038 if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
Anna Bridge 186:707f6e361f3e 1039 {
Anna Bridge 186:707f6e361f3e 1040 /* Clear CRS SYNC event OK flag */
Anna Bridge 186:707f6e361f3e 1041 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
Anna Bridge 186:707f6e361f3e 1042
Anna Bridge 186:707f6e361f3e 1043 /* user callback */
Anna Bridge 186:707f6e361f3e 1044 HAL_RCCEx_CRS_SyncOkCallback();
Anna Bridge 186:707f6e361f3e 1045 }
Anna Bridge 186:707f6e361f3e 1046 /* Check CRS SYNCWARN flag */
Anna Bridge 186:707f6e361f3e 1047 else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
Anna Bridge 186:707f6e361f3e 1048 {
Anna Bridge 186:707f6e361f3e 1049 /* Clear CRS SYNCWARN flag */
Anna Bridge 186:707f6e361f3e 1050 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
Anna Bridge 186:707f6e361f3e 1051
Anna Bridge 186:707f6e361f3e 1052 /* user callback */
Anna Bridge 186:707f6e361f3e 1053 HAL_RCCEx_CRS_SyncWarnCallback();
Anna Bridge 186:707f6e361f3e 1054 }
Anna Bridge 186:707f6e361f3e 1055 /* Check CRS Expected SYNC flag */
Anna Bridge 186:707f6e361f3e 1056 else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
Anna Bridge 186:707f6e361f3e 1057 {
Anna Bridge 186:707f6e361f3e 1058 /* frequency error counter reached a zero value */
Anna Bridge 186:707f6e361f3e 1059 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
Anna Bridge 186:707f6e361f3e 1060
Anna Bridge 186:707f6e361f3e 1061 /* user callback */
Anna Bridge 186:707f6e361f3e 1062 HAL_RCCEx_CRS_ExpectedSyncCallback();
Anna Bridge 186:707f6e361f3e 1063 }
Anna Bridge 186:707f6e361f3e 1064 /* Check CRS Error flags */
Anna Bridge 186:707f6e361f3e 1065 else
Anna Bridge 186:707f6e361f3e 1066 {
Anna Bridge 186:707f6e361f3e 1067 if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
Anna Bridge 186:707f6e361f3e 1068 {
Anna Bridge 186:707f6e361f3e 1069 if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
Anna Bridge 186:707f6e361f3e 1070 {
Anna Bridge 186:707f6e361f3e 1071 crserror |= RCC_CRS_SYNCERR;
Anna Bridge 186:707f6e361f3e 1072 }
Anna Bridge 186:707f6e361f3e 1073 if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
Anna Bridge 186:707f6e361f3e 1074 {
Anna Bridge 186:707f6e361f3e 1075 crserror |= RCC_CRS_SYNCMISS;
Anna Bridge 186:707f6e361f3e 1076 }
Anna Bridge 186:707f6e361f3e 1077 if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
Anna Bridge 186:707f6e361f3e 1078 {
Anna Bridge 186:707f6e361f3e 1079 crserror |= RCC_CRS_TRIMOVF;
Anna Bridge 186:707f6e361f3e 1080 }
Anna Bridge 186:707f6e361f3e 1081
Anna Bridge 186:707f6e361f3e 1082 /* Clear CRS Error flags */
Anna Bridge 186:707f6e361f3e 1083 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
Anna Bridge 186:707f6e361f3e 1084
Anna Bridge 186:707f6e361f3e 1085 /* user error callback */
Anna Bridge 186:707f6e361f3e 1086 HAL_RCCEx_CRS_ErrorCallback(crserror);
Anna Bridge 186:707f6e361f3e 1087 }
Anna Bridge 186:707f6e361f3e 1088 }
<> 144:ef7eb2e8f9f7 1089 }
Anna Bridge 186:707f6e361f3e 1090
Anna Bridge 186:707f6e361f3e 1091 /**
Anna Bridge 186:707f6e361f3e 1092 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
Anna Bridge 186:707f6e361f3e 1093 * @retval none
Anna Bridge 186:707f6e361f3e 1094 */
Anna Bridge 186:707f6e361f3e 1095 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
Anna Bridge 186:707f6e361f3e 1096 {
Anna Bridge 186:707f6e361f3e 1097 /* NOTE : This function should not be modified, when the callback is needed,
Anna Bridge 186:707f6e361f3e 1098 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
Anna Bridge 186:707f6e361f3e 1099 */
Anna Bridge 186:707f6e361f3e 1100 }
Anna Bridge 186:707f6e361f3e 1101
Anna Bridge 186:707f6e361f3e 1102 /**
Anna Bridge 186:707f6e361f3e 1103 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
Anna Bridge 186:707f6e361f3e 1104 * @retval none
Anna Bridge 186:707f6e361f3e 1105 */
Anna Bridge 186:707f6e361f3e 1106 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
Anna Bridge 186:707f6e361f3e 1107 {
Anna Bridge 186:707f6e361f3e 1108 /* NOTE : This function should not be modified, when the callback is needed,
Anna Bridge 186:707f6e361f3e 1109 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
Anna Bridge 186:707f6e361f3e 1110 */
Anna Bridge 186:707f6e361f3e 1111 }
Anna Bridge 186:707f6e361f3e 1112
Anna Bridge 186:707f6e361f3e 1113 /**
Anna Bridge 186:707f6e361f3e 1114 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
Anna Bridge 186:707f6e361f3e 1115 * @retval none
Anna Bridge 186:707f6e361f3e 1116 */
Anna Bridge 186:707f6e361f3e 1117 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
Anna Bridge 186:707f6e361f3e 1118 {
Anna Bridge 186:707f6e361f3e 1119 /* NOTE : This function should not be modified, when the callback is needed,
Anna Bridge 186:707f6e361f3e 1120 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
Anna Bridge 186:707f6e361f3e 1121 */
Anna Bridge 186:707f6e361f3e 1122 }
Anna Bridge 186:707f6e361f3e 1123
Anna Bridge 186:707f6e361f3e 1124 /**
Anna Bridge 186:707f6e361f3e 1125 * @brief RCCEx Clock Recovery System Error interrupt callback.
Anna Bridge 186:707f6e361f3e 1126 * @param Error Combination of Error status.
Anna Bridge 186:707f6e361f3e 1127 * This parameter can be a combination of the following values:
Anna Bridge 186:707f6e361f3e 1128 * @arg @ref RCC_CRS_SYNCERR
Anna Bridge 186:707f6e361f3e 1129 * @arg @ref RCC_CRS_SYNCMISS
Anna Bridge 186:707f6e361f3e 1130 * @arg @ref RCC_CRS_TRIMOVF
Anna Bridge 186:707f6e361f3e 1131 * @retval none
Anna Bridge 186:707f6e361f3e 1132 */
Anna Bridge 186:707f6e361f3e 1133 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
Anna Bridge 186:707f6e361f3e 1134 {
Anna Bridge 186:707f6e361f3e 1135 /* Prevent unused argument(s) compilation warning */
Anna Bridge 186:707f6e361f3e 1136 UNUSED(Error);
Anna Bridge 186:707f6e361f3e 1137
Anna Bridge 186:707f6e361f3e 1138 /* NOTE : This function should not be modified, when the callback is needed,
Anna Bridge 186:707f6e361f3e 1139 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
Anna Bridge 186:707f6e361f3e 1140 */
Anna Bridge 186:707f6e361f3e 1141 }
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /**
<> 144:ef7eb2e8f9f7 1144 * @}
<> 144:ef7eb2e8f9f7 1145 */
<> 144:ef7eb2e8f9f7 1146
Anna Bridge 186:707f6e361f3e 1147 #endif /* CRS */
<> 144:ef7eb2e8f9f7 1148 /**
<> 144:ef7eb2e8f9f7 1149 * @}
<> 144:ef7eb2e8f9f7 1150 */
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @}
<> 144:ef7eb2e8f9f7 1154 */
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /**
<> 144:ef7eb2e8f9f7 1157 * @}
<> 144:ef7eb2e8f9f7 1158 */
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1161 /**
<> 144:ef7eb2e8f9f7 1162 * @}
<> 144:ef7eb2e8f9f7 1163 */
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/