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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 186:707f6e361f3e

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief Header file of RCC HAL module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
<>	144:ef7eb2e8f9f7	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	37	#ifndef __STM32L0xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	38	#define __STM32L0xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	45	#include "stm32l0xx_hal_def.h"
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	48	* @{
<>	144:ef7eb2e8f9f7	49	*/
<>	144:ef7eb2e8f9f7	50
Anna Bridge	186:707f6e361f3e	51	/** @addtogroup RCC
Anna Bridge	186:707f6e361f3e	52	* @{
Anna Bridge	186:707f6e361f3e	53	*/
Anna Bridge	186:707f6e361f3e	54
Anna Bridge	186:707f6e361f3e	55	/** @addtogroup RCC_Private_Constants
Anna Bridge	186:707f6e361f3e	56	* @{
Anna Bridge	186:707f6e361f3e	57	*/
Anna Bridge	186:707f6e361f3e	58
Anna Bridge	186:707f6e361f3e	59	/** @defgroup RCC_Timeout RCC Timeout
Anna Bridge	186:707f6e361f3e	60	* @{
Anna Bridge	186:707f6e361f3e	61	*/
Anna Bridge	186:707f6e361f3e	62
Anna Bridge	186:707f6e361f3e	63	/* Disable Backup domain write protection state change timeout */
Anna Bridge	186:707f6e361f3e	64	#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
Anna Bridge	186:707f6e361f3e	65	/* LSE state change timeout */
Anna Bridge	186:707f6e361f3e	66	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Anna Bridge	186:707f6e361f3e	67	#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
Anna Bridge	186:707f6e361f3e	68	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Anna Bridge	186:707f6e361f3e	69	#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Anna Bridge	186:707f6e361f3e	70	#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Anna Bridge	186:707f6e361f3e	71	#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Anna Bridge	186:707f6e361f3e	72	#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Anna Bridge	186:707f6e361f3e	73	#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Anna Bridge	186:707f6e361f3e	74	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	75	#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Anna Bridge	186:707f6e361f3e	76	#endif /* RCC_HSI48_SUPPORT */
Anna Bridge	186:707f6e361f3e	77	/**
Anna Bridge	186:707f6e361f3e	78	* @}
Anna Bridge	186:707f6e361f3e	79	*/
Anna Bridge	186:707f6e361f3e	80
Anna Bridge	186:707f6e361f3e	81
Anna Bridge	186:707f6e361f3e	82	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
Anna Bridge	186:707f6e361f3e	83	* @brief RCC registers bit address in the alias region
Anna Bridge	186:707f6e361f3e	84	* @{
Anna Bridge	186:707f6e361f3e	85	*/
Anna Bridge	186:707f6e361f3e	86	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Anna Bridge	186:707f6e361f3e	87	/* --- CR Register ---*/
Anna Bridge	186:707f6e361f3e	88	/* Alias word address of HSION bit */
Anna Bridge	186:707f6e361f3e	89	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
Anna Bridge	186:707f6e361f3e	90	/* --- CFGR Register ---*/
Anna Bridge	186:707f6e361f3e	91	/* Alias word address of I2SSRC bit */
Anna Bridge	186:707f6e361f3e	92	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
Anna Bridge	186:707f6e361f3e	93	/* --- CSR Register ---*/
Anna Bridge	186:707f6e361f3e	94	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
Anna Bridge	186:707f6e361f3e	95
Anna Bridge	186:707f6e361f3e	96	/* CR register byte 3 (Bits[23:16]) base address */
Anna Bridge	186:707f6e361f3e	97	#define RCC_CR_BYTE2_ADDRESS (0x40023802U)
Anna Bridge	186:707f6e361f3e	98
Anna Bridge	186:707f6e361f3e	99	/* CIER register byte 0 (Bits[0:8]) base address */
Anna Bridge	186:707f6e361f3e	100	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
Anna Bridge	186:707f6e361f3e	101	/**
Anna Bridge	186:707f6e361f3e	102	* @}
Anna Bridge	186:707f6e361f3e	103	*/
Anna Bridge	186:707f6e361f3e	104
Anna Bridge	186:707f6e361f3e	105
Anna Bridge	186:707f6e361f3e	106	/* Defines used for Flags */
Anna Bridge	186:707f6e361f3e	107	#define CR_REG_INDEX ((uint8_t)1)
Anna Bridge	186:707f6e361f3e	108	#define CSR_REG_INDEX ((uint8_t)2)
Anna Bridge	186:707f6e361f3e	109	#define CRRCR_REG_INDEX ((uint8_t)3)
Anna Bridge	186:707f6e361f3e	110
Anna Bridge	186:707f6e361f3e	111	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Anna Bridge	186:707f6e361f3e	112
Anna Bridge	186:707f6e361f3e	113	/**
Anna Bridge	186:707f6e361f3e	114	* @}
Anna Bridge	186:707f6e361f3e	115	*/
Anna Bridge	186:707f6e361f3e	116
Anna Bridge	186:707f6e361f3e	117	/** @addtogroup RCC_Private_Macros
<>	144:ef7eb2e8f9f7	118	* @{
<>	144:ef7eb2e8f9f7	119	*/
Anna Bridge	186:707f6e361f3e	120	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	121	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
Anna Bridge	186:707f6e361f3e	122	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Anna Bridge	186:707f6e361f3e	123	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Anna Bridge	186:707f6e361f3e	124	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) \|\| \
Anna Bridge	186:707f6e361f3e	125	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Anna Bridge	186:707f6e361f3e	126	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	127	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
Anna Bridge	186:707f6e361f3e	128
Anna Bridge	186:707f6e361f3e	129	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
Anna Bridge	186:707f6e361f3e	130	#else
Anna Bridge	186:707f6e361f3e	131	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
Anna Bridge	186:707f6e361f3e	132	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Anna Bridge	186:707f6e361f3e	133	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Anna Bridge	186:707f6e361f3e	134	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Anna Bridge	186:707f6e361f3e	135	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	136	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
Anna Bridge	186:707f6e361f3e	137	#endif /* RCC_HSI48_SUPPORT */
Anna Bridge	186:707f6e361f3e	138	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
Anna Bridge	186:707f6e361f3e	139	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Anna Bridge	186:707f6e361f3e	140	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Anna Bridge	186:707f6e361f3e	141	((__HSE__) == RCC_HSE_BYPASS))
Anna Bridge	186:707f6e361f3e	142	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Anna Bridge	186:707f6e361f3e	143	((__LSE__) == RCC_LSE_BYPASS))
Anna Bridge	186:707f6e361f3e	144	#if defined(RCC_CR_HSIOUTEN)
Anna Bridge	186:707f6e361f3e	145	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
Anna Bridge	186:707f6e361f3e	146	((__HSI__) == RCC_HSI_DIV4) \|\| ((__HSI__) == RCC_HSI_OUTEN ))
Anna Bridge	186:707f6e361f3e	147	#else
Anna Bridge	186:707f6e361f3e	148	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
Anna Bridge	186:707f6e361f3e	149	((__HSI__) == RCC_HSI_DIV4))
Anna Bridge	186:707f6e361f3e	150	#endif /* RCC_CR_HSIOUTEN */
Anna Bridge	186:707f6e361f3e	151	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Anna Bridge	186:707f6e361f3e	152	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
Anna Bridge	186:707f6e361f3e	153	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
Anna Bridge	186:707f6e361f3e	154	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
Anna Bridge	186:707f6e361f3e	155	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
Anna Bridge	186:707f6e361f3e	156	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
Anna Bridge	186:707f6e361f3e	157	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
Anna Bridge	186:707f6e361f3e	158	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
Anna Bridge	186:707f6e361f3e	159	((__RANGE__) == RCC_MSIRANGE_6))
Anna Bridge	186:707f6e361f3e	160	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Anna Bridge	186:707f6e361f3e	161	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
Anna Bridge	186:707f6e361f3e	162
Anna Bridge	186:707f6e361f3e	163	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
Anna Bridge	186:707f6e361f3e	164	((__PLL__) == RCC_PLL_ON))
Anna Bridge	186:707f6e361f3e	165	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
Anna Bridge	186:707f6e361f3e	166	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
Anna Bridge	186:707f6e361f3e	167
Anna Bridge	186:707f6e361f3e	168	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) \|\| ((__MUL__) == RCC_PLL_MUL4) \|\| \
Anna Bridge	186:707f6e361f3e	169	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL8) \|\| \
Anna Bridge	186:707f6e361f3e	170	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL16) \|\| \
Anna Bridge	186:707f6e361f3e	171	((__MUL__) == RCC_PLL_MUL24) \|\| ((__MUL__) == RCC_PLL_MUL32) \|\| \
Anna Bridge	186:707f6e361f3e	172	((__MUL__) == RCC_PLL_MUL48))
Anna Bridge	186:707f6e361f3e	173	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
Anna Bridge	186:707f6e361f3e	174	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
Anna Bridge	186:707f6e361f3e	175	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
Anna Bridge	186:707f6e361f3e	176	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
Anna Bridge	186:707f6e361f3e	177	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
Anna Bridge	186:707f6e361f3e	178	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Anna Bridge	186:707f6e361f3e	179	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Anna Bridge	186:707f6e361f3e	180	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Anna Bridge	186:707f6e361f3e	181	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) \|\| \
Anna Bridge	186:707f6e361f3e	182	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Anna Bridge	186:707f6e361f3e	183	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Anna Bridge	186:707f6e361f3e	184	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Anna Bridge	186:707f6e361f3e	185	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Anna Bridge	186:707f6e361f3e	186	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Anna Bridge	186:707f6e361f3e	187	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Anna Bridge	186:707f6e361f3e	188	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Anna Bridge	186:707f6e361f3e	189	((__HCLK__) == RCC_SYSCLK_DIV512))
Anna Bridge	186:707f6e361f3e	190	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Anna Bridge	186:707f6e361f3e	191	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Anna Bridge	186:707f6e361f3e	192	((__PCLK__) == RCC_HCLK_DIV16))
Anna Bridge	186:707f6e361f3e	193	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	194	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	195	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) \|\| ((__MCO__) == RCC_MCO2) \|\| ((__MCO__) == RCC_MCO3))
Anna Bridge	186:707f6e361f3e	196	#else
Anna Bridge	186:707f6e361f3e	197	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) \|\| ((__MCO__) == RCC_MCO2))
Anna Bridge	186:707f6e361f3e	198
Anna Bridge	186:707f6e361f3e	199	#endif
Anna Bridge	186:707f6e361f3e	200	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
Anna Bridge	186:707f6e361f3e	201	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
Anna Bridge	186:707f6e361f3e	202	((__DIV__) == RCC_MCODIV_16))
Anna Bridge	186:707f6e361f3e	203	#if defined(RCC_CFGR_MCOSEL_HSI48)
Anna Bridge	186:707f6e361f3e	204	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Anna Bridge	186:707f6e361f3e	205	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
Anna Bridge	186:707f6e361f3e	206	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Anna Bridge	186:707f6e361f3e	207	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	208	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
Anna Bridge	186:707f6e361f3e	209	#else
Anna Bridge	186:707f6e361f3e	210	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Anna Bridge	186:707f6e361f3e	211	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
Anna Bridge	186:707f6e361f3e	212	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Anna Bridge	186:707f6e361f3e	213	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Anna Bridge	186:707f6e361f3e	214	#endif /* RCC_CFGR_MCOSEL_HSI48 */
Anna Bridge	186:707f6e361f3e	215	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
Anna Bridge	186:707f6e361f3e	216	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
Anna Bridge	186:707f6e361f3e	217	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
Anna Bridge	186:707f6e361f3e	218	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
Anna Bridge	186:707f6e361f3e	219	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
Anna Bridge	186:707f6e361f3e	220	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
Anna Bridge	186:707f6e361f3e	221	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
Anna Bridge	186:707f6e361f3e	222
Anna Bridge	186:707f6e361f3e	223	/**
Anna Bridge	186:707f6e361f3e	224	* @}
Anna Bridge	186:707f6e361f3e	225	*/
Anna Bridge	186:707f6e361f3e	226
Anna Bridge	186:707f6e361f3e	227	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/** @defgroup RCC_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	230	* @{
<>	144:ef7eb2e8f9f7	231	*/
<>	144:ef7eb2e8f9f7	232
Anna Bridge	186:707f6e361f3e	233	/**
Anna Bridge	186:707f6e361f3e	234	* @brief RCC PLL configuration structure definition
<>	144:ef7eb2e8f9f7	235	*/
<>	144:ef7eb2e8f9f7	236	typedef struct
<>	144:ef7eb2e8f9f7	237	{
Anna Bridge	186:707f6e361f3e	238	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Anna Bridge	186:707f6e361f3e	239	This parameter can be a value of @ref RCC_PLL_Config */
<>	144:ef7eb2e8f9f7	240
Anna Bridge	186:707f6e361f3e	241	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Anna Bridge	186:707f6e361f3e	242	This parameter must be a value of @ref RCC_PLL_Clock_Source */
<>	144:ef7eb2e8f9f7	243
Anna Bridge	186:707f6e361f3e	244	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Anna Bridge	186:707f6e361f3e	245	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
<>	144:ef7eb2e8f9f7	246
Anna Bridge	186:707f6e361f3e	247	uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
Anna Bridge	186:707f6e361f3e	248	This parameter must be a value of @ref RCC_PLL_Division_Factor*/
Anna Bridge	186:707f6e361f3e	249	} RCC_PLLInitTypeDef;
Anna Bridge	186:707f6e361f3e	250
<>	144:ef7eb2e8f9f7	251	/**
<>	144:ef7eb2e8f9f7	252	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254	typedef struct
<>	144:ef7eb2e8f9f7	255	{
Anna Bridge	186:707f6e361f3e	256	uint32_t OscillatorType; /*!< The oscillators to be configured.
Anna Bridge	186:707f6e361f3e	257	This parameter can be a value of @ref RCC_Oscillator_Type */
<>	144:ef7eb2e8f9f7	258
Anna Bridge	186:707f6e361f3e	259	uint32_t HSEState; /*!< The new state of the HSE.
Anna Bridge	186:707f6e361f3e	260	This parameter can be a value of @ref RCC_HSE_Config */
<>	144:ef7eb2e8f9f7	261
Anna Bridge	186:707f6e361f3e	262	uint32_t LSEState; /*!< The new state of the LSE.
Anna Bridge	186:707f6e361f3e	263	This parameter can be a value of @ref RCC_LSE_Config */
<>	144:ef7eb2e8f9f7	264
Anna Bridge	186:707f6e361f3e	265	uint32_t HSIState; /*!< The new state of the HSI.
Anna Bridge	186:707f6e361f3e	266	This parameter can be a value of @ref RCC_HSI_Config */
<>	144:ef7eb2e8f9f7	267
Anna Bridge	186:707f6e361f3e	268	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Anna Bridge	186:707f6e361f3e	269	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Anna Bridge	186:707f6e361f3e	270
Anna Bridge	186:707f6e361f3e	271	uint32_t LSIState; /*!< The new state of the LSI.
Anna Bridge	186:707f6e361f3e	272	This parameter can be a value of @ref RCC_LSI_Config */
<>	144:ef7eb2e8f9f7	273
Anna Bridge	186:707f6e361f3e	274	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	275	uint32_t HSI48State; /*!< The new state of the HSI48.
Anna Bridge	186:707f6e361f3e	276	This parameter can be a value of @ref RCC_HSI48_Config */
<>	144:ef7eb2e8f9f7	277
Anna Bridge	186:707f6e361f3e	278	#endif /* RCC_HSI48_SUPPORT */
Anna Bridge	186:707f6e361f3e	279	uint32_t MSIState; /*!< The new state of the MSI.
Anna Bridge	186:707f6e361f3e	280	This parameter can be a value of @ref RCC_MSI_Config */
<>	144:ef7eb2e8f9f7	281
Anna Bridge	186:707f6e361f3e	282	uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
Anna Bridge	186:707f6e361f3e	283	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<>	144:ef7eb2e8f9f7	284
<>	144:ef7eb2e8f9f7	285	uint32_t MSIClockRange; /*!< The MSI frequency range.
Anna Bridge	186:707f6e361f3e	286	This parameter can be a value of @ref RCC_MSI_Clock_Range */
<>	144:ef7eb2e8f9f7	287
Anna Bridge	186:707f6e361f3e	288	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
<>	144:ef7eb2e8f9f7	289
Anna Bridge	186:707f6e361f3e	290	} RCC_OscInitTypeDef;
<>	144:ef7eb2e8f9f7	291
<>	144:ef7eb2e8f9f7	292	/**
<>	144:ef7eb2e8f9f7	293	* @brief RCC System, AHB and APB busses clock configuration structure definition
<>	144:ef7eb2e8f9f7	294	*/
<>	144:ef7eb2e8f9f7	295	typedef struct
<>	144:ef7eb2e8f9f7	296	{
<>	144:ef7eb2e8f9f7	297	uint32_t ClockType; /*!< The clock to be configured.
<>	144:ef7eb2e8f9f7	298	This parameter can be a value of @ref RCC_System_Clock_Type */
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<>	144:ef7eb2e8f9f7	301	This parameter can be a value of @ref RCC_System_Clock_Source */
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	304	This parameter can be a value of @ref RCC_AHB_Clock_Source */
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	307	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	310	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Anna Bridge	186:707f6e361f3e	311	} RCC_ClkInitTypeDef;
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	/**
<>	144:ef7eb2e8f9f7	314	* @}
<>	144:ef7eb2e8f9f7	315	*/
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	318	/** @defgroup RCC_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	319	* @{
<>	144:ef7eb2e8f9f7	320	*/
<>	144:ef7eb2e8f9f7	321
Anna Bridge	186:707f6e361f3e	322	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<>	144:ef7eb2e8f9f7	323	* @{
<>	144:ef7eb2e8f9f7	324	*/
<>	144:ef7eb2e8f9f7	325
Anna Bridge	186:707f6e361f3e	326	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
Anna Bridge	186:707f6e361f3e	327	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	/**
<>	144:ef7eb2e8f9f7	330	* @}
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332
Anna Bridge	186:707f6e361f3e	333	/** @defgroup RCC_Oscillator_Type Oscillator Type
<>	144:ef7eb2e8f9f7	334	* @{
<>	144:ef7eb2e8f9f7	335	*/
Anna Bridge	186:707f6e361f3e	336	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Anna Bridge	186:707f6e361f3e	337	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Anna Bridge	186:707f6e361f3e	338	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Anna Bridge	186:707f6e361f3e	339	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Anna Bridge	186:707f6e361f3e	340	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Anna Bridge	186:707f6e361f3e	341	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
Anna Bridge	186:707f6e361f3e	342	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	343	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Anna Bridge	186:707f6e361f3e	344	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	345	/**
<>	144:ef7eb2e8f9f7	346	* @}
<>	144:ef7eb2e8f9f7	347	*/
<>	144:ef7eb2e8f9f7	348
Anna Bridge	186:707f6e361f3e	349	/** @defgroup RCC_HSE_Config HSE Config
<>	144:ef7eb2e8f9f7	350	* @{
<>	144:ef7eb2e8f9f7	351	*/
Anna Bridge	186:707f6e361f3e	352	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
Anna Bridge	186:707f6e361f3e	353	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
Anna Bridge	186:707f6e361f3e	354	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
Anna Bridge	186:707f6e361f3e	355	/**
Anna Bridge	186:707f6e361f3e	356	* @}
Anna Bridge	186:707f6e361f3e	357	*/
<>	144:ef7eb2e8f9f7	358
Anna Bridge	186:707f6e361f3e	359	/** @defgroup RCC_LSE_Config LSE Config
Anna Bridge	186:707f6e361f3e	360	* @{
Anna Bridge	186:707f6e361f3e	361	*/
Anna Bridge	186:707f6e361f3e	362	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
Anna Bridge	186:707f6e361f3e	363	#define RCC_LSE_ON RCC_CSR_LSEON /!< LSE clock activation /
Anna Bridge	186:707f6e361f3e	364	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON)) /!< External clock source for LSE clock /
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/**
<>	144:ef7eb2e8f9f7	367	* @}
<>	144:ef7eb2e8f9f7	368	*/
<>	144:ef7eb2e8f9f7	369
Anna Bridge	186:707f6e361f3e	370	/** @defgroup RCC_HSI_Config HSI Config
<>	144:ef7eb2e8f9f7	371	* @{
<>	144:ef7eb2e8f9f7	372	*/
Anna Bridge	186:707f6e361f3e	373	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
Anna Bridge	186:707f6e361f3e	374	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
Anna Bridge	186:707f6e361f3e	375	#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN \| RCC_CR_HSION) /!< HSI_DIV4 clock activation /
Anna Bridge	186:707f6e361f3e	376	#if defined(RCC_CR_HSIOUTEN)
Anna Bridge	186:707f6e361f3e	377	#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN /!< HSI_OUTEN clock activation /
Anna Bridge	186:707f6e361f3e	378	#endif /* RCC_CR_HSIOUTEN */
<>	144:ef7eb2e8f9f7	379
Anna Bridge	186:707f6e361f3e	380	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/**
<>	144:ef7eb2e8f9f7	383	* @}
<>	144:ef7eb2e8f9f7	384	*/
<>	144:ef7eb2e8f9f7	385
Anna Bridge	186:707f6e361f3e	386	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
<>	144:ef7eb2e8f9f7	387	* @{
<>	144:ef7eb2e8f9f7	388	*/
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
<>	144:ef7eb2e8f9f7	391	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
<>	144:ef7eb2e8f9f7	392	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
<>	144:ef7eb2e8f9f7	393	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
<>	144:ef7eb2e8f9f7	394	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
<>	144:ef7eb2e8f9f7	395	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
<>	144:ef7eb2e8f9f7	396	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
<>	144:ef7eb2e8f9f7	397
Anna Bridge	186:707f6e361f3e	398	/**
Anna Bridge	186:707f6e361f3e	399	* @}
Anna Bridge	186:707f6e361f3e	400	*/
Anna Bridge	186:707f6e361f3e	401
Anna Bridge	186:707f6e361f3e	402	/** @defgroup RCC_LSI_Config LSI Config
Anna Bridge	186:707f6e361f3e	403	* @{
Anna Bridge	186:707f6e361f3e	404	*/
Anna Bridge	186:707f6e361f3e	405	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
Anna Bridge	186:707f6e361f3e	406	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
Anna Bridge	186:707f6e361f3e	407
Anna Bridge	186:707f6e361f3e	408	/**
Anna Bridge	186:707f6e361f3e	409	* @}
Anna Bridge	186:707f6e361f3e	410	*/
Anna Bridge	186:707f6e361f3e	411
Anna Bridge	186:707f6e361f3e	412	/** @defgroup RCC_MSI_Config MSI Config
Anna Bridge	186:707f6e361f3e	413	* @{
Anna Bridge	186:707f6e361f3e	414	*/
Anna Bridge	186:707f6e361f3e	415	#define RCC_MSI_OFF ((uint32_t)0x00000000)
Anna Bridge	186:707f6e361f3e	416	#define RCC_MSI_ON ((uint32_t)0x00000001)
Anna Bridge	186:707f6e361f3e	417
Anna Bridge	186:707f6e361f3e	418	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00000000U) /* Default MSI calibration trimming value */
Anna Bridge	186:707f6e361f3e	419
Anna Bridge	186:707f6e361f3e	420	/**
Anna Bridge	186:707f6e361f3e	421	* @}
Anna Bridge	186:707f6e361f3e	422	*/
Anna Bridge	186:707f6e361f3e	423
Anna Bridge	186:707f6e361f3e	424	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	425	/** @defgroup RCC_HSI48_Config HSI48 Config
Anna Bridge	186:707f6e361f3e	426	* @{
Anna Bridge	186:707f6e361f3e	427	*/
Anna Bridge	186:707f6e361f3e	428	#define RCC_HSI48_OFF ((uint8_t)0x00)
Anna Bridge	186:707f6e361f3e	429	#define RCC_HSI48_ON ((uint8_t)0x01)
Anna Bridge	186:707f6e361f3e	430
Anna Bridge	186:707f6e361f3e	431	/**
Anna Bridge	186:707f6e361f3e	432	* @}
Anna Bridge	186:707f6e361f3e	433	*/
Anna Bridge	186:707f6e361f3e	434	#endif /* RCC_HSI48_SUPPORT */
Anna Bridge	186:707f6e361f3e	435
Anna Bridge	186:707f6e361f3e	436	/** @defgroup RCC_PLL_Config PLL Config
Anna Bridge	186:707f6e361f3e	437	* @{
Anna Bridge	186:707f6e361f3e	438	*/
Anna Bridge	186:707f6e361f3e	439	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
Anna Bridge	186:707f6e361f3e	440	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
Anna Bridge	186:707f6e361f3e	441	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
Anna Bridge	186:707f6e361f3e	442
Anna Bridge	186:707f6e361f3e	443	/**
Anna Bridge	186:707f6e361f3e	444	* @}
Anna Bridge	186:707f6e361f3e	445	*/
Anna Bridge	186:707f6e361f3e	446
Anna Bridge	186:707f6e361f3e	447	/** @defgroup RCC_System_Clock_Type System Clock Type
Anna Bridge	186:707f6e361f3e	448	* @{
Anna Bridge	186:707f6e361f3e	449	*/
Anna Bridge	186:707f6e361f3e	450	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
Anna Bridge	186:707f6e361f3e	451	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
Anna Bridge	186:707f6e361f3e	452	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
Anna Bridge	186:707f6e361f3e	453	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
Anna Bridge	186:707f6e361f3e	454
Anna Bridge	186:707f6e361f3e	455	/**
Anna Bridge	186:707f6e361f3e	456	* @}
Anna Bridge	186:707f6e361f3e	457	*/
Anna Bridge	186:707f6e361f3e	458
Anna Bridge	186:707f6e361f3e	459	/** @defgroup RCC_System_Clock_Source System Clock Source
Anna Bridge	186:707f6e361f3e	460	* @{
Anna Bridge	186:707f6e361f3e	461	*/
Anna Bridge	186:707f6e361f3e	462	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selected as system clock /
Anna Bridge	186:707f6e361f3e	463	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
Anna Bridge	186:707f6e361f3e	464	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
Anna Bridge	186:707f6e361f3e	465	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
Anna Bridge	186:707f6e361f3e	466
Anna Bridge	186:707f6e361f3e	467	/**
Anna Bridge	186:707f6e361f3e	468	* @}
Anna Bridge	186:707f6e361f3e	469	*/
Anna Bridge	186:707f6e361f3e	470
Anna Bridge	186:707f6e361f3e	471	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Anna Bridge	186:707f6e361f3e	472	* @{
Anna Bridge	186:707f6e361f3e	473	*/
Anna Bridge	186:707f6e361f3e	474	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
Anna Bridge	186:707f6e361f3e	475	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Anna Bridge	186:707f6e361f3e	476	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Anna Bridge	186:707f6e361f3e	477	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	478
<>	144:ef7eb2e8f9f7	479	/**
<>	144:ef7eb2e8f9f7	480	* @}
<>	144:ef7eb2e8f9f7	481	*/
<>	144:ef7eb2e8f9f7	482
Anna Bridge	186:707f6e361f3e	483	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
<>	144:ef7eb2e8f9f7	484	* @{
<>	144:ef7eb2e8f9f7	485	*/
Anna Bridge	186:707f6e361f3e	486	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
Anna Bridge	186:707f6e361f3e	487	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
Anna Bridge	186:707f6e361f3e	488	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
Anna Bridge	186:707f6e361f3e	489	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
Anna Bridge	186:707f6e361f3e	490	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
Anna Bridge	186:707f6e361f3e	491	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
Anna Bridge	186:707f6e361f3e	492	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
Anna Bridge	186:707f6e361f3e	493	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
Anna Bridge	186:707f6e361f3e	494	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	144:ef7eb2e8f9f7	495
<>	144:ef7eb2e8f9f7	496	/**
<>	144:ef7eb2e8f9f7	497	* @}
<>	144:ef7eb2e8f9f7	498	*/
Anna Bridge	186:707f6e361f3e	499
Anna Bridge	186:707f6e361f3e	500	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
<>	144:ef7eb2e8f9f7	501	* @{
<>	144:ef7eb2e8f9f7	502	*/
Anna Bridge	186:707f6e361f3e	503	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
Anna Bridge	186:707f6e361f3e	504	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
Anna Bridge	186:707f6e361f3e	505	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
Anna Bridge	186:707f6e361f3e	506	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
Anna Bridge	186:707f6e361f3e	507	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	508
<>	144:ef7eb2e8f9f7	509	/**
<>	144:ef7eb2e8f9f7	510	* @}
<>	144:ef7eb2e8f9f7	511	*/
<>	144:ef7eb2e8f9f7	512
Anna Bridge	186:707f6e361f3e	513	/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
<>	144:ef7eb2e8f9f7	514	* @{
<>	144:ef7eb2e8f9f7	515	*/
Anna Bridge	186:707f6e361f3e	516	#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /!< HSE is divided by 2 for RTC clock /
Anna Bridge	186:707f6e361f3e	517	#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
Anna Bridge	186:707f6e361f3e	518	#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
Anna Bridge	186:707f6e361f3e	519	#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
Anna Bridge	186:707f6e361f3e	520	/**
Anna Bridge	186:707f6e361f3e	521	* @}
Anna Bridge	186:707f6e361f3e	522	*/
<>	144:ef7eb2e8f9f7	523
Anna Bridge	186:707f6e361f3e	524	/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
Anna Bridge	186:707f6e361f3e	525	* @{
Anna Bridge	186:707f6e361f3e	526	*/
Anna Bridge	186:707f6e361f3e	527	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /!< No clock /
Anna Bridge	186:707f6e361f3e	528	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
Anna Bridge	186:707f6e361f3e	529	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
Anna Bridge	186:707f6e361f3e	530	#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /!< HSE oscillator clock divided by X used as RTC clock /
Anna Bridge	186:707f6e361f3e	531	#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 2 used as RTC clock /
Anna Bridge	186:707f6e361f3e	532	#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 4 used as RTC clock /
Anna Bridge	186:707f6e361f3e	533	#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 8 used as RTC clock /
Anna Bridge	186:707f6e361f3e	534	#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 16 used as RTC clock /
<>	144:ef7eb2e8f9f7	535	/**
<>	144:ef7eb2e8f9f7	536	* @}
<>	144:ef7eb2e8f9f7	537	*/
<>	144:ef7eb2e8f9f7	538
Anna Bridge	186:707f6e361f3e	539	/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
Anna Bridge	186:707f6e361f3e	540	* @{
Anna Bridge	186:707f6e361f3e	541	*/
Anna Bridge	186:707f6e361f3e	542
Anna Bridge	186:707f6e361f3e	543	#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
Anna Bridge	186:707f6e361f3e	544	#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
Anna Bridge	186:707f6e361f3e	545	#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
Anna Bridge	186:707f6e361f3e	546
Anna Bridge	186:707f6e361f3e	547	/**
Anna Bridge	186:707f6e361f3e	548	* @}
Anna Bridge	186:707f6e361f3e	549	*/
Anna Bridge	186:707f6e361f3e	550
Anna Bridge	186:707f6e361f3e	551	/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
<>	144:ef7eb2e8f9f7	552	* @{
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554
Anna Bridge	186:707f6e361f3e	555	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Anna Bridge	186:707f6e361f3e	556	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Anna Bridge	186:707f6e361f3e	557	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Anna Bridge	186:707f6e361f3e	558	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Anna Bridge	186:707f6e361f3e	559	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Anna Bridge	186:707f6e361f3e	560	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Anna Bridge	186:707f6e361f3e	561	#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
Anna Bridge	186:707f6e361f3e	562	#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
Anna Bridge	186:707f6e361f3e	563	#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
<>	144:ef7eb2e8f9f7	564
<>	144:ef7eb2e8f9f7	565	/**
<>	144:ef7eb2e8f9f7	566	* @}
Anna Bridge	186:707f6e361f3e	567	*/
<>	144:ef7eb2e8f9f7	568
Anna Bridge	186:707f6e361f3e	569	/** @defgroup RCC_MCO_Index MCO Index
<>	144:ef7eb2e8f9f7	570	* @{
<>	144:ef7eb2e8f9f7	571	*/
Anna Bridge	186:707f6e361f3e	572	#define RCC_MCO1 ((uint32_t)0x00000000)
Anna Bridge	186:707f6e361f3e	573	#define RCC_MCO2 ((uint32_t)0x00000001)
Anna Bridge	186:707f6e361f3e	574	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
Anna Bridge	186:707f6e361f3e	575	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Anna Bridge	186:707f6e361f3e	576	#define RCC_MCO3 ((uint32_t)0x00000002)
<>	144:ef7eb2e8f9f7	577	#endif
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	/**
<>	144:ef7eb2e8f9f7	580	* @}
<>	144:ef7eb2e8f9f7	581	*/
<>	144:ef7eb2e8f9f7	582
Anna Bridge	186:707f6e361f3e	583	/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
<>	144:ef7eb2e8f9f7	584	* @{
<>	144:ef7eb2e8f9f7	585	*/
Anna Bridge	186:707f6e361f3e	586	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
Anna Bridge	186:707f6e361f3e	587	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
Anna Bridge	186:707f6e361f3e	588	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
Anna Bridge	186:707f6e361f3e	589	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
Anna Bridge	186:707f6e361f3e	590	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
<>	144:ef7eb2e8f9f7	591
<>	144:ef7eb2e8f9f7	592	/**
<>	144:ef7eb2e8f9f7	593	* @}
<>	144:ef7eb2e8f9f7	594	*/
<>	144:ef7eb2e8f9f7	595
Anna Bridge	186:707f6e361f3e	596	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Anna Bridge	186:707f6e361f3e	597	* @{
Anna Bridge	186:707f6e361f3e	598	*/
Anna Bridge	186:707f6e361f3e	599	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Anna Bridge	186:707f6e361f3e	600	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Anna Bridge	186:707f6e361f3e	601	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
Anna Bridge	186:707f6e361f3e	602	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
Anna Bridge	186:707f6e361f3e	603	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
Anna Bridge	186:707f6e361f3e	604	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
Anna Bridge	186:707f6e361f3e	605	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
Anna Bridge	186:707f6e361f3e	606	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
Anna Bridge	186:707f6e361f3e	607	#if defined(RCC_CFGR_MCOSEL_HSI48)
Anna Bridge	186:707f6e361f3e	608	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
Anna Bridge	186:707f6e361f3e	609	#endif /* RCC_CFGR_MCOSEL_HSI48 */
Anna Bridge	186:707f6e361f3e	610
Anna Bridge	186:707f6e361f3e	611	/**
Anna Bridge	186:707f6e361f3e	612	* @}
Anna Bridge	186:707f6e361f3e	613	*/
Anna Bridge	186:707f6e361f3e	614	/** @defgroup RCC_Interrupt Interrupts
Anna Bridge	186:707f6e361f3e	615	* @{
Anna Bridge	186:707f6e361f3e	616	*/
Anna Bridge	186:707f6e361f3e	617	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
Anna Bridge	186:707f6e361f3e	618	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
Anna Bridge	186:707f6e361f3e	619	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
Anna Bridge	186:707f6e361f3e	620	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
Anna Bridge	186:707f6e361f3e	621	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
Anna Bridge	186:707f6e361f3e	622	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
Anna Bridge	186:707f6e361f3e	623	#define RCC_IT_LSECSS RCC_CIFR_CSSLSEF /!< LSE Clock Security System Interrupt flag /
Anna Bridge	186:707f6e361f3e	624	#if defined(RCC_HSECSS_SUPPORT)
Anna Bridge	186:707f6e361f3e	625	#define RCC_IT_CSS RCC_CIFR_CSSHSEF /!< Clock Security System Interrupt flag /
Anna Bridge	186:707f6e361f3e	626	#endif /* RCC_HSECSS_SUPPORT */
Anna Bridge	186:707f6e361f3e	627	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	628	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
Anna Bridge	186:707f6e361f3e	629	#endif /* RCC_HSI48_SUPPORT */
Anna Bridge	186:707f6e361f3e	630	/**
Anna Bridge	186:707f6e361f3e	631	* @}
Anna Bridge	186:707f6e361f3e	632	*/
Anna Bridge	186:707f6e361f3e	633
Anna Bridge	186:707f6e361f3e	634	/** @defgroup RCC_Flag Flags
Anna Bridge	186:707f6e361f3e	635	* Elements values convention: XXXYYYYYb
<>	144:ef7eb2e8f9f7	636	* - YYYYY : Flag position in the register
Anna Bridge	186:707f6e361f3e	637	* - XXX : Register index
Anna Bridge	186:707f6e361f3e	638	* - 001: CR register
Anna Bridge	186:707f6e361f3e	639	* - 010: CSR register
Anna Bridge	186:707f6e361f3e	640	* - 011: CRRCR register (*)
Anna Bridge	186:707f6e361f3e	641	* (*) Applicable only for STM32L052xx, STM32L053xx, (...), STM32L073xx & STM32L082xx
<>	144:ef7eb2e8f9f7	642	* @{
<>	144:ef7eb2e8f9f7	643	*/
<>	144:ef7eb2e8f9f7	644	/* Flags in the CR register */
Anna Bridge	186:707f6e361f3e	645	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| 2)) /!< Internal High Speed clock ready flag /
Anna Bridge	186:707f6e361f3e	646	#define RCC_FLAG_HSIDIV ((uint8_t)((CR_REG_INDEX << 5) \| 4)) /!< HSI16 divider flag /
Anna Bridge	186:707f6e361f3e	647	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| 9)) /!< MSI clock ready flag /
Anna Bridge	186:707f6e361f3e	648	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| 17)) /!< External High Speed clock ready flag /
Anna Bridge	186:707f6e361f3e	649	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| 25)) /!< PLL clock ready flag /
<>	144:ef7eb2e8f9f7	650	/* Flags in the CSR register */
Anna Bridge	186:707f6e361f3e	651	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| 1)) /!< Internal Low Speed oscillator Ready /
Anna Bridge	186:707f6e361f3e	652	#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) \| 9)) /!< External Low Speed oscillator Ready /
Anna Bridge	186:707f6e361f3e	653	#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) \| 14)) /!< CSS on LSE failure Detection /
Anna Bridge	186:707f6e361f3e	654	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| 25)) /!< Options bytes loading reset flag /
Anna Bridge	186:707f6e361f3e	655	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| 26)) /!< PIN reset flag /
Anna Bridge	186:707f6e361f3e	656	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| 27)) /!< POR/PDR reset flag /
Anna Bridge	186:707f6e361f3e	657	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| 28)) /!< Software Reset flag /
Anna Bridge	186:707f6e361f3e	658	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| 29)) /!< Independent Watchdog reset flag /
Anna Bridge	186:707f6e361f3e	659	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| 30)) /!< Window watchdog reset flag /
Anna Bridge	186:707f6e361f3e	660	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| 31)) /!< Low-Power reset flag /
Anna Bridge	186:707f6e361f3e	661	#if defined(RCC_CSR_FWRSTF)
Anna Bridge	186:707f6e361f3e	662	#define RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) \| 8)) /!< RCC flag FW reset /
Anna Bridge	186:707f6e361f3e	663	#endif /* RCC_CSR_FWRSTF */
<>	144:ef7eb2e8f9f7	664	/* Flags in the CRRCR register */
Anna Bridge	186:707f6e361f3e	665	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	666	#define RCC_FLAG_HSI48RDY ((uint8_t)((CRRCR_REG_INDEX << 5) \| 1)) /!< HSI48 clock ready flag /
Anna Bridge	186:707f6e361f3e	667	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	/**
<>	144:ef7eb2e8f9f7	670	* @}
Anna Bridge	186:707f6e361f3e	671	*/
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	/**
<>	144:ef7eb2e8f9f7	674	* @}
Anna Bridge	186:707f6e361f3e	675	*/
Anna Bridge	186:707f6e361f3e	676
<>	144:ef7eb2e8f9f7	677	/* Exported macro ------------------------------------------------------------*/
Anna Bridge	186:707f6e361f3e	678
<>	144:ef7eb2e8f9f7	679	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Anna Bridge	186:707f6e361f3e	680	* @{
Anna Bridge	186:707f6e361f3e	681	*/
Anna Bridge	186:707f6e361f3e	682
<>	144:ef7eb2e8f9f7	683	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	684	* @brief Enable or disable the AHB peripheral clock.
<>	144:ef7eb2e8f9f7	685	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	686	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	687	* using it.
<>	144:ef7eb2e8f9f7	688	* @{
<>	144:ef7eb2e8f9f7	689	*/
<>	144:ef7eb2e8f9f7	690	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	691	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	692	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	693	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	694	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	695	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	696	} while(0)
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	699	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	700	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
<>	144:ef7eb2e8f9f7	701	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	702	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
<>	144:ef7eb2e8f9f7	703	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	704	} while(0)
<>	144:ef7eb2e8f9f7	705
<>	144:ef7eb2e8f9f7	706	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	707	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	708	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<>	144:ef7eb2e8f9f7	709	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	710	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<>	144:ef7eb2e8f9f7	711	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	712	} while(0)
<>	144:ef7eb2e8f9f7	713
<>	144:ef7eb2e8f9f7	714
<>	144:ef7eb2e8f9f7	715	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
<>	144:ef7eb2e8f9f7	716	#define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
<>	144:ef7eb2e8f9f7	717	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	/**
<>	144:ef7eb2e8f9f7	720	* @}
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	724	* @brief Enable or disable the IOPORT peripheral clock.
<>	144:ef7eb2e8f9f7	725	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	726	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	727	* using it.
<>	144:ef7eb2e8f9f7	728	* @{
<>	144:ef7eb2e8f9f7	729	*/
<>	144:ef7eb2e8f9f7	730	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	731	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	732	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	733	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	734	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	735	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	736	} while(0)
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	739	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	740	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	741	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	742	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	743	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	744	} while(0)
<>	144:ef7eb2e8f9f7	745
<>	144:ef7eb2e8f9f7	746	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	747	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	748	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	749	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	750	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	751	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	752	} while(0)
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	755	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	756	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	757	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	758	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	759	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	760	} while(0)
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
<>	144:ef7eb2e8f9f7	764	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
<>	144:ef7eb2e8f9f7	765	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
<>	144:ef7eb2e8f9f7	766	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
<>	144:ef7eb2e8f9f7	767
<>	144:ef7eb2e8f9f7	768	/**
<>	144:ef7eb2e8f9f7	769	* @}
<>	144:ef7eb2e8f9f7	770	*/
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	773	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<>	144:ef7eb2e8f9f7	774	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	775	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	776	* using it.
<>	144:ef7eb2e8f9f7	777	* @{
<>	144:ef7eb2e8f9f7	778	*/
<>	144:ef7eb2e8f9f7	779	#define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	780	#define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	781
<>	144:ef7eb2e8f9f7	782	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	783	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	784	/**
<>	144:ef7eb2e8f9f7	785	* @}
<>	144:ef7eb2e8f9f7	786	*/
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	789	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<>	144:ef7eb2e8f9f7	790	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	791	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	792	* using it.
<>	144:ef7eb2e8f9f7	793	* @{
<>	144:ef7eb2e8f9f7	794	*/
<>	144:ef7eb2e8f9f7	795	#define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
<>	144:ef7eb2e8f9f7	796	#define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
<>	144:ef7eb2e8f9f7	799	#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
<>	144:ef7eb2e8f9f7	800	/**
<>	144:ef7eb2e8f9f7	801	* @}
<>	144:ef7eb2e8f9f7	802	*/
<>	144:ef7eb2e8f9f7	803
<>	144:ef7eb2e8f9f7	804	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	805	* @brief Check whether the AHB peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	806	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	807	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	808	* using it.
<>	144:ef7eb2e8f9f7	809	* @{
<>	144:ef7eb2e8f9f7	810	*/
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
<>	144:ef7eb2e8f9f7	813	#define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET)
<>	144:ef7eb2e8f9f7	814	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
Anna Bridge	186:707f6e361f3e	815	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET)
Anna Bridge	186:707f6e361f3e	816	#define __HAL_RCC_MIF_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == RESET)
Anna Bridge	186:707f6e361f3e	817	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)
<>	144:ef7eb2e8f9f7	818
<>	144:ef7eb2e8f9f7	819	/**
<>	144:ef7eb2e8f9f7	820	* @}
<>	144:ef7eb2e8f9f7	821	*/
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	/** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	824	* @brief Check whether the IOPORT peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	825	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	826	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	827	* using it.
<>	144:ef7eb2e8f9f7	828	* @{
<>	144:ef7eb2e8f9f7	829	*/
<>	144:ef7eb2e8f9f7	830
<>	144:ef7eb2e8f9f7	831	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
<>	144:ef7eb2e8f9f7	832	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
<>	144:ef7eb2e8f9f7	833	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
<>	144:ef7eb2e8f9f7	834	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET)
Anna Bridge	186:707f6e361f3e	835	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)
Anna Bridge	186:707f6e361f3e	836	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)
Anna Bridge	186:707f6e361f3e	837	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)
Anna Bridge	186:707f6e361f3e	838	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == RESET)
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	/**
<>	144:ef7eb2e8f9f7	841	* @}
<>	144:ef7eb2e8f9f7	842	*/
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	845	* @brief Check whether the APB1 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	846	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	847	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	848	* using it.
<>	144:ef7eb2e8f9f7	849	* @{
<>	144:ef7eb2e8f9f7	850	*/
<>	144:ef7eb2e8f9f7	851	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET)
<>	144:ef7eb2e8f9f7	852	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET)
Anna Bridge	186:707f6e361f3e	853	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == RESET)
Anna Bridge	186:707f6e361f3e	854	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == RESET)
<>	144:ef7eb2e8f9f7	855
<>	144:ef7eb2e8f9f7	856	/**
<>	144:ef7eb2e8f9f7	857	* @}
<>	144:ef7eb2e8f9f7	858	*/
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	861	* @brief Check whether the APB2 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	862	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	863	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	864	* using it.
<>	144:ef7eb2e8f9f7	865	* @{
<>	144:ef7eb2e8f9f7	866	*/
<>	144:ef7eb2e8f9f7	867	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
<>	144:ef7eb2e8f9f7	868	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET)
Anna Bridge	186:707f6e361f3e	869	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
Anna Bridge	186:707f6e361f3e	870	#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == RESET)
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	/**
<>	144:ef7eb2e8f9f7	873	* @}
<>	144:ef7eb2e8f9f7	874	*/
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	877	* @brief Force or release AHB peripheral reset.
<>	144:ef7eb2e8f9f7	878	* @{
<>	144:ef7eb2e8f9f7	879	*/
<>	151:5eaa88a5bcc7	880	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	881	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	882	#define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
<>	144:ef7eb2e8f9f7	883	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
<>	144:ef7eb2e8f9f7	884
Anna Bridge	186:707f6e361f3e	885	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
<>	144:ef7eb2e8f9f7	886	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
<>	144:ef7eb2e8f9f7	887	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	888	#define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
<>	144:ef7eb2e8f9f7	889	/**
<>	144:ef7eb2e8f9f7	890	* @}
<>	144:ef7eb2e8f9f7	891	*/
<>	144:ef7eb2e8f9f7	892
<>	144:ef7eb2e8f9f7	893	/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	894	* @brief Force or release IOPORT peripheral reset.
<>	144:ef7eb2e8f9f7	895	* @{
<>	144:ef7eb2e8f9f7	896	*/
<>	151:5eaa88a5bcc7	897	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	898	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	899	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	900	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	901	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	902
Anna Bridge	186:707f6e361f3e	903	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00000000U)
<>	144:ef7eb2e8f9f7	904	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	905	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	906	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	907	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	/**
<>	144:ef7eb2e8f9f7	910	* @}
<>	144:ef7eb2e8f9f7	911	*/
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	914	* @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	915	* @{
<>	144:ef7eb2e8f9f7	916	*/
<>	151:5eaa88a5bcc7	917	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	918	#define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	919	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	920
Anna Bridge	186:707f6e361f3e	921	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
<>	144:ef7eb2e8f9f7	922	#define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	923	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	/**
<>	144:ef7eb2e8f9f7	926	* @}
<>	144:ef7eb2e8f9f7	927	*/
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	930	* @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	931	* @{
<>	144:ef7eb2e8f9f7	932	*/
<>	151:5eaa88a5bcc7	933	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	934	#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
<>	144:ef7eb2e8f9f7	935	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	936
Anna Bridge	186:707f6e361f3e	937	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
<>	144:ef7eb2e8f9f7	938	#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
<>	144:ef7eb2e8f9f7	939	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	940	/**
<>	144:ef7eb2e8f9f7	941	* @}
<>	144:ef7eb2e8f9f7	942	*/
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944
<>	144:ef7eb2e8f9f7	945	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	946	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	947	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	948	* power consumption.
<>	144:ef7eb2e8f9f7	949	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	950	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	951	* @{
<>	144:ef7eb2e8f9f7	952	*/
<>	144:ef7eb2e8f9f7	953	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
<>	144:ef7eb2e8f9f7	954	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
<>	144:ef7eb2e8f9f7	955	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
<>	144:ef7eb2e8f9f7	956	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
<>	144:ef7eb2e8f9f7	959	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
<>	144:ef7eb2e8f9f7	960	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
<>	144:ef7eb2e8f9f7	961	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
<>	144:ef7eb2e8f9f7	962	/**
<>	144:ef7eb2e8f9f7	963	* @}
<>	144:ef7eb2e8f9f7	964	*/
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	967	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	968	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	969	* power consumption.
<>	144:ef7eb2e8f9f7	970	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	971	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	972	* @{
<>	144:ef7eb2e8f9f7	973	*/
<>	144:ef7eb2e8f9f7	974
<>	144:ef7eb2e8f9f7	975	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
<>	144:ef7eb2e8f9f7	976	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
<>	144:ef7eb2e8f9f7	977	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
<>	144:ef7eb2e8f9f7	978	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
<>	144:ef7eb2e8f9f7	981	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
<>	144:ef7eb2e8f9f7	982	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
<>	144:ef7eb2e8f9f7	983	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
<>	144:ef7eb2e8f9f7	984	/**
<>	144:ef7eb2e8f9f7	985	* @}
<>	144:ef7eb2e8f9f7	986	*/
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	989	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	990	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	991	* power consumption.
<>	144:ef7eb2e8f9f7	992	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	993	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	994	* @{
<>	144:ef7eb2e8f9f7	995	*/
<>	144:ef7eb2e8f9f7	996	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
<>	144:ef7eb2e8f9f7	997	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
<>	144:ef7eb2e8f9f7	1000	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
<>	144:ef7eb2e8f9f7	1001
<>	144:ef7eb2e8f9f7	1002	/**
<>	144:ef7eb2e8f9f7	1003	* @}
<>	144:ef7eb2e8f9f7	1004	*/
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	1007	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1008	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1009	* power consumption.
<>	144:ef7eb2e8f9f7	1010	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1011	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1012	* @{
<>	144:ef7eb2e8f9f7	1013	*/
<>	144:ef7eb2e8f9f7	1014	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
<>	144:ef7eb2e8f9f7	1015	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
<>	144:ef7eb2e8f9f7	1016
<>	144:ef7eb2e8f9f7	1017	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
<>	144:ef7eb2e8f9f7	1018	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/**
<>	144:ef7eb2e8f9f7	1021	* @}
<>	144:ef7eb2e8f9f7	1022	*/
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1025	* @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	1026	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1027	* power consumption.
<>	144:ef7eb2e8f9f7	1028	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1029	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1030	* @{
<>	144:ef7eb2e8f9f7	1031	*/
<>	144:ef7eb2e8f9f7	1032	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	1033	#define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET)
<>	144:ef7eb2e8f9f7	1034	#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
<>	144:ef7eb2e8f9f7	1035	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1036	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1037	#define __HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1038	#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1039	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET)
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	/**
<>	144:ef7eb2e8f9f7	1042	* @}
<>	144:ef7eb2e8f9f7	1043	*/
<>	144:ef7eb2e8f9f7	1044
<>	144:ef7eb2e8f9f7	1045	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1046	* @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	1047	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1048	* power consumption.
<>	144:ef7eb2e8f9f7	1049	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1050	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1051	* @{
<>	144:ef7eb2e8f9f7	1052	*/
<>	144:ef7eb2e8f9f7	1053	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET)
<>	144:ef7eb2e8f9f7	1054	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET)
<>	144:ef7eb2e8f9f7	1055	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	1056	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1057	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1058	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1059	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1060	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == RESET)
<>	144:ef7eb2e8f9f7	1061
<>	144:ef7eb2e8f9f7	1062	/**
<>	144:ef7eb2e8f9f7	1063	* @}
<>	144:ef7eb2e8f9f7	1064	*/
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1067	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	1068	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1069	* power consumption.
<>	144:ef7eb2e8f9f7	1070	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1071	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1072	* @{
<>	144:ef7eb2e8f9f7	1073	*/
<>	144:ef7eb2e8f9f7	1074	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	1075	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1076	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1077	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == RESET)
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079	/**
<>	144:ef7eb2e8f9f7	1080	* @}
<>	144:ef7eb2e8f9f7	1081	*/
<>	144:ef7eb2e8f9f7	1082
<>	144:ef7eb2e8f9f7	1083	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	1084	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	1085	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1086	* power consumption.
<>	144:ef7eb2e8f9f7	1087	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1088	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1089	* @{
<>	144:ef7eb2e8f9f7	1090	*/
<>	144:ef7eb2e8f9f7	1091	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	1092	#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET)
Anna Bridge	186:707f6e361f3e	1093	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
Anna Bridge	186:707f6e361f3e	1094	#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == RESET)
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	/**
<>	144:ef7eb2e8f9f7	1097	* @}
<>	144:ef7eb2e8f9f7	1098	*/
Anna Bridge	186:707f6e361f3e	1099	/** @defgroup RCC_HSI_Configuration HSI Configuration
<>	144:ef7eb2e8f9f7	1100	* @{
<>	144:ef7eb2e8f9f7	1101	*/
<>	144:ef7eb2e8f9f7	1102
Anna Bridge	186:707f6e361f3e	1103	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
Anna Bridge	186:707f6e361f3e	1104	* @note After enabling the HSI, the application software should wait on
Anna Bridge	186:707f6e361f3e	1105	* HSIRDY flag to be set indicating that HSI clock is stable and can
Anna Bridge	186:707f6e361f3e	1106	* be used to clock the PLL and/or system clock.
Anna Bridge	186:707f6e361f3e	1107	* @note HSI can not be stopped if it is used directly or through the PLL
Anna Bridge	186:707f6e361f3e	1108	* as system clock. In this case, you have to select another source
Anna Bridge	186:707f6e361f3e	1109	* of the system clock then stop the HSI.
Anna Bridge	186:707f6e361f3e	1110	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Anna Bridge	186:707f6e361f3e	1111	* @param __STATE__ specifies the new state of the HSI.
Anna Bridge	186:707f6e361f3e	1112	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1113	* @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator
Anna Bridge	186:707f6e361f3e	1114	* @arg @ref RCC_HSI_ON turn ON the HSI oscillator
Anna Bridge	186:707f6e361f3e	1115	* @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
Anna Bridge	186:707f6e361f3e	1116	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Anna Bridge	186:707f6e361f3e	1117	* clock cycles.
<>	144:ef7eb2e8f9f7	1118	*/
Anna Bridge	186:707f6e361f3e	1119	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
Anna Bridge	186:707f6e361f3e	1120	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<>	144:ef7eb2e8f9f7	1123	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1124	* It is used (enabled by hardware) as system clock source after startup
<>	144:ef7eb2e8f9f7	1125	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
<>	144:ef7eb2e8f9f7	1126	* of the HSE used directly or indirectly as system clock (if the Clock
<>	144:ef7eb2e8f9f7	1127	* Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	1128	* @note HSI can not be stopped if it is used as system clock source. In this case,
<>	144:ef7eb2e8f9f7	1129	* you have to select another source of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	1130	* @note After enabling the HSI, the application software should wait on HSIRDY
<>	144:ef7eb2e8f9f7	1131	* flag to be set indicating that HSI clock is stable and can be used as
Anna Bridge	186:707f6e361f3e	1132	* system clock source.
<>	144:ef7eb2e8f9f7	1133	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	1134	* clock cycles.
<>	144:ef7eb2e8f9f7	1135	*/
<>	144:ef7eb2e8f9f7	1136	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
<>	144:ef7eb2e8f9f7	1137	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<>	144:ef7eb2e8f9f7	1140	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	1141	* and temperature that influence the frequency of the internal HSI RC.
Anna Bridge	186:707f6e361f3e	1142	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
Anna Bridge	186:707f6e361f3e	1143	* (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	1144	* This parameter must be a number between 0 and 0x1F.
Anna Bridge	186:707f6e361f3e	1145	*/
Anna Bridge	186:707f6e361f3e	1146	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Anna Bridge	186:707f6e361f3e	1147	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << 8))
<>	144:ef7eb2e8f9f7	1148
<>	144:ef7eb2e8f9f7	1149	/**
Anna Bridge	186:707f6e361f3e	1150	* @}
<>	144:ef7eb2e8f9f7	1151	*/
<>	144:ef7eb2e8f9f7	1152
Anna Bridge	186:707f6e361f3e	1153	/** @defgroup RCC_LSI_Configuration LSI Configuration
Anna Bridge	186:707f6e361f3e	1154	* @{
<>	144:ef7eb2e8f9f7	1155	*/
<>	144:ef7eb2e8f9f7	1156
Anna Bridge	186:707f6e361f3e	1157	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	1158	* @note After enabling the LSI, the application software should wait on
<>	144:ef7eb2e8f9f7	1159	* LSIRDY flag to be set indicating that LSI clock is stable and can
<>	144:ef7eb2e8f9f7	1160	* be used to clock the IWDG and/or the RTC.
Anna Bridge	186:707f6e361f3e	1161	*/
Anna Bridge	186:707f6e361f3e	1162	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Anna Bridge	186:707f6e361f3e	1163
Anna Bridge	186:707f6e361f3e	1164	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
Anna Bridge	186:707f6e361f3e	1165	* @note LSI can not be disabled if the IWDG is running.
<>	144:ef7eb2e8f9f7	1166	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<>	144:ef7eb2e8f9f7	1167	* clock cycles.
<>	144:ef7eb2e8f9f7	1168	*/
<>	144:ef7eb2e8f9f7	1169	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
<>	144:ef7eb2e8f9f7	1170
<>	144:ef7eb2e8f9f7	1171	/**
Anna Bridge	186:707f6e361f3e	1172	* @}
Anna Bridge	186:707f6e361f3e	1173	*/
Anna Bridge	186:707f6e361f3e	1174
Anna Bridge	186:707f6e361f3e	1175	/** @defgroup RCC_HSE_Configuration HSE Configuration
Anna Bridge	186:707f6e361f3e	1176	* @{
Anna Bridge	186:707f6e361f3e	1177	*/
Anna Bridge	186:707f6e361f3e	1178
Anna Bridge	186:707f6e361f3e	1179	/**
<>	144:ef7eb2e8f9f7	1180	* @brief Macro to configure the External High Speed oscillator (HSE).
<>	144:ef7eb2e8f9f7	1181	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<>	144:ef7eb2e8f9f7	1182	* supported by this macro. User should request a transition to HSE Off
<>	144:ef7eb2e8f9f7	1183	* first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	1184	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<>	144:ef7eb2e8f9f7	1185	* software should wait on HSERDY flag to be set indicating that HSE clock
<>	144:ef7eb2e8f9f7	1186	* is stable and can be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	1187	* @note HSE state can not be changed if it is used directly or through the
<>	144:ef7eb2e8f9f7	1188	* PLL as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	1189	* of the system clock then change the HSE state (ex. disable it).
Anna Bridge	186:707f6e361f3e	1190	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1191	* @note This function reset the CSSON bit, so if the clock security system(CSS)
<>	144:ef7eb2e8f9f7	1192	* was previously enabled you have to enable it again after calling this
Anna Bridge	186:707f6e361f3e	1193	* function.
Anna Bridge	186:707f6e361f3e	1194	* @param __STATE__ specifies the new state of the HSE.
Anna Bridge	186:707f6e361f3e	1195	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1196	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
<>	144:ef7eb2e8f9f7	1197	* 6 HSE oscillator clock cycles.
Anna Bridge	186:707f6e361f3e	1198	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
Anna Bridge	186:707f6e361f3e	1199	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
<>	144:ef7eb2e8f9f7	1200	*/
Anna Bridge	186:707f6e361f3e	1201	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Anna Bridge	186:707f6e361f3e	1202	do{ \
Anna Bridge	186:707f6e361f3e	1203	__IO uint32_t tmpreg; \
Anna Bridge	186:707f6e361f3e	1204	if ((__STATE__) == RCC_HSE_ON) \
Anna Bridge	186:707f6e361f3e	1205	{ \
Anna Bridge	186:707f6e361f3e	1206	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Anna Bridge	186:707f6e361f3e	1207	} \
Anna Bridge	186:707f6e361f3e	1208	else if ((__STATE__) == RCC_HSE_BYPASS) \
Anna Bridge	186:707f6e361f3e	1209	{ \
Anna Bridge	186:707f6e361f3e	1210	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Anna Bridge	186:707f6e361f3e	1211	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Anna Bridge	186:707f6e361f3e	1212	} \
Anna Bridge	186:707f6e361f3e	1213	else \
Anna Bridge	186:707f6e361f3e	1214	{ \
Anna Bridge	186:707f6e361f3e	1215	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Anna Bridge	186:707f6e361f3e	1216	/* Delay after an RCC peripheral clock */ \
Anna Bridge	186:707f6e361f3e	1217	tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
Anna Bridge	186:707f6e361f3e	1218	UNUSED(tmpreg); \
Anna Bridge	186:707f6e361f3e	1219	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Anna Bridge	186:707f6e361f3e	1220	} \
Anna Bridge	186:707f6e361f3e	1221	}while(0)
Anna Bridge	186:707f6e361f3e	1222
Anna Bridge	186:707f6e361f3e	1223	/**
Anna Bridge	186:707f6e361f3e	1224	* @}
Anna Bridge	186:707f6e361f3e	1225	*/
Anna Bridge	186:707f6e361f3e	1226
Anna Bridge	186:707f6e361f3e	1227	/** @defgroup RCC_LSE_Configuration LSE Configuration
Anna Bridge	186:707f6e361f3e	1228	* @{
Anna Bridge	186:707f6e361f3e	1229	*/
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	/**
<>	144:ef7eb2e8f9f7	1232	* @brief Macro to configure the External Low Speed oscillator (LSE).
Anna Bridge	186:707f6e361f3e	1233	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
<>	144:ef7eb2e8f9f7	1234	* @note As the LSE is in the Backup domain and write access is denied to
Anna Bridge	186:707f6e361f3e	1235	* this domain after reset, you have to enable write access using
Anna Bridge	186:707f6e361f3e	1236	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Anna Bridge	186:707f6e361f3e	1237	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	1238	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<>	144:ef7eb2e8f9f7	1239	* software should wait on LSERDY flag to be set indicating that LSE clock
<>	144:ef7eb2e8f9f7	1240	* is stable and can be used to clock the RTC.
Anna Bridge	186:707f6e361f3e	1241	* @param __STATE__ specifies the new state of the LSE.
<>	144:ef7eb2e8f9f7	1242	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1243	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
<>	144:ef7eb2e8f9f7	1244	* 6 LSE oscillator clock cycles.
Anna Bridge	186:707f6e361f3e	1245	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
Anna Bridge	186:707f6e361f3e	1246	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	1247	*/
Anna Bridge	186:707f6e361f3e	1248	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Anna Bridge	186:707f6e361f3e	1249	do{ \
Anna Bridge	186:707f6e361f3e	1250	if ((__STATE__) == RCC_LSE_ON) \
Anna Bridge	186:707f6e361f3e	1251	{ \
Anna Bridge	186:707f6e361f3e	1252	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Anna Bridge	186:707f6e361f3e	1253	} \
Anna Bridge	186:707f6e361f3e	1254	else if ((__STATE__) == RCC_LSE_OFF) \
Anna Bridge	186:707f6e361f3e	1255	{ \
Anna Bridge	186:707f6e361f3e	1256	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Anna Bridge	186:707f6e361f3e	1257	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Anna Bridge	186:707f6e361f3e	1258	} \
Anna Bridge	186:707f6e361f3e	1259	else if ((__STATE__) == RCC_LSE_BYPASS) \
Anna Bridge	186:707f6e361f3e	1260	{ \
Anna Bridge	186:707f6e361f3e	1261	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Anna Bridge	186:707f6e361f3e	1262	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Anna Bridge	186:707f6e361f3e	1263	} \
Anna Bridge	186:707f6e361f3e	1264	else \
Anna Bridge	186:707f6e361f3e	1265	{ \
Anna Bridge	186:707f6e361f3e	1266	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Anna Bridge	186:707f6e361f3e	1267	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Anna Bridge	186:707f6e361f3e	1268	} \
Anna Bridge	186:707f6e361f3e	1269	}while(0)
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	/**
Anna Bridge	186:707f6e361f3e	1272	* @}
Anna Bridge	186:707f6e361f3e	1273	*/
Anna Bridge	186:707f6e361f3e	1274
Anna Bridge	186:707f6e361f3e	1275	/** @defgroup RCC_MSI_Configuration MSI Configuration
Anna Bridge	186:707f6e361f3e	1276	* @{
Anna Bridge	186:707f6e361f3e	1277	*/
Anna Bridge	186:707f6e361f3e	1278
Anna Bridge	186:707f6e361f3e	1279	/** @brief Macro to enable Internal Multi Speed oscillator (MSI).
Anna Bridge	186:707f6e361f3e	1280	* @note After enabling the MSI, the application software should wait on MSIRDY
Anna Bridge	186:707f6e361f3e	1281	* flag to be set indicating that MSI clock is stable and can be used as
Anna Bridge	186:707f6e361f3e	1282	* system clock source.
<>	144:ef7eb2e8f9f7	1283	*/
Anna Bridge	186:707f6e361f3e	1284	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Anna Bridge	186:707f6e361f3e	1285
Anna Bridge	186:707f6e361f3e	1286	/** @brief Macro to disable the Internal Multi Speed oscillator (MSI).
Anna Bridge	186:707f6e361f3e	1287	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Anna Bridge	186:707f6e361f3e	1288	* It is used (enabled by hardware) as system clock source after startup
Anna Bridge	186:707f6e361f3e	1289	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Anna Bridge	186:707f6e361f3e	1290	* of the HSE used directly or indirectly as system clock (if the Clock
Anna Bridge	186:707f6e361f3e	1291	* Security System CSS is enabled).
Anna Bridge	186:707f6e361f3e	1292	* @note MSI can not be stopped if it is used as system clock source. In this case,
Anna Bridge	186:707f6e361f3e	1293	* you have to select another source of the system clock then stop the MSI.
Anna Bridge	186:707f6e361f3e	1294	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Anna Bridge	186:707f6e361f3e	1295	* clock cycles.
Anna Bridge	186:707f6e361f3e	1296	*/
Anna Bridge	186:707f6e361f3e	1297	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
<>	144:ef7eb2e8f9f7	1298
Anna Bridge	186:707f6e361f3e	1299	/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
Anna Bridge	186:707f6e361f3e	1300	* @note The calibration is used to compensate for the variations in voltage
Anna Bridge	186:707f6e361f3e	1301	* and temperature that influence the frequency of the internal MSI RC.
Anna Bridge	186:707f6e361f3e	1302	* Refer to the Application Note AN3300 for more details on how to
Anna Bridge	186:707f6e361f3e	1303	* calibrate the MSI.
Anna Bridge	186:707f6e361f3e	1304	* @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
Anna Bridge	186:707f6e361f3e	1305	* (default is RCC_MSICALIBRATION_DEFAULT).
Anna Bridge	186:707f6e361f3e	1306	* This parameter must be a number between 0 and 0xFF.
Anna Bridge	186:707f6e361f3e	1307	*/
Anna Bridge	186:707f6e361f3e	1308	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
Anna Bridge	186:707f6e361f3e	1309	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << 24))
Anna Bridge	186:707f6e361f3e	1310
Anna Bridge	186:707f6e361f3e	1311	/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
Anna Bridge	186:707f6e361f3e	1312	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
Anna Bridge	186:707f6e361f3e	1313	* around 2.097 MHz. The MSI clock does not change after wake-up from
Anna Bridge	186:707f6e361f3e	1314	* STOP mode.
Anna Bridge	186:707f6e361f3e	1315	* @note The MSI clock range can be modified on the fly.
Anna Bridge	186:707f6e361f3e	1316	* @param _MSIRANGEVALUE_ specifies the MSI Clock range.
Anna Bridge	186:707f6e361f3e	1317	* This parameter must be one of the following values:
Anna Bridge	186:707f6e361f3e	1318	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
Anna Bridge	186:707f6e361f3e	1319	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
Anna Bridge	186:707f6e361f3e	1320	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
Anna Bridge	186:707f6e361f3e	1321	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
Anna Bridge	186:707f6e361f3e	1322	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
Anna Bridge	186:707f6e361f3e	1323	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
Anna Bridge	186:707f6e361f3e	1324	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
Anna Bridge	186:707f6e361f3e	1325	*/
Anna Bridge	186:707f6e361f3e	1326	#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
Anna Bridge	186:707f6e361f3e	1327	RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
<>	144:ef7eb2e8f9f7	1328
Anna Bridge	186:707f6e361f3e	1329	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
Anna Bridge	186:707f6e361f3e	1330	* @retval MSI clock range.
Anna Bridge	186:707f6e361f3e	1331	* This parameter must be one of the following values:
Anna Bridge	186:707f6e361f3e	1332	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
Anna Bridge	186:707f6e361f3e	1333	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
Anna Bridge	186:707f6e361f3e	1334	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
Anna Bridge	186:707f6e361f3e	1335	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
Anna Bridge	186:707f6e361f3e	1336	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
Anna Bridge	186:707f6e361f3e	1337	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
Anna Bridge	186:707f6e361f3e	1338	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
<>	144:ef7eb2e8f9f7	1339	*/
Anna Bridge	186:707f6e361f3e	1340	#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
Anna Bridge	186:707f6e361f3e	1341
Anna Bridge	186:707f6e361f3e	1342	/**
Anna Bridge	186:707f6e361f3e	1343	* @}
Anna Bridge	186:707f6e361f3e	1344	*/
<>	144:ef7eb2e8f9f7	1345
Anna Bridge	186:707f6e361f3e	1346	/** @defgroup RCC_PLL_Configuration PLL Configuration
Anna Bridge	186:707f6e361f3e	1347	* @{
Anna Bridge	186:707f6e361f3e	1348	*/
Anna Bridge	186:707f6e361f3e	1349
Anna Bridge	186:707f6e361f3e	1350	/** @brief Macro to enable the main PLL.
<>	144:ef7eb2e8f9f7	1351	* @note After enabling the main PLL, the application software should wait on
<>	144:ef7eb2e8f9f7	1352	* PLLRDY flag to be set indicating that PLL clock is stable and can
<>	144:ef7eb2e8f9f7	1353	* be used as system clock source.
<>	144:ef7eb2e8f9f7	1354	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1355	*/
Anna Bridge	186:707f6e361f3e	1356	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Anna Bridge	186:707f6e361f3e	1357
Anna Bridge	186:707f6e361f3e	1358	/** @brief Macro to disable the main PLL.
Anna Bridge	186:707f6e361f3e	1359	* @note The main PLL can not be disabled if it is used as system clock source
Anna Bridge	186:707f6e361f3e	1360	*/
<>	144:ef7eb2e8f9f7	1361	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	1362
Anna Bridge	186:707f6e361f3e	1363	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<>	144:ef7eb2e8f9f7	1364	* @note This function must be used only when the main PLL is disabled.
Anna Bridge	186:707f6e361f3e	1365	*
Anna Bridge	186:707f6e361f3e	1366	* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
Anna Bridge	186:707f6e361f3e	1367	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1368	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Anna Bridge	186:707f6e361f3e	1369	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Anna Bridge	186:707f6e361f3e	1370	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
Anna Bridge	186:707f6e361f3e	1371	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1372	* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
Anna Bridge	186:707f6e361f3e	1373	* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
Anna Bridge	186:707f6e361f3e	1374	* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
Anna Bridge	186:707f6e361f3e	1375	* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
Anna Bridge	186:707f6e361f3e	1376	* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
Anna Bridge	186:707f6e361f3e	1377	* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
Anna Bridge	186:707f6e361f3e	1378	* @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24
Anna Bridge	186:707f6e361f3e	1379	* @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32
Anna Bridge	186:707f6e361f3e	1380	* @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48
Anna Bridge	186:707f6e361f3e	1381	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
Anna Bridge	186:707f6e361f3e	1382	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
Anna Bridge	186:707f6e361f3e	1383	* in Range 3.
Anna Bridge	186:707f6e361f3e	1384	*
Anna Bridge	186:707f6e361f3e	1385	* @param __PLLDIV__ specifies the division factor for PLL VCO input clock
Anna Bridge	186:707f6e361f3e	1386	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1387	* @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
Anna Bridge	186:707f6e361f3e	1388	* @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
Anna Bridge	186:707f6e361f3e	1389	* @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
Anna Bridge	186:707f6e361f3e	1390	*
Anna Bridge	186:707f6e361f3e	1391	*/
Anna Bridge	186:707f6e361f3e	1392	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
Anna Bridge	186:707f6e361f3e	1393	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC\|RCC_CFGR_PLLMUL\|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) \| (__PLLMUL__) \| (__PLLDIV__)))
Anna Bridge	186:707f6e361f3e	1394
Anna Bridge	186:707f6e361f3e	1395	/** @brief Get oscillator clock selected as PLL input clock
Anna Bridge	186:707f6e361f3e	1396	* @retval The clock source used for PLL entry. The returned value can be one
Anna Bridge	186:707f6e361f3e	1397	* of the following:
Anna Bridge	186:707f6e361f3e	1398	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
Anna Bridge	186:707f6e361f3e	1399	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
Anna Bridge	186:707f6e361f3e	1400	*/
Anna Bridge	186:707f6e361f3e	1401	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Anna Bridge	186:707f6e361f3e	1402
Anna Bridge	186:707f6e361f3e	1403	/**
Anna Bridge	186:707f6e361f3e	1404	* @}
<>	144:ef7eb2e8f9f7	1405	*/
<>	144:ef7eb2e8f9f7	1406
Anna Bridge	186:707f6e361f3e	1407	/** @defgroup RCC_Get_Clock_source Get Clock source
Anna Bridge	186:707f6e361f3e	1408	* @{
<>	144:ef7eb2e8f9f7	1409	*/
<>	144:ef7eb2e8f9f7	1410
<>	144:ef7eb2e8f9f7	1411	/**
<>	144:ef7eb2e8f9f7	1412	* @brief Macro to configure the system clock source.
Anna Bridge	186:707f6e361f3e	1413	* @param __SYSCLKSOURCE__ specifies the system clock source.
<>	144:ef7eb2e8f9f7	1414	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1415	* @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
Anna Bridge	186:707f6e361f3e	1416	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
Anna Bridge	186:707f6e361f3e	1417	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
Anna Bridge	186:707f6e361f3e	1418	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
<>	144:ef7eb2e8f9f7	1419	*/
<>	144:ef7eb2e8f9f7	1420	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1421	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
<>	144:ef7eb2e8f9f7	1422
<>	144:ef7eb2e8f9f7	1423	/** @brief Macro to get the clock source used as system clock.
<>	144:ef7eb2e8f9f7	1424	* @retval The clock source used as system clock. The returned value can be one
<>	144:ef7eb2e8f9f7	1425	* of the following:
Anna Bridge	186:707f6e361f3e	1426	* @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
Anna Bridge	186:707f6e361f3e	1427	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
Anna Bridge	186:707f6e361f3e	1428	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
Anna Bridge	186:707f6e361f3e	1429	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
<>	144:ef7eb2e8f9f7	1430	*/
Anna Bridge	186:707f6e361f3e	1431	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
<>	144:ef7eb2e8f9f7	1432
Anna Bridge	186:707f6e361f3e	1433	/**
Anna Bridge	186:707f6e361f3e	1434	* @}
Anna Bridge	186:707f6e361f3e	1435	*/
Anna Bridge	186:707f6e361f3e	1436
Anna Bridge	186:707f6e361f3e	1437	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Anna Bridge	186:707f6e361f3e	1438	* @{
Anna Bridge	186:707f6e361f3e	1439	*/
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	/** @brief Macro to configure the MCO clock.
<>	144:ef7eb2e8f9f7	1442	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	1443	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1444	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1445	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1446	* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1447	* @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1448	* @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1449	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1450	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1451	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1452	@if STM32L052xx
Anna Bridge	186:707f6e361f3e	1453	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1454	@elseif STM32L053xx
Anna Bridge	186:707f6e361f3e	1455	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1456	@elseif STM32L062xx
Anna Bridge	186:707f6e361f3e	1457	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1458	@elseif STM32L063xx
Anna Bridge	186:707f6e361f3e	1459	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1460	@elseif STM32L072xx
Anna Bridge	186:707f6e361f3e	1461	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1462	@elseif STM32L073xx
Anna Bridge	186:707f6e361f3e	1463	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1464	@elseif STM32L082xx
Anna Bridge	186:707f6e361f3e	1465	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1466	@elseif STM32L083xx
Anna Bridge	186:707f6e361f3e	1467	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge	186:707f6e361f3e	1468	@endif
<>	144:ef7eb2e8f9f7	1469	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	1470	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1471	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
Anna Bridge	186:707f6e361f3e	1472	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
Anna Bridge	186:707f6e361f3e	1473	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
Anna Bridge	186:707f6e361f3e	1474	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
Anna Bridge	186:707f6e361f3e	1475	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
<>	144:ef7eb2e8f9f7	1476	*/
<>	144:ef7eb2e8f9f7	1477	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1478	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
<>	144:ef7eb2e8f9f7	1479
Anna Bridge	186:707f6e361f3e	1480	/**
Anna Bridge	186:707f6e361f3e	1481	* @}
Anna Bridge	186:707f6e361f3e	1482	*/
<>	144:ef7eb2e8f9f7	1483
Anna Bridge	186:707f6e361f3e	1484	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Anna Bridge	186:707f6e361f3e	1485	* @{
Anna Bridge	186:707f6e361f3e	1486	*/
Anna Bridge	186:707f6e361f3e	1487
Anna Bridge	186:707f6e361f3e	1488	/** @brief Macro to configure the RTC clock (RTCCLK).
Anna Bridge	186:707f6e361f3e	1489	* @note As the RTC clock configuration bits are in the Backup domain and write
Anna Bridge	186:707f6e361f3e	1490	* access is denied to this domain after reset, you have to enable write
Anna Bridge	186:707f6e361f3e	1491	* access using the Power Backup Access macro before to configure
Anna Bridge	186:707f6e361f3e	1492	* the RTC clock source (to be done once after reset).
Anna Bridge	186:707f6e361f3e	1493	* @note Once the RTC clock is configured it cannot be changed unless the
Anna Bridge	186:707f6e361f3e	1494	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Anna Bridge	186:707f6e361f3e	1495	* a Power On Reset (POR).
Anna Bridge	186:707f6e361f3e	1496	* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
Anna Bridge	186:707f6e361f3e	1497	*
Anna Bridge	186:707f6e361f3e	1498	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
Anna Bridge	186:707f6e361f3e	1499	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1500	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Anna Bridge	186:707f6e361f3e	1501	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Anna Bridge	186:707f6e361f3e	1502	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Anna Bridge	186:707f6e361f3e	1503	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1504	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1505	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1506	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1507	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Anna Bridge	186:707f6e361f3e	1508	* work in STOP and STANDBY modes, and can be used as wakeup source.
Anna Bridge	186:707f6e361f3e	1509	* However, when the HSE clock is used as RTC clock source, the RTC
Anna Bridge	186:707f6e361f3e	1510	* cannot be used in STOP and STANDBY modes.
Anna Bridge	186:707f6e361f3e	1511	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Anna Bridge	186:707f6e361f3e	1512	* RTC clock source).
Anna Bridge	186:707f6e361f3e	1513	*/
Anna Bridge	186:707f6e361f3e	1514	#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
Anna Bridge	186:707f6e361f3e	1515	if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
Anna Bridge	186:707f6e361f3e	1516	{ \
Anna Bridge	186:707f6e361f3e	1517	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
Anna Bridge	186:707f6e361f3e	1518	} \
Anna Bridge	186:707f6e361f3e	1519	} while (0)
Anna Bridge	186:707f6e361f3e	1520
Anna Bridge	186:707f6e361f3e	1521	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
Anna Bridge	186:707f6e361f3e	1522	__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
Anna Bridge	186:707f6e361f3e	1523	RCC->CSR \|= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
Anna Bridge	186:707f6e361f3e	1524	} while (0)
Anna Bridge	186:707f6e361f3e	1525
Anna Bridge	186:707f6e361f3e	1526	/** @brief Macro to get the RTC clock source.
Anna Bridge	186:707f6e361f3e	1527	* @retval The clock source can be one of the following values:
Anna Bridge	186:707f6e361f3e	1528	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Anna Bridge	186:707f6e361f3e	1529	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Anna Bridge	186:707f6e361f3e	1530	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Anna Bridge	186:707f6e361f3e	1531	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
Anna Bridge	186:707f6e361f3e	1532	*/
Anna Bridge	186:707f6e361f3e	1533	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
Anna Bridge	186:707f6e361f3e	1534
Anna Bridge	186:707f6e361f3e	1535	/**
Anna Bridge	186:707f6e361f3e	1536	* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
Anna Bridge	186:707f6e361f3e	1537	*
Anna Bridge	186:707f6e361f3e	1538	* @retval Returned value can be one of the following values:
Anna Bridge	186:707f6e361f3e	1539	* @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1540	* @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1541	* @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1542	* @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
Anna Bridge	186:707f6e361f3e	1543	*
Anna Bridge	186:707f6e361f3e	1544	*/
Anna Bridge	186:707f6e361f3e	1545	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
Anna Bridge	186:707f6e361f3e	1546
Anna Bridge	186:707f6e361f3e	1547	/** @brief Macro to enable the the RTC clock.
Anna Bridge	186:707f6e361f3e	1548	* @note These macros must be used only after the RTC clock source was selected.
Anna Bridge	186:707f6e361f3e	1549	*/
Anna Bridge	186:707f6e361f3e	1550	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
Anna Bridge	186:707f6e361f3e	1551
Anna Bridge	186:707f6e361f3e	1552	/** @brief Macro to disable the the RTC clock.
Anna Bridge	186:707f6e361f3e	1553	* @note These macros must be used only after the RTC clock source was selected.
Anna Bridge	186:707f6e361f3e	1554	*/
Anna Bridge	186:707f6e361f3e	1555	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
Anna Bridge	186:707f6e361f3e	1556
Anna Bridge	186:707f6e361f3e	1557	/** @brief Macro to force the Backup domain reset.
Anna Bridge	186:707f6e361f3e	1558	* @note This function resets the RTC peripheral (including the backup registers)
Anna Bridge	186:707f6e361f3e	1559	* and the RTC clock source selection in RCC_CSR register.
Anna Bridge	186:707f6e361f3e	1560	* @note The BKPSRAM is not affected by this reset.
Anna Bridge	186:707f6e361f3e	1561	*/
Anna Bridge	186:707f6e361f3e	1562	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
Anna Bridge	186:707f6e361f3e	1563
Anna Bridge	186:707f6e361f3e	1564	/** @brief Macros to release the Backup domain reset.
Anna Bridge	186:707f6e361f3e	1565	*/
Anna Bridge	186:707f6e361f3e	1566	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
Anna Bridge	186:707f6e361f3e	1567
Anna Bridge	186:707f6e361f3e	1568	/**
Anna Bridge	186:707f6e361f3e	1569	* @}
Anna Bridge	186:707f6e361f3e	1570	*/
Anna Bridge	186:707f6e361f3e	1571
Anna Bridge	186:707f6e361f3e	1572	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<>	144:ef7eb2e8f9f7	1573	* @brief macros to manage the specified RCC Flags and interrupts.
<>	144:ef7eb2e8f9f7	1574	* @{
<>	144:ef7eb2e8f9f7	1575	*/
<>	144:ef7eb2e8f9f7	1576
Anna Bridge	186:707f6e361f3e	1577	/** @brief Enable RCC interrupt.
<>	144:ef7eb2e8f9f7	1578	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
<>	144:ef7eb2e8f9f7	1579	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
<>	144:ef7eb2e8f9f7	1580	* automatically generated. The NMI will be executed indefinitely, and
<>	144:ef7eb2e8f9f7	1581	* since NMI has higher priority than any other IRQ (and main program)
<>	144:ef7eb2e8f9f7	1582	* the application will be stacked in the NMI ISR unless the CSS interrupt
<>	144:ef7eb2e8f9f7	1583	* pending bit is cleared.
Anna Bridge	186:707f6e361f3e	1584	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
Anna Bridge	186:707f6e361f3e	1585	* This parameter can be any combination of the following values:
Anna Bridge	186:707f6e361f3e	1586	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Anna Bridge	186:707f6e361f3e	1587	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
Anna Bridge	186:707f6e361f3e	1588	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Anna Bridge	186:707f6e361f3e	1589	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
Anna Bridge	186:707f6e361f3e	1590	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
Anna Bridge	186:707f6e361f3e	1591	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Anna Bridge	186:707f6e361f3e	1592	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
Anna Bridge	186:707f6e361f3e	1593	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
<>	144:ef7eb2e8f9f7	1594	*/
<>	144:ef7eb2e8f9f7	1595	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1596
Anna Bridge	186:707f6e361f3e	1597	/** @brief Disable RCC interrupt.
<>	144:ef7eb2e8f9f7	1598	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
<>	144:ef7eb2e8f9f7	1599	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
<>	144:ef7eb2e8f9f7	1600	* automatically generated. The NMI will be executed indefinitely, and
<>	144:ef7eb2e8f9f7	1601	* since NMI has higher priority than any other IRQ (and main program)
<>	144:ef7eb2e8f9f7	1602	* the application will be stacked in the NMI ISR unless the CSS interrupt
Anna Bridge	186:707f6e361f3e	1603	* pending bit is cleared.
Anna Bridge	186:707f6e361f3e	1604	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
Anna Bridge	186:707f6e361f3e	1605	* This parameter can be any combination of the following values:
Anna Bridge	186:707f6e361f3e	1606	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Anna Bridge	186:707f6e361f3e	1607	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
Anna Bridge	186:707f6e361f3e	1608	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Anna Bridge	186:707f6e361f3e	1609	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
Anna Bridge	186:707f6e361f3e	1610	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
Anna Bridge	186:707f6e361f3e	1611	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Anna Bridge	186:707f6e361f3e	1612	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
Anna Bridge	186:707f6e361f3e	1613	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
<>	144:ef7eb2e8f9f7	1614	*/
<>	144:ef7eb2e8f9f7	1615	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1616
Anna Bridge	186:707f6e361f3e	1617	/** @brief Clear the RCC's interrupt pending bits.
Anna Bridge	186:707f6e361f3e	1618	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
Anna Bridge	186:707f6e361f3e	1619	* This parameter can be any combination of the following values:
Anna Bridge	186:707f6e361f3e	1620	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
Anna Bridge	186:707f6e361f3e	1621	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
Anna Bridge	186:707f6e361f3e	1622	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
Anna Bridge	186:707f6e361f3e	1623	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
Anna Bridge	186:707f6e361f3e	1624	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
Anna Bridge	186:707f6e361f3e	1625	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Anna Bridge	186:707f6e361f3e	1626	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
Anna Bridge	186:707f6e361f3e	1627	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
Anna Bridge	186:707f6e361f3e	1628	* @arg @ref RCC_IT_CSS Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1629	*/
Anna Bridge	186:707f6e361f3e	1630	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	/** @brief Check the RCC's interrupt has occurred or not.
Anna Bridge	186:707f6e361f3e	1633	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
<>	144:ef7eb2e8f9f7	1634	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1635	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Anna Bridge	186:707f6e361f3e	1636	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
Anna Bridge	186:707f6e361f3e	1637	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Anna Bridge	186:707f6e361f3e	1638	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
Anna Bridge	186:707f6e361f3e	1639	* @arg @ref RCC_IT_PLLRDY PLL ready interrupt
Anna Bridge	186:707f6e361f3e	1640	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Anna Bridge	186:707f6e361f3e	1641	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
Anna Bridge	186:707f6e361f3e	1642	* @arg @ref RCC_IT_CSS Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1643	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1644	*/
<>	144:ef7eb2e8f9f7	1645	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1646
<>	144:ef7eb2e8f9f7	1647
<>	144:ef7eb2e8f9f7	1648	/** @brief Set RMVF bit to clear the reset flags.
Anna Bridge	186:707f6e361f3e	1649	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Anna Bridge	186:707f6e361f3e	1650	* RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
<>	144:ef7eb2e8f9f7	1651	*/
<>	144:ef7eb2e8f9f7	1652	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
<>	144:ef7eb2e8f9f7	1653
<>	144:ef7eb2e8f9f7	1654	/** @brief Check RCC flag is set or not.
Anna Bridge	186:707f6e361f3e	1655	* @param __FLAG__ specifies the flag to check.
<>	144:ef7eb2e8f9f7	1656	* This parameter can be one of the following values:
Anna Bridge	186:707f6e361f3e	1657	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
Anna Bridge	186:707f6e361f3e	1658	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready (not available on all devices)
Anna Bridge	186:707f6e361f3e	1659	* @arg @ref RCC_FLAG_HSIDIV HSI16 divider flag
Anna Bridge	186:707f6e361f3e	1660	* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
Anna Bridge	186:707f6e361f3e	1661	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
Anna Bridge	186:707f6e361f3e	1662	* @arg @ref RCC_FLAG_PLLRDY PLL clock ready
Anna Bridge	186:707f6e361f3e	1663	* @arg @ref RCC_FLAG_LSECSS LSE oscillator clock CSS detected
Anna Bridge	186:707f6e361f3e	1664	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
Anna Bridge	186:707f6e361f3e	1665	* @arg @ref RCC_FLAG_FWRST Firewall reset
Anna Bridge	186:707f6e361f3e	1666	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
Anna Bridge	186:707f6e361f3e	1667	* @arg @ref RCC_FLAG_OBLRST Option Byte Loader (OBL) reset
Anna Bridge	186:707f6e361f3e	1668	* @arg @ref RCC_FLAG_PINRST Pin reset
Anna Bridge	186:707f6e361f3e	1669	* @arg @ref RCC_FLAG_PORRST POR/PDR reset
Anna Bridge	186:707f6e361f3e	1670	* @arg @ref RCC_FLAG_SFTRST Software reset
Anna Bridge	186:707f6e361f3e	1671	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
Anna Bridge	186:707f6e361f3e	1672	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
Anna Bridge	186:707f6e361f3e	1673	* @arg @ref RCC_FLAG_LPWRRST Low Power reset
<>	144:ef7eb2e8f9f7	1674	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1675	*/
Anna Bridge	186:707f6e361f3e	1676	#if defined(RCC_HSI48_SUPPORT)
Anna Bridge	186:707f6e361f3e	1677	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == CSR_REG_INDEX) ? RCC->CSR :RCC->CRRCR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
Anna Bridge	186:707f6e361f3e	1678	#else
Anna Bridge	186:707f6e361f3e	1679	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
Anna Bridge	186:707f6e361f3e	1680	#endif /* RCC_HSI48_SUPPORT */
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/**
<>	144:ef7eb2e8f9f7	1683	* @}
<>	144:ef7eb2e8f9f7	1684	*/
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	/**
<>	144:ef7eb2e8f9f7	1687	* @}
<>	144:ef7eb2e8f9f7	1688	*/
<>	144:ef7eb2e8f9f7	1689
<>	144:ef7eb2e8f9f7	1690	/* Include RCC HAL Extension module */
<>	144:ef7eb2e8f9f7	1691	#include "stm32l0xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	1692
Anna Bridge	186:707f6e361f3e	1693	/* Exported functions --------------------------------------------------------*/
Anna Bridge	186:707f6e361f3e	1694	/** @addtogroup RCC_Exported_Functions
<>	144:ef7eb2e8f9f7	1695	* @{
<>	144:ef7eb2e8f9f7	1696	*/
<>	144:ef7eb2e8f9f7	1697
Anna Bridge	186:707f6e361f3e	1698	/** @addtogroup RCC_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1699	* @{
<>	144:ef7eb2e8f9f7	1700	*/
<>	144:ef7eb2e8f9f7	1701
Anna Bridge	186:707f6e361f3e	1702	/* Initialization and de-initialization functions ******************************/
Anna Bridge	186:707f6e361f3e	1703	void HAL_RCC_DeInit(void);
Anna Bridge	186:707f6e361f3e	1704	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Anna Bridge	186:707f6e361f3e	1705	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	/**
<>	144:ef7eb2e8f9f7	1708	* @}
<>	144:ef7eb2e8f9f7	1709	*/
<>	144:ef7eb2e8f9f7	1710
Anna Bridge	186:707f6e361f3e	1711	/** @addtogroup RCC_Exported_Functions_Group2
Anna Bridge	186:707f6e361f3e	1712	* @{
Anna Bridge	186:707f6e361f3e	1713	*/
Anna Bridge	186:707f6e361f3e	1714
Anna Bridge	186:707f6e361f3e	1715	/* Peripheral Control functions ************************************************/
Anna Bridge	186:707f6e361f3e	1716	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Anna Bridge	186:707f6e361f3e	1717	#if defined(RCC_HSECSS_SUPPORT)
Anna Bridge	186:707f6e361f3e	1718	void HAL_RCC_EnableCSS(void);
Anna Bridge	186:707f6e361f3e	1719	/* CSS NMI IRQ handler */
Anna Bridge	186:707f6e361f3e	1720	void HAL_RCC_NMI_IRQHandler(void);
Anna Bridge	186:707f6e361f3e	1721	/* User Callbacks in non blocking mode (IT mode) */
Anna Bridge	186:707f6e361f3e	1722	void HAL_RCC_CSSCallback(void);
Anna Bridge	186:707f6e361f3e	1723	#endif /* RCC_HSECSS_SUPPORT */
Anna Bridge	186:707f6e361f3e	1724	uint32_t HAL_RCC_GetSysClockFreq(void);
Anna Bridge	186:707f6e361f3e	1725	uint32_t HAL_RCC_GetHCLKFreq(void);
Anna Bridge	186:707f6e361f3e	1726	uint32_t HAL_RCC_GetPCLK1Freq(void);
Anna Bridge	186:707f6e361f3e	1727	uint32_t HAL_RCC_GetPCLK2Freq(void);
Anna Bridge	186:707f6e361f3e	1728	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Anna Bridge	186:707f6e361f3e	1729	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Anna Bridge	186:707f6e361f3e	1730
Anna Bridge	186:707f6e361f3e	1731	/**
Anna Bridge	186:707f6e361f3e	1732	* @}
Anna Bridge	186:707f6e361f3e	1733	*/
Anna Bridge	186:707f6e361f3e	1734
Anna Bridge	186:707f6e361f3e	1735	/**
Anna Bridge	186:707f6e361f3e	1736	* @}
Anna Bridge	186:707f6e361f3e	1737	*/
Anna Bridge	186:707f6e361f3e	1738
Anna Bridge	186:707f6e361f3e	1739	/**
Anna Bridge	186:707f6e361f3e	1740	* @}
Anna Bridge	186:707f6e361f3e	1741	*/
Anna Bridge	186:707f6e361f3e	1742
Anna Bridge	186:707f6e361f3e	1743	/**
Anna Bridge	186:707f6e361f3e	1744	* @}
Anna Bridge	186:707f6e361f3e	1745	*/
Anna Bridge	186:707f6e361f3e	1746
<>	144:ef7eb2e8f9f7	1747	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1748	}
<>	144:ef7eb2e8f9f7	1749	#endif
<>	144:ef7eb2e8f9f7	1750
Anna Bridge	186:707f6e361f3e	1751	#endif /* __STM32L0xx_HAL_RCC_H */
<>	144:ef7eb2e8f9f7	1752
<>	144:ef7eb2e8f9f7	1753	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	1754