mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief RCC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Reset and Clock Control (RCC) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### RCC specific features #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
Anna Bridge 186:707f6e361f3e 15 [..]
Anna Bridge 186:707f6e361f3e 16 After reset the device is running from multispeed internal oscillator clock
Anna Bridge 186:707f6e361f3e 17 (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled,
Anna Bridge 186:707f6e361f3e 18 and all peripherals are off except internal SRAM, Flash and JTAG.
Anna Bridge 186:707f6e361f3e 19 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
Anna Bridge 186:707f6e361f3e 20 all peripherals mapped on these buses are running at MSI speed.
Anna Bridge 186:707f6e361f3e 21 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
Anna Bridge 186:707f6e361f3e 22 (+) All GPIOs are in input floating state, except the JTAG pins which
Anna Bridge 186:707f6e361f3e 23 are assigned to be used for debug purpose.
<> 144:ef7eb2e8f9f7 24 [..] Once the device started from reset, the user application has to:
Anna Bridge 186:707f6e361f3e 25 (+) Configure the clock source to be used to drive the System clock
Anna Bridge 186:707f6e361f3e 26 (if the application needs higher frequency/performance)
Anna Bridge 186:707f6e361f3e 27 (+) Configure the System clock frequency and Flash settings
Anna Bridge 186:707f6e361f3e 28 (+) Configure the AHB and APB buses prescalers
Anna Bridge 186:707f6e361f3e 29 (+) Enable the clock for the peripheral(s) to be used
Anna Bridge 186:707f6e361f3e 30 (+) Configure the clock source(s) for peripherals whose clocks are not
Anna Bridge 186:707f6e361f3e 31 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
Anna Bridge 186:707f6e361f3e 32 (*) SDIO only for STM32L0xxxD devices
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 ##### RCC Limitations #####
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 [..]
<> 144:ef7eb2e8f9f7 37 A delay between an RCC peripheral clock enable and the effective peripheral
<> 144:ef7eb2e8f9f7 38 enabling should be taken into account in order to manage the peripheral read/write
Anna Bridge 186:707f6e361f3e 39 from/to registers.
<> 144:ef7eb2e8f9f7 40 (+) This delay depends on the peripheral mapping.
Anna Bridge 186:707f6e361f3e 41 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 [..]
Anna Bridge 186:707f6e361f3e 44 Workarounds:
Anna Bridge 186:707f6e361f3e 45 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
Anna Bridge 186:707f6e361f3e 46 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
Anna Bridge 186:707f6e361f3e 47
<> 144:ef7eb2e8f9f7 48 @endverbatim
<> 144:ef7eb2e8f9f7 49 ******************************************************************************
<> 144:ef7eb2e8f9f7 50 * @attention
<> 144:ef7eb2e8f9f7 51 *
<> 144:ef7eb2e8f9f7 52 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 53 *
<> 144:ef7eb2e8f9f7 54 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 55 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 56 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 57 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 58 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 59 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 60 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 61 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 62 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 63 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 68 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 71 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 72 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 73 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 74 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 ******************************************************************************
Anna Bridge 186:707f6e361f3e 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
Anna Bridge 186:707f6e361f3e 86 /** @defgroup RCC RCC
Anna Bridge 186:707f6e361f3e 87 * @brief RCC HAL module driver
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
Anna Bridge 186:707f6e361f3e 91 #ifdef HAL_RCC_MODULE_ENABLED
Anna Bridge 186:707f6e361f3e 92
Anna Bridge 186:707f6e361f3e 93 /* Private typedef -----------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 94 /* Private define ------------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 95 /** @defgroup RCC_Private_Constants RCC Private Constants
Anna Bridge 186:707f6e361f3e 96 * @{
Anna Bridge 186:707f6e361f3e 97 */
Anna Bridge 186:707f6e361f3e 98 /* Bits position in in the CFGR register */
Anna Bridge 186:707f6e361f3e 99 #define RCC_CFGR_PLLMUL_BITNUMBER RCC_CFGR_PLLMUL_Pos
Anna Bridge 186:707f6e361f3e 100 #define RCC_CFGR_PLLDIV_BITNUMBER RCC_CFGR_PLLDIV_Pos
Anna Bridge 186:707f6e361f3e 101 #define RCC_CFGR_HPRE_BITNUMBER RCC_CFGR_HPRE_Pos
Anna Bridge 186:707f6e361f3e 102 #define RCC_CFGR_PPRE1_BITNUMBER RCC_CFGR_PPRE1_Pos
Anna Bridge 186:707f6e361f3e 103 #define RCC_CFGR_PPRE2_BITNUMBER RCC_CFGR_PPRE2_Pos
Anna Bridge 186:707f6e361f3e 104 /* Bits position in in the ICSCR register */
Anna Bridge 186:707f6e361f3e 105 #define RCC_ICSCR_MSIRANGE_BITNUMBER RCC_ICSCR_MSIRANGE_Pos
Anna Bridge 186:707f6e361f3e 106 #define RCC_ICSCR_MSITRIM_BITNUMBER RCC_ICSCR_MSITRIM_Pos
Anna Bridge 186:707f6e361f3e 107 /**
Anna Bridge 186:707f6e361f3e 108 * @}
Anna Bridge 186:707f6e361f3e 109 */
Anna Bridge 186:707f6e361f3e 110 /* Private macro -------------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 111 /** @defgroup RCC_Private_Macros RCC Private Macros
<> 144:ef7eb2e8f9f7 112 * @{
Anna Bridge 186:707f6e361f3e 113 */
<> 144:ef7eb2e8f9f7 114
Anna Bridge 186:707f6e361f3e 115 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 116 #define MCO1_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 117 #define MCO1_PIN GPIO_PIN_8
<> 144:ef7eb2e8f9f7 118
Anna Bridge 186:707f6e361f3e 119 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 120 #define MCO2_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 121 #define MCO2_PIN GPIO_PIN_9
<> 144:ef7eb2e8f9f7 122
Anna Bridge 186:707f6e361f3e 123 #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \
Anna Bridge 186:707f6e361f3e 124 || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
Anna Bridge 186:707f6e361f3e 125 #define MCO3_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 126 #define MCO3_GPIO_PORT GPIOB
<> 144:ef7eb2e8f9f7 127 #define MCO3_PIN GPIO_PIN_13
<> 144:ef7eb2e8f9f7 128 #endif
<> 144:ef7eb2e8f9f7 129
Anna Bridge 186:707f6e361f3e 130 /**
Anna Bridge 186:707f6e361f3e 131 * @}
Anna Bridge 186:707f6e361f3e 132 */
Anna Bridge 186:707f6e361f3e 133
Anna Bridge 186:707f6e361f3e 134 /* Private variables ---------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 135 /** @defgroup RCC_Private_Variables RCC Private Variables
Anna Bridge 186:707f6e361f3e 136 * @{
Anna Bridge 186:707f6e361f3e 137 */
<> 144:ef7eb2e8f9f7 138 extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @}
Anna Bridge 186:707f6e361f3e 141 */
<> 144:ef7eb2e8f9f7 142
Anna Bridge 186:707f6e361f3e 143 /* Private function prototypes -----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 144 /** @defgroup RCC_Private_Functions RCC Private Functions
Anna Bridge 186:707f6e361f3e 145 * @{
Anna Bridge 186:707f6e361f3e 146 */
Anna Bridge 186:707f6e361f3e 147 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange);
Anna Bridge 186:707f6e361f3e 148 /**
Anna Bridge 186:707f6e361f3e 149 * @}
Anna Bridge 186:707f6e361f3e 150 */
Anna Bridge 186:707f6e361f3e 151
Anna Bridge 186:707f6e361f3e 152 /* Exported functions ---------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 153
Anna Bridge 186:707f6e361f3e 154 /** @defgroup RCC_Exported_Functions RCC Exported Functions
<> 144:ef7eb2e8f9f7 155 * @{
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
Anna Bridge 186:707f6e361f3e 158 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
Anna Bridge 186:707f6e361f3e 159 * @brief Initialization and Configuration functions
Anna Bridge 186:707f6e361f3e 160 *
Anna Bridge 186:707f6e361f3e 161 @verbatim
Anna Bridge 186:707f6e361f3e 162 ===============================================================================
<> 144:ef7eb2e8f9f7 163 ##### Initialization and de-initialization functions #####
Anna Bridge 186:707f6e361f3e 164 ===============================================================================
Anna Bridge 186:707f6e361f3e 165 [..]
Anna Bridge 186:707f6e361f3e 166 This section provides functions allowing to configure the internal/external oscillators
Anna Bridge 186:707f6e361f3e 167 (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
Anna Bridge 186:707f6e361f3e 168 and APB2).
Anna Bridge 186:707f6e361f3e 169
Anna Bridge 186:707f6e361f3e 170 [..] Internal/external clock and PLL configuration
Anna Bridge 186:707f6e361f3e 171 (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz,
Anna Bridge 186:707f6e361f3e 172 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz.
Anna Bridge 186:707f6e361f3e 173
Anna Bridge 186:707f6e361f3e 174 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
Anna Bridge 186:707f6e361f3e 175 the PLL as System clock source.
Anna Bridge 186:707f6e361f3e 176 (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC
Anna Bridge 186:707f6e361f3e 177 clock source.
Anna Bridge 186:707f6e361f3e 178
Anna Bridge 186:707f6e361f3e 179 (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or
Anna Bridge 186:707f6e361f3e 180 through the PLL as System clock source. Can be used also as RTC clock source.
Anna Bridge 186:707f6e361f3e 181
Anna Bridge 186:707f6e361f3e 182 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
Anna Bridge 186:707f6e361f3e 183
Anna Bridge 186:707f6e361f3e 184 (#) PLL (clocked by HSI or HSE), featuring different output clocks:
Anna Bridge 186:707f6e361f3e 185 (++) The first output is used to generate the high speed system clock (up to 32 MHz)
Anna Bridge 186:707f6e361f3e 186 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
Anna Bridge 186:707f6e361f3e 187
Anna Bridge 186:707f6e361f3e 188 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
Anna Bridge 186:707f6e361f3e 189 and if a HSE clock failure occurs(HSE used directly or through PLL as System
Anna Bridge 186:707f6e361f3e 190 clock source), the System clocks automatically switched to MSI and an interrupt
Anna Bridge 186:707f6e361f3e 191 is generated if enabled. The interrupt is linked to the Cortex-M0+ NMI
Anna Bridge 186:707f6e361f3e 192 (Non-Maskable Interrupt) exception vector.
Anna Bridge 186:707f6e361f3e 193
Anna Bridge 186:707f6e361f3e 194 (#) MCO1/MCO2/MCO3 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE,
Anna Bridge 186:707f6e361f3e 195 HSE, HSI48 or PLL clock (through a configurable prescaler) on PA8/PA9/PB13 pins.
Anna Bridge 186:707f6e361f3e 196
Anna Bridge 186:707f6e361f3e 197 [..] System, AHB and APB buses clocks configuration
Anna Bridge 186:707f6e361f3e 198 (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
Anna Bridge 186:707f6e361f3e 199 HSE and PLL.
Anna Bridge 186:707f6e361f3e 200 The AHB clock (HCLK) is derived from System clock through configurable
Anna Bridge 186:707f6e361f3e 201 prescaler and used to clock the CPU, memory and peripherals mapped
Anna Bridge 186:707f6e361f3e 202 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
Anna Bridge 186:707f6e361f3e 203 from AHB clock through configurable prescalers and used to clock
Anna Bridge 186:707f6e361f3e 204 the peripherals mapped on these buses. You can use
Anna Bridge 186:707f6e361f3e 205 "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<> 144:ef7eb2e8f9f7 206
Anna Bridge 186:707f6e361f3e 207 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
Anna Bridge 186:707f6e361f3e 208 (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
Anna Bridge 186:707f6e361f3e 209 divided by 2 to 16. You have to use @ref __HAL_RCC_RTC_CONFIG() and @ref __HAL_RCC_RTC_ENABLE()
Anna Bridge 186:707f6e361f3e 210 macros to configure this clock.
Anna Bridge 186:707f6e361f3e 211 (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock
Anna Bridge 186:707f6e361f3e 212 divided by 2 to 16. You have to use @ref __HAL_RCC_LCD_CONFIG()
Anna Bridge 186:707f6e361f3e 213 macros to configure this clock.
Anna Bridge 186:707f6e361f3e 214 (+@) USB FS and RNG: USB FS require a frequency equal to 48 MHz to work correctly.
Anna Bridge 186:707f6e361f3e 215 This clock is derived of the main PLL through PLL Multiplier or HSI48 RC oscillator.
Anna Bridge 186:707f6e361f3e 216
Anna Bridge 186:707f6e361f3e 217 (+@) IWDG clock which is always the LSI clock.
<> 151:5eaa88a5bcc7 218
Anna Bridge 186:707f6e361f3e 219 (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz
Anna Bridge 186:707f6e361f3e 220 and PCLK1 32 MHz. Depending on the device voltage range, the maximum
Anna Bridge 186:707f6e361f3e 221 frequency should be adapted accordingly.
Anna Bridge 186:707f6e361f3e 222 @endverbatim
Anna Bridge 186:707f6e361f3e 223 * @{
Anna Bridge 186:707f6e361f3e 224 */
Anna Bridge 186:707f6e361f3e 225
Anna Bridge 186:707f6e361f3e 226 /*
Anna Bridge 186:707f6e361f3e 227 Additional consideration on the HCLK based on Latency settings:
Anna Bridge 186:707f6e361f3e 228 +----------------------------------------------------------------------+
Anna Bridge 186:707f6e361f3e 229 | Latency | HCLK clock frequency (MHz) |
Anna Bridge 186:707f6e361f3e 230 | |------------------------------------------------------|
Anna Bridge 186:707f6e361f3e 231 | | voltage range 1 | voltage range 2 | voltage range 3 |
Anna Bridge 186:707f6e361f3e 232 | | 1.8 V | 1.5 V | 1.2 V |
Anna Bridge 186:707f6e361f3e 233 |---------------|------------------|-----------------|-----------------|
Anna Bridge 186:707f6e361f3e 234 |0WS(1CPU cycle)| 0 < HCLK <= 16 | 0 < HCLK <= 8 | 0 < HCLK <= 2 |
Anna Bridge 186:707f6e361f3e 235 |---------------|------------------|-----------------|-----------------|
Anna Bridge 186:707f6e361f3e 236 |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 |
Anna Bridge 186:707f6e361f3e 237 +----------------------------------------------------------------------+
<> 151:5eaa88a5bcc7 238
Anna Bridge 186:707f6e361f3e 239 The following table gives the different clock source frequencies depending on the product
Anna Bridge 186:707f6e361f3e 240 voltage range:
Anna Bridge 186:707f6e361f3e 241 +------------------------------------------------------------------------------------------+
Anna Bridge 186:707f6e361f3e 242 | Product voltage | Clock frequency |
Anna Bridge 186:707f6e361f3e 243 | |------------------|-----------------------------|-----------------------|
Anna Bridge 186:707f6e361f3e 244 | range | MSI | HSI | HSE | PLL |
Anna Bridge 186:707f6e361f3e 245 |-----------------|---------|--------|-----------------------------|-----------------------|
Anna Bridge 186:707f6e361f3e 246 | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) | 32 MHz |
Anna Bridge 186:707f6e361f3e 247 | | | | or 24 MHz (crystal) | (PLLVCO max = 96 MHz) |
Anna Bridge 186:707f6e361f3e 248 |-----------------|---------|--------|-----------------------------|-----------------------|
Anna Bridge 186:707f6e361f3e 249 | Range 2 (1.5 V) | 4.2 MHz | 16 MHz | 16 MHz | 16 MHz |
Anna Bridge 186:707f6e361f3e 250 | | | | | (PLLVCO max = 48 MHz) |
Anna Bridge 186:707f6e361f3e 251 |-----------------|---------|--------|-----------------------------|-----------------------|
Anna Bridge 186:707f6e361f3e 252 | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz |
Anna Bridge 186:707f6e361f3e 253 | | | | | (PLLVCO max = 24 MHz) |
Anna Bridge 186:707f6e361f3e 254 +------------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Resets the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 259 * @note The default reset state of the clock configuration is given below:
Anna Bridge 186:707f6e361f3e 260 * - MSI ON and used as system clock source
Anna Bridge 186:707f6e361f3e 261 * - HSI, HSE and PLL OFF
Anna Bridge 186:707f6e361f3e 262 * - AHB, APB1 and APB2 prescaler set to 1.
Anna Bridge 186:707f6e361f3e 263 * - CSS and MCO1/MCO2/MCO3 OFF
Anna Bridge 186:707f6e361f3e 264 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 265 * @note This function does not modify the configuration of the
Anna Bridge 186:707f6e361f3e 266 * - Peripheral clocks
Anna Bridge 186:707f6e361f3e 267 * - LSI, LSE and RTC clocks
Anna Bridge 186:707f6e361f3e 268 * - HSI48 clock
<> 144:ef7eb2e8f9f7 269 * @retval None
<> 144:ef7eb2e8f9f7 270 */
<> 151:5eaa88a5bcc7 271 void HAL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 272 {
<> 151:5eaa88a5bcc7 273 __IO uint32_t tmpreg;
Anna Bridge 186:707f6e361f3e 274
<> 151:5eaa88a5bcc7 275 /* Set MSION bit */
Anna Bridge 186:707f6e361f3e 276 SET_BIT(RCC->CR, RCC_CR_MSION);
<> 151:5eaa88a5bcc7 277
Anna Bridge 186:707f6e361f3e 278 /* Switch SYSCLK to MSI*/
Anna Bridge 186:707f6e361f3e 279 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
Anna Bridge 186:707f6e361f3e 280
<> 151:5eaa88a5bcc7 281 /* Reset HSE, HSI, CSS, PLL */
Anna Bridge 186:707f6e361f3e 282 #if defined(RCC_CR_CSSHSEON) && defined(RCC_CR_HSIOUTEN)
<> 151:5eaa88a5bcc7 283 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
<> 151:5eaa88a5bcc7 284 RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
Anna Bridge 186:707f6e361f3e 285 #elif !defined(RCC_CR_CSSHSEON) && defined(RCC_CR_HSIOUTEN)
<> 151:5eaa88a5bcc7 286 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
<> 151:5eaa88a5bcc7 287 RCC_CR_HSEON | RCC_CR_PLLON);
Anna Bridge 186:707f6e361f3e 288 #elif defined(RCC_CR_CSSHSEON) && !defined(RCC_CR_HSIOUTEN)
<> 151:5eaa88a5bcc7 289 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
<> 151:5eaa88a5bcc7 290 RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
<> 151:5eaa88a5bcc7 291 #endif
<> 151:5eaa88a5bcc7 292
<> 151:5eaa88a5bcc7 293 /* Delay after an RCC peripheral clock */ \
<> 151:5eaa88a5bcc7 294 tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
<> 151:5eaa88a5bcc7 295 UNUSED(tmpreg);
<> 151:5eaa88a5bcc7 296
<> 151:5eaa88a5bcc7 297 /* Reset HSEBYP bit */
<> 151:5eaa88a5bcc7 298 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 151:5eaa88a5bcc7 299
<> 151:5eaa88a5bcc7 300 /* Reset CFGR register */
<> 151:5eaa88a5bcc7 301 CLEAR_REG(RCC->CFGR);
<> 151:5eaa88a5bcc7 302
Anna Bridge 186:707f6e361f3e 303 /* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */
Anna Bridge 186:707f6e361f3e 304 MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << RCC_ICSCR_MSITRIM_BITNUMBER) | RCC_ICSCR_MSIRANGE_5));
Anna Bridge 186:707f6e361f3e 305
Anna Bridge 186:707f6e361f3e 306 /* Set HSITRIM bits to the reset value */
Anna Bridge 186:707f6e361f3e 307 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << 8));
Anna Bridge 186:707f6e361f3e 308
<> 151:5eaa88a5bcc7 309 /* Disable all interrupts */
<> 151:5eaa88a5bcc7 310 CLEAR_REG(RCC->CIER);
Anna Bridge 186:707f6e361f3e 311
<> 151:5eaa88a5bcc7 312 /* Update the SystemCoreClock global variable */
Anna Bridge 186:707f6e361f3e 313 SystemCoreClock = MSI_VALUE;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief Initializes the RCC Oscillators according to the specified parameters in the
<> 144:ef7eb2e8f9f7 318 * RCC_OscInitTypeDef.
Anna Bridge 186:707f6e361f3e 319 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 320 * contains the configuration information for the RCC Oscillators.
<> 144:ef7eb2e8f9f7 321 * @note The PLL is not disabled when used as system clock.
<> 144:ef7eb2e8f9f7 322 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<> 144:ef7eb2e8f9f7 323 * supported by this macro. User should request a transition to LSE Off
<> 144:ef7eb2e8f9f7 324 * first and then LSE On or LSE Bypass.
<> 144:ef7eb2e8f9f7 325 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 326 * supported by this macro. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 327 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 328 * @retval HAL status
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 331 {
Anna Bridge 186:707f6e361f3e 332 uint32_t tickstart = 0U;
Anna Bridge 186:707f6e361f3e 333
<> 144:ef7eb2e8f9f7 334 /* Check the parameters */
<> 144:ef7eb2e8f9f7 335 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 336 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
Anna Bridge 186:707f6e361f3e 337
<> 144:ef7eb2e8f9f7 338 /*------------------------------- HSE Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 339 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 /* Check the parameters */
<> 144:ef7eb2e8f9f7 342 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
Anna Bridge 186:707f6e361f3e 343
Anna Bridge 186:707f6e361f3e 344 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
Anna Bridge 186:707f6e361f3e 345 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
Anna Bridge 186:707f6e361f3e 346 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 else
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 /* Set the new HSE configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 356 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<> 144:ef7eb2e8f9f7 357
Anna Bridge 186:707f6e361f3e 358
Anna Bridge 186:707f6e361f3e 359 /* Check the HSE State */
Anna Bridge 186:707f6e361f3e 360 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<> 144:ef7eb2e8f9f7 361 {
Anna Bridge 186:707f6e361f3e 362 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 363 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 364
Anna Bridge 186:707f6e361f3e 365 /* Wait till HSE is ready */
<> 144:ef7eb2e8f9f7 366 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 367 {
Anna Bridge 186:707f6e361f3e 368 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 371 }
Anna Bridge 186:707f6e361f3e 372 }
<> 144:ef7eb2e8f9f7 373 }
<> 144:ef7eb2e8f9f7 374 else
<> 144:ef7eb2e8f9f7 375 {
Anna Bridge 186:707f6e361f3e 376 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 377 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 378
Anna Bridge 186:707f6e361f3e 379 /* Wait till HSE is disabled */
<> 144:ef7eb2e8f9f7 380 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<> 144:ef7eb2e8f9f7 381 {
Anna Bridge 186:707f6e361f3e 382 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 385 }
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390 /*----------------------------- HSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 391 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 /* Check the parameters */
<> 144:ef7eb2e8f9f7 394 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<> 144:ef7eb2e8f9f7 395 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<> 144:ef7eb2e8f9f7 396
Anna Bridge 186:707f6e361f3e 397 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
Anna Bridge 186:707f6e361f3e 398 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
Anna Bridge 186:707f6e361f3e 399 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 /* When HSI is used as system clock it will not disabled */
<> 144:ef7eb2e8f9f7 402 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 /* Otherwise, just the calibration is allowed */
<> 144:ef7eb2e8f9f7 407 else
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 410 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 else
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 /* Check the HSI State */
Anna Bridge 186:707f6e361f3e 416 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
<> 144:ef7eb2e8f9f7 417 {
Anna Bridge 186:707f6e361f3e 418 /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
<> 144:ef7eb2e8f9f7 419 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
<> 144:ef7eb2e8f9f7 420
Anna Bridge 186:707f6e361f3e 421 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 422 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 423
Anna Bridge 186:707f6e361f3e 424 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 425 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 426 {
Anna Bridge 186:707f6e361f3e 427 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 430 }
Anna Bridge 186:707f6e361f3e 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 434 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436 else
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 /* Disable the Internal High Speed oscillator (HSI). */
Anna Bridge 186:707f6e361f3e 439 __HAL_RCC_HSI_DISABLE();
Anna Bridge 186:707f6e361f3e 440
Anna Bridge 186:707f6e361f3e 441 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 442 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 443
Anna Bridge 186:707f6e361f3e 444 /* Wait till HSI is disabled */
<> 144:ef7eb2e8f9f7 445 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 446 {
Anna Bridge 186:707f6e361f3e 447 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 450 }
Anna Bridge 186:707f6e361f3e 451 }
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455 /*----------------------------- MSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 456 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 /* When the MSI is used as system clock it will not be disabled */
<> 144:ef7eb2e8f9f7 459 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 464 }
Anna Bridge 186:707f6e361f3e 465 /* Otherwise, just the calibration and MSI range change are allowed */
<> 144:ef7eb2e8f9f7 466 else
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 /* Check MSICalibrationValue and MSIClockRange input parameters */
<> 144:ef7eb2e8f9f7 469 assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
<> 144:ef7eb2e8f9f7 470 assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
<> 144:ef7eb2e8f9f7 471
Anna Bridge 186:707f6e361f3e 472 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
Anna Bridge 186:707f6e361f3e 473 must be correctly programmed according to the frequency of the CPU clock
Anna Bridge 186:707f6e361f3e 474 (HCLK) and the supply voltage of the device. */
Anna Bridge 186:707f6e361f3e 475 if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
Anna Bridge 186:707f6e361f3e 476 {
Anna Bridge 186:707f6e361f3e 477 /* First increase number of wait states update if necessary */
Anna Bridge 186:707f6e361f3e 478 if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
Anna Bridge 186:707f6e361f3e 479 {
Anna Bridge 186:707f6e361f3e 480 return HAL_ERROR;
Anna Bridge 186:707f6e361f3e 481 }
Anna Bridge 186:707f6e361f3e 482
Anna Bridge 186:707f6e361f3e 483 /* Selects the Multiple Speed oscillator (MSI) clock range .*/
Anna Bridge 186:707f6e361f3e 484 __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
Anna Bridge 186:707f6e361f3e 485 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
Anna Bridge 186:707f6e361f3e 486 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
Anna Bridge 186:707f6e361f3e 487 }
Anna Bridge 186:707f6e361f3e 488 else
Anna Bridge 186:707f6e361f3e 489 {
Anna Bridge 186:707f6e361f3e 490 /* Else, keep current flash latency while decreasing applies */
Anna Bridge 186:707f6e361f3e 491 /* Selects the Multiple Speed oscillator (MSI) clock range .*/
Anna Bridge 186:707f6e361f3e 492 __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
Anna Bridge 186:707f6e361f3e 493 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
Anna Bridge 186:707f6e361f3e 494 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
Anna Bridge 186:707f6e361f3e 495
Anna Bridge 186:707f6e361f3e 496 /* Decrease number of wait states update if necessary */
Anna Bridge 186:707f6e361f3e 497 if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
Anna Bridge 186:707f6e361f3e 498 {
Anna Bridge 186:707f6e361f3e 499 return HAL_ERROR;
Anna Bridge 186:707f6e361f3e 500 }
Anna Bridge 186:707f6e361f3e 501 }
<> 144:ef7eb2e8f9f7 502
<> 151:5eaa88a5bcc7 503 /* Update the SystemCoreClock global variable */
Anna Bridge 186:707f6e361f3e 504 SystemCoreClock = (32768U * (1U << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_BITNUMBER) + 1U)))
Anna Bridge 186:707f6e361f3e 505 >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER)];
Anna Bridge 186:707f6e361f3e 506
<> 144:ef7eb2e8f9f7 507 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 508 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 else
<> 144:ef7eb2e8f9f7 512 {
Anna Bridge 186:707f6e361f3e 513 /* Check MSI State */
<> 144:ef7eb2e8f9f7 514 assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
Anna Bridge 186:707f6e361f3e 515
Anna Bridge 186:707f6e361f3e 516 /* Check the MSI State */
Anna Bridge 186:707f6e361f3e 517 if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
<> 144:ef7eb2e8f9f7 518 {
Anna Bridge 186:707f6e361f3e 519 /* Enable the Multi Speed oscillator (MSI). */
<> 144:ef7eb2e8f9f7 520 __HAL_RCC_MSI_ENABLE();
Anna Bridge 186:707f6e361f3e 521
Anna Bridge 186:707f6e361f3e 522 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 523 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 524
Anna Bridge 186:707f6e361f3e 525 /* Wait till MSI is ready */
<> 144:ef7eb2e8f9f7 526 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 527 {
Anna Bridge 186:707f6e361f3e 528 if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 531 }
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 /* Check MSICalibrationValue and MSIClockRange input parameters */
<> 144:ef7eb2e8f9f7 534 assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
<> 144:ef7eb2e8f9f7 535 assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
<> 144:ef7eb2e8f9f7 536
Anna Bridge 186:707f6e361f3e 537 /* Selects the Multiple Speed oscillator (MSI) clock range .*/
Anna Bridge 186:707f6e361f3e 538 __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
<> 144:ef7eb2e8f9f7 539 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
<> 144:ef7eb2e8f9f7 540 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
Anna Bridge 186:707f6e361f3e 541
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543 else
<> 144:ef7eb2e8f9f7 544 {
Anna Bridge 186:707f6e361f3e 545 /* Disable the Multi Speed oscillator (MSI). */
<> 144:ef7eb2e8f9f7 546 __HAL_RCC_MSI_DISABLE();
Anna Bridge 186:707f6e361f3e 547
Anna Bridge 186:707f6e361f3e 548 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 549 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 550
Anna Bridge 186:707f6e361f3e 551 /* Wait till MSI is ready */
<> 144:ef7eb2e8f9f7 552 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 553 {
Anna Bridge 186:707f6e361f3e 554 if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 557 }
Anna Bridge 186:707f6e361f3e 558 }
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560 }
Anna Bridge 186:707f6e361f3e 561 }
<> 144:ef7eb2e8f9f7 562 /*------------------------------ LSI Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 563 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Check the parameters */
<> 144:ef7eb2e8f9f7 566 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Check the LSI State */
Anna Bridge 186:707f6e361f3e 569 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 /* Enable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 572 __HAL_RCC_LSI_ENABLE();
<> 144:ef7eb2e8f9f7 573
Anna Bridge 186:707f6e361f3e 574 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 575 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 578 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 579 {
Anna Bridge 186:707f6e361f3e 580 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 583 }
Anna Bridge 186:707f6e361f3e 584 }
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 else
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 /* Disable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 589 __HAL_RCC_LSI_DISABLE();
<> 144:ef7eb2e8f9f7 590
Anna Bridge 186:707f6e361f3e 591 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 592 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 593
Anna Bridge 186:707f6e361f3e 594 /* Wait till LSI is disabled */
Anna Bridge 186:707f6e361f3e 595 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 596 {
Anna Bridge 186:707f6e361f3e 597 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 600 }
Anna Bridge 186:707f6e361f3e 601 }
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604 /*------------------------------ LSE Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 605 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<> 144:ef7eb2e8f9f7 606 {
<> 144:ef7eb2e8f9f7 607 FlagStatus pwrclkchanged = RESET;
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Check the parameters */
<> 144:ef7eb2e8f9f7 610 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Update LSE configuration in Backup Domain control register */
<> 144:ef7eb2e8f9f7 613 /* Requires to enable write access to Backup Domain of necessary */
Anna Bridge 186:707f6e361f3e 614 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 617 pwrclkchanged = SET;
<> 144:ef7eb2e8f9f7 618 }
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 623 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 626 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 }
Anna Bridge 186:707f6e361f3e 636
<> 144:ef7eb2e8f9f7 637 /* Set the new LSE configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 638 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<> 144:ef7eb2e8f9f7 639 /* Check the LSE State */
Anna Bridge 186:707f6e361f3e 640 if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
Anna Bridge 186:707f6e361f3e 641 {
Anna Bridge 186:707f6e361f3e 642 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 643 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 646 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 651 }
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 else
<> 144:ef7eb2e8f9f7 655 {
Anna Bridge 186:707f6e361f3e 656 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 657 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 658
Anna Bridge 186:707f6e361f3e 659 /* Wait till LSE is disabled */
<> 144:ef7eb2e8f9f7 660 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 665 }
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
Anna Bridge 186:707f6e361f3e 669 /* Require to disable power clock if necessary */
<> 144:ef7eb2e8f9f7 670 if(pwrclkchanged == SET)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 __HAL_RCC_PWR_CLK_DISABLE();
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 }
Anna Bridge 186:707f6e361f3e 675
Anna Bridge 186:707f6e361f3e 676 #if defined(RCC_HSI48_SUPPORT)
Anna Bridge 186:707f6e361f3e 677 /*----------------------------- HSI48 Configuration --------------------------*/
Anna Bridge 186:707f6e361f3e 678 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
Anna Bridge 186:707f6e361f3e 679 {
Anna Bridge 186:707f6e361f3e 680 /* Check the parameters */
Anna Bridge 186:707f6e361f3e 681 assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
Anna Bridge 186:707f6e361f3e 682
Anna Bridge 186:707f6e361f3e 683 /* Check the HSI48 State */
Anna Bridge 186:707f6e361f3e 684 if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
Anna Bridge 186:707f6e361f3e 685 {
Anna Bridge 186:707f6e361f3e 686 /* Enable the Internal High Speed oscillator (HSI48). */
Anna Bridge 186:707f6e361f3e 687 __HAL_RCC_HSI48_ENABLE();
Anna Bridge 186:707f6e361f3e 688
Anna Bridge 186:707f6e361f3e 689 /* Get Start Tick */
Anna Bridge 186:707f6e361f3e 690 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 691
Anna Bridge 186:707f6e361f3e 692 /* Wait till HSI48 is ready */
Anna Bridge 186:707f6e361f3e 693 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
Anna Bridge 186:707f6e361f3e 694 {
Anna Bridge 186:707f6e361f3e 695 if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
Anna Bridge 186:707f6e361f3e 696 {
Anna Bridge 186:707f6e361f3e 697 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 698 }
Anna Bridge 186:707f6e361f3e 699 }
Anna Bridge 186:707f6e361f3e 700 }
Anna Bridge 186:707f6e361f3e 701 else
Anna Bridge 186:707f6e361f3e 702 {
Anna Bridge 186:707f6e361f3e 703 /* Disable the Internal High Speed oscillator (HSI48). */
Anna Bridge 186:707f6e361f3e 704 __HAL_RCC_HSI48_DISABLE();
Anna Bridge 186:707f6e361f3e 705
Anna Bridge 186:707f6e361f3e 706 /* Get Start Tick */
Anna Bridge 186:707f6e361f3e 707 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 708
Anna Bridge 186:707f6e361f3e 709 /* Wait till HSI48 is ready */
Anna Bridge 186:707f6e361f3e 710 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
Anna Bridge 186:707f6e361f3e 711 {
Anna Bridge 186:707f6e361f3e 712 if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
Anna Bridge 186:707f6e361f3e 713 {
Anna Bridge 186:707f6e361f3e 714 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 715 }
Anna Bridge 186:707f6e361f3e 716 }
Anna Bridge 186:707f6e361f3e 717 }
Anna Bridge 186:707f6e361f3e 718 }
Anna Bridge 186:707f6e361f3e 719 #endif /* RCC_HSI48_SUPPORT */
Anna Bridge 186:707f6e361f3e 720
<> 144:ef7eb2e8f9f7 721 /*-------------------------------- PLL Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 722 /* Check the parameters */
<> 144:ef7eb2e8f9f7 723 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<> 144:ef7eb2e8f9f7 724 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 727 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 /* Check the parameters */
<> 144:ef7eb2e8f9f7 732 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<> 144:ef7eb2e8f9f7 733 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
<> 144:ef7eb2e8f9f7 734 assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
Anna Bridge 186:707f6e361f3e 735
<> 144:ef7eb2e8f9f7 736 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 737 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 738
Anna Bridge 186:707f6e361f3e 739 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 740 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 741
Anna Bridge 186:707f6e361f3e 742 /* Wait till PLL is disabled */
Anna Bridge 186:707f6e361f3e 743 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 744 {
Anna Bridge 186:707f6e361f3e 745 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 748 }
Anna Bridge 186:707f6e361f3e 749 }
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Configure the main PLL clock source, multiplication and division factors. */
<> 144:ef7eb2e8f9f7 752 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 144:ef7eb2e8f9f7 753 RCC_OscInitStruct->PLL.PLLMUL,
<> 144:ef7eb2e8f9f7 754 RCC_OscInitStruct->PLL.PLLDIV);
<> 144:ef7eb2e8f9f7 755 /* Enable the main PLL. */
<> 144:ef7eb2e8f9f7 756 __HAL_RCC_PLL_ENABLE();
Anna Bridge 186:707f6e361f3e 757
Anna Bridge 186:707f6e361f3e 758 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 759 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 760
Anna Bridge 186:707f6e361f3e 761 /* Wait till PLL is ready */
Anna Bridge 186:707f6e361f3e 762 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 763 {
Anna Bridge 186:707f6e361f3e 764 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 765 {
<> 144:ef7eb2e8f9f7 766 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 767 }
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770 else
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 /* Disable the main PLL. */
Anna Bridge 186:707f6e361f3e 773 __HAL_RCC_PLL_DISABLE();
Anna Bridge 186:707f6e361f3e 774
Anna Bridge 186:707f6e361f3e 775 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 776 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 777
Anna Bridge 186:707f6e361f3e 778 /* Wait till PLL is disabled */
Anna Bridge 186:707f6e361f3e 779 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 780 {
Anna Bridge 186:707f6e361f3e 781 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 784 }
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788 else
<> 144:ef7eb2e8f9f7 789 {
AnnaBridge 181:57724642e740 790 /* MBED patch - ST internal ticket 42806 */
AnnaBridge 181:57724642e740 791 if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) {
AnnaBridge 181:57724642e740 792 return HAL_ERROR;
AnnaBridge 181:57724642e740 793 }
AnnaBridge 181:57724642e740 794
AnnaBridge 181:57724642e740 795 if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV) {
AnnaBridge 181:57724642e740 796 return HAL_ERROR;
AnnaBridge 181:57724642e740 797 }
AnnaBridge 181:57724642e740 798
AnnaBridge 181:57724642e740 799 if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) {
AnnaBridge 181:57724642e740 800 return HAL_ERROR;
AnnaBridge 181:57724642e740 801 }
AnnaBridge 181:57724642e740 802 /* MBED patch - ST internal ticket 42806 */
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804 }
Anna Bridge 186:707f6e361f3e 805
<> 144:ef7eb2e8f9f7 806 return HAL_OK;
<> 144:ef7eb2e8f9f7 807 }
Anna Bridge 186:707f6e361f3e 808
<> 144:ef7eb2e8f9f7 809 /**
Anna Bridge 186:707f6e361f3e 810 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
<> 144:ef7eb2e8f9f7 811 * parameters in the RCC_ClkInitStruct.
Anna Bridge 186:707f6e361f3e 812 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 813 * contains the configuration information for the RCC peripheral.
Anna Bridge 186:707f6e361f3e 814 * @param FLatency FLASH Latency
Anna Bridge 186:707f6e361f3e 815 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 816 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
Anna Bridge 186:707f6e361f3e 817 * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
Anna Bridge 186:707f6e361f3e 818 *
<> 144:ef7eb2e8f9f7 819 * @note The MSI is used (enabled by hardware) as system clock source after
Anna Bridge 186:707f6e361f3e 820 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
<> 144:ef7eb2e8f9f7 821 * of failure of the HSE used directly or indirectly as system clock
<> 144:ef7eb2e8f9f7 822 * (if the Clock Security System CSS is enabled).
<> 144:ef7eb2e8f9f7 823 *
<> 144:ef7eb2e8f9f7 824 * @note A switch from one clock source to another occurs only if the target
Anna Bridge 186:707f6e361f3e 825 * clock source is ready (clock stable after start-up delay or PLL locked).
<> 144:ef7eb2e8f9f7 826 * If a clock source which is not yet ready is selected, the switch will
<> 144:ef7eb2e8f9f7 827 * occur when the clock source will be ready.
Anna Bridge 186:707f6e361f3e 828 * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
Anna Bridge 186:707f6e361f3e 829 * currently used as system clock source.
Anna Bridge 186:707f6e361f3e 830 * @note Depending on the device voltage range, the software has to set correctly
Anna Bridge 186:707f6e361f3e 831 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
Anna Bridge 186:707f6e361f3e 832 * (for more details refer to section above "Initialization/de-initialization functions")
Anna Bridge 186:707f6e361f3e 833 * @retval HAL status
<> 144:ef7eb2e8f9f7 834 */
<> 144:ef7eb2e8f9f7 835 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<> 144:ef7eb2e8f9f7 836 {
<> 151:5eaa88a5bcc7 837 uint32_t tickstart = 0U;
Anna Bridge 186:707f6e361f3e 838
<> 144:ef7eb2e8f9f7 839 /* Check the parameters */
<> 144:ef7eb2e8f9f7 840 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 841 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<> 144:ef7eb2e8f9f7 842 assert_param(IS_FLASH_LATENCY(FLatency));
Anna Bridge 186:707f6e361f3e 843
<> 144:ef7eb2e8f9f7 844 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
Anna Bridge 186:707f6e361f3e 845 must be correctly programmed according to the frequency of the CPU clock
Anna Bridge 186:707f6e361f3e 846 (HCLK) and the supply voltage of the device. */
Anna Bridge 186:707f6e361f3e 847
Anna Bridge 186:707f6e361f3e 848 /* Increasing the number of wait states because of higher CPU frequency */
<> 144:ef7eb2e8f9f7 849 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 852 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 855 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 856 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 857 {
<> 144:ef7eb2e8f9f7 858 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860 }
Anna Bridge 186:707f6e361f3e 861
<> 144:ef7eb2e8f9f7 862 /*-------------------------- HCLK Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 863 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 866 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /*------------------------- SYSCLK Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 870 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<> 144:ef7eb2e8f9f7 871 {
<> 144:ef7eb2e8f9f7 872 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
Anna Bridge 186:707f6e361f3e 873
<> 144:ef7eb2e8f9f7 874 /* HSE is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 875 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 /* Check the HSE ready flag */
<> 144:ef7eb2e8f9f7 878 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 /* PLL is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 884 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 885 {
<> 144:ef7eb2e8f9f7 886 /* Check the PLL ready flag */
<> 144:ef7eb2e8f9f7 887 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 888 {
<> 144:ef7eb2e8f9f7 889 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892 /* HSI is selected as System Clock Source */
Anna Bridge 186:707f6e361f3e 893 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 /* Check the HSI ready flag */
<> 144:ef7eb2e8f9f7 896 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 899 }
<> 144:ef7eb2e8f9f7 900 }
Anna Bridge 186:707f6e361f3e 901 /* MSI is selected as System Clock Source */
Anna Bridge 186:707f6e361f3e 902 else
Anna Bridge 186:707f6e361f3e 903 {
Anna Bridge 186:707f6e361f3e 904 /* Check the MSI ready flag */
Anna Bridge 186:707f6e361f3e 905 if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
Anna Bridge 186:707f6e361f3e 906 {
Anna Bridge 186:707f6e361f3e 907 return HAL_ERROR;
Anna Bridge 186:707f6e361f3e 908 }
Anna Bridge 186:707f6e361f3e 909 }
Anna Bridge 186:707f6e361f3e 910 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
Anna Bridge 186:707f6e361f3e 911
Anna Bridge 186:707f6e361f3e 912 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 913 tickstart = HAL_GetTick();
Anna Bridge 186:707f6e361f3e 914
<> 144:ef7eb2e8f9f7 915 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 918 {
Anna Bridge 186:707f6e361f3e 919 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 920 {
<> 144:ef7eb2e8f9f7 921 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 922 }
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 928 {
Anna Bridge 186:707f6e361f3e 929 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934 }
Anna Bridge 186:707f6e361f3e 935 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
Anna Bridge 186:707f6e361f3e 936 {
Anna Bridge 186:707f6e361f3e 937 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
Anna Bridge 186:707f6e361f3e 938 {
Anna Bridge 186:707f6e361f3e 939 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
Anna Bridge 186:707f6e361f3e 940 {
Anna Bridge 186:707f6e361f3e 941 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 942 }
Anna Bridge 186:707f6e361f3e 943 }
Anna Bridge 186:707f6e361f3e 944 }
Anna Bridge 186:707f6e361f3e 945 else
Anna Bridge 186:707f6e361f3e 946 {
Anna Bridge 186:707f6e361f3e 947 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
Anna Bridge 186:707f6e361f3e 948 {
Anna Bridge 186:707f6e361f3e 949 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
Anna Bridge 186:707f6e361f3e 950 {
Anna Bridge 186:707f6e361f3e 951 return HAL_TIMEOUT;
Anna Bridge 186:707f6e361f3e 952 }
Anna Bridge 186:707f6e361f3e 953 }
Anna Bridge 186:707f6e361f3e 954 }
Anna Bridge 186:707f6e361f3e 955 }
Anna Bridge 186:707f6e361f3e 956 /* Decreasing the number of wait states because of lower CPU frequency */
Anna Bridge 186:707f6e361f3e 957 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
Anna Bridge 186:707f6e361f3e 958 {
<> 144:ef7eb2e8f9f7 959 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 960 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 963 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 964 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 967 }
Anna Bridge 186:707f6e361f3e 968 }
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /*-------------------------- PCLK1 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 971 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 974 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /*-------------------------- PCLK2 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 978 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
<> 144:ef7eb2e8f9f7 981 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
<> 144:ef7eb2e8f9f7 982 }
Anna Bridge 186:707f6e361f3e 983
<> 151:5eaa88a5bcc7 984 /* Update the SystemCoreClock global variable */
Anna Bridge 186:707f6e361f3e 985 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
Anna Bridge 186:707f6e361f3e 986
<> 144:ef7eb2e8f9f7 987 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 988 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 return HAL_OK;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /**
<> 144:ef7eb2e8f9f7 994 * @}
<> 144:ef7eb2e8f9f7 995 */
<> 144:ef7eb2e8f9f7 996
Anna Bridge 186:707f6e361f3e 997 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
Anna Bridge 186:707f6e361f3e 998 * @brief RCC clocks control functions
Anna Bridge 186:707f6e361f3e 999 *
Anna Bridge 186:707f6e361f3e 1000 @verbatim
Anna Bridge 186:707f6e361f3e 1001 ===============================================================================
Anna Bridge 186:707f6e361f3e 1002 ##### Peripheral Control functions #####
Anna Bridge 186:707f6e361f3e 1003 ===============================================================================
<> 144:ef7eb2e8f9f7 1004 [..]
<> 144:ef7eb2e8f9f7 1005 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 1006 frequencies.
Anna Bridge 186:707f6e361f3e 1007
Anna Bridge 186:707f6e361f3e 1008 @endverbatim
<> 144:ef7eb2e8f9f7 1009 * @{
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @brief Selects the clock source to output on MCO pin.
<> 144:ef7eb2e8f9f7 1014 * @note MCO pin should be configured in alternate function mode.
Anna Bridge 186:707f6e361f3e 1015 * @param RCC_MCOx specifies the output direction for the clock source.
Anna Bridge 186:707f6e361f3e 1016 * This parameter can be one of the following values:
Anna Bridge 186:707f6e361f3e 1017 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
Anna Bridge 186:707f6e361f3e 1018 * @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA9).
Anna Bridge 186:707f6e361f3e 1019 @if STM32L031xx
Anna Bridge 186:707f6e361f3e 1020 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1021 @elseif STM32L041xx
Anna Bridge 186:707f6e361f3e 1022 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1023 @elseif STM32L073xx
Anna Bridge 186:707f6e361f3e 1024 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1025 @elseif STM32L083xx
Anna Bridge 186:707f6e361f3e 1026 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1027 @elseif STM32L072xx
Anna Bridge 186:707f6e361f3e 1028 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1029 @elseif STM32L082xx
Anna Bridge 186:707f6e361f3e 1030 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1031 @elseif STM32L071xx
Anna Bridge 186:707f6e361f3e 1032 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1033 @elseif STM32L081xx
Anna Bridge 186:707f6e361f3e 1034 * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13)
Anna Bridge 186:707f6e361f3e 1035 @endif
Anna Bridge 186:707f6e361f3e 1036 * @param RCC_MCOSource specifies the clock source to output.
<> 144:ef7eb2e8f9f7 1037 * This parameter can be one of the following values:
Anna Bridge 186:707f6e361f3e 1038 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1039 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1040 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
Anna Bridge 186:707f6e361f3e 1041 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
Anna Bridge 186:707f6e361f3e 1042 * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1043 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1044 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1045 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1046 @if STM32L052xx
Anna Bridge 186:707f6e361f3e 1047 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1048 @elseif STM32L053xx
Anna Bridge 186:707f6e361f3e 1049 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1050 @elseif STM32L062xx
Anna Bridge 186:707f6e361f3e 1051 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1052 @elseif STM32L063xx
Anna Bridge 186:707f6e361f3e 1053 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1054 @elseif STM32L072xx
Anna Bridge 186:707f6e361f3e 1055 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1056 @elseif STM32L073xx
Anna Bridge 186:707f6e361f3e 1057 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1058 @elseif STM32L082xx
Anna Bridge 186:707f6e361f3e 1059 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1060 @elseif STM32L083xx
Anna Bridge 186:707f6e361f3e 1061 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
Anna Bridge 186:707f6e361f3e 1062 @endif
Anna Bridge 186:707f6e361f3e 1063 * @param RCC_MCODiv specifies the MCO DIV.
Anna Bridge 186:707f6e361f3e 1064 * This parameter can be one of the following values:
Anna Bridge 186:707f6e361f3e 1065 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
Anna Bridge 186:707f6e361f3e 1066 * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
Anna Bridge 186:707f6e361f3e 1067 * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
Anna Bridge 186:707f6e361f3e 1068 * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
Anna Bridge 186:707f6e361f3e 1069 * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
<> 144:ef7eb2e8f9f7 1070 * @retval None
<> 144:ef7eb2e8f9f7 1071 */
Anna Bridge 186:707f6e361f3e 1072 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<> 144:ef7eb2e8f9f7 1073 {
Anna Bridge 186:707f6e361f3e 1074 GPIO_InitTypeDef gpio = {0};
Anna Bridge 186:707f6e361f3e 1075
<> 144:ef7eb2e8f9f7 1076 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1077 assert_param(IS_RCC_MCO(RCC_MCOx));
<> 144:ef7eb2e8f9f7 1078 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<> 144:ef7eb2e8f9f7 1079 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
Anna Bridge 186:707f6e361f3e 1080
Anna Bridge 186:707f6e361f3e 1081 /* Configure the MCO1 pin in alternate function mode */
Anna Bridge 186:707f6e361f3e 1082 gpio.Mode = GPIO_MODE_AF_PP;
Anna Bridge 186:707f6e361f3e 1083 gpio.Speed = GPIO_SPEED_FREQ_HIGH;
Anna Bridge 186:707f6e361f3e 1084 gpio.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 1085 if(RCC_MCOx == RCC_MCO1)
<> 144:ef7eb2e8f9f7 1086 {
Anna Bridge 186:707f6e361f3e 1087 gpio.Pin = MCO1_PIN;
Anna Bridge 186:707f6e361f3e 1088 gpio.Alternate = GPIO_AF0_MCO;
Anna Bridge 186:707f6e361f3e 1089
Anna Bridge 186:707f6e361f3e 1090 /* MCO1 Clock Enable */
Anna Bridge 186:707f6e361f3e 1091 MCO1_CLK_ENABLE();
Anna Bridge 186:707f6e361f3e 1092 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
<> 144:ef7eb2e8f9f7 1093 }
Anna Bridge 186:707f6e361f3e 1094 #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \
Anna Bridge 186:707f6e361f3e 1095 || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
Anna Bridge 186:707f6e361f3e 1096 else if (RCC_MCOx == RCC_MCO3)
<> 144:ef7eb2e8f9f7 1097 {
Anna Bridge 186:707f6e361f3e 1098 gpio.Pin = MCO3_PIN;
Anna Bridge 186:707f6e361f3e 1099 gpio.Alternate = GPIO_AF2_MCO;
Anna Bridge 186:707f6e361f3e 1100
Anna Bridge 186:707f6e361f3e 1101 /* MCO3 Clock Enable */
Anna Bridge 186:707f6e361f3e 1102 MCO3_CLK_ENABLE();
Anna Bridge 186:707f6e361f3e 1103 HAL_GPIO_Init(MCO3_GPIO_PORT, &gpio);
<> 144:ef7eb2e8f9f7 1104 }
Anna Bridge 186:707f6e361f3e 1105 #endif
Anna Bridge 186:707f6e361f3e 1106 else
Anna Bridge 186:707f6e361f3e 1107 {
Anna Bridge 186:707f6e361f3e 1108 gpio.Pin = MCO2_PIN;
Anna Bridge 186:707f6e361f3e 1109 gpio.Alternate = GPIO_AF0_MCO;
Anna Bridge 186:707f6e361f3e 1110
Anna Bridge 186:707f6e361f3e 1111 /* MCO2 Clock Enable */
Anna Bridge 186:707f6e361f3e 1112 MCO2_CLK_ENABLE();
Anna Bridge 186:707f6e361f3e 1113 HAL_GPIO_Init(MCO2_GPIO_PORT, &gpio);
Anna Bridge 186:707f6e361f3e 1114 }
Anna Bridge 186:707f6e361f3e 1115
Anna Bridge 186:707f6e361f3e 1116 /* Configure the MCO clock source */
Anna Bridge 186:707f6e361f3e 1117 __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119
Anna Bridge 186:707f6e361f3e 1120 #if defined(RCC_HSECSS_SUPPORT)
<> 144:ef7eb2e8f9f7 1121 /**
<> 144:ef7eb2e8f9f7 1122 * @brief Enables the Clock Security System.
<> 144:ef7eb2e8f9f7 1123 * @note If a failure is detected on the HSE oscillator clock, this oscillator
<> 144:ef7eb2e8f9f7 1124 * is automatically disabled and an interrupt is generated to inform the
<> 144:ef7eb2e8f9f7 1125 * software about the failure (Clock Security System Interrupt, CSSI),
<> 144:ef7eb2e8f9f7 1126 * allowing the MCU to perform rescue operations. The CSSI is linked to
<> 144:ef7eb2e8f9f7 1127 * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 1128 * @retval None
<> 144:ef7eb2e8f9f7 1129 */
<> 144:ef7eb2e8f9f7 1130 void HAL_RCC_EnableCSS(void)
<> 144:ef7eb2e8f9f7 1131 {
Anna Bridge 186:707f6e361f3e 1132 SET_BIT(RCC->CR, RCC_CR_CSSON) ;
<> 144:ef7eb2e8f9f7 1133 }
<> 144:ef7eb2e8f9f7 1134
Anna Bridge 186:707f6e361f3e 1135 #endif /* RCC_HSECSS_SUPPORT */
<> 144:ef7eb2e8f9f7 1136 /**
Anna Bridge 186:707f6e361f3e 1137 * @brief Returns the SYSCLK frequency
<> 144:ef7eb2e8f9f7 1138 * @note The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 1139 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 1140 * constant and the selected clock source:
Anna Bridge 186:707f6e361f3e 1141 * @note If SYSCLK source is MSI, function returns a value based on MSI
<> 144:ef7eb2e8f9f7 1142 * Value as defined by the MSI range.
<> 144:ef7eb2e8f9f7 1143 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
Anna Bridge 186:707f6e361f3e 1144 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**)
Anna Bridge 186:707f6e361f3e 1145 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 1146 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 1147 * @note (*) HSI_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 1148 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 1149 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 1150 * @note (**) HSE_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 1151 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 1152 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 1153 * have wrong result.
<> 144:ef7eb2e8f9f7 1154 *
<> 144:ef7eb2e8f9f7 1155 * @note The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 1156 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 1157 *
<> 144:ef7eb2e8f9f7 1158 * @note This function can be used by the user application to compute the
Anna Bridge 186:707f6e361f3e 1159 * baud-rate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 1160 *
<> 144:ef7eb2e8f9f7 1161 * @note Each time SYSCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1162 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1163 *
<> 144:ef7eb2e8f9f7 1164 * @retval SYSCLK frequency
<> 144:ef7eb2e8f9f7 1165 */
<> 144:ef7eb2e8f9f7 1166 uint32_t HAL_RCC_GetSysClockFreq(void)
<> 144:ef7eb2e8f9f7 1167 {
Anna Bridge 186:707f6e361f3e 1168 uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0;
Anna Bridge 186:707f6e361f3e 1169 uint32_t sysclockfreq = 0;
Anna Bridge 186:707f6e361f3e 1170
Anna Bridge 186:707f6e361f3e 1171 tmpreg = RCC->CFGR;
Anna Bridge 186:707f6e361f3e 1172
<> 144:ef7eb2e8f9f7 1173 /* Get SYSCLK source -------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 1174 switch (tmpreg & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 1175 {
Anna Bridge 186:707f6e361f3e 1176 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 1177 {
Anna Bridge 186:707f6e361f3e 1178 if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
<> 144:ef7eb2e8f9f7 1179 {
Anna Bridge 186:707f6e361f3e 1180 sysclockfreq = (HSI_VALUE >> 2);
<> 144:ef7eb2e8f9f7 1181 }
<> 144:ef7eb2e8f9f7 1182 else
<> 144:ef7eb2e8f9f7 1183 {
<> 144:ef7eb2e8f9f7 1184 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1185 }
<> 144:ef7eb2e8f9f7 1186 break;
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 sysclockfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1191 break;
<> 144:ef7eb2e8f9f7 1192 }
<> 144:ef7eb2e8f9f7 1193 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 1194 {
Anna Bridge 186:707f6e361f3e 1195 pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
Anna Bridge 186:707f6e361f3e 1196 plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1;
Anna Bridge 186:707f6e361f3e 1197 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
<> 144:ef7eb2e8f9f7 1198 {
Anna Bridge 186:707f6e361f3e 1199 /* HSE used as PLL clock source */
Anna Bridge 186:707f6e361f3e 1200 pllvco = (HSE_VALUE * pllm) / plld;
Anna Bridge 186:707f6e361f3e 1201 }
Anna Bridge 186:707f6e361f3e 1202 else
Anna Bridge 186:707f6e361f3e 1203 {
Anna Bridge 186:707f6e361f3e 1204 if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
<> 144:ef7eb2e8f9f7 1205 {
Anna Bridge 186:707f6e361f3e 1206 pllvco = ((HSI_VALUE >> 2) * pllm) / plld;
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208 else
<> 144:ef7eb2e8f9f7 1209 {
Anna Bridge 186:707f6e361f3e 1210 pllvco = (HSI_VALUE * pllm) / plld;
<> 144:ef7eb2e8f9f7 1211 }
<> 144:ef7eb2e8f9f7 1212 }
Anna Bridge 186:707f6e361f3e 1213 sysclockfreq = pllvco;
<> 144:ef7eb2e8f9f7 1214 break;
<> 144:ef7eb2e8f9f7 1215 }
Anna Bridge 186:707f6e361f3e 1216 case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
<> 144:ef7eb2e8f9f7 1217 default: /* MSI used as system clock */
<> 144:ef7eb2e8f9f7 1218 {
Anna Bridge 186:707f6e361f3e 1219 msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_BITNUMBER;
Anna Bridge 186:707f6e361f3e 1220 sysclockfreq = (32768 * (1 << (msiclkrange + 1)));
<> 144:ef7eb2e8f9f7 1221 break;
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223 }
<> 144:ef7eb2e8f9f7 1224 return sysclockfreq;
<> 144:ef7eb2e8f9f7 1225 }
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /**
<> 144:ef7eb2e8f9f7 1228 * @brief Returns the HCLK frequency
<> 144:ef7eb2e8f9f7 1229 * @note Each time HCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1230 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
Anna Bridge 186:707f6e361f3e 1231 *
<> 144:ef7eb2e8f9f7 1232 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
Anna Bridge 186:707f6e361f3e 1233 * and updated within this function
<> 144:ef7eb2e8f9f7 1234 * @retval HCLK frequency
<> 144:ef7eb2e8f9f7 1235 */
<> 144:ef7eb2e8f9f7 1236 uint32_t HAL_RCC_GetHCLKFreq(void)
<> 144:ef7eb2e8f9f7 1237 {
Anna Bridge 186:707f6e361f3e 1238 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /**
<> 144:ef7eb2e8f9f7 1242 * @brief Returns the PCLK1 frequency
<> 144:ef7eb2e8f9f7 1243 * @note Each time PCLK1 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1244 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1245 * @retval PCLK1 frequency
<> 144:ef7eb2e8f9f7 1246 */
<> 144:ef7eb2e8f9f7 1247 uint32_t HAL_RCC_GetPCLK1Freq(void)
<> 144:ef7eb2e8f9f7 1248 {
Anna Bridge 186:707f6e361f3e 1249 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
Anna Bridge 186:707f6e361f3e 1250 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /**
<> 144:ef7eb2e8f9f7 1254 * @brief Returns the PCLK2 frequency
<> 144:ef7eb2e8f9f7 1255 * @note Each time PCLK2 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1256 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1257 * @retval PCLK2 frequency
<> 144:ef7eb2e8f9f7 1258 */
<> 144:ef7eb2e8f9f7 1259 uint32_t HAL_RCC_GetPCLK2Freq(void)
<> 144:ef7eb2e8f9f7 1260 {
Anna Bridge 186:707f6e361f3e 1261 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
Anna Bridge 186:707f6e361f3e 1262 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /**
<> 144:ef7eb2e8f9f7 1266 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1267 * RCC configuration registers.
Anna Bridge 186:707f6e361f3e 1268 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1269 * will be configured.
<> 144:ef7eb2e8f9f7 1270 * @retval None
<> 144:ef7eb2e8f9f7 1271 */
<> 144:ef7eb2e8f9f7 1272 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 1273 {
Anna Bridge 186:707f6e361f3e 1274 /* Check the parameters */
Anna Bridge 186:707f6e361f3e 1275 assert_param(RCC_OscInitStruct != NULL);
Anna Bridge 186:707f6e361f3e 1276
<> 144:ef7eb2e8f9f7 1277 /* Set all possible values for the Oscillator type parameter ---------------*/
Anna Bridge 186:707f6e361f3e 1278 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
Anna Bridge 186:707f6e361f3e 1279 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI;
Anna Bridge 186:707f6e361f3e 1280 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 1281 RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
Anna Bridge 186:707f6e361f3e 1282 #endif /* RCC_HSI48_SUPPORT */
Anna Bridge 186:707f6e361f3e 1283
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /* Get the HSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1286 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<> 144:ef7eb2e8f9f7 1287 {
<> 144:ef7eb2e8f9f7 1288 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<> 144:ef7eb2e8f9f7 1289 }
<> 144:ef7eb2e8f9f7 1290 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<> 144:ef7eb2e8f9f7 1291 {
<> 144:ef7eb2e8f9f7 1292 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294 else
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 1297 }
Anna Bridge 186:707f6e361f3e 1298
Anna Bridge 186:707f6e361f3e 1299 /* Get the HSI configuration -----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 1300 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
Anna Bridge 186:707f6e361f3e 1301 {
Anna Bridge 186:707f6e361f3e 1302 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
Anna Bridge 186:707f6e361f3e 1303 }
Anna Bridge 186:707f6e361f3e 1304 else
Anna Bridge 186:707f6e361f3e 1305 {
Anna Bridge 186:707f6e361f3e 1306 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
Anna Bridge 186:707f6e361f3e 1307 }
Anna Bridge 186:707f6e361f3e 1308
Anna Bridge 186:707f6e361f3e 1309 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> 8);
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 /* Get the MSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1312 if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION)
<> 144:ef7eb2e8f9f7 1313 {
<> 144:ef7eb2e8f9f7 1314 RCC_OscInitStruct->MSIState = RCC_MSI_ON;
<> 144:ef7eb2e8f9f7 1315 }
<> 144:ef7eb2e8f9f7 1316 else
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
<> 144:ef7eb2e8f9f7 1319 }
<> 144:ef7eb2e8f9f7 1320
Anna Bridge 186:707f6e361f3e 1321 RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_BITNUMBER);
Anna Bridge 186:707f6e361f3e 1322 RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE));
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Get the LSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1325 if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)
<> 144:ef7eb2e8f9f7 1326 {
<> 144:ef7eb2e8f9f7 1327 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329 else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON)
<> 144:ef7eb2e8f9f7 1330 {
<> 144:ef7eb2e8f9f7 1331 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333 else
<> 144:ef7eb2e8f9f7 1334 {
<> 144:ef7eb2e8f9f7 1335 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 1336 }
<> 144:ef7eb2e8f9f7 1337
<> 144:ef7eb2e8f9f7 1338 /* Get the LSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1339 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1340 {
<> 144:ef7eb2e8f9f7 1341 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<> 144:ef7eb2e8f9f7 1342 }
<> 144:ef7eb2e8f9f7 1343 else
<> 144:ef7eb2e8f9f7 1344 {
<> 144:ef7eb2e8f9f7 1345 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 1346 }
<> 144:ef7eb2e8f9f7 1347
Anna Bridge 186:707f6e361f3e 1348 #if defined(RCC_HSI48_SUPPORT)
Anna Bridge 186:707f6e361f3e 1349 /* Get the HSI48 configuration if any-----------------------------------------*/
Anna Bridge 186:707f6e361f3e 1350 RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
Anna Bridge 186:707f6e361f3e 1351 #endif /* RCC_HSI48_SUPPORT */
Anna Bridge 186:707f6e361f3e 1352
<> 144:ef7eb2e8f9f7 1353 /* Get the PLL configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1354 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1355 {
<> 144:ef7eb2e8f9f7 1356 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358 else
<> 144:ef7eb2e8f9f7 1359 {
<> 144:ef7eb2e8f9f7 1360 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
Anna Bridge 186:707f6e361f3e 1363 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
Anna Bridge 186:707f6e361f3e 1364 RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV);
<> 144:ef7eb2e8f9f7 1365 }
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /**
Anna Bridge 186:707f6e361f3e 1368 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1369 * RCC configuration registers.
Anna Bridge 186:707f6e361f3e 1370 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
Anna Bridge 186:707f6e361f3e 1371 * contains the current clock configuration.
Anna Bridge 186:707f6e361f3e 1372 * @param pFLatency Pointer on the Flash Latency.
<> 144:ef7eb2e8f9f7 1373 * @retval None
<> 144:ef7eb2e8f9f7 1374 */
<> 144:ef7eb2e8f9f7 1375 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
<> 144:ef7eb2e8f9f7 1376 {
Anna Bridge 186:707f6e361f3e 1377 /* Check the parameters */
Anna Bridge 186:707f6e361f3e 1378 assert_param(RCC_ClkInitStruct != NULL);
Anna Bridge 186:707f6e361f3e 1379 assert_param(pFLatency != NULL);
Anna Bridge 186:707f6e361f3e 1380
<> 144:ef7eb2e8f9f7 1381 /* Set all possible values for the Clock type parameter --------------------*/
<> 144:ef7eb2e8f9f7 1382 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
Anna Bridge 186:707f6e361f3e 1383
<> 144:ef7eb2e8f9f7 1384 /* Get the SYSCLK configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1385 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Get the HCLK configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1388 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Get the APB1 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1391 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /* Get the APB2 configuration ----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 1394 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Get the Flash Wait State (Latency) configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1397 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399
Anna Bridge 186:707f6e361f3e 1400 #if defined(RCC_HSECSS_SUPPORT)
<> 144:ef7eb2e8f9f7 1401 /**
<> 144:ef7eb2e8f9f7 1402 * @brief This function handles the RCC CSS interrupt request.
<> 144:ef7eb2e8f9f7 1403 * @note This API should be called under the NMI_Handler().
<> 144:ef7eb2e8f9f7 1404 * @retval None
<> 144:ef7eb2e8f9f7 1405 */
<> 144:ef7eb2e8f9f7 1406 void HAL_RCC_NMI_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1407 {
<> 144:ef7eb2e8f9f7 1408 /* Check RCC CSSF flag */
Anna Bridge 186:707f6e361f3e 1409 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 /* RCC Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 1412 HAL_RCC_CSSCallback();
Anna Bridge 186:707f6e361f3e 1413
<> 144:ef7eb2e8f9f7 1414 /* Clear RCC CSS pending bit */
Anna Bridge 186:707f6e361f3e 1415 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<> 144:ef7eb2e8f9f7 1416 }
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 /**
<> 144:ef7eb2e8f9f7 1420 * @brief RCC Clock Security System interrupt callback
Anna Bridge 186:707f6e361f3e 1421 * @retval none
<> 144:ef7eb2e8f9f7 1422 */
<> 144:ef7eb2e8f9f7 1423 __weak void HAL_RCC_CSSCallback(void)
<> 144:ef7eb2e8f9f7 1424 {
<> 144:ef7eb2e8f9f7 1425 /* NOTE : This function Should not be modified, when the callback is needed,
Anna Bridge 186:707f6e361f3e 1426 the HAL_RCC_CSSCallback could be implemented in the user file
Anna Bridge 186:707f6e361f3e 1427 */
<> 144:ef7eb2e8f9f7 1428 }
<> 144:ef7eb2e8f9f7 1429
Anna Bridge 186:707f6e361f3e 1430 #endif /* RCC_HSECSS_SUPPORT */
<> 144:ef7eb2e8f9f7 1431 /**
<> 144:ef7eb2e8f9f7 1432 * @}
<> 144:ef7eb2e8f9f7 1433 */
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /**
<> 144:ef7eb2e8f9f7 1436 * @}
<> 144:ef7eb2e8f9f7 1437 */
<> 144:ef7eb2e8f9f7 1438
Anna Bridge 186:707f6e361f3e 1439 /* Private function prototypes -----------------------------------------------*/
Anna Bridge 186:707f6e361f3e 1440 /** @addtogroup RCC_Private_Functions
Anna Bridge 186:707f6e361f3e 1441 * @{
Anna Bridge 186:707f6e361f3e 1442 */
Anna Bridge 186:707f6e361f3e 1443 /**
Anna Bridge 186:707f6e361f3e 1444 * @brief Update number of Flash wait states in line with MSI range and current
Anna Bridge 186:707f6e361f3e 1445 voltage range
Anna Bridge 186:707f6e361f3e 1446 * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
Anna Bridge 186:707f6e361f3e 1447 * @retval HAL status
Anna Bridge 186:707f6e361f3e 1448 */
Anna Bridge 186:707f6e361f3e 1449 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
Anna Bridge 186:707f6e361f3e 1450 {
Anna Bridge 186:707f6e361f3e 1451 uint32_t vos = 0;
Anna Bridge 186:707f6e361f3e 1452 uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
Anna Bridge 186:707f6e361f3e 1453
Anna Bridge 186:707f6e361f3e 1454 /* HCLK can reach 4 MHz only if AHB prescaler = 1 */
Anna Bridge 186:707f6e361f3e 1455 if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
Anna Bridge 186:707f6e361f3e 1456 {
Anna Bridge 186:707f6e361f3e 1457 if(__HAL_RCC_PWR_IS_CLK_ENABLED())
Anna Bridge 186:707f6e361f3e 1458 {
Anna Bridge 186:707f6e361f3e 1459 vos = READ_BIT(PWR->CR, PWR_CR_VOS);
Anna Bridge 186:707f6e361f3e 1460 }
Anna Bridge 186:707f6e361f3e 1461 else
Anna Bridge 186:707f6e361f3e 1462 {
Anna Bridge 186:707f6e361f3e 1463 __HAL_RCC_PWR_CLK_ENABLE();
Anna Bridge 186:707f6e361f3e 1464 vos = READ_BIT(PWR->CR, PWR_CR_VOS);
Anna Bridge 186:707f6e361f3e 1465 __HAL_RCC_PWR_CLK_DISABLE();
Anna Bridge 186:707f6e361f3e 1466 }
Anna Bridge 186:707f6e361f3e 1467
Anna Bridge 186:707f6e361f3e 1468 /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
Anna Bridge 186:707f6e361f3e 1469 if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
Anna Bridge 186:707f6e361f3e 1470 {
Anna Bridge 186:707f6e361f3e 1471 latency = FLASH_LATENCY_1; /* 1WS */
Anna Bridge 186:707f6e361f3e 1472 }
Anna Bridge 186:707f6e361f3e 1473 }
Anna Bridge 186:707f6e361f3e 1474
Anna Bridge 186:707f6e361f3e 1475 __HAL_FLASH_SET_LATENCY(latency);
Anna Bridge 186:707f6e361f3e 1476
Anna Bridge 186:707f6e361f3e 1477 /* Check that the new number of wait states is taken into account to access the Flash
Anna Bridge 186:707f6e361f3e 1478 memory by reading the FLASH_ACR register */
Anna Bridge 186:707f6e361f3e 1479 if((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
Anna Bridge 186:707f6e361f3e 1480 {
Anna Bridge 186:707f6e361f3e 1481 return HAL_ERROR;
Anna Bridge 186:707f6e361f3e 1482 }
Anna Bridge 186:707f6e361f3e 1483
Anna Bridge 186:707f6e361f3e 1484 return HAL_OK;
Anna Bridge 186:707f6e361f3e 1485 }
Anna Bridge 186:707f6e361f3e 1486
Anna Bridge 186:707f6e361f3e 1487 /**
Anna Bridge 186:707f6e361f3e 1488 * @}
Anna Bridge 186:707f6e361f3e 1489 */
Anna Bridge 186:707f6e361f3e 1490
<> 144:ef7eb2e8f9f7 1491 #endif /* HAL_RCC_MODULE_ENABLED */
Anna Bridge 186:707f6e361f3e 1492 /**
Anna Bridge 186:707f6e361f3e 1493 * @}
Anna Bridge 186:707f6e361f3e 1494 */
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 /**
<> 144:ef7eb2e8f9f7 1497 * @}
<> 144:ef7eb2e8f9f7 1498 */
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/