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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 186:707f6e361f3e

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_lptim.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief Header file of LPTIM HAL module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
<>	144:ef7eb2e8f9f7	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	37	#ifndef __STM32L0xx_HAL_LPTIM_H
<>	144:ef7eb2e8f9f7	38	#define __STM32L0xx_HAL_LPTIM_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	45	#include "stm32l0xx_hal_def.h"
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	48	* @{
<>	144:ef7eb2e8f9f7	49	*/
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	/** @defgroup LPTIM LPTIM (Low power timer)
<>	144:ef7eb2e8f9f7	52	* @{
<>	144:ef7eb2e8f9f7	53	*/
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	56	/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
<>	144:ef7eb2e8f9f7	57	* @{
<>	144:ef7eb2e8f9f7	58	*/
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	/** @defgroup LPTIM_Clock_Configuration LPTIM Clock configuration structure
<>	144:ef7eb2e8f9f7	61	* @{
<>	144:ef7eb2e8f9f7	62	*/
<>	151:5eaa88a5bcc7	63	#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM29) /!< External interrupt line 29 Connected to the LPTIM EXTI Line /
<>	151:5eaa88a5bcc7	64
<>	144:ef7eb2e8f9f7	65	/**
<>	144:ef7eb2e8f9f7	66	* @brief LPTIM Clock configuration definition
<>	144:ef7eb2e8f9f7	67	*/
<>	144:ef7eb2e8f9f7	68	typedef struct
<>	144:ef7eb2e8f9f7	69	{
<>	144:ef7eb2e8f9f7	70	uint32_t Source; /*!< Selects the clock source.
<>	144:ef7eb2e8f9f7	71	This parameter can be a value of @ref LPTIM_Clock_Source */
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
<>	144:ef7eb2e8f9f7	74	This parameter can be a value of @ref LPTIM_Clock_Prescaler */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	}LPTIM_ClockConfigTypeDef;
<>	144:ef7eb2e8f9f7	77	/**
<>	144:ef7eb2e8f9f7	78	* @}
<>	144:ef7eb2e8f9f7	79	*/
<>	144:ef7eb2e8f9f7	80
<>	144:ef7eb2e8f9f7	81	/** @defgroup LPTIM_ULPClock_Configuration LPTIM ULP Clock configuration structure
<>	144:ef7eb2e8f9f7	82	* @{
<>	144:ef7eb2e8f9f7	83	*/
<>	144:ef7eb2e8f9f7	84	/**
<>	144:ef7eb2e8f9f7	85	* @brief LPTIM ULP Clock configuration definition
<>	144:ef7eb2e8f9f7	86	*/
<>	144:ef7eb2e8f9f7	87	typedef struct
<>	144:ef7eb2e8f9f7	88	{
<>	144:ef7eb2e8f9f7	89	uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
<>	144:ef7eb2e8f9f7	90	if the ULPTIM input is selected.
<>	144:ef7eb2e8f9f7	91	Note: This parameter is used only when Ultra low power clock source is used.
<>	144:ef7eb2e8f9f7	92	Note: If the polarity is configured on 'both edges', an auxiliary clock
<>	144:ef7eb2e8f9f7	93	(one of the Low power oscillator) must be active.
<>	144:ef7eb2e8f9f7	94	This parameter can be a value of @ref LPTIM_Clock_Polarity */
<>	144:ef7eb2e8f9f7	95
<>	144:ef7eb2e8f9f7	96	uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
<>	144:ef7eb2e8f9f7	97	Note: This parameter is used only when Ultra low power clock source is used.
<>	144:ef7eb2e8f9f7	98	This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	}LPTIM_ULPClockConfigTypeDef;
<>	144:ef7eb2e8f9f7	101	/**
<>	144:ef7eb2e8f9f7	102	* @}
<>	144:ef7eb2e8f9f7	103	*/
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	/** @defgroup LPTIM_Trigger_Configuration LPTIM Trigger configuration structure
<>	144:ef7eb2e8f9f7	106	* @{
<>	144:ef7eb2e8f9f7	107	*/
<>	144:ef7eb2e8f9f7	108	/**
<>	144:ef7eb2e8f9f7	109	* @brief LPTIM Trigger configuration structure
<>	144:ef7eb2e8f9f7	110	*/
<>	144:ef7eb2e8f9f7	111	typedef struct
<>	144:ef7eb2e8f9f7	112	{
<>	144:ef7eb2e8f9f7	113	uint32_t Source; /*!< Selects the Trigger source.
Anna Bridge	186:707f6e361f3e	114	This parameter can be a value of @ref LPTIM_Trigger_Source */
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
<>	144:ef7eb2e8f9f7	117	Note: This parameter is used only when an external trigger is used.
<>	144:ef7eb2e8f9f7	118	This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
<>	144:ef7eb2e8f9f7	119
<>	144:ef7eb2e8f9f7	120	uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
<>	144:ef7eb2e8f9f7	121	Note: This parameter is used only when an external trigger is used.
<>	144:ef7eb2e8f9f7	122	This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
<>	144:ef7eb2e8f9f7	123	}LPTIM_TriggerConfigTypeDef;
<>	144:ef7eb2e8f9f7	124	/**
<>	144:ef7eb2e8f9f7	125	* @}
<>	144:ef7eb2e8f9f7	126	*/
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	/** @defgroup LPTIM_Init_Configuration LPTIM Initialization configuration structure
<>	144:ef7eb2e8f9f7	129	* @{
<>	144:ef7eb2e8f9f7	130	*/
<>	144:ef7eb2e8f9f7	131	/**
<>	144:ef7eb2e8f9f7	132	* @brief LPTIM Initialization Structure definition
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134	typedef struct
<>	144:ef7eb2e8f9f7	135	{
<>	144:ef7eb2e8f9f7	136	LPTIM_ClockConfigTypeDef Clock; /!< Specifies the clock parameters /
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /!< Specifies the Ultra Low Power clock parameters /
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	LPTIM_TriggerConfigTypeDef Trigger; /!< Specifies the Trigger parameters /
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	uint32_t OutputPolarity; /*!< Specifies the Output polarity.
<>	144:ef7eb2e8f9f7	143	This parameter can be a value of @ref LPTIM_Output_Polarity */
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
<>	144:ef7eb2e8f9f7	146	values is done immediately or after the end of current period.
<>	144:ef7eb2e8f9f7	147	This parameter can be a value of @ref LPTIM_Updating_Mode */
<>	144:ef7eb2e8f9f7	148
<>	144:ef7eb2e8f9f7	149	uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
<>	144:ef7eb2e8f9f7	150	or each external event.
<>	144:ef7eb2e8f9f7	151	This parameter can be a value of @ref LPTIM_Counter_Source */
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	}LPTIM_InitTypeDef;
<>	144:ef7eb2e8f9f7	154	/**
<>	144:ef7eb2e8f9f7	155	* @}
<>	144:ef7eb2e8f9f7	156	*/
<>	144:ef7eb2e8f9f7	157	/** @defgroup LPTIM_State_structure LPTIM state definition
<>	144:ef7eb2e8f9f7	158	* @{
<>	144:ef7eb2e8f9f7	159	*/
<>	144:ef7eb2e8f9f7	160	/**
<>	144:ef7eb2e8f9f7	161	* @brief HAL LPTIM State structure definition
<>	144:ef7eb2e8f9f7	162	*/
<>	144:ef7eb2e8f9f7	163	typedef enum __HAL_LPTIM_StateTypeDef
<>	144:ef7eb2e8f9f7	164	{
<>	151:5eaa88a5bcc7	165	HAL_LPTIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
<>	151:5eaa88a5bcc7	166	HAL_LPTIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
<>	151:5eaa88a5bcc7	167	HAL_LPTIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
<>	151:5eaa88a5bcc7	168	HAL_LPTIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
<>	151:5eaa88a5bcc7	169	HAL_LPTIM_STATE_ERROR = 0x04U /!< Internal Process is ongoing /
<>	144:ef7eb2e8f9f7	170	}HAL_LPTIM_StateTypeDef;
<>	144:ef7eb2e8f9f7	171	/**
<>	144:ef7eb2e8f9f7	172	* @}
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	/** @defgroup LPTIM_Handle LPTIM handler
<>	144:ef7eb2e8f9f7	176	* @{
<>	144:ef7eb2e8f9f7	177	*/
<>	144:ef7eb2e8f9f7	178	/**
<>	144:ef7eb2e8f9f7	179	* @brief LPTIM handle Structure definition
<>	144:ef7eb2e8f9f7	180	*/
<>	144:ef7eb2e8f9f7	181	typedef struct
<>	144:ef7eb2e8f9f7	182	{
<>	144:ef7eb2e8f9f7	183	LPTIM_TypeDef Instance; /!< Register base address */
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	LPTIM_InitTypeDef Init; /!< LPTIM required parameters /
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	HAL_StatusTypeDef Status; /!< LPTIM peripheral status /
<>	144:ef7eb2e8f9f7	188
<>	144:ef7eb2e8f9f7	189	HAL_LockTypeDef Lock; /!< LPTIM locking object /
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	__IO HAL_LPTIM_StateTypeDef State; /!< LPTIM peripheral state /
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	}LPTIM_HandleTypeDef;
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	/**
<>	144:ef7eb2e8f9f7	196	* @}
<>	144:ef7eb2e8f9f7	197	*/
<>	144:ef7eb2e8f9f7	198	/**
<>	144:ef7eb2e8f9f7	199	* @}
<>	144:ef7eb2e8f9f7	200	*/
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	203
<>	144:ef7eb2e8f9f7	204	/** @defgroup LPTIM_Exported_Constants LPTIM Exported constants
<>	144:ef7eb2e8f9f7	205	* @{
<>	144:ef7eb2e8f9f7	206	*/
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208	/* Check autoreload value */
<>	151:5eaa88a5bcc7	209	#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211	/* Check compare value */
<>	151:5eaa88a5bcc7	212	#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	/** @defgroup LPTIM_Clock_Source Clock source
<>	144:ef7eb2e8f9f7	215	* @{
<>	144:ef7eb2e8f9f7	216	*/
<>	151:5eaa88a5bcc7	217	#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
<>	144:ef7eb2e8f9f7	218	#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
<>	144:ef7eb2e8f9f7	219	/**
<>	144:ef7eb2e8f9f7	220	* @}
<>	144:ef7eb2e8f9f7	221	*/
<>	144:ef7eb2e8f9f7	222	#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) \|\| \
<>	144:ef7eb2e8f9f7	223	((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
<>	144:ef7eb2e8f9f7	224
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226	/** @defgroup LPTIM_Clock_Prescaler Prescaler
<>	144:ef7eb2e8f9f7	227	* @{
<>	144:ef7eb2e8f9f7	228	*/
<>	151:5eaa88a5bcc7	229	#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
<>	144:ef7eb2e8f9f7	230	#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
<>	144:ef7eb2e8f9f7	231	#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
<>	144:ef7eb2e8f9f7	232	#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 \| LPTIM_CFGR_PRESC_1))
<>	144:ef7eb2e8f9f7	233	#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
<>	144:ef7eb2e8f9f7	234	#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 \| LPTIM_CFGR_PRESC_2))
<>	144:ef7eb2e8f9f7	235	#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 \| LPTIM_CFGR_PRESC_2))
<>	144:ef7eb2e8f9f7	236	#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
<>	144:ef7eb2e8f9f7	237	/**
<>	144:ef7eb2e8f9f7	238	* @}
<>	144:ef7eb2e8f9f7	239	*/
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) \|\| \
<>	144:ef7eb2e8f9f7	242	((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) \|\| \
<>	144:ef7eb2e8f9f7	243	((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) \|\| \
<>	144:ef7eb2e8f9f7	244	((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) \|\| \
<>	144:ef7eb2e8f9f7	245	((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) \|\| \
<>	144:ef7eb2e8f9f7	246	((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) \|\| \
<>	144:ef7eb2e8f9f7	247	((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) \|\| \
<>	144:ef7eb2e8f9f7	248	((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
<>	144:ef7eb2e8f9f7	249
<>	144:ef7eb2e8f9f7	250	#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252
<>	144:ef7eb2e8f9f7	253	/** @defgroup LPTIM_Output_Polarity Output polarity
<>	144:ef7eb2e8f9f7	254	* @{
<>	144:ef7eb2e8f9f7	255	*/
<>	151:5eaa88a5bcc7	256	#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	257	#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
<>	144:ef7eb2e8f9f7	258	/**
<>	144:ef7eb2e8f9f7	259	* @}
<>	144:ef7eb2e8f9f7	260	*/
<>	144:ef7eb2e8f9f7	261	#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) \|\| \
<>	144:ef7eb2e8f9f7	262	((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/** @defgroup LPTIM_Clock_Sample_Time Clock sample time
<>	144:ef7eb2e8f9f7	265	* @{
<>	144:ef7eb2e8f9f7	266	*/
<>	151:5eaa88a5bcc7	267	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	268	#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
<>	144:ef7eb2e8f9f7	269	#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
<>	144:ef7eb2e8f9f7	270	#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
<>	144:ef7eb2e8f9f7	271	/**
<>	144:ef7eb2e8f9f7	272	* @}
<>	144:ef7eb2e8f9f7	273	*/
<>	144:ef7eb2e8f9f7	274	#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) \|\| \
<>	144:ef7eb2e8f9f7	275	((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) \|\| \
<>	144:ef7eb2e8f9f7	276	((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) \|\| \
<>	144:ef7eb2e8f9f7	277	((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
<>	144:ef7eb2e8f9f7	278
<>	144:ef7eb2e8f9f7	279	/** @defgroup LPTIM_Clock_Polarity Clock polarity
<>	144:ef7eb2e8f9f7	280	* @{
<>	144:ef7eb2e8f9f7	281	*/
<>	151:5eaa88a5bcc7	282	#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	283	#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
<>	144:ef7eb2e8f9f7	284	#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
<>	144:ef7eb2e8f9f7	285	/**
<>	144:ef7eb2e8f9f7	286	* @}
<>	144:ef7eb2e8f9f7	287	*/
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) \|\| \
<>	144:ef7eb2e8f9f7	290	((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	291	((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/** @defgroup LPTIM_External_Trigger_Polarity Trigger polarity
<>	144:ef7eb2e8f9f7	294	* @{
<>	144:ef7eb2e8f9f7	295	*/
<>	144:ef7eb2e8f9f7	296	#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
<>	144:ef7eb2e8f9f7	297	#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
<>	144:ef7eb2e8f9f7	298	#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
<>	144:ef7eb2e8f9f7	299	/**
<>	144:ef7eb2e8f9f7	300	* @}
<>	144:ef7eb2e8f9f7	301	*/
<>	144:ef7eb2e8f9f7	302	#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) \|\| \
<>	144:ef7eb2e8f9f7	303	((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) \|\| \
<>	144:ef7eb2e8f9f7	304	((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306	/** @defgroup LPTIM_Trigger_Sample_Time Trigger sample time
<>	144:ef7eb2e8f9f7	307	* @{
<>	144:ef7eb2e8f9f7	308	*/
<>	151:5eaa88a5bcc7	309	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	310	#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
<>	144:ef7eb2e8f9f7	311	#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
<>	144:ef7eb2e8f9f7	312	#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
<>	144:ef7eb2e8f9f7	313	/**
<>	144:ef7eb2e8f9f7	314	* @}
<>	144:ef7eb2e8f9f7	315	*/
<>	144:ef7eb2e8f9f7	316	#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ) \|\| \
<>	144:ef7eb2e8f9f7	317	((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) \|\| \
<>	144:ef7eb2e8f9f7	318	((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) \|\| \
<>	144:ef7eb2e8f9f7	319	((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321
<>	144:ef7eb2e8f9f7	322	/** @defgroup LPTIM_Updating_Mode Updating mode
<>	144:ef7eb2e8f9f7	323	* @{
<>	144:ef7eb2e8f9f7	324	*/
<>	144:ef7eb2e8f9f7	325
<>	151:5eaa88a5bcc7	326	#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	327	#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
<>	144:ef7eb2e8f9f7	328	/**
<>	144:ef7eb2e8f9f7	329	* @}
<>	144:ef7eb2e8f9f7	330	*/
<>	144:ef7eb2e8f9f7	331	#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) \|\| \
<>	144:ef7eb2e8f9f7	332	((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/** @defgroup LPTIM_Counter_Source Counter source
<>	144:ef7eb2e8f9f7	337	* @{
<>	144:ef7eb2e8f9f7	338	*/
<>	151:5eaa88a5bcc7	339	#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	340	#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
<>	144:ef7eb2e8f9f7	341	/**
<>	144:ef7eb2e8f9f7	342	* @}
<>	144:ef7eb2e8f9f7	343	*/
<>	144:ef7eb2e8f9f7	344	#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) \|\| \
<>	144:ef7eb2e8f9f7	345	((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	/* Check for period value */
<>	151:5eaa88a5bcc7	350	#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFU)
<>	144:ef7eb2e8f9f7	351
<>	144:ef7eb2e8f9f7	352	/* Check for pulse value */
<>	151:5eaa88a5bcc7	353	#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFU)
<>	144:ef7eb2e8f9f7	354
<>	144:ef7eb2e8f9f7	355	/** @defgroup LPTIM_Flag_Definition Flag definition
<>	144:ef7eb2e8f9f7	356	* @{
<>	144:ef7eb2e8f9f7	357	*/
<>	144:ef7eb2e8f9f7	358	#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
<>	144:ef7eb2e8f9f7	359	#define LPTIM_FLAG_UP LPTIM_ISR_UP
<>	144:ef7eb2e8f9f7	360	#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
<>	144:ef7eb2e8f9f7	361	#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
<>	144:ef7eb2e8f9f7	362	#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
<>	144:ef7eb2e8f9f7	363	#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
<>	144:ef7eb2e8f9f7	364	#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
<>	144:ef7eb2e8f9f7	365	/**
<>	144:ef7eb2e8f9f7	366	* @}
<>	144:ef7eb2e8f9f7	367	*/
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/** @defgroup LPTIM_Interrupts_Definition Interrupts definition
<>	144:ef7eb2e8f9f7	370	* @{
<>	144:ef7eb2e8f9f7	371	*/
<>	144:ef7eb2e8f9f7	372	#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
<>	144:ef7eb2e8f9f7	373	#define LPTIM_IT_UP LPTIM_IER_UPIE
<>	144:ef7eb2e8f9f7	374	#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
<>	144:ef7eb2e8f9f7	375	#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
<>	144:ef7eb2e8f9f7	376	#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
<>	144:ef7eb2e8f9f7	377	#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
<>	144:ef7eb2e8f9f7	378	#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
<>	144:ef7eb2e8f9f7	379	/**
<>	144:ef7eb2e8f9f7	380	* @}
<>	144:ef7eb2e8f9f7	381	*/
<>	144:ef7eb2e8f9f7	382
<>	144:ef7eb2e8f9f7	383	/**
<>	144:ef7eb2e8f9f7	384	* @}
<>	144:ef7eb2e8f9f7	385	*/
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
<>	144:ef7eb2e8f9f7	390	* @{
<>	144:ef7eb2e8f9f7	391	*/
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	/** @brief Reset LPTIM handle state
<>	144:ef7eb2e8f9f7	394	* @param __HANDLE__: LPTIM handle
<>	144:ef7eb2e8f9f7	395	* @retval None
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397	#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	398
<>	144:ef7eb2e8f9f7	399	/**
<>	144:ef7eb2e8f9f7	400	* @brief Enable/Disable the LPTIM peripheral.
<>	144:ef7eb2e8f9f7	401	* @param __HANDLE__: LPTIM handle
<>	144:ef7eb2e8f9f7	402	* @retval None
<>	144:ef7eb2e8f9f7	403	*/
<>	144:ef7eb2e8f9f7	404	#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= (LPTIM_CR_ENABLE))
<>	144:ef7eb2e8f9f7	405	#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
<>	144:ef7eb2e8f9f7	406
<>	144:ef7eb2e8f9f7	407	/**
<>	144:ef7eb2e8f9f7	408	* @brief Starts the LPTIM peripheral in Continuous or in single mode.
<>	144:ef7eb2e8f9f7	409	* @param __HANDLE__: DMA handle
<>	144:ef7eb2e8f9f7	410	* @retval None
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412	#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR \|= LPTIM_CR_CNTSTRT)
<>	144:ef7eb2e8f9f7	413	#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= LPTIM_CR_SNGSTRT)
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/**
<>	144:ef7eb2e8f9f7	417	* @brief Writes the passed parameter in the Autoreload register.
<>	144:ef7eb2e8f9f7	418	* @param __HANDLE__: LPTIM handle
<>	144:ef7eb2e8f9f7	419	* @param __VALUE__ : Autoreload value
<>	144:ef7eb2e8f9f7	420	* @retval None
<>	144:ef7eb2e8f9f7	421	*/
<>	144:ef7eb2e8f9f7	422	#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/**
<>	144:ef7eb2e8f9f7	425	* @brief Writes the passed parameter in the Compare register.
<>	144:ef7eb2e8f9f7	426	* @param __HANDLE__: LPTIM handle
<>	144:ef7eb2e8f9f7	427	* @param __VALUE__ : Compare value
<>	144:ef7eb2e8f9f7	428	* @retval None
<>	144:ef7eb2e8f9f7	429	*/
<>	144:ef7eb2e8f9f7	430	#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/**
<>	144:ef7eb2e8f9f7	433	* @brief Checks whether the specified LPTIM flag is set or not.
<>	144:ef7eb2e8f9f7	434	* @param __HANDLE__: LPTIM handle
<>	144:ef7eb2e8f9f7	435	* @param __FLAG__ : LPTIM flag to check
<>	144:ef7eb2e8f9f7	436	* This parameter can be a value of:
<>	144:ef7eb2e8f9f7	437	* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
<>	144:ef7eb2e8f9f7	438	* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
<>	144:ef7eb2e8f9f7	439	* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
<>	144:ef7eb2e8f9f7	440	* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
<>	144:ef7eb2e8f9f7	441	* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
<>	144:ef7eb2e8f9f7	442	* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
<>	144:ef7eb2e8f9f7	443	* @arg LPTIM_FLAG_CMPM : Compare match Flag.
<>	144:ef7eb2e8f9f7	444	* @retval The state of the specified flag (SET or RESET).
<>	144:ef7eb2e8f9f7	445	*/
<>	144:ef7eb2e8f9f7	446	#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	/**
<>	144:ef7eb2e8f9f7	449	* @brief Clears the specified LPTIM flag.
<>	144:ef7eb2e8f9f7	450	* @param __HANDLE__: LPTIM handle.
<>	144:ef7eb2e8f9f7	451	* @param __FLAG__ : LPTIM flag to clear.
<>	144:ef7eb2e8f9f7	452	* This parameter can be a value of:
<>	144:ef7eb2e8f9f7	453	* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
<>	144:ef7eb2e8f9f7	454	* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
<>	144:ef7eb2e8f9f7	455	* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
<>	144:ef7eb2e8f9f7	456	* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
<>	144:ef7eb2e8f9f7	457	* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
<>	144:ef7eb2e8f9f7	458	* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
<>	144:ef7eb2e8f9f7	459	* @arg LPTIM_FLAG_CMPM : Compare match Flag.
<>	144:ef7eb2e8f9f7	460	* @retval None.
<>	144:ef7eb2e8f9f7	461	*/
<>	144:ef7eb2e8f9f7	462	#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	/**
<>	144:ef7eb2e8f9f7	465	* @brief Enable the specified LPTIM interrupt.
<>	144:ef7eb2e8f9f7	466	* @param __HANDLE__ : LPTIM handle.
<>	144:ef7eb2e8f9f7	467	* @param __INTERRUPT__ : LPTIM interrupt to set.
<>	144:ef7eb2e8f9f7	468	* This parameter can be a value of:
<>	144:ef7eb2e8f9f7	469	* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
<>	144:ef7eb2e8f9f7	470	* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
<>	144:ef7eb2e8f9f7	471	* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
<>	144:ef7eb2e8f9f7	472	* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
<>	144:ef7eb2e8f9f7	473	* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
<>	144:ef7eb2e8f9f7	474	* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
<>	144:ef7eb2e8f9f7	475	* @arg LPTIM_IT_CMPM : Compare match Interrupt.
<>	144:ef7eb2e8f9f7	476	* @retval None.
<>	144:ef7eb2e8f9f7	477	*/
<>	144:ef7eb2e8f9f7	478	#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/**
<>	144:ef7eb2e8f9f7	481	* @brief Disable the specified LPTIM interrupt.
<>	144:ef7eb2e8f9f7	482	* @param __HANDLE__ : LPTIM handle.
<>	144:ef7eb2e8f9f7	483	* @param __INTERRUPT__ : LPTIM interrupt to set.
<>	144:ef7eb2e8f9f7	484	* This parameter can be a value of:
<>	144:ef7eb2e8f9f7	485	* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
<>	144:ef7eb2e8f9f7	486	* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
<>	144:ef7eb2e8f9f7	487	* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
<>	144:ef7eb2e8f9f7	488	* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
<>	144:ef7eb2e8f9f7	489	* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
<>	144:ef7eb2e8f9f7	490	* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
<>	144:ef7eb2e8f9f7	491	* @arg LPTIM_IT_CMPM : Compare match Interrupt.
<>	144:ef7eb2e8f9f7	492	* @retval None.
<>	144:ef7eb2e8f9f7	493	*/
<>	144:ef7eb2e8f9f7	494	#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	495
<>	144:ef7eb2e8f9f7	496	/**
<>	144:ef7eb2e8f9f7	497	* @brief Checks whether the specified LPTIM interrupt is set or not.
<>	144:ef7eb2e8f9f7	498	* @param __HANDLE__ : LPTIM handle.
<>	144:ef7eb2e8f9f7	499	* @param __INTERRUPT__ : LPTIM interrupt to check.
<>	144:ef7eb2e8f9f7	500	* This parameter can be a value of:
<>	144:ef7eb2e8f9f7	501	* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
<>	144:ef7eb2e8f9f7	502	* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
<>	144:ef7eb2e8f9f7	503	* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
<>	144:ef7eb2e8f9f7	504	* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
<>	144:ef7eb2e8f9f7	505	* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
<>	144:ef7eb2e8f9f7	506	* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
<>	144:ef7eb2e8f9f7	507	* @arg LPTIM_IT_CMPM : Compare match Interrupt.
<>	144:ef7eb2e8f9f7	508	* @retval Interrupt status.
<>	144:ef7eb2e8f9f7	509	*/
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	/**
<>	151:5eaa88a5bcc7	514	* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	515	* @retval None
<>	151:5eaa88a5bcc7	516	*/
<>	151:5eaa88a5bcc7	517	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR \|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
<>	151:5eaa88a5bcc7	518
<>	151:5eaa88a5bcc7	519	/**
<>	151:5eaa88a5bcc7	520	* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	521	* @retval None
<>	151:5eaa88a5bcc7	522	*/
<>	151:5eaa88a5bcc7	523	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
<>	151:5eaa88a5bcc7	524
<>	151:5eaa88a5bcc7	525	/**
<>	151:5eaa88a5bcc7	526	* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	527	* @retval None.
<>	151:5eaa88a5bcc7	528	*/
<>	151:5eaa88a5bcc7	529	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR \|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
<>	151:5eaa88a5bcc7	530
<>	151:5eaa88a5bcc7	531	/**
<>	151:5eaa88a5bcc7	532	* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	533	* @retval None.
<>	151:5eaa88a5bcc7	534	*/
<>	151:5eaa88a5bcc7	535	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
<>	151:5eaa88a5bcc7	536
<>	151:5eaa88a5bcc7	537	/**
<>	151:5eaa88a5bcc7	538	* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	539	* @retval None.
<>	151:5eaa88a5bcc7	540	*/
<>	151:5eaa88a5bcc7	541	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR \|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
<>	151:5eaa88a5bcc7	542
<>	151:5eaa88a5bcc7	543	/**
<>	151:5eaa88a5bcc7	544	* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	545	* @retval None.
<>	151:5eaa88a5bcc7	546	*/
<>	151:5eaa88a5bcc7	547	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
<>	151:5eaa88a5bcc7	548
<>	151:5eaa88a5bcc7	549	/**
<>	151:5eaa88a5bcc7	550	* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	551	* @retval None.
<>	151:5eaa88a5bcc7	552	*/
<>	151:5eaa88a5bcc7	553	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR \|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
<>	151:5eaa88a5bcc7	554
<>	151:5eaa88a5bcc7	555	/**
<>	151:5eaa88a5bcc7	556	* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	557	* @retval None.
<>	151:5eaa88a5bcc7	558	*/
<>	151:5eaa88a5bcc7	559	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
<>	151:5eaa88a5bcc7	560
<>	151:5eaa88a5bcc7	561	/**
<>	151:5eaa88a5bcc7	562	* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	563	* @retval None.
<>	151:5eaa88a5bcc7	564	*/
<>	151:5eaa88a5bcc7	565	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
<>	151:5eaa88a5bcc7	566	__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
<>	151:5eaa88a5bcc7	567	}while(0)
<>	151:5eaa88a5bcc7	568
<>	151:5eaa88a5bcc7	569	/**
<>	151:5eaa88a5bcc7	570	* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	571	* @retval None.
<>	151:5eaa88a5bcc7	572	*/
<>	151:5eaa88a5bcc7	573	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
<>	151:5eaa88a5bcc7	574	__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
<>	151:5eaa88a5bcc7	575	}while(0)
<>	151:5eaa88a5bcc7	576
<>	151:5eaa88a5bcc7	577	/**
<>	151:5eaa88a5bcc7	578	* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
<>	151:5eaa88a5bcc7	579	* @retval Line Status.
<>	151:5eaa88a5bcc7	580	*/
<>	151:5eaa88a5bcc7	581	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
<>	151:5eaa88a5bcc7	582
<>	151:5eaa88a5bcc7	583	/**
<>	151:5eaa88a5bcc7	584	* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
<>	151:5eaa88a5bcc7	585	* @retval None.
<>	151:5eaa88a5bcc7	586	*/
<>	151:5eaa88a5bcc7	587	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
<>	151:5eaa88a5bcc7	588
<>	151:5eaa88a5bcc7	589	/**
<>	151:5eaa88a5bcc7	590	* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
<>	151:5eaa88a5bcc7	591	* @retval None.
<>	151:5eaa88a5bcc7	592	*/
<>	151:5eaa88a5bcc7	593	#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER \|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
<>	151:5eaa88a5bcc7	594
<>	151:5eaa88a5bcc7	595	/**
<>	144:ef7eb2e8f9f7	596	* @}
<>	144:ef7eb2e8f9f7	597	*/
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	/* Include LPTIM HAL Extension module */
<>	144:ef7eb2e8f9f7	601	#include "stm32l0xx_hal_lptim_ex.h"
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
<>	144:ef7eb2e8f9f7	606	* @{
<>	144:ef7eb2e8f9f7	607	*/
<>	144:ef7eb2e8f9f7	608	/* Initialization/de-initialization functions ********************************/
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
<>	144:ef7eb2e8f9f7	611	* @{
<>	144:ef7eb2e8f9f7	612	*/
<>	144:ef7eb2e8f9f7	613	HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	614	HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	615
<>	144:ef7eb2e8f9f7	616
<>	144:ef7eb2e8f9f7	617	/* MSP functions *************************************************************/
<>	144:ef7eb2e8f9f7	618
<>	144:ef7eb2e8f9f7	619	void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	620	void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	621
<>	144:ef7eb2e8f9f7	622	/**
<>	144:ef7eb2e8f9f7	623	* @}
<>	144:ef7eb2e8f9f7	624	*/
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/* Start/Stop operation functions *********************************************/
<>	144:ef7eb2e8f9f7	627
<>	144:ef7eb2e8f9f7	628	/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
<>	144:ef7eb2e8f9f7	629	* @{
<>	144:ef7eb2e8f9f7	630	*/
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	/* ################################# PWM Mode ################################*/
<>	144:ef7eb2e8f9f7	633	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	634	HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
<>	144:ef7eb2e8f9f7	635	HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	636	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	637	HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
<>	144:ef7eb2e8f9f7	638	HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	/* ############################# One Pulse Mode ##############################*/
<>	144:ef7eb2e8f9f7	641	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	642	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
<>	144:ef7eb2e8f9f7	643	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	644	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	645	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
<>	144:ef7eb2e8f9f7	646	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	647
<>	144:ef7eb2e8f9f7	648	/* ############################## Set once Mode ##############################*/
<>	144:ef7eb2e8f9f7	649	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	650	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
<>	144:ef7eb2e8f9f7	651	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	652	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	653	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
<>	144:ef7eb2e8f9f7	654	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/* ############################### Encoder Mode ##############################*/
<>	144:ef7eb2e8f9f7	657	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	658	HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
<>	144:ef7eb2e8f9f7	659	HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	660	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	661	HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
<>	144:ef7eb2e8f9f7	662	HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	/* ############################# Time out Mode ##############################*/
<>	144:ef7eb2e8f9f7	665	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	666	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	667	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	668	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	669	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	670	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	671
<>	144:ef7eb2e8f9f7	672	/* ############################## Counter Mode ###############################*/
<>	144:ef7eb2e8f9f7	673	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	674	HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
<>	144:ef7eb2e8f9f7	675	HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	676	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	677	HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
<>	144:ef7eb2e8f9f7	678	HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	/**
<>	144:ef7eb2e8f9f7	681	* @}
<>	144:ef7eb2e8f9f7	682	*/
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	/* Reading operation functions ************************************************/
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
<>	144:ef7eb2e8f9f7	687	* @{
<>	144:ef7eb2e8f9f7	688	*/
<>	144:ef7eb2e8f9f7	689	uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	690	uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	691	uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	692	/**
<>	144:ef7eb2e8f9f7	693	* @}
<>	144:ef7eb2e8f9f7	694	*/
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	/* LPTIM IRQ functions *******************************************************/
<>	144:ef7eb2e8f9f7	697	/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler
<>	144:ef7eb2e8f9f7	698	* @{
<>	144:ef7eb2e8f9f7	699	*/
<>	144:ef7eb2e8f9f7	700	void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702	/* CallBack functions ********************************************************/
<>	144:ef7eb2e8f9f7	703	void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	704	void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	705	void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	706	void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	707	void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	708	void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	709	void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	710	/**
<>	144:ef7eb2e8f9f7	711	* @}
<>	144:ef7eb2e8f9f7	712	*/
<>	144:ef7eb2e8f9f7	713	/* Peripheral State functions ************************************************/
<>	144:ef7eb2e8f9f7	714	/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions
<>	144:ef7eb2e8f9f7	715	* @{
<>	144:ef7eb2e8f9f7	716	*/
<>	144:ef7eb2e8f9f7	717
<>	144:ef7eb2e8f9f7	718	HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	/**
<>	144:ef7eb2e8f9f7	721	* @}
<>	144:ef7eb2e8f9f7	722	*/
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/**
<>	144:ef7eb2e8f9f7	725	* @}
<>	144:ef7eb2e8f9f7	726	*/
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	/**
<>	144:ef7eb2e8f9f7	729	* @}
<>	144:ef7eb2e8f9f7	730	*/
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	/**
<>	144:ef7eb2e8f9f7	733	* @}
<>	144:ef7eb2e8f9f7	734	*/
<>	144:ef7eb2e8f9f7	735
<>	144:ef7eb2e8f9f7	736	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	737	}
<>	144:ef7eb2e8f9f7	738	#endif
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	#endif /* __STM32L0xx_HAL_LPTIM_H */
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	743