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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_i2s.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of I2S HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32L0xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 38 #define __STM32L0xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L011xx) && !defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 45 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 46 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @defgroup I2S I2S
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /** @defgroup I2S_Exported_Types I2S Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief I2S Init structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 144:ef7eb2e8f9f7 67 This parameter can be a value of @ref I2S_Mode */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref I2S_Standard */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref I2S_Data_Format */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref I2S_MCLK_Output */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref I2S_Audio_Frequency */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref I2S_Clock_Polarity */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 }I2S_InitTypeDef;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /**
<> 144:ef7eb2e8f9f7 87 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89 typedef enum
<> 144:ef7eb2e8f9f7 90 {
<> 151:5eaa88a5bcc7 91 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
<> 151:5eaa88a5bcc7 92 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
<> 151:5eaa88a5bcc7 93 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
<> 151:5eaa88a5bcc7 94 HAL_I2S_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
<> 151:5eaa88a5bcc7 95 HAL_I2S_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 151:5eaa88a5bcc7 96 HAL_I2S_STATE_TIMEOUT = 0x03U, /*!< I2S timeout state */
<> 151:5eaa88a5bcc7 97 HAL_I2S_STATE_ERROR = 0x04U /*!< I2S error state */
<> 144:ef7eb2e8f9f7 98 }HAL_I2S_StateTypeDef;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @brief I2S handle Structure definition
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 typedef struct
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 SPI_TypeDef *Instance; /* I2S registers base address */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 I2S_InitTypeDef Init; /* I2S communication parameters */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 __IO uint16_t RxXferCount; /* I2S Rx transfer counter
<> 144:ef7eb2e8f9f7 120 (This field is initialized at the
<> 144:ef7eb2e8f9f7 121 same value as transfer size at the
<> 144:ef7eb2e8f9f7 122 beginning of the transfer and
<> 144:ef7eb2e8f9f7 123 decremented when a sample is received.
<> 144:ef7eb2e8f9f7 124 NbSamplesReceived = RxBufferSize-RxBufferCount) */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 __IO HAL_LockTypeDef Lock; /* I2S locking object */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 __IO uint32_t ErrorCode; /* I2S Error code */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 }I2S_HandleTypeDef;
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @}
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /** @defgroup I2S_Exported_Constants I2S Exported Constants
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @defgroup I2S_ErrorCode I2S Error Code
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 151:5eaa88a5bcc7 150 #define HAL_I2S_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
<> 151:5eaa88a5bcc7 151 #define HAL_I2S_ERROR_UDR ((uint32_t)0x01U) /*!< I2S Underrun error */
<> 151:5eaa88a5bcc7 152 #define HAL_I2S_ERROR_OVR ((uint32_t)0x02U) /*!< I2S Overrun error */
<> 151:5eaa88a5bcc7 153 #define HAL_I2S_ERROR_FRE ((uint32_t)0x04U) /*!< I2S Frame format error */
<> 151:5eaa88a5bcc7 154 #define HAL_I2S_ERROR_DMA ((uint32_t)0x08U) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /** @defgroup I2S_Mode I2S Mode
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 151:5eaa88a5bcc7 162 #define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000U)
<> 144:ef7eb2e8f9f7 163 #define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0)
<> 144:ef7eb2e8f9f7 164 #define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1)
<> 144:ef7eb2e8f9f7 165 #define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\
<> 144:ef7eb2e8f9f7 166 SPI_I2SCFGR_I2SCFG_1))
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup I2S_Standard I2S Standard
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 151:5eaa88a5bcc7 174 #define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000U)
<> 144:ef7eb2e8f9f7 175 #define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
<> 144:ef7eb2e8f9f7 176 #define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
<> 144:ef7eb2e8f9f7 177 #define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
<> 144:ef7eb2e8f9f7 178 SPI_I2SCFGR_I2SSTD_1))
<> 144:ef7eb2e8f9f7 179 #define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
<> 144:ef7eb2e8f9f7 180 SPI_I2SCFGR_I2SSTD_1 |\
<> 144:ef7eb2e8f9f7 181 SPI_I2SCFGR_PCMSYNC))
<> 144:ef7eb2e8f9f7 182 /** @defgroup I2S_Legacy I2S Legacy
<> 144:ef7eb2e8f9f7 183 * @{
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
<> 144:ef7eb2e8f9f7 186 /**
<> 144:ef7eb2e8f9f7 187 * @}
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @defgroup I2S_Data_Format I2S Data Format
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 151:5eaa88a5bcc7 197 #define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000U)
<> 144:ef7eb2e8f9f7 198 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
<> 144:ef7eb2e8f9f7 199 #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
<> 144:ef7eb2e8f9f7 200 #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @}
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup I2S_MCLK_Output I2S MCLK Output
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
<> 151:5eaa88a5bcc7 209 #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @}
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
<> 144:ef7eb2e8f9f7 215 * @{
<> 144:ef7eb2e8f9f7 216 */
<> 151:5eaa88a5bcc7 217 #define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
<> 151:5eaa88a5bcc7 218 #define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
<> 151:5eaa88a5bcc7 219 #define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
<> 151:5eaa88a5bcc7 220 #define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
<> 151:5eaa88a5bcc7 221 #define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
<> 151:5eaa88a5bcc7 222 #define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
<> 151:5eaa88a5bcc7 223 #define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
<> 151:5eaa88a5bcc7 224 #define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
<> 151:5eaa88a5bcc7 225 #define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
<> 151:5eaa88a5bcc7 226 #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
<> 151:5eaa88a5bcc7 234 #define I2S_CPOL_LOW ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 235 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 #define I2S_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 244 #define I2S_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 245 #define I2S_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @}
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /** @defgroup I2S_Flag_definition I2S Flag definition
<> 144:ef7eb2e8f9f7 251 * @{
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253 #define I2S_FLAG_TXE SPI_SR_TXE
<> 144:ef7eb2e8f9f7 254 #define I2S_FLAG_RXNE SPI_SR_RXNE
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 #define I2S_FLAG_UDR SPI_SR_UDR
<> 144:ef7eb2e8f9f7 257 #define I2S_FLAG_OVR SPI_SR_OVR
<> 144:ef7eb2e8f9f7 258 #define I2S_FLAG_FRE SPI_SR_FRE
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
<> 144:ef7eb2e8f9f7 261 #define I2S_FLAG_BSY SPI_SR_BSY
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @}
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 271 /** @defgroup I2S_Exported_Macros I2S Exported Macros
<> 144:ef7eb2e8f9f7 272 * @{
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /** @brief Reset I2S handle state
<> 144:ef7eb2e8f9f7 276 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 277 * @retval None
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /** @brief Enable the specified SPI peripheral (in I2S mode).
<> 144:ef7eb2e8f9f7 282 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 283 * @retval None
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /** @brief Disable the specified SPI peripheral (in I2S mode).
<> 144:ef7eb2e8f9f7 288 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 289 * @retval None
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @brief Enable the specified I2S interrupts.
<> 144:ef7eb2e8f9f7 294 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 295 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 144:ef7eb2e8f9f7 296 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 297 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 298 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 299 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 300 * @retval None
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @brief Disable the specified I2S interrupts.
<> 144:ef7eb2e8f9f7 305 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 306 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 144:ef7eb2e8f9f7 307 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 308 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 309 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 310 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 311 * @retval None
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 316 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 317 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
<> 144:ef7eb2e8f9f7 318 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
<> 144:ef7eb2e8f9f7 319 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 320 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 321 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 322 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 323 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /** @brief Checks whether the specified I2S flag is set or not.
<> 144:ef7eb2e8f9f7 328 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 329 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 330 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 331 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 332 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 333 * @arg I2S_FLAG_UDR: Underrun flag
<> 144:ef7eb2e8f9f7 334 * @arg I2S_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 335 * @arg I2S_FLAG_CHSIDE: Channel Side flag
<> 144:ef7eb2e8f9f7 336 * @arg I2S_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 337 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @brief Clears the I2S OVR pending flag.
<> 144:ef7eb2e8f9f7 342 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 343 * @retval None
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
<> 144:ef7eb2e8f9f7 346 tmpreg = (__HANDLE__)->Instance->SR;\
<> 144:ef7eb2e8f9f7 347 UNUSED(tmpreg);\
<> 144:ef7eb2e8f9f7 348 }while(0)
<> 144:ef7eb2e8f9f7 349 /** @brief Clears the I2S UDR pending flag.
<> 144:ef7eb2e8f9f7 350 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 351 * @retval None
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @}
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 359 /** @defgroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 360 * @{
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 /* Initialization/de-initialization functions ********************************/
<> 144:ef7eb2e8f9f7 367 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 368 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 369 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 370 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @}
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 376 * @{
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 379 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 380 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 381 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 384 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 385 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 386 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 389 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 390 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 393 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
<> 144:ef7eb2e8f9f7 397 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 398 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 399 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 400 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 401 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /** @defgroup I2S_Exported_Functions_Group3 Peripheral Control and State functions
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 /* Peripheral Control and State functions ************************************/
<> 144:ef7eb2e8f9f7 410 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 411 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @}
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 421 /** @defgroup I2S_Private I2S Private
<> 144:ef7eb2e8f9f7 422 * @{
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
<> 144:ef7eb2e8f9f7 425 ((MODE) == I2S_MODE_SLAVE_RX) || \
<> 144:ef7eb2e8f9f7 426 ((MODE) == I2S_MODE_MASTER_TX) || \
<> 144:ef7eb2e8f9f7 427 ((MODE) == I2S_MODE_MASTER_RX))
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
<> 144:ef7eb2e8f9f7 430 ((STANDARD) == I2S_STANDARD_MSB) || \
<> 144:ef7eb2e8f9f7 431 ((STANDARD) == I2S_STANDARD_LSB) || \
<> 144:ef7eb2e8f9f7 432 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
<> 144:ef7eb2e8f9f7 433 ((STANDARD) == I2S_STANDARD_PCM_LONG))
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
<> 144:ef7eb2e8f9f7 436 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
<> 144:ef7eb2e8f9f7 437 ((FORMAT) == I2S_DATAFORMAT_24B) || \
<> 144:ef7eb2e8f9f7 438 ((FORMAT) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
<> 144:ef7eb2e8f9f7 441 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
<> 144:ef7eb2e8f9f7 444 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
<> 144:ef7eb2e8f9f7 445 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
<> 144:ef7eb2e8f9f7 448 ((CPOL) == I2S_CPOL_HIGH))
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @}
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 454 /**************************************************************/
<> 144:ef7eb2e8f9f7 455 /** @defgroup I2S_Private I2S Private
<> 144:ef7eb2e8f9f7 456 * @{
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 /**************************************************************/
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /**
<> 144:ef7eb2e8f9f7 464 * @}
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /**
<> 144:ef7eb2e8f9f7 468 * @}
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #endif /* !STM32L031xx && !STM32L041xx && !STM32L011xx && !STM32L021xx */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 #endif
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 #endif /* __STM32L0xx_HAL_I2S_H */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/